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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/nau8825.c

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  1 /*
  2  * Nuvoton NAU8825 audio codec driver
  3  *
  4  * Copyright 2015 Google Chromium project.
  5  *  Author: Anatol Pomozov <anatol@chromium.org>
  6  * Copyright 2015 Nuvoton Technology Corp.
  7  *  Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
  8  *
  9  * Licensed under the GPL-2.
 10  */
 11 
 12 #include <linux/module.h>
 13 #include <linux/delay.h>
 14 #include <linux/init.h>
 15 #include <linux/i2c.h>
 16 #include <linux/regmap.h>
 17 #include <linux/slab.h>
 18 #include <linux/clk.h>
 19 #include <linux/acpi.h>
 20 #include <linux/math64.h>
 21 #include <linux/semaphore.h>
 22 
 23 #include <sound/initval.h>
 24 #include <sound/tlv.h>
 25 #include <sound/core.h>
 26 #include <sound/pcm.h>
 27 #include <sound/pcm_params.h>
 28 #include <sound/soc.h>
 29 #include <sound/jack.h>
 30 
 31 
 32 #include "nau8825.h"
 33 
 34 
 35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
 36 
 37 #define NAU_FREF_MAX 13500000
 38 #define NAU_FVCO_MAX 124000000
 39 #define NAU_FVCO_MIN 90000000
 40 
 41 /* cross talk suppression detection */
 42 #define LOG10_MAGIC 646456993
 43 #define GAIN_AUGMENT 22500
 44 #define SIDETONE_BASE 207000
 45 
 46 /* the maximum frequency of CLK_ADC and CLK_DAC */
 47 #define CLK_DA_AD_MAX 6144000
 48 
 49 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
 50                 int clk_id, unsigned int freq);
 51 
 52 struct nau8825_fll {
 53         int mclk_src;
 54         int ratio;
 55         int fll_frac;
 56         int fll_int;
 57         int clk_ref_div;
 58 };
 59 
 60 struct nau8825_fll_attr {
 61         unsigned int param;
 62         unsigned int val;
 63 };
 64 
 65 /* scaling for mclk from sysclk_src output */
 66 static const struct nau8825_fll_attr mclk_src_scaling[] = {
 67         { 1, 0x0 },
 68         { 2, 0x2 },
 69         { 4, 0x3 },
 70         { 8, 0x4 },
 71         { 16, 0x5 },
 72         { 32, 0x6 },
 73         { 3, 0x7 },
 74         { 6, 0xa },
 75         { 12, 0xb },
 76         { 24, 0xc },
 77         { 48, 0xd },
 78         { 96, 0xe },
 79         { 5, 0xf },
 80 };
 81 
 82 /* ratio for input clk freq */
 83 static const struct nau8825_fll_attr fll_ratio[] = {
 84         { 512000, 0x01 },
 85         { 256000, 0x02 },
 86         { 128000, 0x04 },
 87         { 64000, 0x08 },
 88         { 32000, 0x10 },
 89         { 8000, 0x20 },
 90         { 4000, 0x40 },
 91 };
 92 
 93 static const struct nau8825_fll_attr fll_pre_scalar[] = {
 94         { 1, 0x0 },
 95         { 2, 0x1 },
 96         { 4, 0x2 },
 97         { 8, 0x3 },
 98 };
 99 
100 /* over sampling rate */
101 struct nau8825_osr_attr {
102         unsigned int osr;
103         unsigned int clk_src;
104 };
105 
106 static const struct nau8825_osr_attr osr_dac_sel[] = {
107         { 64, 2 },      /* OSR 64, SRC 1/4 */
108         { 256, 0 },     /* OSR 256, SRC 1 */
109         { 128, 1 },     /* OSR 128, SRC 1/2 */
110         { 0, 0 },
111         { 32, 3 },      /* OSR 32, SRC 1/8 */
112 };
113 
114 static const struct nau8825_osr_attr osr_adc_sel[] = {
115         { 32, 3 },      /* OSR 32, SRC 1/8 */
116         { 64, 2 },      /* OSR 64, SRC 1/4 */
117         { 128, 1 },     /* OSR 128, SRC 1/2 */
118         { 256, 0 },     /* OSR 256, SRC 1 */
119 };
120 
121 static const struct reg_default nau8825_reg_defaults[] = {
122         { NAU8825_REG_ENA_CTRL, 0x00ff },
123         { NAU8825_REG_IIC_ADDR_SET, 0x0 },
124         { NAU8825_REG_CLK_DIVIDER, 0x0050 },
125         { NAU8825_REG_FLL1, 0x0 },
126         { NAU8825_REG_FLL2, 0x3126 },
127         { NAU8825_REG_FLL3, 0x0008 },
128         { NAU8825_REG_FLL4, 0x0010 },
129         { NAU8825_REG_FLL5, 0x0 },
130         { NAU8825_REG_FLL6, 0x6000 },
131         { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
132         { NAU8825_REG_HSD_CTRL, 0x000c },
133         { NAU8825_REG_JACK_DET_CTRL, 0x0 },
134         { NAU8825_REG_INTERRUPT_MASK, 0x0 },
135         { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
136         { NAU8825_REG_SAR_CTRL, 0x0015 },
137         { NAU8825_REG_KEYDET_CTRL, 0x0110 },
138         { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
139         { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
140         { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
141         { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
142         { NAU8825_REG_GPIO34_CTRL, 0x0 },
143         { NAU8825_REG_GPIO12_CTRL, 0x0 },
144         { NAU8825_REG_TDM_CTRL, 0x0 },
145         { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
146         { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
147         { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
148         { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
149         { NAU8825_REG_BIQ_CTRL, 0x0 },
150         { NAU8825_REG_BIQ_COF1, 0x0 },
151         { NAU8825_REG_BIQ_COF2, 0x0 },
152         { NAU8825_REG_BIQ_COF3, 0x0 },
153         { NAU8825_REG_BIQ_COF4, 0x0 },
154         { NAU8825_REG_BIQ_COF5, 0x0 },
155         { NAU8825_REG_BIQ_COF6, 0x0 },
156         { NAU8825_REG_BIQ_COF7, 0x0 },
157         { NAU8825_REG_BIQ_COF8, 0x0 },
158         { NAU8825_REG_BIQ_COF9, 0x0 },
159         { NAU8825_REG_BIQ_COF10, 0x0 },
160         { NAU8825_REG_ADC_RATE, 0x0010 },
161         { NAU8825_REG_DAC_CTRL1, 0x0001 },
162         { NAU8825_REG_DAC_CTRL2, 0x0 },
163         { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
164         { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
165         { NAU8825_REG_MUTE_CTRL, 0x0 },
166         { NAU8825_REG_HSVOL_CTRL, 0x0 },
167         { NAU8825_REG_DACL_CTRL, 0x02cf },
168         { NAU8825_REG_DACR_CTRL, 0x00cf },
169         { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
170         { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
171         { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
172         { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
173         { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
174         { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
175         { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
176         { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
177         { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
178         { NAU8825_REG_CLASSG_CTRL, 0x0 },
179         { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
180         { NAU8825_REG_MISC_CTRL, 0x0 },
181         { NAU8825_REG_BIAS_ADJ, 0x0 },
182         { NAU8825_REG_TRIM_SETTINGS, 0x0 },
183         { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
184         { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
185         { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
186         { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
187         { NAU8825_REG_RDAC, 0x0008 },
188         { NAU8825_REG_MIC_BIAS, 0x0006 },
189         { NAU8825_REG_BOOST, 0x0 },
190         { NAU8825_REG_FEPGA, 0x0 },
191         { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
192         { NAU8825_REG_CHARGE_PUMP, 0x0 },
193 };
194 
195 /* register backup table when cross talk detection */
196 static struct reg_default nau8825_xtalk_baktab[] = {
197         { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
198         { NAU8825_REG_HSVOL_CTRL, 0 },
199         { NAU8825_REG_DACL_CTRL, 0 },
200         { NAU8825_REG_DACR_CTRL, 0 },
201 };
202 
203 static const unsigned short logtable[256] = {
204         0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
205         0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
206         0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
207         0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
208         0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
209         0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
210         0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
211         0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
212         0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
213         0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
214         0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
215         0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
216         0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
217         0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
218         0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
219         0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
220         0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
221         0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
222         0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
223         0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
224         0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
225         0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
226         0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
227         0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
228         0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
229         0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
230         0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
231         0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
232         0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
233         0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
234         0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
235         0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
236 };
237 
238 /**
239  * nau8825_sema_acquire - acquire the semaphore of nau88l25
240  * @nau8825:  component to register the codec private data with
241  * @timeout: how long in jiffies to wait before failure or zero to wait
242  * until release
243  *
244  * Attempts to acquire the semaphore with number of jiffies. If no more
245  * tasks are allowed to acquire the semaphore, calling this function will
246  * put the task to sleep. If the semaphore is not released within the
247  * specified number of jiffies, this function returns.
248  * Acquires the semaphore without jiffies. If no more tasks are allowed
249  * to acquire the semaphore, calling this function will put the task to
250  * sleep until the semaphore is released.
251  * If the semaphore is not released within the specified number of jiffies,
252  * this function returns -ETIME.
253  * If the sleep is interrupted by a signal, this function will return -EINTR.
254  * It returns 0 if the semaphore was acquired successfully.
255  */
256 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
257 {
258         int ret;
259 
260         if (timeout) {
261                 ret = down_timeout(&nau8825->xtalk_sem, timeout);
262                 if (ret < 0)
263                         dev_warn(nau8825->dev, "Acquire semaphone timeout\n");
264         } else {
265                 ret = down_interruptible(&nau8825->xtalk_sem);
266                 if (ret < 0)
267                         dev_warn(nau8825->dev, "Acquire semaphone fail\n");
268         }
269 
270         return ret;
271 }
272 
273 /**
274  * nau8825_sema_release - release the semaphore of nau88l25
275  * @nau8825:  component to register the codec private data with
276  *
277  * Release the semaphore which may be called from any context and
278  * even by tasks which have never called down().
279  */
280 static inline void nau8825_sema_release(struct nau8825 *nau8825)
281 {
282         up(&nau8825->xtalk_sem);
283 }
284 
285 /**
286  * nau8825_sema_reset - reset the semaphore for nau88l25
287  * @nau8825:  component to register the codec private data with
288  *
289  * Reset the counter of the semaphore. Call this function to restart
290  * a new round task management.
291  */
292 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
293 {
294         nau8825->xtalk_sem.count = 1;
295 }
296 
297 /**
298  * Ramp up the headphone volume change gradually to target level.
299  *
300  * @nau8825:  component to register the codec private data with
301  * @vol_from: the volume to start up
302  * @vol_to: the target volume
303  * @step: the volume span to move on
304  *
305  * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
306  * If the volume changes sharp, there is a pop noise heard in headphone. We
307  * provide the function to ramp up the volume up or down by delaying 10ms
308  * per step.
309  */
310 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
311         unsigned int vol_from, unsigned int vol_to, unsigned int step)
312 {
313         unsigned int value, volume, ramp_up, from, to;
314 
315         if (vol_from == vol_to || step == 0) {
316                 return;
317         } else if (vol_from < vol_to) {
318                 ramp_up = true;
319                 from = vol_from;
320                 to = vol_to;
321         } else {
322                 ramp_up = false;
323                 from = vol_to;
324                 to = vol_from;
325         }
326         /* only handle volume from 0dB to minimum -54dB */
327         if (to > NAU8825_HP_VOL_MIN)
328                 to = NAU8825_HP_VOL_MIN;
329 
330         for (volume = from; volume < to; volume += step) {
331                 if (ramp_up)
332                         value = volume;
333                 else
334                         value = to - volume + from;
335                 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
336                         NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
337                         (value << NAU8825_HPL_VOL_SFT) | value);
338                 usleep_range(10000, 10500);
339         }
340         if (ramp_up)
341                 value = to;
342         else
343                 value = from;
344         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
345                 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
346                 (value << NAU8825_HPL_VOL_SFT) | value);
347 }
348 
349 /**
350  * Computes log10 of a value; the result is round off to 3 decimal. This func-
351  * tion takes reference to dvb-math. The source code locates as the following.
352  * Linux/drivers/media/dvb-core/dvb_math.c
353  *
354  * return log10(value) * 1000
355  */
356 static u32 nau8825_intlog10_dec3(u32 value)
357 {
358         u32 msb, logentry, significand, interpolation, log10val;
359         u64 log2val;
360 
361         /* first detect the msb (count begins at 0) */
362         msb = fls(value) - 1;
363         /**
364          *      now we use a logtable after the following method:
365          *
366          *      log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
367          *      where x = msb and therefore 1 <= y < 2
368          *      first y is determined by shifting the value left
369          *      so that msb is bit 31
370          *              0x00231f56 -> 0x8C7D5800
371          *      the result is y * 2^31 -> "significand"
372          *      then the highest 9 bits are used for a table lookup
373          *      the highest bit is discarded because it's always set
374          *      the highest nine bits in our example are 100011000
375          *      so we would use the entry 0x18
376          */
377         significand = value << (31 - msb);
378         logentry = (significand >> 23) & 0xff;
379         /**
380          *      last step we do is interpolation because of the
381          *      limitations of the log table the error is that part of
382          *      the significand which isn't used for lookup then we
383          *      compute the ratio between the error and the next table entry
384          *      and interpolate it between the log table entry used and the
385          *      next one the biggest error possible is 0x7fffff
386          *      (in our example it's 0x7D5800)
387          *      needed value for next table entry is 0x800000
388          *      so the interpolation is
389          *      (error / 0x800000) * (logtable_next - logtable_current)
390          *      in the implementation the division is moved to the end for
391          *      better accuracy there is also an overflow correction if
392          *      logtable_next is 256
393          */
394         interpolation = ((significand & 0x7fffff) *
395                 ((logtable[(logentry + 1) & 0xff] -
396                 logtable[logentry]) & 0xffff)) >> 15;
397 
398         log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
399         /**
400          *      log10(x) = log2(x) * log10(2)
401          */
402         log10val = (log2val * LOG10_MAGIC) >> 31;
403         /**
404          *      the result is round off to 3 decimal
405          */
406         return log10val / ((1 << 24) / 1000);
407 }
408 
409 /**
410  * computes cross talk suppression sidetone gain.
411  *
412  * @sig_org: orignal signal level
413  * @sig_cros: cross talk signal level
414  *
415  * The orignal and cross talk signal vlues need to be characterized.
416  * Once these values have been characterized, this sidetone value
417  * can be converted to decibel with the equation below.
418  * sidetone = 20 * log (original signal level / crosstalk signal level)
419  *
420  * return cross talk sidetone gain
421  */
422 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
423 {
424         u32 gain, sidetone;
425 
426         if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
427                 WARN_ON(1);
428                 return 0;
429         }
430 
431         sig_org = nau8825_intlog10_dec3(sig_org);
432         sig_cros = nau8825_intlog10_dec3(sig_cros);
433         if (sig_org >= sig_cros)
434                 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
435         else
436                 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
437         sidetone = SIDETONE_BASE - gain * 2;
438         sidetone /= 1000;
439 
440         return sidetone;
441 }
442 
443 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
444 {
445         int index;
446 
447         for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
448                 if (nau8825_xtalk_baktab[index].reg == reg)
449                         return index;
450         return -EINVAL;
451 }
452 
453 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
454 {
455         int i;
456 
457         /* Backup some register values to backup table */
458         for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
459                 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
460                                 &nau8825_xtalk_baktab[i].def);
461 }
462 
463 static void nau8825_xtalk_restore(struct nau8825 *nau8825)
464 {
465         int i, volume;
466 
467         /* Restore register values from backup table; When the driver restores
468          * the headphone volumem, it needs recover to original level gradually
469          * with 3dB per step for less pop noise.
470          */
471         for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
472                 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
473                         /* Ramping up the volume change to reduce pop noise */
474                         volume = nau8825_xtalk_baktab[i].def &
475                                 NAU8825_HPR_VOL_MASK;
476                         nau8825_hpvol_ramp(nau8825, 0, volume, 3);
477                         continue;
478                 }
479                 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
480                                 nau8825_xtalk_baktab[i].def);
481         }
482 }
483 
484 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
485 {
486         /* Enable power of DAC path */
487         regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
488                 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
489                 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
490                 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
491                 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
492                 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
493         /* Prevent startup click by letting charge pump to ramp up and
494          * change bump enable
495          */
496         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
497                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
498                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
499         /* Enable clock sync of DAC and DAC clock */
500         regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
501                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
502                 NAU8825_RDAC_FS_BCLK_ENB,
503                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
504         /* Power up output driver with 2 stage */
505         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
506                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
507                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
508                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
509                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
510         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
511                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
512                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
513         /* HP outputs not shouted to ground  */
514         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
515                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
516         /* Enable HP boost driver */
517         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
518                 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
519         /* Enable class G compare path to supply 1.8V or 0.9V. */
520         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
521                 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
522                 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
523 }
524 
525 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
526 {
527         /* Power up left ADC and raise 5dB than Vmid for Vref  */
528         regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
529                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
530                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
531 }
532 
533 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
534 {
535         /* Recover FLL default value */
536         regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
537         regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
538         regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
539         regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
540         regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
541         regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
542         /* Enable internal VCO clock for detection signal generated */
543         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
544                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
545         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
546                 NAU8825_DCO_EN);
547         /* Given specific clock frequency of internal clock to
548          * generate signal.
549          */
550         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
551                 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
552         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
553                 NAU8825_FLL_RATIO_MASK, 0x10);
554 }
555 
556 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
557 {
558         int volume, index;
559 
560         /* Backup those registers changed by cross talk detection */
561         nau8825_xtalk_backup(nau8825);
562         /* Config IIS as master to output signal by codec */
563         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
564                 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
565                 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
566                 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
567         /* Ramp up headphone volume to 0dB to get better performance and
568          * avoid pop noise in headphone.
569          */
570         index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
571         if (index != -EINVAL) {
572                 volume = nau8825_xtalk_baktab[index].def &
573                                 NAU8825_HPR_VOL_MASK;
574                 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
575         }
576         nau8825_xtalk_clock(nau8825);
577         nau8825_xtalk_prepare_dac(nau8825);
578         nau8825_xtalk_prepare_adc(nau8825);
579         /* Config channel path and digital gain */
580         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
581                 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
582                 NAU8825_DACL_CH_SEL_L | 0xab);
583         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
584                 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
585                 NAU8825_DACR_CH_SEL_R | 0xab);
586         /* Config cross talk parameters and generate the 23Hz sine wave with
587          * 1/16 full scale of signal level for impedance measurement.
588          */
589         regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
590                 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
591                 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
592                 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
593                 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
594         /* RMS intrruption enable */
595         regmap_update_bits(nau8825->regmap,
596                 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
597         /* Power up left and right DAC */
598         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
599                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
600 }
601 
602 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
603 {
604         /* Disable HP boost driver */
605         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
606                 NAU8825_HP_BOOST_DIS, 0);
607         /* HP outputs shouted to ground  */
608         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
609                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
610                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
611         /* Power down left and right DAC */
612         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
613                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
614                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
615         /* Enable the TESTDAC and  disable L/R HP impedance */
616         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
617                 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
618                 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
619         /* Power down output driver with 2 stage */
620         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
621                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
622         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
623                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
624                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
625         /* Disable clock sync of DAC and DAC clock */
626         regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
627                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
628         /* Disable charge pump ramp up function and change bump */
629         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
630                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
631         /* Disable power of DAC path */
632         regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
633                 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
634                 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
635         if (!nau8825->irq)
636                 regmap_update_bits(nau8825->regmap,
637                         NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
638 }
639 
640 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
641 {
642         /* Power down left ADC and restore voltage to Vmid */
643         regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
644                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
645 }
646 
647 static void nau8825_xtalk_clean(struct nau8825 *nau8825)
648 {
649         /* Enable internal VCO needed for interruptions */
650         nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
651         nau8825_xtalk_clean_dac(nau8825);
652         nau8825_xtalk_clean_adc(nau8825);
653         /* Clear cross talk parameters and disable */
654         regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
655         /* RMS intrruption disable */
656         regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
657                 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
658         /* Recover default value for IIS */
659         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
660                 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
661                 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
662         /* Restore value of specific register for cross talk */
663         nau8825_xtalk_restore(nau8825);
664 }
665 
666 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
667 {
668         /* Apply ADC volume for better cross talk performance */
669         regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
670                                 NAU8825_ADC_DIG_VOL_MASK, vol);
671         /* Disables JKTIP(HPL) DAC channel for right to left measurement.
672          * Do it before sending signal in order to erase pop noise.
673          */
674         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
675                 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
676                 NAU8825_BIAS_TESTDACL_EN);
677         switch (nau8825->xtalk_state) {
678         case NAU8825_XTALK_HPR_R2L:
679                 /* Enable right headphone impedance */
680                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
681                         NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
682                         NAU8825_BIAS_HPR_IMP);
683                 break;
684         case NAU8825_XTALK_HPL_R2L:
685                 /* Enable left headphone impedance */
686                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
687                         NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
688                         NAU8825_BIAS_HPL_IMP);
689                 break;
690         default:
691                 break;
692         }
693         msleep(100);
694         /* Impedance measurement mode enable */
695         regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
696                                 NAU8825_IMM_EN, NAU8825_IMM_EN);
697 }
698 
699 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
700 {
701         /* Impedance measurement mode disable */
702         regmap_update_bits(nau8825->regmap,
703                 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
704 }
705 
706 /* The cross talk measurement function can reduce cross talk across the
707  * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
708  * level to determine what cross talk reduction gain is. This system works by
709  * sending a 23Hz -24dBV sine wave into the headset output DAC and through
710  * the PGA. The output of the PGA is then connected to an internal current
711  * sense which measures the attenuated 23Hz signal and passing the output to
712  * an ADC which converts the measurement to a binary code. With two separated
713  * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
714  * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
715  * Thus, the measurement function has four states to complete whole sequence.
716  * 1. Prepare state : Prepare the resource for detection and transfer to HPR
717  *     IMM stat to make JKR1(HPR) impedance measure.
718  * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
719  *     to HPL IMM state to make JKTIP(HPL) impedance measure.
720  * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
721  *     transfer to IMM state to determine suppression sidetone gain.
722  * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
723  *     and cross talk signal level. Apply this gain and then restore codec
724  *     configuration. Then transfer to Done state for ending.
725  */
726 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
727 {
728         u32 sidetone;
729 
730         switch (nau8825->xtalk_state) {
731         case NAU8825_XTALK_PREPARE:
732                 /* In prepare state, set up clock, intrruption, DAC path, ADC
733                  * path and cross talk detection parameters for preparation.
734                  */
735                 nau8825_xtalk_prepare(nau8825);
736                 msleep(280);
737                 /* Trigger right headphone impedance detection */
738                 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
739                 nau8825_xtalk_imm_start(nau8825, 0x00d2);
740                 break;
741         case NAU8825_XTALK_HPR_R2L:
742                 /* In right headphone IMM state, read out right headphone
743                  * impedance measure result, and then start up left side.
744                  */
745                 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
746                         &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
747                 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
748                         nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
749                 /* Disable then re-enable IMM mode to update */
750                 nau8825_xtalk_imm_stop(nau8825);
751                 /* Trigger left headphone impedance detection */
752                 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
753                 nau8825_xtalk_imm_start(nau8825, 0x00ff);
754                 break;
755         case NAU8825_XTALK_HPL_R2L:
756                 /* In left headphone IMM state, read out left headphone
757                  * impedance measure result, and delay some time to wait
758                  * detection sine wave output finish. Then, we can calculate
759                  * the cross talk suppresstion side tone according to the L/R
760                  * headphone imedance.
761                  */
762                 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
763                         &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
764                 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
765                         nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
766                 nau8825_xtalk_imm_stop(nau8825);
767                 msleep(150);
768                 nau8825->xtalk_state = NAU8825_XTALK_IMM;
769                 break;
770         case NAU8825_XTALK_IMM:
771                 /* In impedance measure state, the orignal and cross talk
772                  * signal level vlues are ready. The side tone gain is deter-
773                  * mined with these signal level. After all, restore codec
774                  * configuration.
775                  */
776                 sidetone = nau8825_xtalk_sidetone(
777                         nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
778                         nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
779                 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
780                 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
781                                         (sidetone << 8) | sidetone);
782                 nau8825_xtalk_clean(nau8825);
783                 nau8825->xtalk_state = NAU8825_XTALK_DONE;
784                 break;
785         default:
786                 break;
787         }
788 }
789 
790 static void nau8825_xtalk_work(struct work_struct *work)
791 {
792         struct nau8825 *nau8825 = container_of(
793                 work, struct nau8825, xtalk_work);
794 
795         nau8825_xtalk_measure(nau8825);
796         /* To determine the cross talk side tone gain when reach
797          * the impedance measure state.
798          */
799         if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
800                 nau8825_xtalk_measure(nau8825);
801 
802         /* Delay jack report until cross talk detection process
803          * completed. It can avoid application to do playback
804          * preparation before cross talk detection is still working.
805          * Meanwhile, the protection of the cross talk detection
806          * is released.
807          */
808         if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
809                 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
810                                 nau8825->xtalk_event_mask);
811                 nau8825_sema_release(nau8825);
812                 nau8825->xtalk_protect = false;
813         }
814 }
815 
816 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
817 {
818         /* If the xtalk_protect is true, that means the process is still
819          * on going. The driver forces to cancel the cross talk task and
820          * restores the configuration to original status.
821          */
822         if (nau8825->xtalk_protect) {
823                 cancel_work_sync(&nau8825->xtalk_work);
824                 nau8825_xtalk_clean(nau8825);
825         }
826         /* Reset parameters for cross talk suppression function */
827         nau8825_sema_reset(nau8825);
828         nau8825->xtalk_state = NAU8825_XTALK_DONE;
829         nau8825->xtalk_protect = false;
830 }
831 
832 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
833 {
834         switch (reg) {
835         case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
836         case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
837         case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
838         case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
839         case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
840         case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
841         case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
842         case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
843         case NAU8825_REG_MISC_CTRL:
844         case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
845         case NAU8825_REG_BIAS_ADJ:
846         case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
847         case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
848         case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
849         case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
850                 return true;
851         default:
852                 return false;
853         }
854 
855 }
856 
857 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
858 {
859         switch (reg) {
860         case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
861         case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
862         case NAU8825_REG_INTERRUPT_MASK:
863         case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
864         case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
865         case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
866         case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
867         case NAU8825_REG_IMM_MODE_CTRL:
868         case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
869         case NAU8825_REG_MISC_CTRL:
870         case NAU8825_REG_BIAS_ADJ:
871         case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
872         case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
873         case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
874         case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
875                 return true;
876         default:
877                 return false;
878         }
879 }
880 
881 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
882 {
883         switch (reg) {
884         case NAU8825_REG_RESET:
885         case NAU8825_REG_IRQ_STATUS:
886         case NAU8825_REG_INT_CLR_KEY_STATUS:
887         case NAU8825_REG_IMM_RMS_L:
888         case NAU8825_REG_IMM_RMS_R:
889         case NAU8825_REG_I2C_DEVICE_ID:
890         case NAU8825_REG_SARDOUT_RAM_STATUS:
891         case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
892         case NAU8825_REG_GENERAL_STATUS:
893         case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
894                 return true;
895         default:
896                 return false;
897         }
898 }
899 
900 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
901                 struct snd_kcontrol *kcontrol, int event)
902 {
903         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
904         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
905 
906         switch (event) {
907         case SND_SOC_DAPM_POST_PMU:
908                 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
909                         NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
910                 break;
911         case SND_SOC_DAPM_POST_PMD:
912                 if (!nau8825->irq)
913                         regmap_update_bits(nau8825->regmap,
914                                 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
915                 break;
916         default:
917                 return -EINVAL;
918         }
919 
920         return 0;
921 }
922 
923 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
924         struct snd_kcontrol *kcontrol, int event)
925 {
926         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
927         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
928 
929         switch (event) {
930         case SND_SOC_DAPM_POST_PMU:
931                 /* Prevent startup click by letting charge pump to ramp up */
932                 msleep(10);
933                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
934                         NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
935                 break;
936         case SND_SOC_DAPM_PRE_PMD:
937                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
938                         NAU8825_JAMNODCLOW, 0);
939                 break;
940         default:
941                 return -EINVAL;
942         }
943 
944         return 0;
945 }
946 
947 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
948         struct snd_kcontrol *kcontrol, int event)
949 {
950         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
951         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
952 
953         switch (event) {
954         case SND_SOC_DAPM_PRE_PMU:
955                 /* Disables the TESTDAC to let DAC signal pass through. */
956                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
957                         NAU8825_BIAS_TESTDAC_EN, 0);
958                 break;
959         case SND_SOC_DAPM_POST_PMD:
960                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
961                         NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
962                 break;
963         default:
964                 return -EINVAL;
965         }
966 
967         return 0;
968 }
969 
970 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
971                                      struct snd_ctl_elem_value *ucontrol)
972 {
973         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
974         struct soc_bytes_ext *params = (void *)kcontrol->private_value;
975 
976         if (!component->regmap)
977                 return -EINVAL;
978 
979         regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
980                 ucontrol->value.bytes.data, params->max);
981         return 0;
982 }
983 
984 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
985                                      struct snd_ctl_elem_value *ucontrol)
986 {
987         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
988         struct soc_bytes_ext *params = (void *)kcontrol->private_value;
989         void *data;
990 
991         if (!component->regmap)
992                 return -EINVAL;
993 
994         data = kmemdup(ucontrol->value.bytes.data,
995                 params->max, GFP_KERNEL | GFP_DMA);
996         if (!data)
997                 return -ENOMEM;
998 
999         regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1000                 NAU8825_BIQ_WRT_EN, 0);
1001         regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1002                 data, params->max);
1003         regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1004                 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1005 
1006         kfree(data);
1007         return 0;
1008 }
1009 
1010 static const char * const nau8825_biq_path[] = {
1011         "ADC", "DAC"
1012 };
1013 
1014 static const struct soc_enum nau8825_biq_path_enum =
1015         SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1016                 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1017 
1018 static const char * const nau8825_adc_decimation[] = {
1019         "32", "64", "128", "256"
1020 };
1021 
1022 static const struct soc_enum nau8825_adc_decimation_enum =
1023         SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1024                 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1025 
1026 static const char * const nau8825_dac_oversampl[] = {
1027         "64", "256", "128", "", "32"
1028 };
1029 
1030 static const struct soc_enum nau8825_dac_oversampl_enum =
1031         SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1032                 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1033 
1034 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1035 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1036 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1037 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1038 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1039 
1040 static const struct snd_kcontrol_new nau8825_controls[] = {
1041         SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1042                 0, 0xff, 0, adc_vol_tlv),
1043         SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1044                 12, 8, 0x0f, 0, sidetone_vol_tlv),
1045         SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1046                 6, 0, 0x3f, 1, dac_vol_tlv),
1047         SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1048                 8, 37, 0, fepga_gain_tlv),
1049         SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1050                 0, 8, 0xff, 0, crosstalk_vol_tlv),
1051 
1052         SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1053         SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1054         /* programmable biquad filter */
1055         SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1056         SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1057                   nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1058 };
1059 
1060 /* DAC Mux 0x33[9] and 0x34[9] */
1061 static const char * const nau8825_dac_src[] = {
1062         "DACL", "DACR",
1063 };
1064 
1065 static SOC_ENUM_SINGLE_DECL(
1066         nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1067         NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1068 
1069 static SOC_ENUM_SINGLE_DECL(
1070         nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1071         NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1072 
1073 static const struct snd_kcontrol_new nau8825_dacl_mux =
1074         SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1075 
1076 static const struct snd_kcontrol_new nau8825_dacr_mux =
1077         SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1078 
1079 
1080 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1081         SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1082                 15, 1),
1083 
1084         SND_SOC_DAPM_INPUT("MIC"),
1085         SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1086 
1087         SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1088                 NULL, 0),
1089 
1090         SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1091                 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1092                 SND_SOC_DAPM_POST_PMD),
1093         SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1094         SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1095                 0),
1096 
1097         /* ADC for button press detection. A dapm supply widget is used to
1098          * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1099          * during suspend.
1100          */
1101         SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1102                 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1103 
1104         SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1105         SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1106         SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1107         SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1108 
1109         SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1110                 NAU8825_ENABLE_DACR_SFT, 0),
1111         SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1112                 NAU8825_ENABLE_DACL_SFT, 0),
1113         SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1114 
1115         SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1116         SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1117 
1118         SND_SOC_DAPM_PGA_S("HP amp L", 0,
1119                 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1120         SND_SOC_DAPM_PGA_S("HP amp R", 0,
1121                 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1122 
1123         SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1124                 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1125                 SND_SOC_DAPM_PRE_PMD),
1126 
1127         SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1128                 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1129         SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1130                 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1131         SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1132                 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1133         SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1134                 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1135         SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1136                 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1137         SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1138                 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1139 
1140         SND_SOC_DAPM_PGA_S("Output DACL", 7,
1141                 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1142                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1143         SND_SOC_DAPM_PGA_S("Output DACR", 7,
1144                 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1145                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1146 
1147         /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1148         SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1149                 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1150         SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1151                 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1152 
1153         /* High current HPOL/R boost driver */
1154         SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1155                 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1156 
1157         /* Class G operation control*/
1158         SND_SOC_DAPM_PGA_S("Class G", 10,
1159                 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1160 
1161         SND_SOC_DAPM_OUTPUT("HPOL"),
1162         SND_SOC_DAPM_OUTPUT("HPOR"),
1163 };
1164 
1165 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1166         {"Frontend PGA", NULL, "MIC"},
1167         {"ADC", NULL, "Frontend PGA"},
1168         {"ADC", NULL, "ADC Clock"},
1169         {"ADC", NULL, "ADC Power"},
1170         {"AIFTX", NULL, "ADC"},
1171 
1172         {"DDACL", NULL, "Playback"},
1173         {"DDACR", NULL, "Playback"},
1174         {"DDACL", NULL, "DDAC Clock"},
1175         {"DDACR", NULL, "DDAC Clock"},
1176         {"DACL Mux", "DACL", "DDACL"},
1177         {"DACL Mux", "DACR", "DDACR"},
1178         {"DACR Mux", "DACL", "DDACL"},
1179         {"DACR Mux", "DACR", "DDACR"},
1180         {"HP amp L", NULL, "DACL Mux"},
1181         {"HP amp R", NULL, "DACR Mux"},
1182         {"Charge Pump", NULL, "HP amp L"},
1183         {"Charge Pump", NULL, "HP amp R"},
1184         {"ADACL", NULL, "Charge Pump"},
1185         {"ADACR", NULL, "Charge Pump"},
1186         {"ADACL Clock", NULL, "ADACL"},
1187         {"ADACR Clock", NULL, "ADACR"},
1188         {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1189         {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1190         {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1191         {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1192         {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1193         {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1194         {"Output DACL", NULL, "Output Driver L Stage 3"},
1195         {"Output DACR", NULL, "Output Driver R Stage 3"},
1196         {"HPOL Pulldown", NULL, "Output DACL"},
1197         {"HPOR Pulldown", NULL, "Output DACR"},
1198         {"HP Boost Driver", NULL, "HPOL Pulldown"},
1199         {"HP Boost Driver", NULL, "HPOR Pulldown"},
1200         {"Class G", NULL, "HP Boost Driver"},
1201         {"HPOL", NULL, "Class G"},
1202         {"HPOR", NULL, "Class G"},
1203 };
1204 
1205 static int nau8825_clock_check(struct nau8825 *nau8825,
1206         int stream, int rate, int osr)
1207 {
1208         int osrate;
1209 
1210         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1211                 if (osr >= ARRAY_SIZE(osr_dac_sel))
1212                         return -EINVAL;
1213                 osrate = osr_dac_sel[osr].osr;
1214         } else {
1215                 if (osr >= ARRAY_SIZE(osr_adc_sel))
1216                         return -EINVAL;
1217                 osrate = osr_adc_sel[osr].osr;
1218         }
1219 
1220         if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1221                 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1222                 return -EINVAL;
1223         }
1224 
1225         return 0;
1226 }
1227 
1228 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1229                                 struct snd_pcm_hw_params *params,
1230                                 struct snd_soc_dai *dai)
1231 {
1232         struct snd_soc_codec *codec = dai->codec;
1233         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1234         unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1235 
1236         nau8825_sema_acquire(nau8825, 3 * HZ);
1237 
1238         /* CLK_DAC or CLK_ADC = OSR * FS
1239          * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1240          * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1241          * values must be selected such that the maximum frequency is less
1242          * than 6.144 MHz.
1243          */
1244         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1245                 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
1246                 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1247                 if (nau8825_clock_check(nau8825, substream->stream,
1248                         params_rate(params), osr))
1249                         return -EINVAL;
1250                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1251                         NAU8825_CLK_DAC_SRC_MASK,
1252                         osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
1253         } else {
1254                 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
1255                 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1256                 if (nau8825_clock_check(nau8825, substream->stream,
1257                         params_rate(params), osr))
1258                         return -EINVAL;
1259                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1260                         NAU8825_CLK_ADC_SRC_MASK,
1261                         osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
1262         }
1263 
1264         /* make BCLK and LRC divde configuration if the codec as master. */
1265         regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1266         if (ctrl_val & NAU8825_I2S_MS_MASTER) {
1267                 /* get the bclk and fs ratio */
1268                 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
1269                 if (bclk_fs <= 32)
1270                         bclk_div = 2;
1271                 else if (bclk_fs <= 64)
1272                         bclk_div = 1;
1273                 else if (bclk_fs <= 128)
1274                         bclk_div = 0;
1275                 else
1276                         return -EINVAL;
1277                 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1278                         NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
1279                         ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
1280         }
1281 
1282         switch (params_width(params)) {
1283         case 16:
1284                 val_len |= NAU8825_I2S_DL_16;
1285                 break;
1286         case 20:
1287                 val_len |= NAU8825_I2S_DL_20;
1288                 break;
1289         case 24:
1290                 val_len |= NAU8825_I2S_DL_24;
1291                 break;
1292         case 32:
1293                 val_len |= NAU8825_I2S_DL_32;
1294                 break;
1295         default:
1296                 return -EINVAL;
1297         }
1298 
1299         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1300                 NAU8825_I2S_DL_MASK, val_len);
1301 
1302         /* Release the semaphone. */
1303         nau8825_sema_release(nau8825);
1304 
1305         return 0;
1306 }
1307 
1308 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1309 {
1310         struct snd_soc_codec *codec = codec_dai->codec;
1311         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1312         unsigned int ctrl1_val = 0, ctrl2_val = 0;
1313 
1314         nau8825_sema_acquire(nau8825, 3 * HZ);
1315 
1316         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1317         case SND_SOC_DAIFMT_CBM_CFM:
1318                 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1319                 break;
1320         case SND_SOC_DAIFMT_CBS_CFS:
1321                 break;
1322         default:
1323                 return -EINVAL;
1324         }
1325 
1326         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1327         case SND_SOC_DAIFMT_NB_NF:
1328                 break;
1329         case SND_SOC_DAIFMT_IB_NF:
1330                 ctrl1_val |= NAU8825_I2S_BP_INV;
1331                 break;
1332         default:
1333                 return -EINVAL;
1334         }
1335 
1336         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1337         case SND_SOC_DAIFMT_I2S:
1338                 ctrl1_val |= NAU8825_I2S_DF_I2S;
1339                 break;
1340         case SND_SOC_DAIFMT_LEFT_J:
1341                 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1342                 break;
1343         case SND_SOC_DAIFMT_RIGHT_J:
1344                 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1345                 break;
1346         case SND_SOC_DAIFMT_DSP_A:
1347                 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1348                 break;
1349         case SND_SOC_DAIFMT_DSP_B:
1350                 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1351                 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1352                 break;
1353         default:
1354                 return -EINVAL;
1355         }
1356 
1357         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1358                 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1359                 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1360                 ctrl1_val);
1361         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1362                 NAU8825_I2S_MS_MASK, ctrl2_val);
1363 
1364         /* Release the semaphone. */
1365         nau8825_sema_release(nau8825);
1366 
1367         return 0;
1368 }
1369 
1370 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1371         .hw_params      = nau8825_hw_params,
1372         .set_fmt        = nau8825_set_dai_fmt,
1373 };
1374 
1375 #define NAU8825_RATES   SNDRV_PCM_RATE_8000_192000
1376 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1377                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1378 
1379 static struct snd_soc_dai_driver nau8825_dai = {
1380         .name = "nau8825-hifi",
1381         .playback = {
1382                 .stream_name     = "Playback",
1383                 .channels_min    = 1,
1384                 .channels_max    = 2,
1385                 .rates           = NAU8825_RATES,
1386                 .formats         = NAU8825_FORMATS,
1387         },
1388         .capture = {
1389                 .stream_name     = "Capture",
1390                 .channels_min    = 1,
1391                 .channels_max    = 1,
1392                 .rates           = NAU8825_RATES,
1393                 .formats         = NAU8825_FORMATS,
1394         },
1395         .ops = &nau8825_dai_ops,
1396 };
1397 
1398 /**
1399  * nau8825_enable_jack_detect - Specify a jack for event reporting
1400  *
1401  * @component:  component to register the jack with
1402  * @jack: jack to use to report headset and button events on
1403  *
1404  * After this function has been called the headset insert/remove and button
1405  * events will be routed to the given jack.  Jack can be null to stop
1406  * reporting.
1407  */
1408 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1409                                 struct snd_soc_jack *jack)
1410 {
1411         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1412         struct regmap *regmap = nau8825->regmap;
1413 
1414         nau8825->jack = jack;
1415 
1416         /* Ground HP Outputs[1:0], needed for headset auto detection
1417          * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1418          */
1419         regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1420                 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1421                 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1422 
1423         return 0;
1424 }
1425 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1426 
1427 
1428 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1429 {
1430         bool active_high, is_high;
1431         int status, jkdet;
1432 
1433         regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1434         active_high = jkdet & NAU8825_JACK_POLARITY;
1435         regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1436         is_high = status & NAU8825_GPIO2JD1;
1437         /* return jack connection status according to jack insertion logic
1438          * active high or active low.
1439          */
1440         return active_high == is_high;
1441 }
1442 
1443 static void nau8825_restart_jack_detection(struct regmap *regmap)
1444 {
1445         /* this will restart the entire jack detection process including MIC/GND
1446          * switching and create interrupts. We have to go from 0 to 1 and back
1447          * to 0 to restart.
1448          */
1449         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1450                 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1451         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1452                 NAU8825_JACK_DET_RESTART, 0);
1453 }
1454 
1455 static void nau8825_int_status_clear_all(struct regmap *regmap)
1456 {
1457         int active_irq, clear_irq, i;
1458 
1459         /* Reset the intrruption status from rightmost bit if the corres-
1460          * ponding irq event occurs.
1461          */
1462         regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1463         for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1464                 clear_irq = (0x1 << i);
1465                 if (active_irq & clear_irq)
1466                         regmap_write(regmap,
1467                                 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1468         }
1469 }
1470 
1471 static void nau8825_eject_jack(struct nau8825 *nau8825)
1472 {
1473         struct snd_soc_dapm_context *dapm = nau8825->dapm;
1474         struct regmap *regmap = nau8825->regmap;
1475 
1476         /* Force to cancel the cross talk detection process */
1477         nau8825_xtalk_cancel(nau8825);
1478 
1479         snd_soc_dapm_disable_pin(dapm, "SAR");
1480         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1481         /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1482         regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1483                 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1484         /* ground HPL/HPR, MICGRND1/2 */
1485         regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1486 
1487         snd_soc_dapm_sync(dapm);
1488 
1489         /* Clear all interruption status */
1490         nau8825_int_status_clear_all(regmap);
1491 
1492         /* Enable the insertion interruption, disable the ejection inter-
1493          * ruption, and then bypass de-bounce circuit.
1494          */
1495         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1496                 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1497                 NAU8825_IRQ_EJECT_DIS);
1498         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1499                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1500                 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1501                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1502                 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1503         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1504                 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1505 
1506         /* Disable ADC needed for interruptions at audo mode */
1507         regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1508                 NAU8825_ENABLE_ADC, 0);
1509 
1510         /* Close clock for jack type detection at manual mode */
1511         nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1512 }
1513 
1514 /* Enable audo mode interruptions with internal clock. */
1515 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1516 {
1517         struct regmap *regmap = nau8825->regmap;
1518 
1519         /* Enable headset jack type detection complete interruption and
1520          * jack ejection interruption.
1521          */
1522         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1523                 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1524 
1525         /* Enable internal VCO needed for interruptions */
1526         nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1527 
1528         /* Enable ADC needed for interruptions */
1529         regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1530                 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1531 
1532         /* Chip needs one FSCLK cycle in order to generate interruptions,
1533          * as we cannot guarantee one will be provided by the system. Turning
1534          * master mode on then off enables us to generate that FSCLK cycle
1535          * with a minimum of contention on the clock bus.
1536          */
1537         regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1538                 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1539         regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1540                 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1541 
1542         /* Not bypass de-bounce circuit */
1543         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1544                 NAU8825_JACK_DET_DB_BYPASS, 0);
1545 
1546         /* Unmask all interruptions */
1547         regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1548 
1549         /* Restart the jack detection process at auto mode */
1550         nau8825_restart_jack_detection(regmap);
1551 }
1552 
1553 static int nau8825_button_decode(int value)
1554 {
1555         int buttons = 0;
1556 
1557         /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1558         if (value & BIT(0))
1559                 buttons |= SND_JACK_BTN_0;
1560         if (value & BIT(1))
1561                 buttons |= SND_JACK_BTN_1;
1562         if (value & BIT(2))
1563                 buttons |= SND_JACK_BTN_2;
1564         if (value & BIT(3))
1565                 buttons |= SND_JACK_BTN_3;
1566         if (value & BIT(4))
1567                 buttons |= SND_JACK_BTN_4;
1568         if (value & BIT(5))
1569                 buttons |= SND_JACK_BTN_5;
1570 
1571         return buttons;
1572 }
1573 
1574 static int nau8825_jack_insert(struct nau8825 *nau8825)
1575 {
1576         struct regmap *regmap = nau8825->regmap;
1577         struct snd_soc_dapm_context *dapm = nau8825->dapm;
1578         int jack_status_reg, mic_detected;
1579         int type = 0;
1580 
1581         regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1582         mic_detected = (jack_status_reg >> 10) & 3;
1583         /* The JKSLV and JKR2 all detected in high impedance headset */
1584         if (mic_detected == 0x3)
1585                 nau8825->high_imped = true;
1586         else
1587                 nau8825->high_imped = false;
1588 
1589         switch (mic_detected) {
1590         case 0:
1591                 /* no mic */
1592                 type = SND_JACK_HEADPHONE;
1593                 break;
1594         case 1:
1595                 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1596                 type = SND_JACK_HEADSET;
1597 
1598                 /* Unground MICGND1 */
1599                 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1600                         1 << 2);
1601                 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1602                 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1603                         NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1604                         NAU8825_MICBIAS_JKR2);
1605                 /* Attach SARADC to MICGND1 */
1606                 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1607                         NAU8825_SAR_INPUT_MASK,
1608                         NAU8825_SAR_INPUT_JKR2);
1609 
1610                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1611                 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1612                 snd_soc_dapm_sync(dapm);
1613                 break;
1614         case 2:
1615         case 3:
1616                 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1617                 type = SND_JACK_HEADSET;
1618 
1619                 /* Unground MICGND2 */
1620                 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1621                         2 << 2);
1622                 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1623                 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1624                         NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1625                         NAU8825_MICBIAS_JKSLV);
1626                 /* Attach SARADC to MICGND2 */
1627                 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1628                         NAU8825_SAR_INPUT_MASK,
1629                         NAU8825_SAR_INPUT_JKSLV);
1630 
1631                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1632                 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1633                 snd_soc_dapm_sync(dapm);
1634                 break;
1635         }
1636 
1637         /* Leaving HPOL/R grounded after jack insert by default. They will be
1638          * ungrounded as part of the widget power up sequence at the beginning
1639          * of playback to reduce pop.
1640          */
1641         return type;
1642 }
1643 
1644 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1645                 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1646 
1647 static irqreturn_t nau8825_interrupt(int irq, void *data)
1648 {
1649         struct nau8825 *nau8825 = (struct nau8825 *)data;
1650         struct regmap *regmap = nau8825->regmap;
1651         int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1652 
1653         if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1654                 dev_err(nau8825->dev, "failed to read irq status\n");
1655                 return IRQ_NONE;
1656         }
1657 
1658         if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1659                 NAU8825_JACK_EJECTION_DETECTED) {
1660 
1661                 nau8825_eject_jack(nau8825);
1662                 event_mask |= SND_JACK_HEADSET;
1663                 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1664         } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1665                 int key_status;
1666 
1667                 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1668                         &key_status);
1669 
1670                 /* upper 8 bits of the register are for short pressed keys,
1671                  * lower 8 bits - for long pressed buttons
1672                  */
1673                 nau8825->button_pressed = nau8825_button_decode(
1674                         key_status >> 8);
1675 
1676                 event |= nau8825->button_pressed;
1677                 event_mask |= NAU8825_BUTTONS;
1678                 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1679         } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1680                 event_mask = NAU8825_BUTTONS;
1681                 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1682         } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1683                 if (nau8825_is_jack_inserted(regmap)) {
1684                         event |= nau8825_jack_insert(nau8825);
1685                         if (!nau8825->high_imped) {
1686                                 /* Apply the cross talk suppression in the
1687                                  * headset without high impedance.
1688                                  */
1689                                 if (!nau8825->xtalk_protect) {
1690                                         /* Raise protection for cross talk de-
1691                                          * tection if no protection before.
1692                                          * The driver has to cancel the pro-
1693                                          * cess and restore changes if process
1694                                          * is ongoing when ejection.
1695                                          */
1696                                         int ret;
1697                                         nau8825->xtalk_protect = true;
1698                                         ret = nau8825_sema_acquire(nau8825, 0);
1699                                         if (ret < 0)
1700                                                 nau8825->xtalk_protect = false;
1701                                 }
1702                                 /* Startup cross talk detection process */
1703                                 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1704                                 schedule_work(&nau8825->xtalk_work);
1705                         } else {
1706                                 /* The cross talk suppression shouldn't apply
1707                                  * in the headset with high impedance. Thus,
1708                                  * relieve the protection raised before.
1709                                  */
1710                                 if (nau8825->xtalk_protect) {
1711                                         nau8825_sema_release(nau8825);
1712                                         nau8825->xtalk_protect = false;
1713                                 }
1714                         }
1715                 } else {
1716                         dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1717                         nau8825_eject_jack(nau8825);
1718                 }
1719 
1720                 event_mask |= SND_JACK_HEADSET;
1721                 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1722                 /* Record the interruption report event for driver to report
1723                  * the event later. The jack report will delay until cross
1724                  * talk detection process is done.
1725                  */
1726                 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1727                         nau8825->xtalk_event = event;
1728                         nau8825->xtalk_event_mask = event_mask;
1729                 }
1730         } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1731                 schedule_work(&nau8825->xtalk_work);
1732                 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1733         } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1734                 NAU8825_JACK_INSERTION_DETECTED) {
1735                 /* One more step to check GPIO status directly. Thus, the
1736                  * driver can confirm the real insertion interruption because
1737                  * the intrruption at manual mode has bypassed debounce
1738                  * circuit which can get rid of unstable status.
1739                  */
1740                 if (nau8825_is_jack_inserted(regmap)) {
1741                         /* Turn off insertion interruption at manual mode */
1742                         regmap_update_bits(regmap,
1743                                 NAU8825_REG_INTERRUPT_DIS_CTRL,
1744                                 NAU8825_IRQ_INSERT_DIS,
1745                                 NAU8825_IRQ_INSERT_DIS);
1746                         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1747                                 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1748                         /* Enable interruption for jack type detection at audo
1749                          * mode which can detect microphone and jack type.
1750                          */
1751                         nau8825_setup_auto_irq(nau8825);
1752                 }
1753         }
1754 
1755         if (!clear_irq)
1756                 clear_irq = active_irq;
1757         /* clears the rightmost interruption */
1758         regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1759 
1760         /* Delay jack report until cross talk detection is done. It can avoid
1761          * application to do playback preparation when cross talk detection
1762          * process is still working. Otherwise, the resource like clock and
1763          * power will be issued by them at the same time and conflict happens.
1764          */
1765         if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1766                 snd_soc_jack_report(nau8825->jack, event, event_mask);
1767 
1768         return IRQ_HANDLED;
1769 }
1770 
1771 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1772 {
1773         struct regmap *regmap = nau8825->regmap;
1774 
1775         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1776                 NAU8825_SAR_TRACKING_GAIN_MASK,
1777                 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1778         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1779                 NAU8825_SAR_COMPARE_TIME_MASK,
1780                 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1781         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1782                 NAU8825_SAR_SAMPLING_TIME_MASK,
1783                 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1784 
1785         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1786                 NAU8825_KEYDET_LEVELS_NR_MASK,
1787                 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1788         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1789                 NAU8825_KEYDET_HYSTERESIS_MASK,
1790                 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1791         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1792                 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1793                 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1794 
1795         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1796                 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1797         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1798                 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1799         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1800                 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1801         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1802                 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1803 
1804         /* Enable short press and release interruptions */
1805         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1806                 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1807                 0);
1808 }
1809 
1810 static void nau8825_init_regs(struct nau8825 *nau8825)
1811 {
1812         struct regmap *regmap = nau8825->regmap;
1813 
1814         /* Latch IIC LSB value */
1815         regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1816         /* Enable Bias/Vmid */
1817         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1818                 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1819         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1820                 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1821 
1822         /* VMID Tieoff */
1823         regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1824                 NAU8825_BIAS_VMID_SEL_MASK,
1825                 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1826         /* Disable Boost Driver, Automatic Short circuit protection enable */
1827         regmap_update_bits(regmap, NAU8825_REG_BOOST,
1828                 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1829                 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1830                 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1831                 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1832 
1833         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1834                 NAU8825_JKDET_OUTPUT_EN,
1835                 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1836         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1837                 NAU8825_JKDET_PULL_EN,
1838                 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1839         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1840                 NAU8825_JKDET_PULL_UP,
1841                 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1842         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1843                 NAU8825_JACK_POLARITY,
1844                 /* jkdet_polarity - 1  is for active-low */
1845                 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1846 
1847         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1848                 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1849                 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1850         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1851                 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1852                 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1853 
1854         /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1855         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1856 
1857         regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1858                 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1859 
1860         if (nau8825->sar_threshold_num)
1861                 nau8825_setup_buttons(nau8825);
1862 
1863         /* Default oversampling/decimations settings are unusable
1864          * (audible hiss). Set it to something better.
1865          */
1866         regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1867                 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
1868                 NAU8825_ADC_SYNC_DOWN_64);
1869         regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1870                 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
1871         /* Disable DACR/L power */
1872         regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1873                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1874                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1875         /* Enable TESTDAC. This sets the analog DAC inputs to a '' input
1876          * signal to avoid any glitches due to power up transients in both
1877          * the analog and digital DAC circuit.
1878          */
1879         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1880                 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1881         /* CICCLP off */
1882         regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1883                 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1884 
1885         /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1886         regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1887                 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1888                 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1889                 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1890                 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1891         /* Class G timer 64ms */
1892         regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1893                 NAU8825_CLASSG_TIMER_MASK,
1894                 0x20 << NAU8825_CLASSG_TIMER_SFT);
1895         /* DAC clock delay 2ns, VREF */
1896         regmap_update_bits(regmap, NAU8825_REG_RDAC,
1897                 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1898                 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1899                 (0x3 << NAU8825_RDAC_VREF_SFT));
1900         /* Config L/R channel */
1901         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1902                 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1903         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1904                 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1905         /* Disable short Frame Sync detection logic */
1906         regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
1907                 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
1908 }
1909 
1910 static const struct regmap_config nau8825_regmap_config = {
1911         .val_bits = NAU8825_REG_DATA_LEN,
1912         .reg_bits = NAU8825_REG_ADDR_LEN,
1913 
1914         .max_register = NAU8825_REG_MAX,
1915         .readable_reg = nau8825_readable_reg,
1916         .writeable_reg = nau8825_writeable_reg,
1917         .volatile_reg = nau8825_volatile_reg,
1918 
1919         .cache_type = REGCACHE_RBTREE,
1920         .reg_defaults = nau8825_reg_defaults,
1921         .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1922 };
1923 
1924 static int nau8825_codec_probe(struct snd_soc_codec *codec)
1925 {
1926         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1927         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1928 
1929         nau8825->dapm = dapm;
1930 
1931         return 0;
1932 }
1933 
1934 static int nau8825_codec_remove(struct snd_soc_codec *codec)
1935 {
1936         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1937 
1938         /* Cancel and reset cross tak suppresstion detection funciton */
1939         nau8825_xtalk_cancel(nau8825);
1940 
1941         return 0;
1942 }
1943 
1944 /**
1945  * nau8825_calc_fll_param - Calculate FLL parameters.
1946  * @fll_in: external clock provided to codec.
1947  * @fs: sampling rate.
1948  * @fll_param: Pointer to structure of FLL parameters.
1949  *
1950  * Calculate FLL parameters to configure codec.
1951  *
1952  * Returns 0 for success or negative error code.
1953  */
1954 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1955                 struct nau8825_fll *fll_param)
1956 {
1957         u64 fvco, fvco_max;
1958         unsigned int fref, i, fvco_sel;
1959 
1960         /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1961          * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1962          * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1963          */
1964         for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1965                 fref = fll_in / fll_pre_scalar[i].param;
1966                 if (fref <= NAU_FREF_MAX)
1967                         break;
1968         }
1969         if (i == ARRAY_SIZE(fll_pre_scalar))
1970                 return -EINVAL;
1971         fll_param->clk_ref_div = fll_pre_scalar[i].val;
1972 
1973         /* Choose the FLL ratio based on FREF */
1974         for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1975                 if (fref >= fll_ratio[i].param)
1976                         break;
1977         }
1978         if (i == ARRAY_SIZE(fll_ratio))
1979                 return -EINVAL;
1980         fll_param->ratio = fll_ratio[i].val;
1981 
1982         /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1983          * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1984          * guaranteed across the full range of operation.
1985          * FDCO = freq_out * 2 * mclk_src_scaling
1986          */
1987         fvco_max = 0;
1988         fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1989         for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1990                 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1991                 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1992                         fvco_max < fvco) {
1993                         fvco_max = fvco;
1994                         fvco_sel = i;
1995                 }
1996         }
1997         if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1998                 return -EINVAL;
1999         fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
2000 
2001         /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2002          * input based on FDCO, FREF and FLL ratio.
2003          */
2004         fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
2005         fll_param->fll_int = (fvco >> 16) & 0x3FF;
2006         fll_param->fll_frac = fvco & 0xFFFF;
2007         return 0;
2008 }
2009 
2010 static void nau8825_fll_apply(struct nau8825 *nau8825,
2011                 struct nau8825_fll *fll_param)
2012 {
2013         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2014                 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
2015                 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
2016         /* Make DSP operate at high speed for better performance. */
2017         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2018                 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2019                 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2020         /* FLL 16-bit fractional input */
2021         regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2022         /* FLL 10-bit integer input */
2023         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2024                         NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2025         /* FLL pre-scaler */
2026         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2027                         NAU8825_FLL_REF_DIV_MASK,
2028                         fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2029         /* select divided VCO input */
2030         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2031                 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2032         /* Disable free-running mode */
2033         regmap_update_bits(nau8825->regmap,
2034                 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2035         if (fll_param->fll_frac) {
2036                 /* set FLL loop filter enable and cutoff frequency at 500Khz */
2037                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2038                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2039                         NAU8825_FLL_FTR_SW_MASK,
2040                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2041                         NAU8825_FLL_FTR_SW_FILTER);
2042                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2043                         NAU8825_SDM_EN | NAU8825_CUTOFF500,
2044                         NAU8825_SDM_EN | NAU8825_CUTOFF500);
2045         } else {
2046                 /* disable FLL loop filter and cutoff frequency */
2047                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2048                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2049                         NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
2050                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2051                         NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
2052         }
2053 }
2054 
2055 /* freq_out must be 256*Fs in order to achieve the best performance */
2056 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
2057                 unsigned int freq_in, unsigned int freq_out)
2058 {
2059         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2060         struct nau8825_fll fll_param;
2061         int ret, fs;
2062 
2063         fs = freq_out / 256;
2064         ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2065         if (ret < 0) {
2066                 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
2067                 return ret;
2068         }
2069         dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2070                 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2071                 fll_param.fll_int, fll_param.clk_ref_div);
2072 
2073         nau8825_fll_apply(nau8825, &fll_param);
2074         mdelay(2);
2075         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2076                         NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2077         return 0;
2078 }
2079 
2080 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2081 {
2082         int ret = 0;
2083 
2084         nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2085         if (IS_ERR(nau8825->mclk)) {
2086                 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2087                 return 0;
2088         }
2089 
2090         if (!nau8825->mclk_freq) {
2091                 ret = clk_prepare_enable(nau8825->mclk);
2092                 if (ret) {
2093                         dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2094                         return ret;
2095                 }
2096         }
2097 
2098         if (nau8825->mclk_freq != freq) {
2099                 freq = clk_round_rate(nau8825->mclk, freq);
2100                 ret = clk_set_rate(nau8825->mclk, freq);
2101                 if (ret) {
2102                         dev_err(nau8825->dev, "Unable to set mclk rate\n");
2103                         return ret;
2104                 }
2105                 nau8825->mclk_freq = freq;
2106         }
2107 
2108         return 0;
2109 }
2110 
2111 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2112 {
2113         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2114                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2115         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2116                 NAU8825_DCO_EN, 0);
2117         /* Make DSP operate as default setting for power saving. */
2118         regmap_update_bits(regmap, NAU8825_REG_FLL1,
2119                 NAU8825_ICTRL_LATCH_MASK, 0);
2120 }
2121 
2122 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2123         unsigned int freq)
2124 {
2125         struct regmap *regmap = nau8825->regmap;
2126         int ret;
2127 
2128         switch (clk_id) {
2129         case NAU8825_CLK_DIS:
2130                 /* Clock provided externally and disable internal VCO clock */
2131                 nau8825_configure_mclk_as_sysclk(regmap);
2132                 if (nau8825->mclk_freq) {
2133                         clk_disable_unprepare(nau8825->mclk);
2134                         nau8825->mclk_freq = 0;
2135                 }
2136 
2137                 break;
2138         case NAU8825_CLK_MCLK:
2139                 /* Acquire the semaphone to synchronize the playback and
2140                  * interrupt handler. In order to avoid the playback inter-
2141                  * fered by cross talk process, the driver make the playback
2142                  * preparation halted until cross talk process finish.
2143                  */
2144                 nau8825_sema_acquire(nau8825, 3 * HZ);
2145                 nau8825_configure_mclk_as_sysclk(regmap);
2146                 /* MCLK not changed by clock tree */
2147                 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2148                         NAU8825_CLK_MCLK_SRC_MASK, 0);
2149                 /* Release the semaphone. */
2150                 nau8825_sema_release(nau8825);
2151 
2152                 ret = nau8825_mclk_prepare(nau8825, freq);
2153                 if (ret)
2154                         return ret;
2155 
2156                 break;
2157         case NAU8825_CLK_INTERNAL:
2158                 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2159                         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2160                                 NAU8825_DCO_EN, NAU8825_DCO_EN);
2161                         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2162                                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2163                         /* Decrease the VCO frequency and make DSP operate
2164                          * as default setting for power saving.
2165                          */
2166                         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2167                                 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2168                         regmap_update_bits(regmap, NAU8825_REG_FLL1,
2169                                 NAU8825_ICTRL_LATCH_MASK |
2170                                 NAU8825_FLL_RATIO_MASK, 0x10);
2171                         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2172                                 NAU8825_SDM_EN, NAU8825_SDM_EN);
2173                 } else {
2174                         /* The clock turns off intentionally for power saving
2175                          * when no headset connected.
2176                          */
2177                         nau8825_configure_mclk_as_sysclk(regmap);
2178                         dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2179                 }
2180                 if (nau8825->mclk_freq) {
2181                         clk_disable_unprepare(nau8825->mclk);
2182                         nau8825->mclk_freq = 0;
2183                 }
2184 
2185                 break;
2186         case NAU8825_CLK_FLL_MCLK:
2187                 /* Acquire the semaphone to synchronize the playback and
2188                  * interrupt handler. In order to avoid the playback inter-
2189                  * fered by cross talk process, the driver make the playback
2190                  * preparation halted until cross talk process finish.
2191                  */
2192                 nau8825_sema_acquire(nau8825, 3 * HZ);
2193                 /* Higher FLL reference input frequency can only set lower
2194                  * gain error, such as 0000 for input reference from MCLK
2195                  * 12.288Mhz.
2196                  */
2197                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2198                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2199                         NAU8825_FLL_CLK_SRC_MCLK | 0);
2200                 /* Release the semaphone. */
2201                 nau8825_sema_release(nau8825);
2202 
2203                 ret = nau8825_mclk_prepare(nau8825, freq);
2204                 if (ret)
2205                         return ret;
2206 
2207                 break;
2208         case NAU8825_CLK_FLL_BLK:
2209                 /* Acquire the semaphone to synchronize the playback and
2210                  * interrupt handler. In order to avoid the playback inter-
2211                  * fered by cross talk process, the driver make the playback
2212                  * preparation halted until cross talk process finish.
2213                  */
2214                 nau8825_sema_acquire(nau8825, 3 * HZ);
2215                 /* If FLL reference input is from low frequency source,
2216                  * higher error gain can apply such as 0xf which has
2217                  * the most sensitive gain error correction threshold,
2218                  * Therefore, FLL has the most accurate DCO to
2219                  * target frequency.
2220                  */
2221                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2222                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2223                         NAU8825_FLL_CLK_SRC_BLK |
2224                         (0xf << NAU8825_GAIN_ERR_SFT));
2225                 /* Release the semaphone. */
2226                 nau8825_sema_release(nau8825);
2227 
2228                 if (nau8825->mclk_freq) {
2229                         clk_disable_unprepare(nau8825->mclk);
2230                         nau8825->mclk_freq = 0;
2231                 }
2232 
2233                 break;
2234         case NAU8825_CLK_FLL_FS:
2235                 /* Acquire the semaphone to synchronize the playback and
2236                  * interrupt handler. In order to avoid the playback inter-
2237                  * fered by cross talk process, the driver make the playback
2238                  * preparation halted until cross talk process finish.
2239                  */
2240                 nau8825_sema_acquire(nau8825, 3 * HZ);
2241                 /* If FLL reference input is from low frequency source,
2242                  * higher error gain can apply such as 0xf which has
2243                  * the most sensitive gain error correction threshold,
2244                  * Therefore, FLL has the most accurate DCO to
2245                  * target frequency.
2246                  */
2247                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2248                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2249                         NAU8825_FLL_CLK_SRC_FS |
2250                         (0xf << NAU8825_GAIN_ERR_SFT));
2251                 /* Release the semaphone. */
2252                 nau8825_sema_release(nau8825);
2253 
2254                 if (nau8825->mclk_freq) {
2255                         clk_disable_unprepare(nau8825->mclk);
2256                         nau8825->mclk_freq = 0;
2257                 }
2258 
2259                 break;
2260         default:
2261                 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2262                 return -EINVAL;
2263         }
2264 
2265         dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2266                 clk_id);
2267         return 0;
2268 }
2269 
2270 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2271         int source, unsigned int freq, int dir)
2272 {
2273         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2274 
2275         return nau8825_configure_sysclk(nau8825, clk_id, freq);
2276 }
2277 
2278 static int nau8825_resume_setup(struct nau8825 *nau8825)
2279 {
2280         struct regmap *regmap = nau8825->regmap;
2281 
2282         /* Close clock when jack type detection at manual mode */
2283         nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2284 
2285         /* Clear all interruption status */
2286         nau8825_int_status_clear_all(regmap);
2287 
2288         /* Enable both insertion and ejection interruptions, and then
2289          * bypass de-bounce circuit.
2290          */
2291         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2292                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2293                 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2294                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2295         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2296                 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2297         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2298                 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2299 
2300         return 0;
2301 }
2302 
2303 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2304                                    enum snd_soc_bias_level level)
2305 {
2306         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2307         int ret;
2308 
2309         switch (level) {
2310         case SND_SOC_BIAS_ON:
2311                 break;
2312 
2313         case SND_SOC_BIAS_PREPARE:
2314                 break;
2315 
2316         case SND_SOC_BIAS_STANDBY:
2317                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2318                         if (nau8825->mclk_freq) {
2319                                 ret = clk_prepare_enable(nau8825->mclk);
2320                                 if (ret) {
2321                                         dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2322                                         return ret;
2323                                 }
2324                         }
2325                         /* Setup codec configuration after resume */
2326                         nau8825_resume_setup(nau8825);
2327                 }
2328                 break;
2329 
2330         case SND_SOC_BIAS_OFF:
2331                 /* Cancel and reset cross talk detection funciton */
2332                 nau8825_xtalk_cancel(nau8825);
2333                 /* Turn off all interruptions before system shutdown. Keep the
2334                  * interruption quiet before resume setup completes.
2335                  */
2336                 regmap_write(nau8825->regmap,
2337                         NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2338                 /* Disable ADC needed for interruptions at audo mode */
2339                 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2340                         NAU8825_ENABLE_ADC, 0);
2341                 if (nau8825->mclk_freq)
2342                         clk_disable_unprepare(nau8825->mclk);
2343                 break;
2344         }
2345         return 0;
2346 }
2347 
2348 static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2349 {
2350         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2351 
2352         disable_irq(nau8825->irq);
2353         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2354         regcache_cache_only(nau8825->regmap, true);
2355         regcache_mark_dirty(nau8825->regmap);
2356 
2357         return 0;
2358 }
2359 
2360 static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2361 {
2362         struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2363         int ret;
2364 
2365         regcache_cache_only(nau8825->regmap, false);
2366         regcache_sync(nau8825->regmap);
2367         nau8825->xtalk_protect = true;
2368         ret = nau8825_sema_acquire(nau8825, 0);
2369         if (ret < 0)
2370                 nau8825->xtalk_protect = false;
2371         enable_irq(nau8825->irq);
2372 
2373         return 0;
2374 }
2375 
2376 static struct snd_soc_codec_driver nau8825_codec_driver = {
2377         .probe = nau8825_codec_probe,
2378         .remove = nau8825_codec_remove,
2379         .set_sysclk = nau8825_set_sysclk,
2380         .set_pll = nau8825_set_pll,
2381         .set_bias_level = nau8825_set_bias_level,
2382         .suspend_bias_off = true,
2383         .suspend = nau8825_suspend,
2384         .resume = nau8825_resume,
2385 
2386         .component_driver = {
2387                 .controls               = nau8825_controls,
2388                 .num_controls           = ARRAY_SIZE(nau8825_controls),
2389                 .dapm_widgets           = nau8825_dapm_widgets,
2390                 .num_dapm_widgets       = ARRAY_SIZE(nau8825_dapm_widgets),
2391                 .dapm_routes            = nau8825_dapm_routes,
2392                 .num_dapm_routes        = ARRAY_SIZE(nau8825_dapm_routes),
2393         },
2394 };
2395 
2396 static void nau8825_reset_chip(struct regmap *regmap)
2397 {
2398         regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2399         regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2400 }
2401 
2402 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2403 {
2404         int i;
2405         struct device *dev = nau8825->dev;
2406 
2407         dev_dbg(dev, "jkdet-enable:         %d\n", nau8825->jkdet_enable);
2408         dev_dbg(dev, "jkdet-pull-enable:    %d\n", nau8825->jkdet_pull_enable);
2409         dev_dbg(dev, "jkdet-pull-up:        %d\n", nau8825->jkdet_pull_up);
2410         dev_dbg(dev, "jkdet-polarity:       %d\n", nau8825->jkdet_polarity);
2411         dev_dbg(dev, "micbias-voltage:      %d\n", nau8825->micbias_voltage);
2412         dev_dbg(dev, "vref-impedance:       %d\n", nau8825->vref_impedance);
2413 
2414         dev_dbg(dev, "sar-threshold-num:    %d\n", nau8825->sar_threshold_num);
2415         for (i = 0; i < nau8825->sar_threshold_num; i++)
2416                 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2417                                 nau8825->sar_threshold[i]);
2418 
2419         dev_dbg(dev, "sar-hysteresis:       %d\n", nau8825->sar_hysteresis);
2420         dev_dbg(dev, "sar-voltage:          %d\n", nau8825->sar_voltage);
2421         dev_dbg(dev, "sar-compare-time:     %d\n", nau8825->sar_compare_time);
2422         dev_dbg(dev, "sar-sampling-time:    %d\n", nau8825->sar_sampling_time);
2423         dev_dbg(dev, "short-key-debounce:   %d\n", nau8825->key_debounce);
2424         dev_dbg(dev, "jack-insert-debounce: %d\n",
2425                         nau8825->jack_insert_debounce);
2426         dev_dbg(dev, "jack-eject-debounce:  %d\n",
2427                         nau8825->jack_eject_debounce);
2428 }
2429 
2430 static int nau8825_read_device_properties(struct device *dev,
2431         struct nau8825 *nau8825) {
2432 
2433         nau8825->jkdet_enable = device_property_read_bool(dev,
2434                 "nuvoton,jkdet-enable");
2435         nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2436                 "nuvoton,jkdet-pull-enable");
2437         nau8825->jkdet_pull_up = device_property_read_bool(dev,
2438                 "nuvoton,jkdet-pull-up");
2439         device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2440                 &nau8825->jkdet_polarity);
2441         device_property_read_u32(dev, "nuvoton,micbias-voltage",
2442                 &nau8825->micbias_voltage);
2443         device_property_read_u32(dev, "nuvoton,vref-impedance",
2444                 &nau8825->vref_impedance);
2445         device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2446                 &nau8825->sar_threshold_num);
2447         device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2448                 nau8825->sar_threshold, nau8825->sar_threshold_num);
2449         device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2450                 &nau8825->sar_hysteresis);
2451         device_property_read_u32(dev, "nuvoton,sar-voltage",
2452                 &nau8825->sar_voltage);
2453         device_property_read_u32(dev, "nuvoton,sar-compare-time",
2454                 &nau8825->sar_compare_time);
2455         device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2456                 &nau8825->sar_sampling_time);
2457         device_property_read_u32(dev, "nuvoton,short-key-debounce",
2458                 &nau8825->key_debounce);
2459         device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2460                 &nau8825->jack_insert_debounce);
2461         device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2462                 &nau8825->jack_eject_debounce);
2463 
2464         nau8825->mclk = devm_clk_get(dev, "mclk");
2465         if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2466                 return -EPROBE_DEFER;
2467         } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2468                 /* The MCLK is managed externally or not used at all */
2469                 nau8825->mclk = NULL;
2470                 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2471         } else if (IS_ERR(nau8825->mclk)) {
2472                 return -EINVAL;
2473         }
2474 
2475         return 0;
2476 }
2477 
2478 static int nau8825_setup_irq(struct nau8825 *nau8825)
2479 {
2480         int ret;
2481 
2482         ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2483                 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2484                 "nau8825", nau8825);
2485 
2486         if (ret) {
2487                 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2488                         nau8825->irq, ret);
2489                 return ret;
2490         }
2491 
2492         return 0;
2493 }
2494 
2495 static int nau8825_i2c_probe(struct i2c_client *i2c,
2496         const struct i2c_device_id *id)
2497 {
2498         struct device *dev = &i2c->dev;
2499         struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2500         int ret, value;
2501 
2502         if (!nau8825) {
2503                 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2504                 if (!nau8825)
2505                         return -ENOMEM;
2506                 ret = nau8825_read_device_properties(dev, nau8825);
2507                 if (ret)
2508                         return ret;
2509         }
2510 
2511         i2c_set_clientdata(i2c, nau8825);
2512 
2513         nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2514         if (IS_ERR(nau8825->regmap))
2515                 return PTR_ERR(nau8825->regmap);
2516         nau8825->dev = dev;
2517         nau8825->irq = i2c->irq;
2518         /* Initiate parameters, semaphone and work queue which are needed in
2519          * cross talk suppression measurment function.
2520          */
2521         nau8825->xtalk_state = NAU8825_XTALK_DONE;
2522         nau8825->xtalk_protect = false;
2523         sema_init(&nau8825->xtalk_sem, 1);
2524         INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2525 
2526         nau8825_print_device_properties(nau8825);
2527 
2528         nau8825_reset_chip(nau8825->regmap);
2529         ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2530         if (ret < 0) {
2531                 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2532                         ret);
2533                 return ret;
2534         }
2535         if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2536                         NAU8825_SOFTWARE_ID_NAU8825) {
2537                 dev_err(dev, "Not a NAU8825 chip\n");
2538                 return -ENODEV;
2539         }
2540 
2541         nau8825_init_regs(nau8825);
2542 
2543         if (i2c->irq)
2544                 nau8825_setup_irq(nau8825);
2545 
2546         return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2547                 &nau8825_dai, 1);
2548 }
2549 
2550 static int nau8825_i2c_remove(struct i2c_client *client)
2551 {
2552         snd_soc_unregister_codec(&client->dev);
2553         return 0;
2554 }
2555 
2556 static const struct i2c_device_id nau8825_i2c_ids[] = {
2557         { "nau8825", 0 },
2558         { }
2559 };
2560 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2561 
2562 #ifdef CONFIG_OF
2563 static const struct of_device_id nau8825_of_ids[] = {
2564         { .compatible = "nuvoton,nau8825", },
2565         {}
2566 };
2567 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2568 #endif
2569 
2570 #ifdef CONFIG_ACPI
2571 static const struct acpi_device_id nau8825_acpi_match[] = {
2572         { "10508825", 0 },
2573         {},
2574 };
2575 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2576 #endif
2577 
2578 static struct i2c_driver nau8825_driver = {
2579         .driver = {
2580                 .name = "nau8825",
2581                 .of_match_table = of_match_ptr(nau8825_of_ids),
2582                 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2583         },
2584         .probe = nau8825_i2c_probe,
2585         .remove = nau8825_i2c_remove,
2586         .id_table = nau8825_i2c_ids,
2587 };
2588 module_i2c_driver(nau8825_driver);
2589 
2590 MODULE_DESCRIPTION("ASoC nau8825 driver");
2591 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2592 MODULE_LICENSE("GPL");
2593 

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