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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/rt5514.c

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  1 /*
  2  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
  3  *
  4  * Copyright 2015 Realtek Semiconductor Corp.
  5  * Author: Oder Chiou <oder_chiou@realtek.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 
 12 #include <linux/acpi.h>
 13 #include <linux/fs.h>
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/regmap.h>
 20 #include <linux/i2c.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/firmware.h>
 23 #include <linux/gpio.h>
 24 #include <sound/core.h>
 25 #include <sound/pcm.h>
 26 #include <sound/pcm_params.h>
 27 #include <sound/soc.h>
 28 #include <sound/soc-dapm.h>
 29 #include <sound/initval.h>
 30 #include <sound/tlv.h>
 31 
 32 #include "rl6231.h"
 33 #include "rt5514.h"
 34 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 35 #include "rt5514-spi.h"
 36 #endif
 37 
 38 static const struct reg_sequence rt5514_i2c_patch[] = {
 39         {0x1800101c, 0x00000000},
 40         {0x18001100, 0x0000031f},
 41         {0x18001104, 0x00000007},
 42         {0x18001108, 0x00000000},
 43         {0x1800110c, 0x00000000},
 44         {0x18001110, 0x00000000},
 45         {0x18001114, 0x00000001},
 46         {0x18001118, 0x00000000},
 47         {0x18002f08, 0x00000006},
 48         {0x18002f00, 0x00055149},
 49         {0x18002f00, 0x0005514b},
 50         {0x18002f00, 0x00055149},
 51         {0xfafafafa, 0x00000001},
 52         {0x18002f10, 0x00000001},
 53         {0x18002f10, 0x00000000},
 54         {0x18002f10, 0x00000001},
 55         {0xfafafafa, 0x00000001},
 56         {0x18002000, 0x000010ec},
 57         {0xfafafafa, 0x00000000},
 58 };
 59 
 60 static const struct reg_sequence rt5514_patch[] = {
 61         {RT5514_DIG_IO_CTRL,            0x00000040},
 62         {RT5514_CLK_CTRL1,              0x38020041},
 63         {RT5514_SRC_CTRL,               0x44000eee},
 64         {RT5514_ANA_CTRL_LDO10,         0x00028604},
 65         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
 66         {RT5514_ASRC_IN_CTRL1,          0x00000003},
 67         {RT5514_DOWNFILTER0_CTRL3,      0x10000362},
 68         {RT5514_DOWNFILTER1_CTRL3,      0x10000362},
 69 };
 70 
 71 static const struct reg_default rt5514_reg[] = {
 72         {RT5514_RESET,                  0x00000000},
 73         {RT5514_PWR_ANA1,               0x00808880},
 74         {RT5514_PWR_ANA2,               0x00220000},
 75         {RT5514_I2S_CTRL1,              0x00000330},
 76         {RT5514_I2S_CTRL2,              0x20000000},
 77         {RT5514_VAD_CTRL6,              0xc00007d2},
 78         {RT5514_EXT_VAD_CTRL,           0x80000080},
 79         {RT5514_DIG_IO_CTRL,            0x00000040},
 80         {RT5514_PAD_CTRL1,              0x00804000},
 81         {RT5514_DMIC_DATA_CTRL,         0x00000005},
 82         {RT5514_DIG_SOURCE_CTRL,        0x00000002},
 83         {RT5514_SRC_CTRL,               0x44000eee},
 84         {RT5514_DOWNFILTER2_CTRL1,      0x0000882f},
 85         {RT5514_PLL_SOURCE_CTRL,        0x00000004},
 86         {RT5514_CLK_CTRL1,              0x38020041},
 87         {RT5514_CLK_CTRL2,              0x00000000},
 88         {RT5514_PLL3_CALIB_CTRL1,       0x00400200},
 89         {RT5514_PLL3_CALIB_CTRL5,       0x40220012},
 90         {RT5514_DELAY_BUF_CTRL1,        0x7fff006a},
 91         {RT5514_DELAY_BUF_CTRL3,        0x00000000},
 92         {RT5514_ASRC_IN_CTRL1,          0x00000003},
 93         {RT5514_DOWNFILTER0_CTRL1,      0x00020c2f},
 94         {RT5514_DOWNFILTER0_CTRL2,      0x00020c2f},
 95         {RT5514_DOWNFILTER0_CTRL3,      0x10000362},
 96         {RT5514_DOWNFILTER1_CTRL1,      0x00020c2f},
 97         {RT5514_DOWNFILTER1_CTRL2,      0x00020c2f},
 98         {RT5514_DOWNFILTER1_CTRL3,      0x10000362},
 99         {RT5514_ANA_CTRL_LDO10,         0x00028604},
100         {RT5514_ANA_CTRL_LDO18_16,      0x02000345},
101         {RT5514_ANA_CTRL_ADC12,         0x0000a2a8},
102         {RT5514_ANA_CTRL_ADC21,         0x00001180},
103         {RT5514_ANA_CTRL_ADC22,         0x0000aaa8},
104         {RT5514_ANA_CTRL_ADC23,         0x00151427},
105         {RT5514_ANA_CTRL_MICBST,        0x00002000},
106         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
107         {RT5514_ANA_CTRL_INBUF,         0x00000143},
108         {RT5514_ANA_CTRL_VREF,          0x00008d50},
109         {RT5514_ANA_CTRL_PLL3,          0x0000000e},
110         {RT5514_ANA_CTRL_PLL1_1,        0x00000000},
111         {RT5514_ANA_CTRL_PLL1_2,        0x00030220},
112         {RT5514_DMIC_LP_CTRL,           0x00000000},
113         {RT5514_MISC_CTRL_DSP,          0x00000000},
114         {RT5514_DSP_CTRL1,              0x00055149},
115         {RT5514_DSP_CTRL3,              0x00000006},
116         {RT5514_DSP_CTRL4,              0x00000001},
117         {RT5514_VENDOR_ID1,             0x00000001},
118         {RT5514_VENDOR_ID2,             0x10ec5514},
119 };
120 
121 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
122 {
123         /* Reset */
124         regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
125         /* LDO_I_limit */
126         regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
127         /* I2C bypass enable */
128         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
129         /* mini-core reset */
130         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
131         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
132         /* I2C bypass disable */
133         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
134         /* PIN config */
135         regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
136         /* PLL3(QN)=RCOSC*(10+2) */
137         regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
138         /* PLL3 source=RCOSC, fsi=rt_clk */
139         regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
140         /* Power on RCOSC, pll3 */
141         regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
142         /* DSP clk source = pll3, ENABLE DSP clk */
143         regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
144         /* Enable DSP clk auto switch */
145         regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
146         /* Reduce DSP power */
147         regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
148 }
149 
150 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
151 {
152         switch (reg) {
153         case RT5514_VENDOR_ID1:
154         case RT5514_VENDOR_ID2:
155                 return true;
156 
157         default:
158                 return false;
159         }
160 }
161 
162 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
163 {
164         switch (reg) {
165         case RT5514_RESET:
166         case RT5514_PWR_ANA1:
167         case RT5514_PWR_ANA2:
168         case RT5514_I2S_CTRL1:
169         case RT5514_I2S_CTRL2:
170         case RT5514_VAD_CTRL6:
171         case RT5514_EXT_VAD_CTRL:
172         case RT5514_DIG_IO_CTRL:
173         case RT5514_PAD_CTRL1:
174         case RT5514_DMIC_DATA_CTRL:
175         case RT5514_DIG_SOURCE_CTRL:
176         case RT5514_SRC_CTRL:
177         case RT5514_DOWNFILTER2_CTRL1:
178         case RT5514_PLL_SOURCE_CTRL:
179         case RT5514_CLK_CTRL1:
180         case RT5514_CLK_CTRL2:
181         case RT5514_PLL3_CALIB_CTRL1:
182         case RT5514_PLL3_CALIB_CTRL5:
183         case RT5514_DELAY_BUF_CTRL1:
184         case RT5514_DELAY_BUF_CTRL3:
185         case RT5514_ASRC_IN_CTRL1:
186         case RT5514_DOWNFILTER0_CTRL1:
187         case RT5514_DOWNFILTER0_CTRL2:
188         case RT5514_DOWNFILTER0_CTRL3:
189         case RT5514_DOWNFILTER1_CTRL1:
190         case RT5514_DOWNFILTER1_CTRL2:
191         case RT5514_DOWNFILTER1_CTRL3:
192         case RT5514_ANA_CTRL_LDO10:
193         case RT5514_ANA_CTRL_LDO18_16:
194         case RT5514_ANA_CTRL_ADC12:
195         case RT5514_ANA_CTRL_ADC21:
196         case RT5514_ANA_CTRL_ADC22:
197         case RT5514_ANA_CTRL_ADC23:
198         case RT5514_ANA_CTRL_MICBST:
199         case RT5514_ANA_CTRL_ADCFED:
200         case RT5514_ANA_CTRL_INBUF:
201         case RT5514_ANA_CTRL_VREF:
202         case RT5514_ANA_CTRL_PLL3:
203         case RT5514_ANA_CTRL_PLL1_1:
204         case RT5514_ANA_CTRL_PLL1_2:
205         case RT5514_DMIC_LP_CTRL:
206         case RT5514_MISC_CTRL_DSP:
207         case RT5514_DSP_CTRL1:
208         case RT5514_DSP_CTRL3:
209         case RT5514_DSP_CTRL4:
210         case RT5514_VENDOR_ID1:
211         case RT5514_VENDOR_ID2:
212                 return true;
213 
214         default:
215                 return false;
216         }
217 }
218 
219 static bool rt5514_i2c_readable_register(struct device *dev,
220         unsigned int reg)
221 {
222         switch (reg) {
223         case RT5514_DSP_MAPPING | RT5514_RESET:
224         case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
225         case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
226         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
227         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
228         case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
229         case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
230         case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
231         case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
232         case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
233         case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
234         case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
235         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
236         case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
237         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
238         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
239         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
240         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
241         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
242         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
243         case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
244         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
245         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
246         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
247         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
248         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
249         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
250         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
251         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
252         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
253         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
254         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
255         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
256         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
257         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
258         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
259         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
260         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
261         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
262         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
263         case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
264         case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
265         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
266         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
267         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
268         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
269         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
270                 return true;
271 
272         default:
273                 return false;
274         }
275 }
276 
277 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
278 static const DECLARE_TLV_DB_RANGE(bst_tlv,
279         0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
280         3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
281         4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
282         5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
283         6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
284         7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
285         8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
286 );
287 
288 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
289 
290 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
291                 struct snd_ctl_elem_value *ucontrol)
292 {
293         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
294         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
295 
296         ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
297 
298         return 0;
299 }
300 
301 static int rt5514_calibration(struct rt5514_priv *rt5514, bool on)
302 {
303         if (on) {
304                 regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a);
305                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
306                         0xa);
307                 regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301,
308                         0x301);
309                 regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4,
310                         0x80000000 | rt5514->pll3_cal_value);
311                 regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1,
312                         0x8bb80800);
313                 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
314                         0xc0000000, 0x80000000);
315                 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
316                         0xc0000000, 0xc0000000);
317         } else {
318                 regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
319                         0xc0000000, 0x40000000);
320                 regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0);
321                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
322                         0x4);
323         }
324 
325         return 0;
326 }
327 
328 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
329                 struct snd_ctl_elem_value *ucontrol)
330 {
331         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
332         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
333         const struct firmware *fw = NULL;
334         u8 buf[8];
335 
336         if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
337                 return 0;
338 
339         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
340                 rt5514->dsp_enabled = ucontrol->value.integer.value[0];
341 
342                 if (rt5514->dsp_enabled) {
343                         if (rt5514->pdata.dsp_calib_clk_name &&
344                                 !IS_ERR(rt5514->dsp_calib_clk)) {
345                                 if (clk_set_rate(rt5514->dsp_calib_clk,
346                                         rt5514->pdata.dsp_calib_clk_rate))
347                                         dev_err(component->dev,
348                                                 "Can't set rate for mclk");
349 
350                                 if (clk_prepare_enable(rt5514->dsp_calib_clk))
351                                         dev_err(component->dev,
352                                                 "Can't enable dsp_calib_clk");
353 
354                                 rt5514_calibration(rt5514, true);
355 
356                                 msleep(20);
357 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
358                                 rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 |
359                                         RT5514_DSP_MAPPING, buf, sizeof(buf));
360 #else
361                                 dev_err(component->dev, "There is no SPI driver for"
362                                         " loading the firmware\n");
363                                 memset(buf, 0, sizeof(buf));
364 #endif
365                                 rt5514->pll3_cal_value = buf[0] | buf[1] << 8 |
366                                         buf[2] << 16 | buf[3] << 24;
367 
368                                 rt5514_calibration(rt5514, false);
369                                 clk_disable_unprepare(rt5514->dsp_calib_clk);
370                         }
371 
372                         rt5514_enable_dsp_prepare(rt5514);
373 
374                         request_firmware(&fw, RT5514_FIRMWARE1, component->dev);
375                         if (fw) {
376 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
377                                 rt5514_spi_burst_write(0x4ff60000, fw->data,
378                                         ((fw->size/8)+1)*8);
379 #else
380                                 dev_err(component->dev, "There is no SPI driver for"
381                                         " loading the firmware\n");
382 #endif
383                                 release_firmware(fw);
384                                 fw = NULL;
385                         }
386 
387                         request_firmware(&fw, RT5514_FIRMWARE2, component->dev);
388                         if (fw) {
389 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
390                                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
391                                         ((fw->size/8)+1)*8);
392 #else
393                                 dev_err(component->dev, "There is no SPI driver for"
394                                         " loading the firmware\n");
395 #endif
396                                 release_firmware(fw);
397                                 fw = NULL;
398                         }
399 
400                         /* DSP run */
401                         regmap_write(rt5514->i2c_regmap, 0x18002f00,
402                                 0x00055148);
403 
404                         if (rt5514->pdata.dsp_calib_clk_name &&
405                                 !IS_ERR(rt5514->dsp_calib_clk)) {
406                                 msleep(20);
407 
408                                 regmap_write(rt5514->i2c_regmap, 0x1800211c,
409                                         rt5514->pll3_cal_value);
410                                 regmap_write(rt5514->i2c_regmap, 0x18002124,
411                                         0x00220012);
412                                 regmap_write(rt5514->i2c_regmap, 0x18002124,
413                                         0x80220042);
414                                 regmap_write(rt5514->i2c_regmap, 0x18002124,
415                                         0xe0220042);
416                         }
417                 } else {
418                         regmap_multi_reg_write(rt5514->i2c_regmap,
419                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
420                         regcache_mark_dirty(rt5514->regmap);
421                         regcache_sync(rt5514->regmap);
422                 }
423         }
424 
425         return 0;
426 }
427 
428 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
429         SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
430                 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
431         SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
432                 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
433                 adc_vol_tlv),
434         SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
435                 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
436                 adc_vol_tlv),
437         SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
438                 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
439 };
440 
441 /* ADC Mixer*/
442 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
443         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
444                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
445         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
446                 RT5514_AD_AD_MIX_BIT, 1, 1),
447 };
448 
449 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
450         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
451                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
452         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
453                 RT5514_AD_AD_MIX_BIT, 1, 1),
454 };
455 
456 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
457         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
458                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
459         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
460                 RT5514_AD_AD_MIX_BIT, 1, 1),
461 };
462 
463 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
464         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
465                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
466         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
467                 RT5514_AD_AD_MIX_BIT, 1, 1),
468 };
469 
470 /* DMIC Source */
471 static const char * const rt5514_dmic_src[] = {
472         "DMIC1", "DMIC2"
473 };
474 
475 static SOC_ENUM_SINGLE_DECL(
476         rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
477         RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
478 
479 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
480         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
481 
482 static SOC_ENUM_SINGLE_DECL(
483         rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
484         RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
485 
486 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
487         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
488 
489 /**
490  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
491  *
492  * @rate: base clock rate.
493  *
494  * Choose divider parameter that gives the highest possible DMIC frequency in
495  * 1MHz - 3MHz range.
496  */
497 static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
498 {
499         int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
500         int i;
501 
502         if (rate < 1000000 * div[0]) {
503                 pr_warn("Base clock rate %d is too low\n", rate);
504                 return -EINVAL;
505         }
506 
507         for (i = 0; i < ARRAY_SIZE(div); i++) {
508                 /* find divider that gives DMIC frequency below 3.072MHz */
509                 if (3072000 * div[i] >= rate)
510                         return i;
511         }
512 
513         dev_warn(component->dev, "Base clock rate %d is too high\n", rate);
514         return -EINVAL;
515 }
516 
517 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
518         struct snd_kcontrol *kcontrol, int event)
519 {
520         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
521         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
522         int idx;
523 
524         idx = rt5514_calc_dmic_clk(component, rt5514->sysclk);
525         if (idx < 0)
526                 dev_err(component->dev, "Failed to set DMIC clock\n");
527         else
528                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
529                         RT5514_CLK_DMIC_OUT_SEL_MASK,
530                         idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
531 
532         if (rt5514->pdata.dmic_init_delay)
533                 msleep(rt5514->pdata.dmic_init_delay);
534 
535         return idx;
536 }
537 
538 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
539                          struct snd_soc_dapm_widget *sink)
540 {
541         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
542         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
543 
544         if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
545                 return 1;
546         else
547                 return 0;
548 }
549 
550 static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
551         struct snd_soc_dapm_widget *sink)
552 {
553         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
554         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
555 
556         return (rt5514->sysclk > rt5514->lrck * 384);
557 }
558 
559 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
560         /* Input Lines */
561         SND_SOC_DAPM_INPUT("DMIC1L"),
562         SND_SOC_DAPM_INPUT("DMIC1R"),
563         SND_SOC_DAPM_INPUT("DMIC2L"),
564         SND_SOC_DAPM_INPUT("DMIC2R"),
565 
566         SND_SOC_DAPM_INPUT("AMICL"),
567         SND_SOC_DAPM_INPUT("AMICR"),
568 
569         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
570         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
571 
572         SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
573                 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
574 
575         SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
576                 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
577 
578         SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
579                 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
580         SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
581                 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
582         SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
583                 NULL, 0),
584         SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
585                 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
586         SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
587                 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
588         SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
589                 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
590         SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
591                 NULL, 0),
592         SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
593                 NULL, 0),
594         SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
595                 NULL, 0),
596         SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
597 
598 
599         SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
600                 NULL, 0),
601         SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
602                 NULL, 0),
603         SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
604                 NULL, 0),
605         SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
606                 NULL, 0),
607         SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
608                 0, NULL, 0),
609         SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
610 
611         SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
612                 NULL, 0),
613         SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
614                 NULL, 0),
615         SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
616                 NULL, 0),
617         SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
618                 NULL, 0),
619         SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
620                 0, NULL, 0),
621         SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
622 
623         SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
624                 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
625         SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
626                 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
627         SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
628                 NULL, 0),
629         SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
630                 RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
631         SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
632                 RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
633 
634         /* ADC Mux */
635         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
636                                 &rt5514_sto1_dmic_mux),
637         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
638                                 &rt5514_sto2_dmic_mux),
639 
640         /* ADC Mixer */
641         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
642                 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
643         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
644                 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
645 
646         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
647                 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
648         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
649                 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
650         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
651                 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
652         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
653                 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
654 
655         SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
656                 RT5514_AD_AD_MUTE_BIT, 1),
657         SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
658                 RT5514_AD_AD_MUTE_BIT, 1),
659         SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
660                 RT5514_AD_AD_MUTE_BIT, 1),
661         SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
662                 RT5514_AD_AD_MUTE_BIT, 1),
663 
664         /* ADC PGA */
665         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
666         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
667 
668         /* Audio Interface */
669         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
670 };
671 
672 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
673         { "DMIC1", NULL, "DMIC1L" },
674         { "DMIC1", NULL, "DMIC1R" },
675         { "DMIC2", NULL, "DMIC2L" },
676         { "DMIC2", NULL, "DMIC2R" },
677 
678         { "DMIC1L", NULL, "DMIC CLK" },
679         { "DMIC1R", NULL, "DMIC CLK" },
680         { "DMIC2L", NULL, "DMIC CLK" },
681         { "DMIC2R", NULL, "DMIC CLK" },
682 
683         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
684         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
685 
686         { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
687         { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
688         { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
689         { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
690 
691         { "ADC Power", NULL, "LDO18 IN" },
692         { "ADC Power", NULL, "LDO18 ADC" },
693         { "ADC Power", NULL, "LDO21" },
694         { "ADC Power", NULL, "BG LDO18 IN" },
695         { "ADC Power", NULL, "BG LDO21" },
696         { "ADC Power", NULL, "BG MBIAS" },
697         { "ADC Power", NULL, "MBIAS" },
698         { "ADC Power", NULL, "VREF2" },
699         { "ADC Power", NULL, "VREF1" },
700 
701         { "ADCL Power", NULL, "LDO16L" },
702         { "ADCL Power", NULL, "ADC1L" },
703         { "ADCL Power", NULL, "BSTL2" },
704         { "ADCL Power", NULL, "BSTL" },
705         { "ADCL Power", NULL, "ADCFEDL" },
706 
707         { "ADCR Power", NULL, "LDO16R" },
708         { "ADCR Power", NULL, "ADC1R" },
709         { "ADCR Power", NULL, "BSTR2" },
710         { "ADCR Power", NULL, "BSTR" },
711         { "ADCR Power", NULL, "ADCFEDR" },
712 
713         { "AMICL", NULL, "ADC CLK" },
714         { "AMICL", NULL, "ADC Power" },
715         { "AMICL", NULL, "ADCL Power" },
716         { "AMICR", NULL, "ADC CLK" },
717         { "AMICR", NULL, "ADC Power" },
718         { "AMICR", NULL, "ADCR Power" },
719 
720         { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
721         { "PLL1", NULL, "PLL1 LDO" },
722 
723         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
724         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
725 
726         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
727         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
728         { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
729         { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
730         { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
731 
732         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
733         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
734 
735         { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
736         { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
737         { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
738         { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
739 
740         { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
741         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
742 
743         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
744         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
745         { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
746         { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
747         { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
748 
749         { "AIF1TX", NULL, "Stereo1 ADC MIX"},
750         { "AIF1TX", NULL, "Stereo2 ADC MIX"},
751 };
752 
753 static int rt5514_hw_params(struct snd_pcm_substream *substream,
754         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
755 {
756         struct snd_soc_component *component = dai->component;
757         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
758         int pre_div, bclk_ms, frame_size;
759         unsigned int val_len = 0;
760 
761         rt5514->lrck = params_rate(params);
762         pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
763         if (pre_div < 0) {
764                 dev_err(component->dev, "Unsupported clock setting\n");
765                 return -EINVAL;
766         }
767 
768         frame_size = snd_soc_params_to_frame_size(params);
769         if (frame_size < 0) {
770                 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
771                 return -EINVAL;
772         }
773 
774         bclk_ms = frame_size > 32;
775         rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
776 
777         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
778                 rt5514->bclk, rt5514->lrck);
779         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
780                                 bclk_ms, pre_div, dai->id);
781 
782         switch (params_format(params)) {
783         case SNDRV_PCM_FORMAT_S16_LE:
784                 break;
785         case SNDRV_PCM_FORMAT_S20_3LE:
786                 val_len = RT5514_I2S_DL_20;
787                 break;
788         case SNDRV_PCM_FORMAT_S24_LE:
789                 val_len = RT5514_I2S_DL_24;
790                 break;
791         case SNDRV_PCM_FORMAT_S8:
792                 val_len = RT5514_I2S_DL_8;
793                 break;
794         default:
795                 return -EINVAL;
796         }
797 
798         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
799                 val_len);
800         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
801                 RT5514_CLK_AD_ANA1_SEL_MASK,
802                 (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
803         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
804                 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
805                 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
806                 pre_div << RT5514_SEL_ADC_OSR_SFT);
807 
808         return 0;
809 }
810 
811 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
812 {
813         struct snd_soc_component *component = dai->component;
814         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
815         unsigned int reg_val = 0;
816 
817         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
818         case SND_SOC_DAIFMT_NB_NF:
819                 break;
820 
821         case SND_SOC_DAIFMT_NB_IF:
822                 reg_val |= RT5514_I2S_LR_INV;
823                 break;
824 
825         case SND_SOC_DAIFMT_IB_NF:
826                 reg_val |= RT5514_I2S_BP_INV;
827                 break;
828 
829         case SND_SOC_DAIFMT_IB_IF:
830                 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
831                 break;
832 
833         default:
834                 return -EINVAL;
835         }
836 
837         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
838         case SND_SOC_DAIFMT_I2S:
839                 break;
840 
841         case SND_SOC_DAIFMT_LEFT_J:
842                 reg_val |= RT5514_I2S_DF_LEFT;
843                 break;
844 
845         case SND_SOC_DAIFMT_DSP_A:
846                 reg_val |= RT5514_I2S_DF_PCM_A;
847                 break;
848 
849         case SND_SOC_DAIFMT_DSP_B:
850                 reg_val |= RT5514_I2S_DF_PCM_B;
851                 break;
852 
853         default:
854                 return -EINVAL;
855         }
856 
857         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
858                 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
859                 reg_val);
860 
861         return 0;
862 }
863 
864 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
865                 int clk_id, unsigned int freq, int dir)
866 {
867         struct snd_soc_component *component = dai->component;
868         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
869         unsigned int reg_val = 0;
870 
871         if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
872                 return 0;
873 
874         switch (clk_id) {
875         case RT5514_SCLK_S_MCLK:
876                 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
877                 break;
878 
879         case RT5514_SCLK_S_PLL1:
880                 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
881                 break;
882 
883         default:
884                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
885                 return -EINVAL;
886         }
887 
888         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
889                 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
890 
891         rt5514->sysclk = freq;
892         rt5514->sysclk_src = clk_id;
893 
894         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
895 
896         return 0;
897 }
898 
899 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
900                         unsigned int freq_in, unsigned int freq_out)
901 {
902         struct snd_soc_component *component = dai->component;
903         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
904         struct rl6231_pll_code pll_code;
905         int ret;
906 
907         if (!freq_in || !freq_out) {
908                 dev_dbg(component->dev, "PLL disabled\n");
909 
910                 rt5514->pll_in = 0;
911                 rt5514->pll_out = 0;
912                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
913                         RT5514_CLK_SYS_PRE_SEL_MASK,
914                         RT5514_CLK_SYS_PRE_SEL_MCLK);
915 
916                 return 0;
917         }
918 
919         if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
920             freq_out == rt5514->pll_out)
921                 return 0;
922 
923         switch (source) {
924         case RT5514_PLL1_S_MCLK:
925                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
926                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
927                 break;
928 
929         case RT5514_PLL1_S_BCLK:
930                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
931                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
932                 break;
933 
934         default:
935                 dev_err(component->dev, "Unknown PLL source %d\n", source);
936                 return -EINVAL;
937         }
938 
939         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
940         if (ret < 0) {
941                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
942                 return ret;
943         }
944 
945         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
946                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
947                 pll_code.n_code, pll_code.k_code);
948 
949         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
950                 pll_code.k_code << RT5514_PLL_K_SFT |
951                 pll_code.n_code << RT5514_PLL_N_SFT |
952                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
953         regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
954                 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
955 
956         rt5514->pll_in = freq_in;
957         rt5514->pll_out = freq_out;
958         rt5514->pll_src = source;
959 
960         return 0;
961 }
962 
963 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
964                         unsigned int rx_mask, int slots, int slot_width)
965 {
966         struct snd_soc_component *component = dai->component;
967         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
968         unsigned int val = 0, val2 = 0;
969 
970         if (rx_mask || tx_mask)
971                 val |= RT5514_TDM_MODE;
972 
973         switch (tx_mask) {
974         case 0x3:
975                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
976                         RT5514_TDM_DOCKING_START_SLOT0;
977                 break;
978 
979         case 0x30:
980                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
981                         RT5514_TDM_DOCKING_START_SLOT4;
982                 break;
983 
984         case 0xf:
985                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
986                         RT5514_TDM_DOCKING_START_SLOT0;
987                 break;
988 
989         case 0xf0:
990                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
991                         RT5514_TDM_DOCKING_START_SLOT4;
992                 break;
993 
994         default:
995                 break;
996         }
997 
998 
999 
1000         switch (slots) {
1001         case 4:
1002                 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
1003                 break;
1004 
1005         case 6:
1006                 val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
1007                 break;
1008 
1009         case 8:
1010                 val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
1011                 break;
1012 
1013         case 2:
1014         default:
1015                 break;
1016         }
1017 
1018         switch (slot_width) {
1019         case 20:
1020                 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
1021                 break;
1022 
1023         case 24:
1024                 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
1025                 break;
1026 
1027         case 25:
1028                 val |= RT5514_TDM_MODE2;
1029                 break;
1030 
1031         case 32:
1032                 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
1033                 break;
1034 
1035         case 16:
1036         default:
1037                 break;
1038         }
1039 
1040         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
1041                 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
1042                 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
1043                 RT5514_TDM_MODE2, val);
1044 
1045         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
1046                 RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
1047                 RT5514_TDM_DOCKING_START_MASK, val2);
1048 
1049         return 0;
1050 }
1051 
1052 static int rt5514_set_bias_level(struct snd_soc_component *component,
1053                         enum snd_soc_bias_level level)
1054 {
1055         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1056         int ret;
1057 
1058         switch (level) {
1059         case SND_SOC_BIAS_PREPARE:
1060                 if (IS_ERR(rt5514->mclk))
1061                         break;
1062 
1063                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1064                         clk_disable_unprepare(rt5514->mclk);
1065                 } else {
1066                         ret = clk_prepare_enable(rt5514->mclk);
1067                         if (ret)
1068                                 return ret;
1069                 }
1070                 break;
1071 
1072         case SND_SOC_BIAS_STANDBY:
1073                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1074                         /*
1075                          * If the DSP is enabled in start of recording, the DSP
1076                          * should be disabled, and sync back to normal recording
1077                          * settings to make sure recording properly.
1078                          */
1079                         if (rt5514->dsp_enabled) {
1080                                 rt5514->dsp_enabled = 0;
1081                                 regmap_multi_reg_write(rt5514->i2c_regmap,
1082                                         rt5514_i2c_patch,
1083                                         ARRAY_SIZE(rt5514_i2c_patch));
1084                                 regcache_mark_dirty(rt5514->regmap);
1085                                 regcache_sync(rt5514->regmap);
1086                         }
1087                 }
1088                 break;
1089 
1090         default:
1091                 break;
1092         }
1093 
1094         return 0;
1095 }
1096 
1097 static int rt5514_probe(struct snd_soc_component *component)
1098 {
1099         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1100         struct platform_device *pdev = container_of(component->dev,
1101                                                    struct platform_device, dev);
1102 
1103         rt5514->mclk = devm_clk_get(component->dev, "mclk");
1104         if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
1105                 return -EPROBE_DEFER;
1106 
1107         if (rt5514->pdata.dsp_calib_clk_name) {
1108                 rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev,
1109                                 rt5514->pdata.dsp_calib_clk_name);
1110                 if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER)
1111                         return -EPROBE_DEFER;
1112         }
1113 
1114         rt5514->component = component;
1115         rt5514->pll3_cal_value = 0x0078b000;
1116 
1117         return 0;
1118 }
1119 
1120 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
1121 {
1122         struct i2c_client *client = context;
1123         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1124 
1125         regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1126 
1127         return 0;
1128 }
1129 
1130 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
1131 {
1132         struct i2c_client *client = context;
1133         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1134 
1135         regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1136 
1137         return 0;
1138 }
1139 
1140 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1141 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1142                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1143 
1144 static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1145         .hw_params = rt5514_hw_params,
1146         .set_fmt = rt5514_set_dai_fmt,
1147         .set_sysclk = rt5514_set_dai_sysclk,
1148         .set_pll = rt5514_set_dai_pll,
1149         .set_tdm_slot = rt5514_set_tdm_slot,
1150 };
1151 
1152 static struct snd_soc_dai_driver rt5514_dai[] = {
1153         {
1154                 .name = "rt5514-aif1",
1155                 .id = 0,
1156                 .capture = {
1157                         .stream_name = "AIF1 Capture",
1158                         .channels_min = 1,
1159                         .channels_max = 4,
1160                         .rates = RT5514_STEREO_RATES,
1161                         .formats = RT5514_FORMATS,
1162                 },
1163                 .ops = &rt5514_aif_dai_ops,
1164         }
1165 };
1166 
1167 static const struct snd_soc_component_driver soc_component_dev_rt5514 = {
1168         .probe                  = rt5514_probe,
1169         .set_bias_level         = rt5514_set_bias_level,
1170         .controls               = rt5514_snd_controls,
1171         .num_controls           = ARRAY_SIZE(rt5514_snd_controls),
1172         .dapm_widgets           = rt5514_dapm_widgets,
1173         .num_dapm_widgets       = ARRAY_SIZE(rt5514_dapm_widgets),
1174         .dapm_routes            = rt5514_dapm_routes,
1175         .num_dapm_routes        = ARRAY_SIZE(rt5514_dapm_routes),
1176         .use_pmdown_time        = 1,
1177         .endianness             = 1,
1178         .non_legacy_dai_naming  = 1,
1179 };
1180 
1181 static const struct regmap_config rt5514_i2c_regmap = {
1182         .name = "i2c",
1183         .reg_bits = 32,
1184         .val_bits = 32,
1185 
1186         .readable_reg = rt5514_i2c_readable_register,
1187 
1188         .cache_type = REGCACHE_NONE,
1189 };
1190 
1191 static const struct regmap_config rt5514_regmap = {
1192         .reg_bits = 16,
1193         .val_bits = 32,
1194 
1195         .max_register = RT5514_VENDOR_ID2,
1196         .volatile_reg = rt5514_volatile_register,
1197         .readable_reg = rt5514_readable_register,
1198         .reg_read = rt5514_i2c_read,
1199         .reg_write = rt5514_i2c_write,
1200 
1201         .cache_type = REGCACHE_RBTREE,
1202         .reg_defaults = rt5514_reg,
1203         .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1204         .use_single_rw = true,
1205 };
1206 
1207 static const struct i2c_device_id rt5514_i2c_id[] = {
1208         { "rt5514", 0 },
1209         { }
1210 };
1211 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1212 
1213 #if defined(CONFIG_OF)
1214 static const struct of_device_id rt5514_of_match[] = {
1215         { .compatible = "realtek,rt5514", },
1216         {},
1217 };
1218 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1219 #endif
1220 
1221 #ifdef CONFIG_ACPI
1222 static const struct acpi_device_id rt5514_acpi_match[] = {
1223         { "10EC5514", 0},
1224         {},
1225 };
1226 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
1227 #endif
1228 
1229 static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev)
1230 {
1231         device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1232                 &rt5514->pdata.dmic_init_delay);
1233         device_property_read_string(dev, "realtek,dsp-calib-clk-name",
1234                 &rt5514->pdata.dsp_calib_clk_name);
1235         device_property_read_u32(dev, "realtek,dsp-calib-clk-rate",
1236                 &rt5514->pdata.dsp_calib_clk_rate);
1237 
1238         return 0;
1239 }
1240 
1241 static __maybe_unused int rt5514_i2c_resume(struct device *dev)
1242 {
1243         struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
1244         unsigned int val;
1245 
1246         /*
1247          * Add a bogus read to avoid rt5514's confusion after s2r in case it
1248          * saw glitches on the i2c lines and thought the other side sent a
1249          * start bit.
1250          */
1251         regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1252 
1253         return 0;
1254 }
1255 
1256 static int rt5514_i2c_probe(struct i2c_client *i2c,
1257                     const struct i2c_device_id *id)
1258 {
1259         struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1260         struct rt5514_priv *rt5514;
1261         int ret;
1262         unsigned int val = ~0;
1263 
1264         rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1265                                 GFP_KERNEL);
1266         if (rt5514 == NULL)
1267                 return -ENOMEM;
1268 
1269         i2c_set_clientdata(i2c, rt5514);
1270 
1271         if (pdata)
1272                 rt5514->pdata = *pdata;
1273         else
1274                 rt5514_parse_dp(rt5514, &i2c->dev);
1275 
1276         rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1277         if (IS_ERR(rt5514->i2c_regmap)) {
1278                 ret = PTR_ERR(rt5514->i2c_regmap);
1279                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1280                         ret);
1281                 return ret;
1282         }
1283 
1284         rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1285         if (IS_ERR(rt5514->regmap)) {
1286                 ret = PTR_ERR(rt5514->regmap);
1287                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1288                         ret);
1289                 return ret;
1290         }
1291 
1292         /*
1293          * The rt5514 can get confused if the i2c lines glitch together, as
1294          * can happen at bootup as regulators are turned off and on.  If it's
1295          * in this glitched state the first i2c read will fail, so we'll give
1296          * it one change to retry.
1297          */
1298         ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1299         if (ret || val != RT5514_DEVICE_ID)
1300                 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1301         if (ret || val != RT5514_DEVICE_ID) {
1302                 dev_err(&i2c->dev,
1303                         "Device with ID register %x is not rt5514\n", val);
1304                 return -ENODEV;
1305         }
1306 
1307         ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1308                                     ARRAY_SIZE(rt5514_i2c_patch));
1309         if (ret != 0)
1310                 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1311                         ret);
1312 
1313         ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1314                                     ARRAY_SIZE(rt5514_patch));
1315         if (ret != 0)
1316                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1317 
1318         return devm_snd_soc_register_component(&i2c->dev,
1319                         &soc_component_dev_rt5514,
1320                         rt5514_dai, ARRAY_SIZE(rt5514_dai));
1321 }
1322 
1323 static const struct dev_pm_ops rt5514_i2_pm_ops = {
1324         SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
1325 };
1326 
1327 static struct i2c_driver rt5514_i2c_driver = {
1328         .driver = {
1329                 .name = "rt5514",
1330                 .acpi_match_table = ACPI_PTR(rt5514_acpi_match),
1331                 .of_match_table = of_match_ptr(rt5514_of_match),
1332                 .pm = &rt5514_i2_pm_ops,
1333         },
1334         .probe = rt5514_i2c_probe,
1335         .id_table = rt5514_i2c_id,
1336 };
1337 module_i2c_driver(rt5514_i2c_driver);
1338 
1339 MODULE_DESCRIPTION("ASoC RT5514 driver");
1340 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1341 MODULE_LICENSE("GPL v2");
1342 

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