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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/rt5677.c

Version: ~ [ linux-5.7-rc7 ] ~ [ linux-5.6.14 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.42 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.124 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.181 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.224 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.224 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.84 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * rt5677.c  --  RT5677 ALSA SoC audio codec driver
  3  *
  4  * Copyright 2013 Realtek Semiconductor Corp.
  5  * Author: Oder Chiou <oder_chiou@realtek.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 
 12 #include <linux/acpi.h>
 13 #include <linux/fs.h>
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/regmap.h>
 20 #include <linux/i2c.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/spi/spi.h>
 23 #include <linux/firmware.h>
 24 #include <linux/of_device.h>
 25 #include <linux/property.h>
 26 #include <sound/core.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/soc-dapm.h>
 31 #include <sound/initval.h>
 32 #include <sound/tlv.h>
 33 
 34 #include "rl6231.h"
 35 #include "rt5677.h"
 36 #include "rt5677-spi.h"
 37 
 38 #define RT5677_DEVICE_ID 0x6327
 39 
 40 #define RT5677_PR_RANGE_BASE (0xff + 1)
 41 #define RT5677_PR_SPACING 0x100
 42 
 43 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
 44 
 45 static const struct regmap_range_cfg rt5677_ranges[] = {
 46         {
 47                 .name = "PR",
 48                 .range_min = RT5677_PR_BASE,
 49                 .range_max = RT5677_PR_BASE + 0xfd,
 50                 .selector_reg = RT5677_PRIV_INDEX,
 51                 .selector_mask = 0xff,
 52                 .selector_shift = 0x0,
 53                 .window_start = RT5677_PRIV_DATA,
 54                 .window_len = 0x1,
 55         },
 56 };
 57 
 58 static const struct reg_sequence init_list[] = {
 59         {RT5677_ASRC_12,        0x0018},
 60         {RT5677_PR_BASE + 0x3d, 0x364d},
 61         {RT5677_PR_BASE + 0x17, 0x4fc0},
 62         {RT5677_PR_BASE + 0x13, 0x0312},
 63         {RT5677_PR_BASE + 0x1e, 0x0000},
 64         {RT5677_PR_BASE + 0x12, 0x0eaa},
 65         {RT5677_PR_BASE + 0x14, 0x018a},
 66         {RT5677_PR_BASE + 0x15, 0x0490},
 67         {RT5677_PR_BASE + 0x38, 0x0f71},
 68         {RT5677_PR_BASE + 0x39, 0x0f71},
 69 };
 70 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
 71 
 72 static const struct reg_default rt5677_reg[] = {
 73         {RT5677_RESET                   , 0x0000},
 74         {RT5677_LOUT1                   , 0xa800},
 75         {RT5677_IN1                     , 0x0000},
 76         {RT5677_MICBIAS                 , 0x0000},
 77         {RT5677_SLIMBUS_PARAM           , 0x0000},
 78         {RT5677_SLIMBUS_RX              , 0x0000},
 79         {RT5677_SLIMBUS_CTRL            , 0x0000},
 80         {RT5677_SIDETONE_CTRL           , 0x000b},
 81         {RT5677_ANA_DAC1_2_3_SRC        , 0x0000},
 82         {RT5677_IF_DSP_DAC3_4_MIXER     , 0x1111},
 83         {RT5677_DAC4_DIG_VOL            , 0xafaf},
 84         {RT5677_DAC3_DIG_VOL            , 0xafaf},
 85         {RT5677_DAC1_DIG_VOL            , 0xafaf},
 86         {RT5677_DAC2_DIG_VOL            , 0xafaf},
 87         {RT5677_IF_DSP_DAC2_MIXER       , 0x0011},
 88         {RT5677_STO1_ADC_DIG_VOL        , 0x2f2f},
 89         {RT5677_MONO_ADC_DIG_VOL        , 0x2f2f},
 90         {RT5677_STO1_2_ADC_BST          , 0x0000},
 91         {RT5677_STO2_ADC_DIG_VOL        , 0x2f2f},
 92         {RT5677_ADC_BST_CTRL2           , 0x0000},
 93         {RT5677_STO3_4_ADC_BST          , 0x0000},
 94         {RT5677_STO3_ADC_DIG_VOL        , 0x2f2f},
 95         {RT5677_STO4_ADC_DIG_VOL        , 0x2f2f},
 96         {RT5677_STO4_ADC_MIXER          , 0xd4c0},
 97         {RT5677_STO3_ADC_MIXER          , 0xd4c0},
 98         {RT5677_STO2_ADC_MIXER          , 0xd4c0},
 99         {RT5677_STO1_ADC_MIXER          , 0xd4c0},
100         {RT5677_MONO_ADC_MIXER          , 0xd4d1},
101         {RT5677_ADC_IF_DSP_DAC1_MIXER   , 0x8080},
102         {RT5677_STO1_DAC_MIXER          , 0xaaaa},
103         {RT5677_MONO_DAC_MIXER          , 0xaaaa},
104         {RT5677_DD1_MIXER               , 0xaaaa},
105         {RT5677_DD2_MIXER               , 0xaaaa},
106         {RT5677_IF3_DATA                , 0x0000},
107         {RT5677_IF4_DATA                , 0x0000},
108         {RT5677_PDM_OUT_CTRL            , 0x8888},
109         {RT5677_PDM_DATA_CTRL1          , 0x0000},
110         {RT5677_PDM_DATA_CTRL2          , 0x0000},
111         {RT5677_PDM1_DATA_CTRL2         , 0x0000},
112         {RT5677_PDM1_DATA_CTRL3         , 0x0000},
113         {RT5677_PDM1_DATA_CTRL4         , 0x0000},
114         {RT5677_PDM2_DATA_CTRL2         , 0x0000},
115         {RT5677_PDM2_DATA_CTRL3         , 0x0000},
116         {RT5677_PDM2_DATA_CTRL4         , 0x0000},
117         {RT5677_TDM1_CTRL1              , 0x0300},
118         {RT5677_TDM1_CTRL2              , 0x0000},
119         {RT5677_TDM1_CTRL3              , 0x4000},
120         {RT5677_TDM1_CTRL4              , 0x0123},
121         {RT5677_TDM1_CTRL5              , 0x4567},
122         {RT5677_TDM2_CTRL1              , 0x0300},
123         {RT5677_TDM2_CTRL2              , 0x0000},
124         {RT5677_TDM2_CTRL3              , 0x4000},
125         {RT5677_TDM2_CTRL4              , 0x0123},
126         {RT5677_TDM2_CTRL5              , 0x4567},
127         {RT5677_I2C_MASTER_CTRL1        , 0x0001},
128         {RT5677_I2C_MASTER_CTRL2        , 0x0000},
129         {RT5677_I2C_MASTER_CTRL3        , 0x0000},
130         {RT5677_I2C_MASTER_CTRL4        , 0x0000},
131         {RT5677_I2C_MASTER_CTRL5        , 0x0000},
132         {RT5677_I2C_MASTER_CTRL6        , 0x0000},
133         {RT5677_I2C_MASTER_CTRL7        , 0x0000},
134         {RT5677_I2C_MASTER_CTRL8        , 0x0000},
135         {RT5677_DMIC_CTRL1              , 0x1505},
136         {RT5677_DMIC_CTRL2              , 0x0055},
137         {RT5677_HAP_GENE_CTRL1          , 0x0111},
138         {RT5677_HAP_GENE_CTRL2          , 0x0064},
139         {RT5677_HAP_GENE_CTRL3          , 0xef0e},
140         {RT5677_HAP_GENE_CTRL4          , 0xf0f0},
141         {RT5677_HAP_GENE_CTRL5          , 0xef0e},
142         {RT5677_HAP_GENE_CTRL6          , 0xf0f0},
143         {RT5677_HAP_GENE_CTRL7          , 0xef0e},
144         {RT5677_HAP_GENE_CTRL8          , 0xf0f0},
145         {RT5677_HAP_GENE_CTRL9          , 0xf000},
146         {RT5677_HAP_GENE_CTRL10         , 0x0000},
147         {RT5677_PWR_DIG1                , 0x0000},
148         {RT5677_PWR_DIG2                , 0x0000},
149         {RT5677_PWR_ANLG1               , 0x0055},
150         {RT5677_PWR_ANLG2               , 0x0000},
151         {RT5677_PWR_DSP1                , 0x0001},
152         {RT5677_PWR_DSP_ST              , 0x0000},
153         {RT5677_PWR_DSP2                , 0x0000},
154         {RT5677_ADC_DAC_HPF_CTRL1       , 0x0e00},
155         {RT5677_PRIV_INDEX              , 0x0000},
156         {RT5677_PRIV_DATA               , 0x0000},
157         {RT5677_I2S4_SDP                , 0x8000},
158         {RT5677_I2S1_SDP                , 0x8000},
159         {RT5677_I2S2_SDP                , 0x8000},
160         {RT5677_I2S3_SDP                , 0x8000},
161         {RT5677_CLK_TREE_CTRL1          , 0x1111},
162         {RT5677_CLK_TREE_CTRL2          , 0x1111},
163         {RT5677_CLK_TREE_CTRL3          , 0x0000},
164         {RT5677_PLL1_CTRL1              , 0x0000},
165         {RT5677_PLL1_CTRL2              , 0x0000},
166         {RT5677_PLL2_CTRL1              , 0x0c60},
167         {RT5677_PLL2_CTRL2              , 0x2000},
168         {RT5677_GLB_CLK1                , 0x0000},
169         {RT5677_GLB_CLK2                , 0x0000},
170         {RT5677_ASRC_1                  , 0x0000},
171         {RT5677_ASRC_2                  , 0x0000},
172         {RT5677_ASRC_3                  , 0x0000},
173         {RT5677_ASRC_4                  , 0x0000},
174         {RT5677_ASRC_5                  , 0x0000},
175         {RT5677_ASRC_6                  , 0x0000},
176         {RT5677_ASRC_7                  , 0x0000},
177         {RT5677_ASRC_8                  , 0x0000},
178         {RT5677_ASRC_9                  , 0x0000},
179         {RT5677_ASRC_10                 , 0x0000},
180         {RT5677_ASRC_11                 , 0x0000},
181         {RT5677_ASRC_12                 , 0x0018},
182         {RT5677_ASRC_13                 , 0x0000},
183         {RT5677_ASRC_14                 , 0x0000},
184         {RT5677_ASRC_15                 , 0x0000},
185         {RT5677_ASRC_16                 , 0x0000},
186         {RT5677_ASRC_17                 , 0x0000},
187         {RT5677_ASRC_18                 , 0x0000},
188         {RT5677_ASRC_19                 , 0x0000},
189         {RT5677_ASRC_20                 , 0x0000},
190         {RT5677_ASRC_21                 , 0x000c},
191         {RT5677_ASRC_22                 , 0x0000},
192         {RT5677_ASRC_23                 , 0x0000},
193         {RT5677_VAD_CTRL1               , 0x2184},
194         {RT5677_VAD_CTRL2               , 0x010a},
195         {RT5677_VAD_CTRL3               , 0x0aea},
196         {RT5677_VAD_CTRL4               , 0x000c},
197         {RT5677_VAD_CTRL5               , 0x0000},
198         {RT5677_DSP_INB_CTRL1           , 0x0000},
199         {RT5677_DSP_INB_CTRL2           , 0x0000},
200         {RT5677_DSP_IN_OUTB_CTRL        , 0x0000},
201         {RT5677_DSP_OUTB0_1_DIG_VOL     , 0x2f2f},
202         {RT5677_DSP_OUTB2_3_DIG_VOL     , 0x2f2f},
203         {RT5677_DSP_OUTB4_5_DIG_VOL     , 0x2f2f},
204         {RT5677_DSP_OUTB6_7_DIG_VOL     , 0x2f2f},
205         {RT5677_ADC_EQ_CTRL1            , 0x6000},
206         {RT5677_ADC_EQ_CTRL2            , 0x0000},
207         {RT5677_EQ_CTRL1                , 0xc000},
208         {RT5677_EQ_CTRL2                , 0x0000},
209         {RT5677_EQ_CTRL3                , 0x0000},
210         {RT5677_SOFT_VOL_ZERO_CROSS1    , 0x0009},
211         {RT5677_JD_CTRL1                , 0x0000},
212         {RT5677_JD_CTRL2                , 0x0000},
213         {RT5677_JD_CTRL3                , 0x0000},
214         {RT5677_IRQ_CTRL1               , 0x0000},
215         {RT5677_IRQ_CTRL2               , 0x0000},
216         {RT5677_GPIO_ST                 , 0x0000},
217         {RT5677_GPIO_CTRL1              , 0x0000},
218         {RT5677_GPIO_CTRL2              , 0x0000},
219         {RT5677_GPIO_CTRL3              , 0x0000},
220         {RT5677_STO1_ADC_HI_FILTER1     , 0xb320},
221         {RT5677_STO1_ADC_HI_FILTER2     , 0x0000},
222         {RT5677_MONO_ADC_HI_FILTER1     , 0xb300},
223         {RT5677_MONO_ADC_HI_FILTER2     , 0x0000},
224         {RT5677_STO2_ADC_HI_FILTER1     , 0xb300},
225         {RT5677_STO2_ADC_HI_FILTER2     , 0x0000},
226         {RT5677_STO3_ADC_HI_FILTER1     , 0xb300},
227         {RT5677_STO3_ADC_HI_FILTER2     , 0x0000},
228         {RT5677_STO4_ADC_HI_FILTER1     , 0xb300},
229         {RT5677_STO4_ADC_HI_FILTER2     , 0x0000},
230         {RT5677_MB_DRC_CTRL1            , 0x0f20},
231         {RT5677_DRC1_CTRL1              , 0x001f},
232         {RT5677_DRC1_CTRL2              , 0x020c},
233         {RT5677_DRC1_CTRL3              , 0x1f00},
234         {RT5677_DRC1_CTRL4              , 0x0000},
235         {RT5677_DRC1_CTRL5              , 0x0000},
236         {RT5677_DRC1_CTRL6              , 0x0029},
237         {RT5677_DRC2_CTRL1              , 0x001f},
238         {RT5677_DRC2_CTRL2              , 0x020c},
239         {RT5677_DRC2_CTRL3              , 0x1f00},
240         {RT5677_DRC2_CTRL4              , 0x0000},
241         {RT5677_DRC2_CTRL5              , 0x0000},
242         {RT5677_DRC2_CTRL6              , 0x0029},
243         {RT5677_DRC1_HL_CTRL1           , 0x8000},
244         {RT5677_DRC1_HL_CTRL2           , 0x0200},
245         {RT5677_DRC2_HL_CTRL1           , 0x8000},
246         {RT5677_DRC2_HL_CTRL2           , 0x0200},
247         {RT5677_DSP_INB1_SRC_CTRL1      , 0x5800},
248         {RT5677_DSP_INB1_SRC_CTRL2      , 0x0000},
249         {RT5677_DSP_INB1_SRC_CTRL3      , 0x0000},
250         {RT5677_DSP_INB1_SRC_CTRL4      , 0x0800},
251         {RT5677_DSP_INB2_SRC_CTRL1      , 0x5800},
252         {RT5677_DSP_INB2_SRC_CTRL2      , 0x0000},
253         {RT5677_DSP_INB2_SRC_CTRL3      , 0x0000},
254         {RT5677_DSP_INB2_SRC_CTRL4      , 0x0800},
255         {RT5677_DSP_INB3_SRC_CTRL1      , 0x5800},
256         {RT5677_DSP_INB3_SRC_CTRL2      , 0x0000},
257         {RT5677_DSP_INB3_SRC_CTRL3      , 0x0000},
258         {RT5677_DSP_INB3_SRC_CTRL4      , 0x0800},
259         {RT5677_DSP_OUTB1_SRC_CTRL1     , 0x5800},
260         {RT5677_DSP_OUTB1_SRC_CTRL2     , 0x0000},
261         {RT5677_DSP_OUTB1_SRC_CTRL3     , 0x0000},
262         {RT5677_DSP_OUTB1_SRC_CTRL4     , 0x0800},
263         {RT5677_DSP_OUTB2_SRC_CTRL1     , 0x5800},
264         {RT5677_DSP_OUTB2_SRC_CTRL2     , 0x0000},
265         {RT5677_DSP_OUTB2_SRC_CTRL3     , 0x0000},
266         {RT5677_DSP_OUTB2_SRC_CTRL4     , 0x0800},
267         {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
268         {RT5677_DSP_OUTB_45_MIXER_CTRL  , 0xfefe},
269         {RT5677_DSP_OUTB_67_MIXER_CTRL  , 0xfefe},
270         {RT5677_DIG_MISC                , 0x0000},
271         {RT5677_GEN_CTRL1               , 0x0000},
272         {RT5677_GEN_CTRL2               , 0x0000},
273         {RT5677_VENDOR_ID               , 0x0000},
274         {RT5677_VENDOR_ID1              , 0x10ec},
275         {RT5677_VENDOR_ID2              , 0x6327},
276 };
277 
278 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
279 {
280         int i;
281 
282         for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
283                 if (reg >= rt5677_ranges[i].range_min &&
284                         reg <= rt5677_ranges[i].range_max) {
285                         return true;
286                 }
287         }
288 
289         switch (reg) {
290         case RT5677_RESET:
291         case RT5677_SLIMBUS_PARAM:
292         case RT5677_PDM_DATA_CTRL1:
293         case RT5677_PDM_DATA_CTRL2:
294         case RT5677_PDM1_DATA_CTRL4:
295         case RT5677_PDM2_DATA_CTRL4:
296         case RT5677_I2C_MASTER_CTRL1:
297         case RT5677_I2C_MASTER_CTRL7:
298         case RT5677_I2C_MASTER_CTRL8:
299         case RT5677_HAP_GENE_CTRL2:
300         case RT5677_PWR_DSP_ST:
301         case RT5677_PRIV_DATA:
302         case RT5677_ASRC_22:
303         case RT5677_ASRC_23:
304         case RT5677_VAD_CTRL5:
305         case RT5677_ADC_EQ_CTRL1:
306         case RT5677_EQ_CTRL1:
307         case RT5677_IRQ_CTRL1:
308         case RT5677_IRQ_CTRL2:
309         case RT5677_GPIO_ST:
310         case RT5677_DSP_INB1_SRC_CTRL4:
311         case RT5677_DSP_INB2_SRC_CTRL4:
312         case RT5677_DSP_INB3_SRC_CTRL4:
313         case RT5677_DSP_OUTB1_SRC_CTRL4:
314         case RT5677_DSP_OUTB2_SRC_CTRL4:
315         case RT5677_VENDOR_ID:
316         case RT5677_VENDOR_ID1:
317         case RT5677_VENDOR_ID2:
318                 return true;
319         default:
320                 return false;
321         }
322 }
323 
324 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
325 {
326         int i;
327 
328         for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
329                 if (reg >= rt5677_ranges[i].range_min &&
330                         reg <= rt5677_ranges[i].range_max) {
331                         return true;
332                 }
333         }
334 
335         switch (reg) {
336         case RT5677_RESET:
337         case RT5677_LOUT1:
338         case RT5677_IN1:
339         case RT5677_MICBIAS:
340         case RT5677_SLIMBUS_PARAM:
341         case RT5677_SLIMBUS_RX:
342         case RT5677_SLIMBUS_CTRL:
343         case RT5677_SIDETONE_CTRL:
344         case RT5677_ANA_DAC1_2_3_SRC:
345         case RT5677_IF_DSP_DAC3_4_MIXER:
346         case RT5677_DAC4_DIG_VOL:
347         case RT5677_DAC3_DIG_VOL:
348         case RT5677_DAC1_DIG_VOL:
349         case RT5677_DAC2_DIG_VOL:
350         case RT5677_IF_DSP_DAC2_MIXER:
351         case RT5677_STO1_ADC_DIG_VOL:
352         case RT5677_MONO_ADC_DIG_VOL:
353         case RT5677_STO1_2_ADC_BST:
354         case RT5677_STO2_ADC_DIG_VOL:
355         case RT5677_ADC_BST_CTRL2:
356         case RT5677_STO3_4_ADC_BST:
357         case RT5677_STO3_ADC_DIG_VOL:
358         case RT5677_STO4_ADC_DIG_VOL:
359         case RT5677_STO4_ADC_MIXER:
360         case RT5677_STO3_ADC_MIXER:
361         case RT5677_STO2_ADC_MIXER:
362         case RT5677_STO1_ADC_MIXER:
363         case RT5677_MONO_ADC_MIXER:
364         case RT5677_ADC_IF_DSP_DAC1_MIXER:
365         case RT5677_STO1_DAC_MIXER:
366         case RT5677_MONO_DAC_MIXER:
367         case RT5677_DD1_MIXER:
368         case RT5677_DD2_MIXER:
369         case RT5677_IF3_DATA:
370         case RT5677_IF4_DATA:
371         case RT5677_PDM_OUT_CTRL:
372         case RT5677_PDM_DATA_CTRL1:
373         case RT5677_PDM_DATA_CTRL2:
374         case RT5677_PDM1_DATA_CTRL2:
375         case RT5677_PDM1_DATA_CTRL3:
376         case RT5677_PDM1_DATA_CTRL4:
377         case RT5677_PDM2_DATA_CTRL2:
378         case RT5677_PDM2_DATA_CTRL3:
379         case RT5677_PDM2_DATA_CTRL4:
380         case RT5677_TDM1_CTRL1:
381         case RT5677_TDM1_CTRL2:
382         case RT5677_TDM1_CTRL3:
383         case RT5677_TDM1_CTRL4:
384         case RT5677_TDM1_CTRL5:
385         case RT5677_TDM2_CTRL1:
386         case RT5677_TDM2_CTRL2:
387         case RT5677_TDM2_CTRL3:
388         case RT5677_TDM2_CTRL4:
389         case RT5677_TDM2_CTRL5:
390         case RT5677_I2C_MASTER_CTRL1:
391         case RT5677_I2C_MASTER_CTRL2:
392         case RT5677_I2C_MASTER_CTRL3:
393         case RT5677_I2C_MASTER_CTRL4:
394         case RT5677_I2C_MASTER_CTRL5:
395         case RT5677_I2C_MASTER_CTRL6:
396         case RT5677_I2C_MASTER_CTRL7:
397         case RT5677_I2C_MASTER_CTRL8:
398         case RT5677_DMIC_CTRL1:
399         case RT5677_DMIC_CTRL2:
400         case RT5677_HAP_GENE_CTRL1:
401         case RT5677_HAP_GENE_CTRL2:
402         case RT5677_HAP_GENE_CTRL3:
403         case RT5677_HAP_GENE_CTRL4:
404         case RT5677_HAP_GENE_CTRL5:
405         case RT5677_HAP_GENE_CTRL6:
406         case RT5677_HAP_GENE_CTRL7:
407         case RT5677_HAP_GENE_CTRL8:
408         case RT5677_HAP_GENE_CTRL9:
409         case RT5677_HAP_GENE_CTRL10:
410         case RT5677_PWR_DIG1:
411         case RT5677_PWR_DIG2:
412         case RT5677_PWR_ANLG1:
413         case RT5677_PWR_ANLG2:
414         case RT5677_PWR_DSP1:
415         case RT5677_PWR_DSP_ST:
416         case RT5677_PWR_DSP2:
417         case RT5677_ADC_DAC_HPF_CTRL1:
418         case RT5677_PRIV_INDEX:
419         case RT5677_PRIV_DATA:
420         case RT5677_I2S4_SDP:
421         case RT5677_I2S1_SDP:
422         case RT5677_I2S2_SDP:
423         case RT5677_I2S3_SDP:
424         case RT5677_CLK_TREE_CTRL1:
425         case RT5677_CLK_TREE_CTRL2:
426         case RT5677_CLK_TREE_CTRL3:
427         case RT5677_PLL1_CTRL1:
428         case RT5677_PLL1_CTRL2:
429         case RT5677_PLL2_CTRL1:
430         case RT5677_PLL2_CTRL2:
431         case RT5677_GLB_CLK1:
432         case RT5677_GLB_CLK2:
433         case RT5677_ASRC_1:
434         case RT5677_ASRC_2:
435         case RT5677_ASRC_3:
436         case RT5677_ASRC_4:
437         case RT5677_ASRC_5:
438         case RT5677_ASRC_6:
439         case RT5677_ASRC_7:
440         case RT5677_ASRC_8:
441         case RT5677_ASRC_9:
442         case RT5677_ASRC_10:
443         case RT5677_ASRC_11:
444         case RT5677_ASRC_12:
445         case RT5677_ASRC_13:
446         case RT5677_ASRC_14:
447         case RT5677_ASRC_15:
448         case RT5677_ASRC_16:
449         case RT5677_ASRC_17:
450         case RT5677_ASRC_18:
451         case RT5677_ASRC_19:
452         case RT5677_ASRC_20:
453         case RT5677_ASRC_21:
454         case RT5677_ASRC_22:
455         case RT5677_ASRC_23:
456         case RT5677_VAD_CTRL1:
457         case RT5677_VAD_CTRL2:
458         case RT5677_VAD_CTRL3:
459         case RT5677_VAD_CTRL4:
460         case RT5677_VAD_CTRL5:
461         case RT5677_DSP_INB_CTRL1:
462         case RT5677_DSP_INB_CTRL2:
463         case RT5677_DSP_IN_OUTB_CTRL:
464         case RT5677_DSP_OUTB0_1_DIG_VOL:
465         case RT5677_DSP_OUTB2_3_DIG_VOL:
466         case RT5677_DSP_OUTB4_5_DIG_VOL:
467         case RT5677_DSP_OUTB6_7_DIG_VOL:
468         case RT5677_ADC_EQ_CTRL1:
469         case RT5677_ADC_EQ_CTRL2:
470         case RT5677_EQ_CTRL1:
471         case RT5677_EQ_CTRL2:
472         case RT5677_EQ_CTRL3:
473         case RT5677_SOFT_VOL_ZERO_CROSS1:
474         case RT5677_JD_CTRL1:
475         case RT5677_JD_CTRL2:
476         case RT5677_JD_CTRL3:
477         case RT5677_IRQ_CTRL1:
478         case RT5677_IRQ_CTRL2:
479         case RT5677_GPIO_ST:
480         case RT5677_GPIO_CTRL1:
481         case RT5677_GPIO_CTRL2:
482         case RT5677_GPIO_CTRL3:
483         case RT5677_STO1_ADC_HI_FILTER1:
484         case RT5677_STO1_ADC_HI_FILTER2:
485         case RT5677_MONO_ADC_HI_FILTER1:
486         case RT5677_MONO_ADC_HI_FILTER2:
487         case RT5677_STO2_ADC_HI_FILTER1:
488         case RT5677_STO2_ADC_HI_FILTER2:
489         case RT5677_STO3_ADC_HI_FILTER1:
490         case RT5677_STO3_ADC_HI_FILTER2:
491         case RT5677_STO4_ADC_HI_FILTER1:
492         case RT5677_STO4_ADC_HI_FILTER2:
493         case RT5677_MB_DRC_CTRL1:
494         case RT5677_DRC1_CTRL1:
495         case RT5677_DRC1_CTRL2:
496         case RT5677_DRC1_CTRL3:
497         case RT5677_DRC1_CTRL4:
498         case RT5677_DRC1_CTRL5:
499         case RT5677_DRC1_CTRL6:
500         case RT5677_DRC2_CTRL1:
501         case RT5677_DRC2_CTRL2:
502         case RT5677_DRC2_CTRL3:
503         case RT5677_DRC2_CTRL4:
504         case RT5677_DRC2_CTRL5:
505         case RT5677_DRC2_CTRL6:
506         case RT5677_DRC1_HL_CTRL1:
507         case RT5677_DRC1_HL_CTRL2:
508         case RT5677_DRC2_HL_CTRL1:
509         case RT5677_DRC2_HL_CTRL2:
510         case RT5677_DSP_INB1_SRC_CTRL1:
511         case RT5677_DSP_INB1_SRC_CTRL2:
512         case RT5677_DSP_INB1_SRC_CTRL3:
513         case RT5677_DSP_INB1_SRC_CTRL4:
514         case RT5677_DSP_INB2_SRC_CTRL1:
515         case RT5677_DSP_INB2_SRC_CTRL2:
516         case RT5677_DSP_INB2_SRC_CTRL3:
517         case RT5677_DSP_INB2_SRC_CTRL4:
518         case RT5677_DSP_INB3_SRC_CTRL1:
519         case RT5677_DSP_INB3_SRC_CTRL2:
520         case RT5677_DSP_INB3_SRC_CTRL3:
521         case RT5677_DSP_INB3_SRC_CTRL4:
522         case RT5677_DSP_OUTB1_SRC_CTRL1:
523         case RT5677_DSP_OUTB1_SRC_CTRL2:
524         case RT5677_DSP_OUTB1_SRC_CTRL3:
525         case RT5677_DSP_OUTB1_SRC_CTRL4:
526         case RT5677_DSP_OUTB2_SRC_CTRL1:
527         case RT5677_DSP_OUTB2_SRC_CTRL2:
528         case RT5677_DSP_OUTB2_SRC_CTRL3:
529         case RT5677_DSP_OUTB2_SRC_CTRL4:
530         case RT5677_DSP_OUTB_0123_MIXER_CTRL:
531         case RT5677_DSP_OUTB_45_MIXER_CTRL:
532         case RT5677_DSP_OUTB_67_MIXER_CTRL:
533         case RT5677_DIG_MISC:
534         case RT5677_GEN_CTRL1:
535         case RT5677_GEN_CTRL2:
536         case RT5677_VENDOR_ID:
537         case RT5677_VENDOR_ID1:
538         case RT5677_VENDOR_ID2:
539                 return true;
540         default:
541                 return false;
542         }
543 }
544 
545 /**
546  * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
547  * @rt5677: Private Data.
548  * @addr: Address index.
549  * @value: Address data.
550  *
551  *
552  * Returns 0 for success or negative error code.
553  */
554 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
555                 unsigned int addr, unsigned int value, unsigned int opcode)
556 {
557         struct snd_soc_component *component = rt5677->component;
558         int ret;
559 
560         mutex_lock(&rt5677->dsp_cmd_lock);
561 
562         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563                 addr >> 16);
564         if (ret < 0) {
565                 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
566                 goto err;
567         }
568 
569         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570                 addr & 0xffff);
571         if (ret < 0) {
572                 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
573                 goto err;
574         }
575 
576         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577                 value >> 16);
578         if (ret < 0) {
579                 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
580                 goto err;
581         }
582 
583         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584                 value & 0xffff);
585         if (ret < 0) {
586                 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
587                 goto err;
588         }
589 
590         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591                 opcode);
592         if (ret < 0) {
593                 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
594                 goto err;
595         }
596 
597 err:
598         mutex_unlock(&rt5677->dsp_cmd_lock);
599 
600         return ret;
601 }
602 
603 /**
604  * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
605  * rt5677: Private Data.
606  * @addr: Address index.
607  * @value: Address data.
608  *
609  *
610  * Returns 0 for success or negative error code.
611  */
612 static int rt5677_dsp_mode_i2c_read_addr(
613         struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
614 {
615         struct snd_soc_component *component = rt5677->component;
616         int ret;
617         unsigned int msb, lsb;
618 
619         mutex_lock(&rt5677->dsp_cmd_lock);
620 
621         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622                 addr >> 16);
623         if (ret < 0) {
624                 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
625                 goto err;
626         }
627 
628         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629                 addr & 0xffff);
630         if (ret < 0) {
631                 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
632                 goto err;
633         }
634 
635         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636                 0x0002);
637         if (ret < 0) {
638                 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
639                 goto err;
640         }
641 
642         regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
643         regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
644         *value = (msb << 16) | lsb;
645 
646 err:
647         mutex_unlock(&rt5677->dsp_cmd_lock);
648 
649         return ret;
650 }
651 
652 /**
653  * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
654  * rt5677: Private Data.
655  * @reg: Register index.
656  * @value: Register data.
657  *
658  *
659  * Returns 0 for success or negative error code.
660  */
661 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
662                 unsigned int reg, unsigned int value)
663 {
664         return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
665                 value, 0x0001);
666 }
667 
668 /**
669  * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
670  * @codec: SoC audio codec device.
671  * @reg: Register index.
672  * @value: Register data.
673  *
674  *
675  * Returns 0 for success or negative error code.
676  */
677 static int rt5677_dsp_mode_i2c_read(
678         struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
679 {
680         int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
681                 value);
682 
683         *value &= 0xffff;
684 
685         return ret;
686 }
687 
688 static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on)
689 {
690         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
691 
692         if (on) {
693                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
694                 rt5677->is_dsp_mode = true;
695         } else {
696                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
697                 rt5677->is_dsp_mode = false;
698         }
699 }
700 
701 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
702 {
703         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
704         static bool activity;
705         int ret;
706 
707         if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
708                 return -ENXIO;
709 
710         if (on && !activity) {
711                 activity = true;
712 
713                 regcache_cache_only(rt5677->regmap, false);
714                 regcache_cache_bypass(rt5677->regmap, true);
715 
716                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
717                 regmap_update_bits(rt5677->regmap,
718                         RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
719                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
720                         RT5677_LDO1_SEL_MASK, 0x0);
721                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
722                         RT5677_PWR_LDO1, RT5677_PWR_LDO1);
723                 switch (rt5677->type) {
724                 case RT5677:
725                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
726                                 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
727                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
728                                 RT5677_PLL2_PR_SRC_MASK |
729                                 RT5677_DSP_CLK_SRC_MASK,
730                                 RT5677_PLL2_PR_SRC_MCLK2 |
731                                 RT5677_DSP_CLK_SRC_BYPASS);
732                         break;
733                 case RT5676:
734                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
735                                 RT5677_DSP_CLK_SRC_MASK,
736                                 RT5677_DSP_CLK_SRC_BYPASS);
737                         break;
738                 default:
739                         break;
740                 }
741                 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
742                 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
743                 rt5677_set_dsp_mode(component, true);
744 
745                 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
746                         component->dev);
747                 if (ret == 0) {
748                         rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
749                         release_firmware(rt5677->fw1);
750                 }
751 
752                 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
753                         component->dev);
754                 if (ret == 0) {
755                         rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
756                         release_firmware(rt5677->fw2);
757                 }
758 
759                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
760 
761                 regcache_cache_bypass(rt5677->regmap, false);
762                 regcache_cache_only(rt5677->regmap, true);
763         } else if (!on && activity) {
764                 activity = false;
765 
766                 regcache_cache_only(rt5677->regmap, false);
767                 regcache_cache_bypass(rt5677->regmap, true);
768 
769                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
770                 rt5677_set_dsp_mode(component, false);
771                 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
772 
773                 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
774 
775                 regcache_cache_bypass(rt5677->regmap, false);
776                 regcache_mark_dirty(rt5677->regmap);
777                 regcache_sync(rt5677->regmap);
778         }
779 
780         return 0;
781 }
782 
783 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
784 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
786 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
787 
788 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
789 static const DECLARE_TLV_DB_RANGE(bst_tlv,
790         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
791         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
792         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
793         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
794         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
795         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
796         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
797 );
798 
799 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
800                 struct snd_ctl_elem_value *ucontrol)
801 {
802         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
803         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
804 
805         ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
806 
807         return 0;
808 }
809 
810 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
811                 struct snd_ctl_elem_value *ucontrol)
812 {
813         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
814         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
815 
816         rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
817 
818         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
819                 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en);
820 
821         return 0;
822 }
823 
824 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
825         /* OUTPUT Control */
826         SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
827                 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
828         SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
829                 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
830         SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
831                 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
832 
833         /* DAC Digital Volume */
834         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
835                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
836         SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
837                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
838         SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
839                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
840         SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
841                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
842 
843         /* IN1/IN2 Control */
844         SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
845         SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
846 
847         /* ADC Digital Volume Control */
848         SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
849                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
850         SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
851                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
852         SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
853                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854         SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
855                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856         SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
857                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 
859         SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
860                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
861                 adc_vol_tlv),
862         SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
863                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
864                 adc_vol_tlv),
865         SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
866                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
867                 adc_vol_tlv),
868         SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
869                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
870                 adc_vol_tlv),
871         SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
872                 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
873                 adc_vol_tlv),
874 
875         /* Sidetone Control */
876         SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
877                 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
878 
879         /* ADC Boost Volume Control */
880         SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
881                 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
882                 adc_bst_tlv),
883         SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
884                 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
885                 adc_bst_tlv),
886         SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
887                 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
888                 adc_bst_tlv),
889         SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
890                 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
891                 adc_bst_tlv),
892         SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
893                 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
894                 adc_bst_tlv),
895 
896         SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
897                 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
898 };
899 
900 /**
901  * set_dmic_clk - Set parameter of dmic.
902  *
903  * @w: DAPM widget.
904  * @kcontrol: The kcontrol of this widget.
905  * @event: Event id.
906  *
907  * Choose dmic clock between 1MHz and 3MHz.
908  * It is better for clock to approximate 3MHz.
909  */
910 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
911         struct snd_kcontrol *kcontrol, int event)
912 {
913         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
914         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
915         int idx, rate;
916 
917         rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
918                 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
919         idx = rl6231_calc_dmic_clk(rate);
920         if (idx < 0)
921                 dev_err(component->dev, "Failed to set DMIC clock\n");
922         else
923                 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
924                         RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
925         return idx;
926 }
927 
928 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
929                          struct snd_soc_dapm_widget *sink)
930 {
931         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
932         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
933         unsigned int val;
934 
935         regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
936         val &= RT5677_SCLK_SRC_MASK;
937         if (val == RT5677_SCLK_SRC_PLL1)
938                 return 1;
939         else
940                 return 0;
941 }
942 
943 static int is_using_asrc(struct snd_soc_dapm_widget *source,
944                          struct snd_soc_dapm_widget *sink)
945 {
946         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
947         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
948         unsigned int reg, shift, val;
949 
950         if (source->reg == RT5677_ASRC_1) {
951                 switch (source->shift) {
952                 case 12:
953                         reg = RT5677_ASRC_4;
954                         shift = 0;
955                         break;
956                 case 13:
957                         reg = RT5677_ASRC_4;
958                         shift = 4;
959                         break;
960                 case 14:
961                         reg = RT5677_ASRC_4;
962                         shift = 8;
963                         break;
964                 case 15:
965                         reg = RT5677_ASRC_4;
966                         shift = 12;
967                         break;
968                 default:
969                         return 0;
970                 }
971         } else {
972                 switch (source->shift) {
973                 case 0:
974                         reg = RT5677_ASRC_6;
975                         shift = 8;
976                         break;
977                 case 1:
978                         reg = RT5677_ASRC_6;
979                         shift = 12;
980                         break;
981                 case 2:
982                         reg = RT5677_ASRC_5;
983                         shift = 0;
984                         break;
985                 case 3:
986                         reg = RT5677_ASRC_5;
987                         shift = 4;
988                         break;
989                 case 4:
990                         reg = RT5677_ASRC_5;
991                         shift = 8;
992                         break;
993                 case 5:
994                         reg = RT5677_ASRC_5;
995                         shift = 12;
996                         break;
997                 case 12:
998                         reg = RT5677_ASRC_3;
999                         shift = 0;
1000                         break;
1001                 case 13:
1002                         reg = RT5677_ASRC_3;
1003                         shift = 4;
1004                         break;
1005                 case 14:
1006                         reg = RT5677_ASRC_3;
1007                         shift = 12;
1008                         break;
1009                 default:
1010                         return 0;
1011                 }
1012         }
1013 
1014         regmap_read(rt5677->regmap, reg, &val);
1015         val = (val >> shift) & 0xf;
1016 
1017         switch (val) {
1018         case 1 ... 6:
1019                 return 1;
1020         default:
1021                 return 0;
1022         }
1023 
1024 }
1025 
1026 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1027                          struct snd_soc_dapm_widget *sink)
1028 {
1029         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1030         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1031 
1032         if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1033                 return 1;
1034 
1035         return 0;
1036 }
1037 
1038 /**
1039  * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1040  * @component: SoC audio component device.
1041  * @filter_mask: mask of filters.
1042  * @clk_src: clock source
1043  *
1044  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1045  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1046  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1047  * ASRC function will track i2s clock and generate a corresponding system clock
1048  * for codec. This function provides an API to select the clock source for a
1049  * set of filters specified by the mask. And the codec driver will turn on ASRC
1050  * for these filters if ASRC is selected as their clock source.
1051  */
1052 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
1053                 unsigned int filter_mask, unsigned int clk_src)
1054 {
1055         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1056         unsigned int asrc3_mask = 0, asrc3_value = 0;
1057         unsigned int asrc4_mask = 0, asrc4_value = 0;
1058         unsigned int asrc5_mask = 0, asrc5_value = 0;
1059         unsigned int asrc6_mask = 0, asrc6_value = 0;
1060         unsigned int asrc7_mask = 0, asrc7_value = 0;
1061         unsigned int asrc8_mask = 0, asrc8_value = 0;
1062 
1063         switch (clk_src) {
1064         case RT5677_CLK_SEL_SYS:
1065         case RT5677_CLK_SEL_I2S1_ASRC:
1066         case RT5677_CLK_SEL_I2S2_ASRC:
1067         case RT5677_CLK_SEL_I2S3_ASRC:
1068         case RT5677_CLK_SEL_I2S4_ASRC:
1069         case RT5677_CLK_SEL_I2S5_ASRC:
1070         case RT5677_CLK_SEL_I2S6_ASRC:
1071         case RT5677_CLK_SEL_SYS2:
1072         case RT5677_CLK_SEL_SYS3:
1073         case RT5677_CLK_SEL_SYS4:
1074         case RT5677_CLK_SEL_SYS5:
1075         case RT5677_CLK_SEL_SYS6:
1076         case RT5677_CLK_SEL_SYS7:
1077                 break;
1078 
1079         default:
1080                 return -EINVAL;
1081         }
1082 
1083         /* ASRC 3 */
1084         if (filter_mask & RT5677_DA_STEREO_FILTER) {
1085                 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1086                 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1087                         | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1088         }
1089 
1090         if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1091                 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1092                 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1093                         | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1094         }
1095 
1096         if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1097                 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1098                 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1099                         | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1100         }
1101 
1102         if (asrc3_mask)
1103                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1104                         asrc3_value);
1105 
1106         /* ASRC 4 */
1107         if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1108                 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1109                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1110                         | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1111         }
1112 
1113         if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1114                 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1115                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1116                         | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1117         }
1118 
1119         if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1120                 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1121                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1122                         | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1123         }
1124 
1125         if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1126                 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1127                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1128                         | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1129         }
1130 
1131         if (asrc4_mask)
1132                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1133                         asrc4_value);
1134 
1135         /* ASRC 5 */
1136         if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1137                 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1138                 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1139                         | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1140         }
1141 
1142         if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1143                 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1144                 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1145                         | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1146         }
1147 
1148         if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1149                 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1150                 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1151                         | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1152         }
1153 
1154         if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1155                 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1156                 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1157                         | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1158         }
1159 
1160         if (asrc5_mask)
1161                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1162                         asrc5_value);
1163 
1164         /* ASRC 6 */
1165         if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1166                 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1167                 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1168                         | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1169         }
1170 
1171         if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1172                 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1173                 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1174                         | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1175         }
1176 
1177         if (asrc6_mask)
1178                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1179                         asrc6_value);
1180 
1181         /* ASRC 7 */
1182         if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1183                 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1184                 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1185                         | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1186         }
1187 
1188         if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1189                 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1190                 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1191                         | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1192         }
1193 
1194         if (asrc7_mask)
1195                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1196                         asrc7_value);
1197 
1198         /* ASRC 8 */
1199         if (filter_mask & RT5677_I2S1_SOURCE) {
1200                 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1201                 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1202                         | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1203         }
1204 
1205         if (filter_mask & RT5677_I2S2_SOURCE) {
1206                 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1207                 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1208                         | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1209         }
1210 
1211         if (filter_mask & RT5677_I2S3_SOURCE) {
1212                 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1213                 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1214                         | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1215         }
1216 
1217         if (filter_mask & RT5677_I2S4_SOURCE) {
1218                 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1219                 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1220                         | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1221         }
1222 
1223         if (asrc8_mask)
1224                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1225                         asrc8_value);
1226 
1227         return 0;
1228 }
1229 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1230 
1231 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1232                          struct snd_soc_dapm_widget *sink)
1233 {
1234         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1235         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1236         unsigned int asrc_setting;
1237 
1238         switch (source->shift) {
1239         case 11:
1240                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1241                 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1242                                 RT5677_AD_STO1_CLK_SEL_SFT;
1243                 break;
1244 
1245         case 10:
1246                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1247                 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1248                                 RT5677_AD_STO2_CLK_SEL_SFT;
1249                 break;
1250 
1251         case 9:
1252                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1253                 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1254                                 RT5677_AD_STO3_CLK_SEL_SFT;
1255                 break;
1256 
1257         case 8:
1258                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1259                 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1260                         RT5677_AD_STO4_CLK_SEL_SFT;
1261                 break;
1262 
1263         case 7:
1264                 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1265                 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1266                         RT5677_AD_MONOL_CLK_SEL_SFT;
1267                 break;
1268 
1269         case 6:
1270                 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1271                 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1272                         RT5677_AD_MONOR_CLK_SEL_SFT;
1273                 break;
1274 
1275         default:
1276                 return 0;
1277         }
1278 
1279         if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1280             asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1281                 return 1;
1282 
1283         return 0;
1284 }
1285 
1286 /* Digital Mixer */
1287 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1288         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1289                         RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1290         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1291                         RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1292 };
1293 
1294 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1295         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1296                         RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1297         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1298                         RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1299 };
1300 
1301 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1302         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1303                         RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1304         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1305                         RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1306 };
1307 
1308 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1309         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1310                         RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1311         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1312                         RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1313 };
1314 
1315 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1316         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1317                         RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1318         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1319                         RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1320 };
1321 
1322 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1323         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1324                         RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1325         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1326                         RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1327 };
1328 
1329 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1330         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1331                         RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1332         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1333                         RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1334 };
1335 
1336 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1337         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1338                         RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1339         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1340                         RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1341 };
1342 
1343 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1344         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1345                         RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1346         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1347                         RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1348 };
1349 
1350 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1351         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1352                         RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1353         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1354                         RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1355 };
1356 
1357 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1358         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1359                         RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1360         SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1361                         RT5677_M_DAC1_L_SFT, 1, 1),
1362 };
1363 
1364 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1365         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1366                         RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1367         SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1368                         RT5677_M_DAC1_R_SFT, 1, 1),
1369 };
1370 
1371 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1372         SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1373                         RT5677_M_ST_DAC1_L_SFT, 1, 1),
1374         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1375                         RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1376         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1377                         RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1378         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1379                         RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1380 };
1381 
1382 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1383         SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1384                         RT5677_M_ST_DAC1_R_SFT, 1, 1),
1385         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1386                         RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1387         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1388                         RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1389         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1390                         RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1391 };
1392 
1393 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1394         SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1395                         RT5677_M_ST_DAC2_L_SFT, 1, 1),
1396         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1397                         RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1398         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1399                         RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1400         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1401                         RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1402 };
1403 
1404 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1405         SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1406                         RT5677_M_ST_DAC2_R_SFT, 1, 1),
1407         SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1408                         RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1409         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1410                         RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1411         SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1412                         RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1413 };
1414 
1415 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1416         SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1417                         RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1418         SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1419                         RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1420         SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1421                         RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1422         SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1423                         RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1424 };
1425 
1426 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1427         SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1428                         RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1429         SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1430                         RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1431         SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1432                         RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1433         SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1434                         RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1435 };
1436 
1437 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1438         SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1439                         RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1440         SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1441                         RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1442         SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1443                         RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1444         SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1445                         RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1446 };
1447 
1448 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1449         SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1450                         RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1451         SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1452                         RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1453         SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1454                         RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1455         SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1456                         RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1457 };
1458 
1459 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1460         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1461                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1462         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1463                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1464         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1465                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1466         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1467                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1468         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1469                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1470         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1471                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1472         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1473                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1474 };
1475 
1476 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1477         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1478                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1479         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1481         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1483         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1485         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1487         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1489         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1491 };
1492 
1493 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1494         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1495                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1496         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1497                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1498         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1499                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1500         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1501                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1502         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1503                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1504         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1505                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1506         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1507                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1508 };
1509 
1510 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1511         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1512                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1513         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1515         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1517         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1519         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1521         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1523         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1525 };
1526 
1527 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1528         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1529                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1530         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1531                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1532         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1533                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1534         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1535                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1536         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1537                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1538         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1539                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1540         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1541                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1542 };
1543 
1544 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1545         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1546                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1547         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1549         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1551         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1553         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1555         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1557         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1559 };
1560 
1561 
1562 /* Mux */
1563 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1564 static const char * const rt5677_dac1_src[] = {
1565         "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1566         "OB 01"
1567 };
1568 
1569 static SOC_ENUM_SINGLE_DECL(
1570         rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1571         RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1572 
1573 static const struct snd_kcontrol_new rt5677_dac1_mux =
1574         SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1575 
1576 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1577 static const char * const rt5677_adda1_src[] = {
1578         "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1579 };
1580 
1581 static SOC_ENUM_SINGLE_DECL(
1582         rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1583         RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1584 
1585 static const struct snd_kcontrol_new rt5677_adda1_mux =
1586         SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1587 
1588 
1589 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1590 static const char * const rt5677_dac2l_src[] = {
1591         "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1592         "OB 2",
1593 };
1594 
1595 static SOC_ENUM_SINGLE_DECL(
1596         rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1597         RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1598 
1599 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1600         SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1601 
1602 static const char * const rt5677_dac2r_src[] = {
1603         "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1604         "OB 3", "Haptic Generator", "VAD ADC"
1605 };
1606 
1607 static SOC_ENUM_SINGLE_DECL(
1608         rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1609         RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1610 
1611 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1612         SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1613 
1614 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1615 static const char * const rt5677_dac3l_src[] = {
1616         "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1617         "SLB DAC 4", "OB 4"
1618 };
1619 
1620 static SOC_ENUM_SINGLE_DECL(
1621         rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1622         RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1623 
1624 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1625         SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1626 
1627 static const char * const rt5677_dac3r_src[] = {
1628         "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1629         "SLB DAC 5", "OB 5"
1630 };
1631 
1632 static SOC_ENUM_SINGLE_DECL(
1633         rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1634         RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1635 
1636 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1637         SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1638 
1639 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1640 static const char * const rt5677_dac4l_src[] = {
1641         "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1642         "SLB DAC 6", "OB 6"
1643 };
1644 
1645 static SOC_ENUM_SINGLE_DECL(
1646         rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1647         RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1648 
1649 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1650         SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1651 
1652 static const char * const rt5677_dac4r_src[] = {
1653         "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1654         "SLB DAC 7", "OB 7"
1655 };
1656 
1657 static SOC_ENUM_SINGLE_DECL(
1658         rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1659         RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1660 
1661 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1662         SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1663 
1664 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1665 static const char * const rt5677_iob_bypass_src[] = {
1666         "Bypass", "Pass SRC"
1667 };
1668 
1669 static SOC_ENUM_SINGLE_DECL(
1670         rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1671         RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1672 
1673 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1674         SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1675 
1676 static SOC_ENUM_SINGLE_DECL(
1677         rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1678         RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1679 
1680 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1681         SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1682 
1683 static SOC_ENUM_SINGLE_DECL(
1684         rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1685         RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1686 
1687 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1688         SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1689 
1690 static SOC_ENUM_SINGLE_DECL(
1691         rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1692         RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1693 
1694 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1695         SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1696 
1697 static SOC_ENUM_SINGLE_DECL(
1698         rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1699         RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1700 
1701 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1702         SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1703 
1704 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1705 static const char * const rt5677_stereo_adc2_src[] = {
1706         "DD MIX1", "DMIC", "Stereo DAC MIX"
1707 };
1708 
1709 static SOC_ENUM_SINGLE_DECL(
1710         rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1711         RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1712 
1713 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1714         SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1715 
1716 static SOC_ENUM_SINGLE_DECL(
1717         rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1718         RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1719 
1720 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1721         SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1722 
1723 static SOC_ENUM_SINGLE_DECL(
1724         rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1725         RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1726 
1727 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1728         SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1729 
1730 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1731 static const char * const rt5677_dmic_src[] = {
1732         "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1733 };
1734 
1735 static SOC_ENUM_SINGLE_DECL(
1736         rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1737         RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1738 
1739 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1740         SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1741 
1742 static SOC_ENUM_SINGLE_DECL(
1743         rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1744         RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1745 
1746 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1747         SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1748 
1749 static SOC_ENUM_SINGLE_DECL(
1750         rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1751         RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1752 
1753 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1754         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1755 
1756 static SOC_ENUM_SINGLE_DECL(
1757         rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1758         RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1759 
1760 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1761         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1762 
1763 static SOC_ENUM_SINGLE_DECL(
1764         rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1765         RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1766 
1767 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1768         SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1769 
1770 static SOC_ENUM_SINGLE_DECL(
1771         rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1772         RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1773 
1774 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1775         SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1776 
1777 /* Stereo2 ADC Source */ /* MX-26 [0] */
1778 static const char * const rt5677_stereo2_adc_lr_src[] = {
1779         "L", "LR"
1780 };
1781 
1782 static SOC_ENUM_SINGLE_DECL(
1783         rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1784         RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1785 
1786 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1787         SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1788 
1789 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1790 static const char * const rt5677_stereo_adc1_src[] = {
1791         "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1792 };
1793 
1794 static SOC_ENUM_SINGLE_DECL(
1795         rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1796         RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1797 
1798 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1799         SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1800 
1801 static SOC_ENUM_SINGLE_DECL(
1802         rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1803         RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1804 
1805 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1806         SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1807 
1808 static SOC_ENUM_SINGLE_DECL(
1809         rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1810         RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1811 
1812 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1813         SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1814 
1815 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1816 static const char * const rt5677_mono_adc2_l_src[] = {
1817         "DD MIX1L", "DMIC", "MONO DAC MIXL"
1818 };
1819 
1820 static SOC_ENUM_SINGLE_DECL(
1821         rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1822         RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1823 
1824 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1825         SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1826 
1827 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1828 static const char * const rt5677_mono_adc1_l_src[] = {
1829         "DD MIX1L", "ADC1", "MONO DAC MIXL"
1830 };
1831 
1832 static SOC_ENUM_SINGLE_DECL(
1833         rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1834         RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1835 
1836 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1837         SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1838 
1839 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1840 static const char * const rt5677_mono_adc2_r_src[] = {
1841         "DD MIX1R", "DMIC", "MONO DAC MIXR"
1842 };
1843 
1844 static SOC_ENUM_SINGLE_DECL(
1845         rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1846         RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1847 
1848 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1849         SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1850 
1851 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1852 static const char * const rt5677_mono_adc1_r_src[] = {
1853         "DD MIX1R", "ADC2", "MONO DAC MIXR"
1854 };
1855 
1856 static SOC_ENUM_SINGLE_DECL(
1857         rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1858         RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1859 
1860 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1861         SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1862 
1863 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1864 static const char * const rt5677_stereo4_adc2_src[] = {
1865         "DD MIX1", "DMIC", "DD MIX2"
1866 };
1867 
1868 static SOC_ENUM_SINGLE_DECL(
1869         rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1870         RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1871 
1872 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1873         SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1874 
1875 
1876 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1877 static const char * const rt5677_stereo4_adc1_src[] = {
1878         "DD MIX1", "ADC1/2", "DD MIX2"
1879 };
1880 
1881 static SOC_ENUM_SINGLE_DECL(
1882         rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1883         RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1884 
1885 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1886         SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1887 
1888 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1889 static const char * const rt5677_inbound01_src[] = {
1890         "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1891         "VAD ADC/DAC1 FS"
1892 };
1893 
1894 static SOC_ENUM_SINGLE_DECL(
1895         rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1896         RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1897 
1898 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1899         SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1900 
1901 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1902 static const char * const rt5677_inbound23_src[] = {
1903         "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1904         "DAC1 FS", "IF4 DAC"
1905 };
1906 
1907 static SOC_ENUM_SINGLE_DECL(
1908         rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1909         RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1910 
1911 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1912         SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1913 
1914 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1915 static const char * const rt5677_inbound45_src[] = {
1916         "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1917         "IF3 DAC"
1918 };
1919 
1920 static SOC_ENUM_SINGLE_DECL(
1921         rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1922         RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1923 
1924 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1925         SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1926 
1927 /* InBound6 Source */ /* MX-A3 [2:0] */
1928 static const char * const rt5677_inbound6_src[] = {
1929         "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1930         "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1931 };
1932 
1933 static SOC_ENUM_SINGLE_DECL(
1934         rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1935         RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1936 
1937 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1938         SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1939 
1940 /* InBound7 Source */ /* MX-A4 [14:12] */
1941 static const char * const rt5677_inbound7_src[] = {
1942         "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1943         "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1944 };
1945 
1946 static SOC_ENUM_SINGLE_DECL(
1947         rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1948         RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1949 
1950 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1951         SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1952 
1953 /* InBound8 Source */ /* MX-A4 [10:8] */
1954 static const char * const rt5677_inbound8_src[] = {
1955         "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1956         "MONO ADC MIX L", "DACL1 FS"
1957 };
1958 
1959 static SOC_ENUM_SINGLE_DECL(
1960         rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1961         RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1962 
1963 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1964         SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1965 
1966 /* InBound9 Source */ /* MX-A4 [6:4] */
1967 static const char * const rt5677_inbound9_src[] = {
1968         "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1969         "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1970 };
1971 
1972 static SOC_ENUM_SINGLE_DECL(
1973         rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1974         RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1975 
1976 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1977         SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1978 
1979 /* VAD Source */ /* MX-9F [6:4] */
1980 static const char * const rt5677_vad_src[] = {
1981         "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1982         "STO3 ADC MIX L"
1983 };
1984 
1985 static SOC_ENUM_SINGLE_DECL(
1986         rt5677_vad_enum, RT5677_VAD_CTRL4,
1987         RT5677_VAD_SRC_SFT, rt5677_vad_src);
1988 
1989 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1990         SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1991 
1992 /* Sidetone Source */ /* MX-13 [11:9] */
1993 static const char * const rt5677_sidetone_src[] = {
1994         "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1995 };
1996 
1997 static SOC_ENUM_SINGLE_DECL(
1998         rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1999         RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2000 
2001 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2002         SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2003 
2004 /* DAC1/2 Source */ /* MX-15 [1:0] */
2005 static const char * const rt5677_dac12_src[] = {
2006         "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2007 };
2008 
2009 static SOC_ENUM_SINGLE_DECL(
2010         rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2011         RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2012 
2013 static const struct snd_kcontrol_new rt5677_dac12_mux =
2014         SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2015 
2016 /* DAC3 Source */ /* MX-15 [5:4] */
2017 static const char * const rt5677_dac3_src[] = {
2018         "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2019 };
2020 
2021 static SOC_ENUM_SINGLE_DECL(
2022         rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2023         RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2024 
2025 static const struct snd_kcontrol_new rt5677_dac3_mux =
2026         SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2027 
2028 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2029 static const char * const rt5677_pdm_src[] = {
2030         "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2031 };
2032 
2033 static SOC_ENUM_SINGLE_DECL(
2034         rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2035         RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2036 
2037 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2038         SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2039 
2040 static SOC_ENUM_SINGLE_DECL(
2041         rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2042         RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2043 
2044 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2045         SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2046 
2047 static SOC_ENUM_SINGLE_DECL(
2048         rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2049         RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2050 
2051 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2052         SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2053 
2054 static SOC_ENUM_SINGLE_DECL(
2055         rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2056         RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2057 
2058 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2059         SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2060 
2061 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2062 static const char * const rt5677_if12_adc1_src[] = {
2063         "STO1 ADC MIX", "OB01", "VAD ADC"
2064 };
2065 
2066 static SOC_ENUM_SINGLE_DECL(
2067         rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2068         RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2069 
2070 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2071         SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2072 
2073 static SOC_ENUM_SINGLE_DECL(
2074         rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2075         RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2076 
2077 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2078         SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2079 
2080 static SOC_ENUM_SINGLE_DECL(
2081         rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2082         RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2083 
2084 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2085         SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2086 
2087 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2088 static const char * const rt5677_if12_adc2_src[] = {
2089         "STO2 ADC MIX", "OB23"
2090 };
2091 
2092 static SOC_ENUM_SINGLE_DECL(
2093         rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2094         RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2095 
2096 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2097         SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2098 
2099 static SOC_ENUM_SINGLE_DECL(
2100         rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2101         RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2102 
2103 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2104         SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2105 
2106 static SOC_ENUM_SINGLE_DECL(
2107         rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2108         RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2109 
2110 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2111         SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2112 
2113 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2114 static const char * const rt5677_if12_adc3_src[] = {
2115         "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2116 };
2117 
2118 static SOC_ENUM_SINGLE_DECL(
2119         rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2120         RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2121 
2122 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2123         SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2124 
2125 static SOC_ENUM_SINGLE_DECL(
2126         rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2127         RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2128 
2129 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2130         SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2131 
2132 static SOC_ENUM_SINGLE_DECL(
2133         rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2134         RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2135 
2136 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2137         SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2138 
2139 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2140 static const char * const rt5677_if12_adc4_src[] = {
2141         "STO4 ADC MIX", "OB67", "OB01"
2142 };
2143 
2144 static SOC_ENUM_SINGLE_DECL(
2145         rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2146         RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2147 
2148 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2149         SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2150 
2151 static SOC_ENUM_SINGLE_DECL(
2152         rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2153         RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2154 
2155 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2156         SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2157 
2158 static SOC_ENUM_SINGLE_DECL(
2159         rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2160         RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2161 
2162 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2163         SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2164 
2165 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2166 static const char * const rt5677_if34_adc_src[] = {
2167         "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2168         "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2169 };
2170 
2171 static SOC_ENUM_SINGLE_DECL(
2172         rt5677_if3_adc_enum, RT5677_IF3_DATA,
2173         RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2174 
2175 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2176         SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2177 
2178 static SOC_ENUM_SINGLE_DECL(
2179         rt5677_if4_adc_enum, RT5677_IF4_DATA,
2180         RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2181 
2182 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2183         SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2184 
2185 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2186 static const char * const rt5677_if12_adc_swap_src[] = {
2187         "L/R", "R/L", "L/L", "R/R"
2188 };
2189 
2190 static SOC_ENUM_SINGLE_DECL(
2191         rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2192         RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2193 
2194 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2195         SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2196 
2197 static SOC_ENUM_SINGLE_DECL(
2198         rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2199         RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2200 
2201 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2202         SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2203 
2204 static SOC_ENUM_SINGLE_DECL(
2205         rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2206         RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2207 
2208 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2209         SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2210 
2211 static SOC_ENUM_SINGLE_DECL(
2212         rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2213         RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2214 
2215 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2216         SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2217 
2218 static SOC_ENUM_SINGLE_DECL(
2219         rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2220         RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2221 
2222 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2223         SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2224 
2225 static SOC_ENUM_SINGLE_DECL(
2226         rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2227         RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2228 
2229 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2230         SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2231 
2232 static SOC_ENUM_SINGLE_DECL(
2233         rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2234         RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2235 
2236 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2237         SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2238 
2239 static SOC_ENUM_SINGLE_DECL(
2240         rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2241         RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2242 
2243 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2244         SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2245 
2246 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2247 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2248         "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2249         "3/1/2/4", "3/4/1/2"
2250 };
2251 
2252 static SOC_ENUM_SINGLE_DECL(
2253         rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2254         RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2255 
2256 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2257         SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2258 
2259 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2260 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2261         "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2262         "2/3/1/4", "3/4/1/2"
2263 };
2264 
2265 static SOC_ENUM_SINGLE_DECL(
2266         rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2267         RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2268 
2269 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2270         SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2271 
2272 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2273                                         MX-3F[14:12][10:8][6:4][2:0]
2274                                         MX-43[14:12][10:8][6:4][2:0]
2275                                         MX-44[14:12][10:8][6:4][2:0] */
2276 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2277         "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2278 };
2279 
2280 static SOC_ENUM_SINGLE_DECL(
2281         rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2282         RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2283 
2284 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2285         SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2286 
2287 static SOC_ENUM_SINGLE_DECL(
2288         rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2289         RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2290 
2291 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2292         SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2293 
2294 static SOC_ENUM_SINGLE_DECL(
2295         rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2296         RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2297 
2298 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2299         SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2300 
2301 static SOC_ENUM_SINGLE_DECL(
2302         rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2303         RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2304 
2305 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2306         SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2307 
2308 static SOC_ENUM_SINGLE_DECL(
2309         rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2310         RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2311 
2312 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2313         SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2314 
2315 static SOC_ENUM_SINGLE_DECL(
2316         rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2317         RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2318 
2319 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2320         SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2321 
2322 static SOC_ENUM_SINGLE_DECL(
2323         rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2324         RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2325 
2326 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2327         SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2328 
2329 static SOC_ENUM_SINGLE_DECL(
2330         rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2331         RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2332 
2333 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2334         SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2335 
2336 static SOC_ENUM_SINGLE_DECL(
2337         rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2338         RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2339 
2340 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2341         SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2342 
2343 static SOC_ENUM_SINGLE_DECL(
2344         rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2345         RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2346 
2347 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2348         SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2349 
2350 static SOC_ENUM_SINGLE_DECL(
2351         rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2352         RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2353 
2354 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2355         SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2356 
2357 static SOC_ENUM_SINGLE_DECL(
2358         rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2359         RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2360 
2361 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2362         SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2363 
2364 static SOC_ENUM_SINGLE_DECL(
2365         rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2366         RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2367 
2368 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2369         SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2370 
2371 static SOC_ENUM_SINGLE_DECL(
2372         rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2373         RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2374 
2375 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2376         SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2377 
2378 static SOC_ENUM_SINGLE_DECL(
2379         rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2380         RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2381 
2382 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2383         SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2384 
2385 static SOC_ENUM_SINGLE_DECL(
2386         rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2387         RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2388 
2389 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2390         SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2391 
2392 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2393         struct snd_kcontrol *kcontrol, int event)
2394 {
2395         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2396         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2397 
2398         switch (event) {
2399         case SND_SOC_DAPM_POST_PMU:
2400                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2401                         RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2402                 break;
2403 
2404         case SND_SOC_DAPM_PRE_PMD:
2405                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2406                         RT5677_PWR_BST1_P, 0);
2407                 break;
2408 
2409         default:
2410                 return 0;
2411         }
2412 
2413         return 0;
2414 }
2415 
2416 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2417         struct snd_kcontrol *kcontrol, int event)
2418 {
2419         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2420         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2421 
2422         switch (event) {
2423         case SND_SOC_DAPM_POST_PMU:
2424                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2425                         RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2426                 break;
2427 
2428         case SND_SOC_DAPM_PRE_PMD:
2429                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2430                         RT5677_PWR_BST2_P, 0);
2431                 break;
2432 
2433         default:
2434                 return 0;
2435         }
2436 
2437         return 0;
2438 }
2439 
2440 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2441         struct snd_kcontrol *kcontrol, int event)
2442 {
2443         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2444         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2445 
2446         switch (event) {
2447         case SND_SOC_DAPM_PRE_PMU:
2448                 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2449                 break;
2450 
2451         case SND_SOC_DAPM_POST_PMU:
2452                 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2453                 break;
2454 
2455         default:
2456                 return 0;
2457         }
2458 
2459         return 0;
2460 }
2461 
2462 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2463         struct snd_kcontrol *kcontrol, int event)
2464 {
2465         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2466         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2467 
2468         switch (event) {
2469         case SND_SOC_DAPM_PRE_PMU:
2470                 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2471                 break;
2472 
2473         case SND_SOC_DAPM_POST_PMU:
2474                 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2475                 break;
2476 
2477         default:
2478                 return 0;
2479         }
2480 
2481         return 0;
2482 }
2483 
2484 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2485         struct snd_kcontrol *kcontrol, int event)
2486 {
2487         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2488         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2489 
2490         switch (event) {
2491         case SND_SOC_DAPM_POST_PMU:
2492                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2493                         RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2494                         RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2495                         RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2496                 break;
2497 
2498         case SND_SOC_DAPM_PRE_PMD:
2499                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2500                         RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2501                         RT5677_PWR_CLK_MB, 0);
2502                 break;
2503 
2504         default:
2505                 return 0;
2506         }
2507 
2508         return 0;
2509 }
2510 
2511 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2512         struct snd_kcontrol *kcontrol, int event)
2513 {
2514         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2515         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2516         unsigned int value;
2517 
2518         switch (event) {
2519         case SND_SOC_DAPM_PRE_PMU:
2520                 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2521                 if (value & RT5677_IF1_ADC_CTRL_MASK)
2522                         regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2523                                 RT5677_IF1_ADC_MODE_MASK,
2524                                 RT5677_IF1_ADC_MODE_TDM);
2525                 break;
2526 
2527         default:
2528                 return 0;
2529         }
2530 
2531         return 0;
2532 }
2533 
2534 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2535         struct snd_kcontrol *kcontrol, int event)
2536 {
2537         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2538         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2539         unsigned int value;
2540 
2541         switch (event) {
2542         case SND_SOC_DAPM_PRE_PMU:
2543                 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2544                 if (value & RT5677_IF2_ADC_CTRL_MASK)
2545                         regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2546                                 RT5677_IF2_ADC_MODE_MASK,
2547                                 RT5677_IF2_ADC_MODE_TDM);
2548                 break;
2549 
2550         default:
2551                 return 0;
2552         }
2553 
2554         return 0;
2555 }
2556 
2557 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2558         struct snd_kcontrol *kcontrol, int event)
2559 {
2560         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2561         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2562 
2563         switch (event) {
2564         case SND_SOC_DAPM_POST_PMU:
2565                 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
2566                         !rt5677->is_vref_slow) {
2567                         mdelay(20);
2568                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2569                                 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2570                                 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2571                         rt5677->is_vref_slow = true;
2572                 }
2573                 break;
2574 
2575         default:
2576                 return 0;
2577         }
2578 
2579         return 0;
2580 }
2581 
2582 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2583         struct snd_kcontrol *kcontrol, int event)
2584 {
2585         switch (event) {
2586         case SND_SOC_DAPM_POST_PMU:
2587                 msleep(50);
2588                 break;
2589 
2590         default:
2591                 return 0;
2592         }
2593 
2594         return 0;
2595 }
2596 
2597 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2598         SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2599                 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2600                 SND_SOC_DAPM_POST_PMU),
2601         SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2602                 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2603                 SND_SOC_DAPM_POST_PMU),
2604 
2605         /* ASRC */
2606         SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2607         SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2608         SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2609         SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2610         SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2611         SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2612                 0),
2613         SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2614                 0),
2615         SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2616                 0),
2617         SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2618                 0),
2619         SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2620                 0),
2621         SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2622                 0),
2623         SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2624                 0),
2625         SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2626                 0),
2627         SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2628                 0),
2629         SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2630                 0),
2631         SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2632                 0),
2633         SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2634                 0),
2635         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2636         SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2637         SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2638         SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2639         SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2640                 0),
2641         SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2642                 0),
2643 
2644         /* Input Side */
2645         /* micbias */
2646         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2647                 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2648                 SND_SOC_DAPM_POST_PMU),
2649 
2650         /* Input Lines */
2651         SND_SOC_DAPM_INPUT("DMIC L1"),
2652         SND_SOC_DAPM_INPUT("DMIC R1"),
2653         SND_SOC_DAPM_INPUT("DMIC L2"),
2654         SND_SOC_DAPM_INPUT("DMIC R2"),
2655         SND_SOC_DAPM_INPUT("DMIC L3"),
2656         SND_SOC_DAPM_INPUT("DMIC R3"),
2657         SND_SOC_DAPM_INPUT("DMIC L4"),
2658         SND_SOC_DAPM_INPUT("DMIC R4"),
2659 
2660         SND_SOC_DAPM_INPUT("IN1P"),
2661         SND_SOC_DAPM_INPUT("IN1N"),
2662         SND_SOC_DAPM_INPUT("IN2P"),
2663         SND_SOC_DAPM_INPUT("IN2N"),
2664 
2665         SND_SOC_DAPM_INPUT("Haptic Generator"),
2666 
2667         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2668         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2669         SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2670         SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 
2672         SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2673                 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2674         SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2675                 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2676         SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2677                 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2678         SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2679                 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2680 
2681         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2682                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2683 
2684         /* Boost */
2685         SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2686                 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2687                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2688         SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2689                 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2690                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2691 
2692         /* ADCs */
2693         SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2694                 0, 0),
2695         SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2696                 0, 0),
2697         SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2698 
2699         SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2700                 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2701         SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2702                 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2703         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2704                 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2705         SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2706                 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2707 
2708         /* ADC Mux */
2709         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2710                                 &rt5677_sto1_dmic_mux),
2711         SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2712                                 &rt5677_sto1_adc1_mux),
2713         SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2714                                 &rt5677_sto1_adc2_mux),
2715         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2716                                 &rt5677_sto2_dmic_mux),
2717         SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2718                                 &rt5677_sto2_adc1_mux),
2719         SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2720                                 &rt5677_sto2_adc2_mux),
2721         SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2722                                 &rt5677_sto2_adc_lr_mux),
2723         SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2724                                 &rt5677_sto3_dmic_mux),
2725         SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2726                                 &rt5677_sto3_adc1_mux),
2727         SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2728                                 &rt5677_sto3_adc2_mux),
2729         SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2730                                 &rt5677_sto4_dmic_mux),
2731         SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2732                                 &rt5677_sto4_adc1_mux),
2733         SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2734                                 &rt5677_sto4_adc2_mux),
2735         SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2736                                 &rt5677_mono_dmic_l_mux),
2737         SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2738                                 &rt5677_mono_dmic_r_mux),
2739         SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2740                                 &rt5677_mono_adc2_l_mux),
2741         SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2742                                 &rt5677_mono_adc1_l_mux),
2743         SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2744                                 &rt5677_mono_adc1_r_mux),
2745         SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2746                                 &rt5677_mono_adc2_r_mux),
2747 
2748         /* ADC Mixer */
2749         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2750                 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2751         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2752                 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2753         SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2754                 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2755         SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2756                 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2757         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2758                 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2759         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2760                 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2761         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2762                 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2763         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2764                 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2765         SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2766                 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2767         SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2768                 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2769         SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2770                 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2771         SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2772                 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2773         SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2774                 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2775         SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2776                 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2777         SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2778                 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2779         SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2780                 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2781 
2782         /* ADC PGA */
2783         SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2784         SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2785         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2786         SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2787         SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2788         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2789         SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2790         SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2791         SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2792         SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2793         SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2794         SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2795         SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2796         SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797         SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2798         SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 
2800         /* DSP */
2801         SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2802                         &rt5677_ib9_src_mux),
2803         SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2804                         &rt5677_ib8_src_mux),
2805         SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2806                         &rt5677_ib7_src_mux),
2807         SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2808                         &rt5677_ib6_src_mux),
2809         SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2810                         &rt5677_ib45_src_mux),
2811         SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2812                         &rt5677_ib23_src_mux),
2813         SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2814                         &rt5677_ib01_src_mux),
2815         SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2816                         &rt5677_ib45_bypass_src_mux),
2817         SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2818                         &rt5677_ib23_bypass_src_mux),
2819         SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2820                         &rt5677_ib01_bypass_src_mux),
2821         SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2822                         &rt5677_ob23_bypass_src_mux),
2823         SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2824                         &rt5677_ob01_bypass_src_mux),
2825 
2826         SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2827         SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 
2829         SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2830         SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2831         SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2832         SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2833         SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2834         SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 
2836         /* Digital Interface */
2837         SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2838                 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2839         SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2840         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2841         SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2842         SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2843         SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2844         SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2845         SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2846         SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2847         SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2848         SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2849         SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2850         SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2851         SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2852         SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2853         SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2854         SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 
2856         SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2857                 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2858         SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2859         SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2860         SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2861         SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2862         SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2863         SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2864         SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2865         SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2866         SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2867         SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2868         SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2869         SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2870         SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2871         SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2872         SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2873         SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 
2875         SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2876                 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2877         SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2878         SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2879         SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2880         SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2881         SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2882         SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 
2884         SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2885                 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2886         SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2887         SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2888         SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2889         SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2890         SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2891         SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 
2893         SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2894                 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2895         SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2896         SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2897         SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2898         SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2899         SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2900         SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2901         SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2902         SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2903         SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2904         SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2905         SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2906         SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2907         SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2908         SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2909         SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2910         SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 
2912         /* Digital Interface Select */
2913         SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2914                         &rt5677_if1_adc1_mux),
2915         SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2916                         &rt5677_if1_adc2_mux),
2917         SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2918                         &rt5677_if1_adc3_mux),
2919         SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2920                         &rt5677_if1_adc4_mux),
2921         SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2922                         &rt5677_if1_adc1_swap_mux),
2923         SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2924                         &rt5677_if1_adc2_swap_mux),
2925         SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2926                         &rt5677_if1_adc3_swap_mux),
2927         SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2928                         &rt5677_if1_adc4_swap_mux),
2929         SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2930                         &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2931                         SND_SOC_DAPM_PRE_PMU),
2932         SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2933                         &rt5677_if2_adc1_mux),
2934         SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2935                         &rt5677_if2_adc2_mux),
2936         SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2937                         &rt5677_if2_adc3_mux),
2938         SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2939                         &rt5677_if2_adc4_mux),
2940         SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2941                         &rt5677_if2_adc1_swap_mux),
2942         SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2943                         &rt5677_if2_adc2_swap_mux),
2944         SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2945                         &rt5677_if2_adc3_swap_mux),
2946         SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2947                         &rt5677_if2_adc4_swap_mux),
2948         SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2949                         &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2950                         SND_SOC_DAPM_PRE_PMU),
2951         SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2952                         &rt5677_if3_adc_mux),
2953         SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2954                         &rt5677_if4_adc_mux),
2955         SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2956                         &rt5677_slb_adc1_mux),
2957         SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2958                         &rt5677_slb_adc2_mux),
2959         SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2960                         &rt5677_slb_adc3_mux),
2961         SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2962                         &rt5677_slb_adc4_mux),
2963 
2964         SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2965                         &rt5677_if1_dac0_tdm_sel_mux),
2966         SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2967                         &rt5677_if1_dac1_tdm_sel_mux),
2968         SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2969                         &rt5677_if1_dac2_tdm_sel_mux),
2970         SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2971                         &rt5677_if1_dac3_tdm_sel_mux),
2972         SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2973                         &rt5677_if1_dac4_tdm_sel_mux),
2974         SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2975                         &rt5677_if1_dac5_tdm_sel_mux),
2976         SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2977                         &rt5677_if1_dac6_tdm_sel_mux),
2978         SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2979                         &rt5677_if1_dac7_tdm_sel_mux),
2980 
2981         SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2982                         &rt5677_if2_dac0_tdm_sel_mux),
2983         SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2984                         &rt5677_if2_dac1_tdm_sel_mux),
2985         SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2986                         &rt5677_if2_dac2_tdm_sel_mux),
2987         SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2988                         &rt5677_if2_dac3_tdm_sel_mux),
2989         SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2990                         &rt5677_if2_dac4_tdm_sel_mux),
2991         SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2992                         &rt5677_if2_dac5_tdm_sel_mux),
2993         SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2994                         &rt5677_if2_dac6_tdm_sel_mux),
2995         SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2996                         &rt5677_if2_dac7_tdm_sel_mux),
2997 
2998         /* Audio Interface */
2999         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3000         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3001         SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3002         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3003         SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3004         SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3005         SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3006         SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3007         SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3008         SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3009 
3010         /* Sidetone Mux */
3011         SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3012                         &rt5677_sidetone_mux),
3013         SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3014                 RT5677_ST_EN_SFT, 0, NULL, 0),
3015 
3016         /* VAD Mux*/
3017         SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3018                         &rt5677_vad_src_mux),
3019 
3020         /* Tensilica DSP */
3021         SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3022         SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3023                 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3024         SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3025                 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3026         SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3027                 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3028         SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3029                 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3030         SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3031                 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3032         SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3033                 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3034 
3035         /* Output Side */
3036         /* DAC mixer before sound effect */
3037         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3038                 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3039         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3040                 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3041         SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3042 
3043         /* DAC Mux */
3044         SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3045                                 &rt5677_dac1_mux),
3046         SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3047                                 &rt5677_adda1_mux),
3048         SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3049                                 &rt5677_dac12_mux),
3050         SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3051                                 &rt5677_dac3_mux),
3052 
3053         /* DAC2 channel Mux */
3054         SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3055                                 &rt5677_dac2_l_mux),
3056         SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3057                                 &rt5677_dac2_r_mux),
3058 
3059         /* DAC3 channel Mux */
3060         SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3061                         &rt5677_dac3_l_mux),
3062         SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3063                         &rt5677_dac3_r_mux),
3064 
3065         /* DAC4 channel Mux */
3066         SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3067                         &rt5677_dac4_l_mux),
3068         SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3069                         &rt5677_dac4_r_mux),
3070 
3071         /* DAC Mixer */
3072         SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3073                 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3074                 SND_SOC_DAPM_POST_PMU),
3075         SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3076                 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3077                 SND_SOC_DAPM_POST_PMU),
3078         SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3079                 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3080                 SND_SOC_DAPM_POST_PMU),
3081         SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3082                 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3083                 SND_SOC_DAPM_POST_PMU),
3084         SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3085                 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3086                 SND_SOC_DAPM_POST_PMU),
3087         SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3088                 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3089                 SND_SOC_DAPM_POST_PMU),
3090         SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3091                 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3092                 SND_SOC_DAPM_POST_PMU),
3093 
3094         SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3095                 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3096         SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3097                 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3098         SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3099                 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3100         SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3101                 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3102         SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3103                 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3104         SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3105                 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3106         SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3107                 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3108         SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3109                 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3110         SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3111         SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3112         SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3113         SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3114 
3115         /* DACs */
3116         SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3117                 RT5677_PWR_DAC1_BIT, 0),
3118         SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3119                 RT5677_PWR_DAC2_BIT, 0),
3120         SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3121                 RT5677_PWR_DAC3_BIT, 0),
3122 
3123         /* PDM */
3124         SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3125                 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3126         SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3127                 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3128 
3129         SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3130                 1, &rt5677_pdm1_l_mux),
3131         SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3132                 1, &rt5677_pdm1_r_mux),
3133         SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3134                 1, &rt5677_pdm2_l_mux),
3135         SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3136                 1, &rt5677_pdm2_r_mux),
3137 
3138         SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3139                 0, NULL, 0),
3140         SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3141                 0, NULL, 0),
3142         SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3143                 0, NULL, 0),
3144 
3145         SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3146                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3147         SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3148                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3149         SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3150                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3151 
3152         /* Output Lines */
3153         SND_SOC_DAPM_OUTPUT("LOUT1"),
3154         SND_SOC_DAPM_OUTPUT("LOUT2"),
3155         SND_SOC_DAPM_OUTPUT("LOUT3"),
3156         SND_SOC_DAPM_OUTPUT("PDM1L"),
3157         SND_SOC_DAPM_OUTPUT("PDM1R"),
3158         SND_SOC_DAPM_OUTPUT("PDM2L"),
3159         SND_SOC_DAPM_OUTPUT("PDM2R"),
3160 
3161         SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3162 };
3163 
3164 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3165         { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3166         { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3167         { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3168         { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3169         { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3170         { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3171         { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3172         { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3173         { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3174         { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3175 
3176         { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3177         { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3178         { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3179         { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3180         { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3181         { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3182         { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3183         { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3184         { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3185         { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3186         { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3187         { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3188         { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3189 
3190         { "DMIC1", NULL, "DMIC L1" },
3191         { "DMIC1", NULL, "DMIC R1" },
3192         { "DMIC2", NULL, "DMIC L2" },
3193         { "DMIC2", NULL, "DMIC R2" },
3194         { "DMIC3", NULL, "DMIC L3" },
3195         { "DMIC3", NULL, "DMIC R3" },
3196         { "DMIC4", NULL, "DMIC L4" },
3197         { "DMIC4", NULL, "DMIC R4" },
3198 
3199         { "DMIC L1", NULL, "DMIC CLK" },
3200         { "DMIC R1", NULL, "DMIC CLK" },
3201         { "DMIC L2", NULL, "DMIC CLK" },
3202         { "DMIC R2", NULL, "DMIC CLK" },
3203         { "DMIC L3", NULL, "DMIC CLK" },
3204         { "DMIC R3", NULL, "DMIC CLK" },
3205         { "DMIC L4", NULL, "DMIC CLK" },
3206         { "DMIC R4", NULL, "DMIC CLK" },
3207 
3208         { "DMIC L1", NULL, "DMIC1 power" },
3209         { "DMIC R1", NULL, "DMIC1 power" },
3210         { "DMIC L3", NULL, "DMIC3 power" },
3211         { "DMIC R3", NULL, "DMIC3 power" },
3212         { "DMIC L4", NULL, "DMIC4 power" },
3213         { "DMIC R4", NULL, "DMIC4 power" },
3214 
3215         { "BST1", NULL, "IN1P" },
3216         { "BST1", NULL, "IN1N" },
3217         { "BST2", NULL, "IN2P" },
3218         { "BST2", NULL, "IN2N" },
3219 
3220         { "IN1P", NULL, "MICBIAS1" },
3221         { "IN1N", NULL, "MICBIAS1" },
3222         { "IN2P", NULL, "MICBIAS1" },
3223         { "IN2N", NULL, "MICBIAS1" },
3224 
3225         { "ADC 1", NULL, "BST1" },
3226         { "ADC 1", NULL, "ADC 1 power" },
3227         { "ADC 1", NULL, "ADC1 clock" },
3228         { "ADC 2", NULL, "BST2" },
3229         { "ADC 2", NULL, "ADC 2 power" },
3230         { "ADC 2", NULL, "ADC2 clock" },
3231 
3232         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3233         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3234         { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3235         { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3236 
3237         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3238         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3239         { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3240         { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3241 
3242         { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3243         { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3244         { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3245         { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3246 
3247         { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3248         { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3249         { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3250         { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3251 
3252         { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3253         { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3254         { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3255         { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3256 
3257         { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3258         { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3259         { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3260         { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3261 
3262         { "ADC 1_2", NULL, "ADC 1" },
3263         { "ADC 1_2", NULL, "ADC 2" },
3264 
3265         { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3266         { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3267         { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3268 
3269         { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3270         { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3271         { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3272 
3273         { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3274         { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3275         { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3276 
3277         { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3278         { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3279         { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3280 
3281         { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3282         { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3283         { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3284 
3285         { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3286         { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3287         { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3288 
3289         { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3290         { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3291         { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3292 
3293         { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3294         { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3295         { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3296 
3297         { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3298         { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3299         { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3300 
3301         { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3302         { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3303         { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3304 
3305         { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3306         { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3307         { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3308 
3309         { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3310         { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3311         { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3312 
3313         { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3314         { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3315         { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3316         { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3317 
3318         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3319         { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3320         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3321         { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3322         { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3323 
3324         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3325         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3326 
3327         { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3328         { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3329         { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3330         { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3331 
3332         { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3333         { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3334 
3335         { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3336         { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3337 
3338         { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3339         { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3340         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3341         { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3342         { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3343 
3344         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3345         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3346 
3347         { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3348         { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3349         { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3350         { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3351 
3352         { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3353         { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3354         { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3355         { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3356         { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3357 
3358         { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3359         { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3360 
3361         { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3362         { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3363         { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3364         { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3365 
3366         { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3367         { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3368         { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3369         { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3370         { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3371 
3372         { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3373         { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3374 
3375         { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3376         { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3377         { "Mono ADC MIXL", NULL, "adc mono left filter" },
3378         { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3379 
3380         { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3381         { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3382         { "Mono ADC MIXR", NULL, "adc mono right filter" },
3383         { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3384 
3385         { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3386         { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3387 
3388         { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3389         { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3390         { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3391         { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3392         { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3393 
3394         { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3395         { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3396         { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3397 
3398         { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3399         { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3400 
3401         { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3402         { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3403         { "IF1 ADC3 Mux", "OB45", "OB45" },
3404 
3405         { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3406         { "IF1 ADC4 Mux", "OB67", "OB67" },
3407         { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3408 
3409         { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3410         { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3411         { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3412         { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3413 
3414         { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3415         { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3416         { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3417         { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3418 
3419         { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3420         { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3421         { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3422         { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3423 
3424         { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3425         { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3426         { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3427         { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3428 
3429         { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3430         { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3431         { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3432         { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3433 
3434         { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3435         { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3436         { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3437         { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3438         { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3439         { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3440         { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3441         { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3442 
3443         { "AIF1TX", NULL, "I2S1" },
3444         { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3445 
3446         { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3447         { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3448         { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3449 
3450         { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3451         { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3452 
3453         { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3454         { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3455         { "IF2 ADC3 Mux", "OB45", "OB45" },
3456 
3457         { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3458         { "IF2 ADC4 Mux", "OB67", "OB67" },
3459         { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3460 
3461         { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3462         { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3463         { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3464         { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3465 
3466         { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3467         { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3468         { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3469         { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3470 
3471         { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3472         { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3473         { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3474         { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3475 
3476         { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3477         { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3478         { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3479         { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3480 
3481         { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3482         { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3483         { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3484         { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3485 
3486         { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3487         { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3488         { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3489         { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3490         { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3491         { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3492         { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3493         { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3494 
3495         { "AIF2TX", NULL, "I2S2" },
3496         { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3497 
3498         { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3499         { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3500         { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3501         { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3502         { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3503         { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3504         { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3505         { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3506 
3507         { "AIF3TX", NULL, "I2S3" },
3508         { "AIF3TX", NULL, "IF3 ADC Mux" },
3509 
3510         { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3511         { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3512         { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3513         { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3514         { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3515         { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3516         { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3517         { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3518 
3519         { "AIF4TX", NULL, "I2S4" },
3520         { "AIF4TX", NULL, "IF4 ADC Mux" },
3521 
3522         { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3523         { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3524         { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3525 
3526         { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3527         { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3528 
3529         { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3530         { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3531         { "SLB ADC3 Mux", "OB45", "OB45" },
3532 
3533         { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3534         { "SLB ADC4 Mux", "OB67", "OB67" },
3535         { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3536 
3537         { "SLBTX", NULL, "SLB" },
3538         { "SLBTX", NULL, "SLB ADC1 Mux" },
3539         { "SLBTX", NULL, "SLB ADC2 Mux" },
3540         { "SLBTX", NULL, "SLB ADC3 Mux" },
3541         { "SLBTX", NULL, "SLB ADC4 Mux" },
3542 
3543         { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3544         { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3545         { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3546         { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3547         { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3548 
3549         { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3550         { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3551 
3552         { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3553         { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3554         { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3555         { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3556         { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3557         { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3558 
3559         { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3560         { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3561 
3562         { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3563         { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3564         { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3565         { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3566         { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3567 
3568         { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3569         { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3570 
3571         { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3572         { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3573         { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3574         { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3575         { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3576         { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3577         { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3578         { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3579 
3580         { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3581         { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3582         { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3583         { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3584         { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3585         { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3586         { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3587         { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3588 
3589         { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3590         { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3591         { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3592         { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3593         { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3594         { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3595 
3596         { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3597         { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3598         { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3599         { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3600         { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3601         { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3602         { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3603 
3604         { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3605         { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3606         { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3607         { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3608         { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3609         { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3610         { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3611 
3612         { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3613         { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3614         { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3615         { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3616         { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3617         { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3618         { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3619 
3620         { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3621         { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3622         { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3623         { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3624         { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3625         { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3626         { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3627 
3628         { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3629         { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3630         { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3631         { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3632         { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3633         { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3634         { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3635 
3636         { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3637         { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3638         { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3639         { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3640         { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3641         { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3642         { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3643 
3644         { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3645         { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3646         { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3647         { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3648         { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3649         { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3650         { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3651 
3652         { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3653         { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3654         { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3655         { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3656 
3657         { "OutBound2", NULL, "OB23 Bypass Mux" },
3658         { "OutBound3", NULL, "OB23 Bypass Mux" },
3659         { "OutBound4", NULL, "OB4 MIX" },
3660         { "OutBound5", NULL, "OB5 MIX" },
3661         { "OutBound6", NULL, "OB6 MIX" },
3662         { "OutBound7", NULL, "OB7 MIX" },
3663 
3664         { "OB45", NULL, "OutBound4" },
3665         { "OB45", NULL, "OutBound5" },
3666         { "OB67", NULL, "OutBound6" },
3667         { "OB67", NULL, "OutBound7" },
3668 
3669         { "IF1 DAC0", NULL, "AIF1RX" },
3670         { "IF1 DAC1", NULL, "AIF1RX" },
3671         { "IF1 DAC2", NULL, "AIF1RX" },
3672         { "IF1 DAC3", NULL, "AIF1RX" },
3673         { "IF1 DAC4", NULL, "AIF1RX" },
3674         { "IF1 DAC5", NULL, "AIF1RX" },
3675         { "IF1 DAC6", NULL, "AIF1RX" },
3676         { "IF1 DAC7", NULL, "AIF1RX" },
3677         { "IF1 DAC0", NULL, "I2S1" },
3678         { "IF1 DAC1", NULL, "I2S1" },
3679         { "IF1 DAC2", NULL, "I2S1" },
3680         { "IF1 DAC3", NULL, "I2S1" },
3681         { "IF1 DAC4", NULL, "I2S1" },
3682         { "IF1 DAC5", NULL, "I2S1" },
3683         { "IF1 DAC6", NULL, "I2S1" },
3684         { "IF1 DAC7", NULL, "I2S1" },
3685 
3686         { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3687         { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3688         { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3689         { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3690         { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3691         { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3692         { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3693         { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3694 
3695         { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3696         { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3697         { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3698         { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3699         { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3700         { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3701         { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3702         { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3703 
3704         { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3705         { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3706         { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3707         { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3708         { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3709         { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3710         { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3711         { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3712 
3713         { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3714         { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3715         { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3716         { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3717         { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3718         { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3719         { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3720         { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3721 
3722         { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3723         { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3724         { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3725         { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3726         { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3727         { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3728         { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3729         { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3730 
3731         { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3732         { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3733         { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3734         { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3735         { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3736         { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3737         { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3738         { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3739 
3740         { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3741         { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3742         { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3743         { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3744         { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3745         { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3746         { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3747         { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3748 
3749         { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3750         { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3751         { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3752         { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3753         { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3754         { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3755         { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3756         { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3757 
3758         { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3759         { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3760         { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3761         { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3762         { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3763         { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3764         { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3765         { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3766 
3767         { "IF2 DAC0", NULL, "AIF2RX" },
3768         { "IF2 DAC1", NULL, "AIF2RX" },
3769         { "IF2 DAC2", NULL, "AIF2RX" },
3770         { "IF2 DAC3", NULL, "AIF2RX" },
3771         { "IF2 DAC4", NULL, "AIF2RX" },
3772         { "IF2 DAC5", NULL, "AIF2RX" },
3773         { "IF2 DAC6", NULL, "AIF2RX" },
3774         { "IF2 DAC7", NULL, "AIF2RX" },
3775         { "IF2 DAC0", NULL, "I2S2" },
3776         { "IF2 DAC1", NULL, "I2S2" },
3777         { "IF2 DAC2", NULL, "I2S2" },
3778         { "IF2 DAC3", NULL, "I2S2" },
3779         { "IF2 DAC4", NULL, "I2S2" },
3780         { "IF2 DAC5", NULL, "I2S2" },
3781         { "IF2 DAC6", NULL, "I2S2" },
3782         { "IF2 DAC7", NULL, "I2S2" },
3783 
3784         { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3785         { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3786         { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3787         { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3788         { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3789         { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3790         { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3791         { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3792 
3793         { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3794         { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3795         { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3796         { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3797         { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3798         { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3799         { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3800         { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3801 
3802         { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3803         { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3804         { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3805         { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3806         { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3807         { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3808         { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3809         { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3810 
3811         { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3812         { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3813         { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3814         { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3815         { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3816         { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3817         { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3818         { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3819 
3820         { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3821         { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3822         { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3823         { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3824         { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3825         { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3826         { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3827         { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3828 
3829         { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3830         { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3831         { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3832         { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3833         { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3834         { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3835         { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3836         { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3837 
3838         { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3839         { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3840         { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3841         { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3842         { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3843         { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3844         { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3845         { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3846 
3847         { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3848         { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3849         { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3850         { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3851         { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3852         { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3853         { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3854         { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3855 
3856         { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3857         { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3858         { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3859         { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3860         { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3861         { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3862         { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3863         { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3864 
3865         { "IF3 DAC", NULL, "AIF3RX" },
3866         { "IF3 DAC", NULL, "I2S3" },
3867 
3868         { "IF4 DAC", NULL, "AIF4RX" },
3869         { "IF4 DAC", NULL, "I2S4" },
3870 
3871         { "IF3 DAC L", NULL, "IF3 DAC" },
3872         { "IF3 DAC R", NULL, "IF3 DAC" },
3873 
3874         { "IF4 DAC L", NULL, "IF4 DAC" },
3875         { "IF4 DAC R", NULL, "IF4 DAC" },
3876 
3877         { "SLB DAC0", NULL, "SLBRX" },
3878         { "SLB DAC1", NULL, "SLBRX" },
3879         { "SLB DAC2", NULL, "SLBRX" },
3880         { "SLB DAC3", NULL, "SLBRX" },
3881         { "SLB DAC4", NULL, "SLBRX" },
3882         { "SLB DAC5", NULL, "SLBRX" },
3883         { "SLB DAC6", NULL, "SLBRX" },
3884         { "SLB DAC7", NULL, "SLBRX" },
3885         { "SLB DAC0", NULL, "SLB" },
3886         { "SLB DAC1", NULL, "SLB" },
3887         { "SLB DAC2", NULL, "SLB" },
3888         { "SLB DAC3", NULL, "SLB" },
3889         { "SLB DAC4", NULL, "SLB" },
3890         { "SLB DAC5", NULL, "SLB" },
3891         { "SLB DAC6", NULL, "SLB" },
3892         { "SLB DAC7", NULL, "SLB" },
3893 
3894         { "SLB DAC01", NULL, "SLB DAC0" },
3895         { "SLB DAC01", NULL, "SLB DAC1" },
3896         { "SLB DAC23", NULL, "SLB DAC2" },
3897         { "SLB DAC23", NULL, "SLB DAC3" },
3898         { "SLB DAC45", NULL, "SLB DAC4" },
3899         { "SLB DAC45", NULL, "SLB DAC5" },
3900         { "SLB DAC67", NULL, "SLB DAC6" },
3901         { "SLB DAC67", NULL, "SLB DAC7" },
3902 
3903         { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3904         { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3905         { "ADDA1 Mux", "OB 67", "OB67" },
3906 
3907         { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3908         { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3909         { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3910         { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3911         { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3912         { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3913 
3914         { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3915         { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3916         { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3917         { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3918 
3919         { "DAC1 FS", NULL, "DAC1 MIXL" },
3920         { "DAC1 FS", NULL, "DAC1 MIXR" },
3921 
3922         { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3923         { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3924         { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3925         { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3926         { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3927         { "DAC2 L Mux", "OB 2", "OutBound2" },
3928 
3929         { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3930         { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3931         { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3932         { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3933         { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3934         { "DAC2 R Mux", "OB 3", "OutBound3" },
3935         { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3936         { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3937 
3938         { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3939         { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3940         { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3941         { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3942         { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3943         { "DAC3 L Mux", "OB 4", "OutBound4" },
3944 
3945         { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3946         { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3947         { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3948         { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3949         { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3950         { "DAC3 R Mux", "OB 5", "OutBound5" },
3951 
3952         { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3953         { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3954         { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3955         { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3956         { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3957         { "DAC4 L Mux", "OB 6", "OutBound6" },
3958 
3959         { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3960         { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3961         { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3962         { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3963         { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3964         { "DAC4 R Mux", "OB 7", "OutBound7" },
3965 
3966         { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3967         { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3968         { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3969         { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3970         { "Sidetone Mux", "ADC1", "ADC 1" },
3971         { "Sidetone Mux", "ADC2", "ADC 2" },
3972         { "Sidetone Mux", NULL, "Sidetone Power" },
3973 
3974         { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3975         { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3976         { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3977         { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3978         { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3979         { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3980         { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3981         { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3982         { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3983         { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3984         { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3985 
3986         { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3987         { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3988         { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3989         { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3990         { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3991         { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3992         { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3993         { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3994         { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3995         { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3996         { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3997         { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3998 
3999         { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4000         { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4001         { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4002         { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4003         { "DD1 MIXL", NULL, "dac mono3 left filter" },
4004         { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4005         { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4006         { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4007         { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4008         { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4009         { "DD1 MIXR", NULL, "dac mono3 right filter" },
4010         { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4011 
4012         { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4013         { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4014         { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4015         { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4016         { "DD2 MIXL", NULL, "dac mono4 left filter" },
4017         { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4018         { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4019         { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4020         { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4021         { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4022         { "DD2 MIXR", NULL, "dac mono4 right filter" },
4023         { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4024 
4025         { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4026         { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4027         { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4028         { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4029         { "DD1 MIX", NULL, "DD1 MIXL" },
4030         { "DD1 MIX", NULL, "DD1 MIXR" },
4031         { "DD2 MIX", NULL, "DD2 MIXL" },
4032         { "DD2 MIX", NULL, "DD2 MIXR" },
4033 
4034         { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4035         { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4036         { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4037         { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4038 
4039         { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4040         { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4041         { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4042         { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4043 
4044         { "DAC 1", NULL, "DAC12 SRC Mux" },
4045         { "DAC 2", NULL, "DAC12 SRC Mux" },
4046         { "DAC 3", NULL, "DAC3 SRC Mux" },
4047 
4048         { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4049         { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4050         { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4051         { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4052         { "PDM1 L Mux", NULL, "PDM1 Power" },
4053         { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4054         { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4055         { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4056         { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4057         { "PDM1 R Mux", NULL, "PDM1 Power" },
4058         { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4059         { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4060         { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4061         { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4062         { "PDM2 L Mux", NULL, "PDM2 Power" },
4063         { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4064         { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4065         { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4066         { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4067         { "PDM2 R Mux", NULL, "PDM2 Power" },
4068 
4069         { "LOUT1 amp", NULL, "DAC 1" },
4070         { "LOUT2 amp", NULL, "DAC 2" },
4071         { "LOUT3 amp", NULL, "DAC 3" },
4072 
4073         { "LOUT1 vref", NULL, "LOUT1 amp" },
4074         { "LOUT2 vref", NULL, "LOUT2 amp" },
4075         { "LOUT3 vref", NULL, "LOUT3 amp" },
4076 
4077         { "LOUT1", NULL, "LOUT1 vref" },
4078         { "LOUT2", NULL, "LOUT2 vref" },
4079         { "LOUT3", NULL, "LOUT3 vref" },
4080 
4081         { "PDM1L", NULL, "PDM1 L Mux" },
4082         { "PDM1R", NULL, "PDM1 R Mux" },
4083         { "PDM2L", NULL, "PDM2 L Mux" },
4084         { "PDM2R", NULL, "PDM2 R Mux" },
4085 };
4086 
4087 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4088         { "DMIC L2", NULL, "DMIC1 power" },
4089         { "DMIC R2", NULL, "DMIC1 power" },
4090 };
4091 
4092 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4093         { "DMIC L2", NULL, "DMIC2 power" },
4094         { "DMIC R2", NULL, "DMIC2 power" },
4095 };
4096 
4097 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4098         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4099 {
4100         struct snd_soc_component *component = dai->component;
4101         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4102         unsigned int val_len = 0, val_clk, mask_clk;
4103         int pre_div, bclk_ms, frame_size;
4104 
4105         rt5677->lrck[dai->id] = params_rate(params);
4106         pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4107         if (pre_div < 0) {
4108                 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4109                         rt5677->sysclk, rt5677->lrck[dai->id]);
4110                 return -EINVAL;
4111         }
4112         frame_size = snd_soc_params_to_frame_size(params);
4113         if (frame_size < 0) {
4114                 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4115                 return -EINVAL;
4116         }
4117         bclk_ms = frame_size > 32;
4118         rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4119 
4120         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4121                 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4122         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4123                                 bclk_ms, pre_div, dai->id);
4124 
4125         switch (params_width(params)) {
4126         case 16:
4127                 break;
4128         case 20:
4129                 val_len |= RT5677_I2S_DL_20;
4130                 break;
4131         case 24:
4132                 val_len |= RT5677_I2S_DL_24;
4133                 break;
4134         case 8:
4135                 val_len |= RT5677_I2S_DL_8;
4136                 break;
4137         default:
4138                 return -EINVAL;
4139         }
4140 
4141         switch (dai->id) {
4142         case RT5677_AIF1:
4143                 mask_clk = RT5677_I2S_PD1_MASK;
4144                 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4145                 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4146                         RT5677_I2S_DL_MASK, val_len);
4147                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4148                         mask_clk, val_clk);
4149                 break;
4150         case RT5677_AIF2:
4151                 mask_clk = RT5677_I2S_PD2_MASK;
4152                 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4153                 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4154                         RT5677_I2S_DL_MASK, val_len);
4155                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4156                         mask_clk, val_clk);
4157                 break;
4158         case RT5677_AIF3:
4159                 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4160                 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4161                         pre_div << RT5677_I2S_PD3_SFT;
4162                 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4163                         RT5677_I2S_DL_MASK, val_len);
4164                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4165                         mask_clk, val_clk);
4166                 break;
4167         case RT5677_AIF4:
4168                 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4169                 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4170                         pre_div << RT5677_I2S_PD4_SFT;
4171                 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4172                         RT5677_I2S_DL_MASK, val_len);
4173                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4174                         mask_clk, val_clk);
4175                 break;
4176         default:
4177                 break;
4178         }
4179 
4180         return 0;
4181 }
4182 
4183 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4184 {
4185         struct snd_soc_component *component = dai->component;
4186         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4187         unsigned int reg_val = 0;
4188 
4189         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4190         case SND_SOC_DAIFMT_CBM_CFM:
4191                 rt5677->master[dai->id] = 1;
4192                 break;
4193         case SND_SOC_DAIFMT_CBS_CFS:
4194                 reg_val |= RT5677_I2S_MS_S;
4195                 rt5677->master[dai->id] = 0;
4196                 break;
4197         default:
4198                 return -EINVAL;
4199         }
4200 
4201         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4202         case SND_SOC_DAIFMT_NB_NF:
4203                 break;
4204         case SND_SOC_DAIFMT_IB_NF:
4205                 reg_val |= RT5677_I2S_BP_INV;
4206                 break;
4207         default:
4208                 return -EINVAL;
4209         }
4210 
4211         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4212         case SND_SOC_DAIFMT_I2S:
4213                 break;
4214         case SND_SOC_DAIFMT_LEFT_J:
4215                 reg_val |= RT5677_I2S_DF_LEFT;
4216                 break;
4217         case SND_SOC_DAIFMT_DSP_A:
4218                 reg_val |= RT5677_I2S_DF_PCM_A;
4219                 break;
4220         case SND_SOC_DAIFMT_DSP_B:
4221                 reg_val |= RT5677_I2S_DF_PCM_B;
4222                 break;
4223         default:
4224                 return -EINVAL;
4225         }
4226 
4227         switch (dai->id) {
4228         case RT5677_AIF1:
4229                 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4230                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4231                         RT5677_I2S_DF_MASK, reg_val);
4232                 break;
4233         case RT5677_AIF2:
4234                 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4235                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4236                         RT5677_I2S_DF_MASK, reg_val);
4237                 break;
4238         case RT5677_AIF3:
4239                 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4240                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4241                         RT5677_I2S_DF_MASK, reg_val);
4242                 break;
4243         case RT5677_AIF4:
4244                 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4245                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4246                         RT5677_I2S_DF_MASK, reg_val);
4247                 break;
4248         default:
4249                 break;
4250         }
4251 
4252 
4253         return 0;
4254 }
4255 
4256 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4257                 int clk_id, unsigned int freq, int dir)
4258 {
4259         struct snd_soc_component *component = dai->component;
4260         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4261         unsigned int reg_val = 0;
4262 
4263         if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4264                 return 0;
4265 
4266         switch (clk_id) {
4267         case RT5677_SCLK_S_MCLK:
4268                 reg_val |= RT5677_SCLK_SRC_MCLK;
4269                 break;
4270         case RT5677_SCLK_S_PLL1:
4271                 reg_val |= RT5677_SCLK_SRC_PLL1;
4272                 break;
4273         case RT5677_SCLK_S_RCCLK:
4274                 reg_val |= RT5677_SCLK_SRC_RCCLK;
4275                 break;
4276         default:
4277                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4278                 return -EINVAL;
4279         }
4280         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4281                 RT5677_SCLK_SRC_MASK, reg_val);
4282         rt5677->sysclk = freq;
4283         rt5677->sysclk_src = clk_id;
4284 
4285         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4286 
4287         return 0;
4288 }
4289 
4290 /**
4291  * rt5677_pll_calc - Calcualte PLL M/N/K code.
4292  * @freq_in: external clock provided to codec.
4293  * @freq_out: target clock which codec works on.
4294  * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4295  *
4296  * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4297  *
4298  * Returns 0 for success or negative error code.
4299  */
4300 static int rt5677_pll_calc(const unsigned int freq_in,
4301         const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4302 {
4303         if (RT5677_PLL_INP_MIN > freq_in)
4304                 return -EINVAL;
4305 
4306         return rl6231_pll_calc(freq_in, freq_out, pll_code);
4307 }
4308 
4309 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4310                         unsigned int freq_in, unsigned int freq_out)
4311 {
4312         struct snd_soc_component *component = dai->component;
4313         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4314         struct rl6231_pll_code pll_code;
4315         int ret;
4316 
4317         if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4318             freq_out == rt5677->pll_out)
4319                 return 0;
4320 
4321         if (!freq_in || !freq_out) {
4322                 dev_dbg(component->dev, "PLL disabled\n");
4323 
4324                 rt5677->pll_in = 0;
4325                 rt5677->pll_out = 0;
4326                 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4327                         RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4328                 return 0;
4329         }
4330 
4331         switch (source) {
4332         case RT5677_PLL1_S_MCLK:
4333                 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4334                         RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4335                 break;
4336         case RT5677_PLL1_S_BCLK1:
4337         case RT5677_PLL1_S_BCLK2:
4338         case RT5677_PLL1_S_BCLK3:
4339         case RT5677_PLL1_S_BCLK4:
4340                 switch (dai->id) {
4341                 case RT5677_AIF1:
4342                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4343                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4344                         break;
4345                 case RT5677_AIF2:
4346                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4347                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4348                         break;
4349                 case RT5677_AIF3:
4350                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4351                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4352                         break;
4353                 case RT5677_AIF4:
4354                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4355                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4356                         break;
4357                 default:
4358                         break;
4359                 }
4360                 break;
4361         default:
4362                 dev_err(component->dev, "Unknown PLL source %d\n", source);
4363                 return -EINVAL;
4364         }
4365 
4366         ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4367         if (ret < 0) {
4368                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
4369                 return ret;
4370         }
4371 
4372         dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4373                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4374                 pll_code.n_code, pll_code.k_code);
4375 
4376         regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4377                 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4378         regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4379                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4380                 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4381 
4382         rt5677->pll_in = freq_in;
4383         rt5677->pll_out = freq_out;
4384         rt5677->pll_src = source;
4385 
4386         return 0;
4387 }
4388 
4389 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4390                         unsigned int rx_mask, int slots, int slot_width)
4391 {
4392         struct snd_soc_component *component = dai->component;
4393         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4394         unsigned int val = 0, slot_width_25 = 0;
4395 
4396         if (rx_mask || tx_mask)
4397                 val |= (1 << 12);
4398 
4399         switch (slots) {
4400         case 4:
4401                 val |= (1 << 10);
4402                 break;
4403         case 6:
4404                 val |= (2 << 10);
4405                 break;
4406         case 8:
4407                 val |= (3 << 10);
4408                 break;
4409         case 2:
4410         default:
4411                 break;
4412         }
4413 
4414         switch (slot_width) {
4415         case 20:
4416                 val |= (1 << 8);
4417                 break;
4418         case 25:
4419                 slot_width_25 = 0x8080;
4420                 /* fall through */
4421         case 24:
4422                 val |= (2 << 8);
4423                 break;
4424         case 32:
4425                 val |= (3 << 8);
4426                 break;
4427         case 16:
4428         default:
4429                 break;
4430         }
4431 
4432         switch (dai->id) {
4433         case RT5677_AIF1:
4434                 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4435                         val);
4436                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4437                         slot_width_25);
4438                 break;
4439         case RT5677_AIF2:
4440                 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4441                         val);
4442                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4443                         slot_width_25);
4444                 break;
4445         default:
4446                 break;
4447         }
4448 
4449         return 0;
4450 }
4451 
4452 static int rt5677_set_bias_level(struct snd_soc_component *component,
4453                         enum snd_soc_bias_level level)
4454 {
4455         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4456 
4457         switch (level) {
4458         case SND_SOC_BIAS_ON:
4459                 break;
4460 
4461         case SND_SOC_BIAS_PREPARE:
4462                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
4463                         rt5677_set_dsp_vad(component, false);
4464 
4465                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4466                                 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4467                                 0x0055);
4468                         regmap_update_bits(rt5677->regmap,
4469                                 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4470                                 0x0f00, 0x0f00);
4471                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4472                                 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4473                                 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4474                                 RT5677_PWR_BG | RT5677_PWR_VREF2,
4475                                 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4476                                 RT5677_PWR_BG | RT5677_PWR_VREF2);
4477                         rt5677->is_vref_slow = false;
4478                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4479                                 RT5677_PWR_CORE, RT5677_PWR_CORE);
4480                         regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4481                                 0x1, 0x1);
4482                 }
4483                 break;
4484 
4485         case SND_SOC_BIAS_STANDBY:
4486                 break;
4487 
4488         case SND_SOC_BIAS_OFF:
4489                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4490                 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4491                 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4492                 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4493                 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4494                 regmap_update_bits(rt5677->regmap,
4495                         RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4496 
4497                 if (rt5677->dsp_vad_en)
4498                         rt5677_set_dsp_vad(component, true);
4499                 break;
4500 
4501         default:
4502                 break;
4503         }
4504 
4505         return 0;
4506 }
4507 
4508 #ifdef CONFIG_GPIOLIB
4509 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4510 {
4511         struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4512 
4513         switch (offset) {
4514         case RT5677_GPIO1 ... RT5677_GPIO5:
4515                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4516                         0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4517                 break;
4518 
4519         case RT5677_GPIO6:
4520                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4521                         RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4522                 break;
4523 
4524         default:
4525                 break;
4526         }
4527 }
4528 
4529 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4530                                      unsigned offset, int value)
4531 {
4532         struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4533 
4534         switch (offset) {
4535         case RT5677_GPIO1 ... RT5677_GPIO5:
4536                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4537                         0x3 << (offset * 3 + 1),
4538                         (0x2 | !!value) << (offset * 3 + 1));
4539                 break;
4540 
4541         case RT5677_GPIO6:
4542                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4543                         RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4544                         RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4545                 break;
4546 
4547         default:
4548                 break;
4549         }
4550 
4551         return 0;
4552 }
4553 
4554 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4555 {
4556         struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4557         int value, ret;
4558 
4559         ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4560         if (ret < 0)
4561                 return ret;
4562 
4563         return (value & (0x1 << offset)) >> offset;
4564 }
4565 
4566 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4567 {
4568         struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4569 
4570         switch (offset) {
4571         case RT5677_GPIO1 ... RT5677_GPIO5:
4572                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4573                         0x1 << (offset * 3 + 2), 0x0);
4574                 break;
4575 
4576         case RT5677_GPIO6:
4577                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4578                         RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4579                 break;
4580 
4581         default:
4582                 break;
4583         }
4584 
4585         return 0;
4586 }
4587 
4588 /** Configures the gpio as
4589  *   0 - floating
4590  *   1 - pull down
4591  *   2 - pull up
4592  */
4593 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4594                 int value)
4595 {
4596         int shift;
4597 
4598         switch (offset) {
4599         case RT5677_GPIO1 ... RT5677_GPIO2:
4600                 shift = 2 * (1 - offset);
4601                 regmap_update_bits(rt5677->regmap,
4602                         RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4603                         0x3 << shift,
4604                         (value & 0x3) << shift);
4605                 break;
4606 
4607         case RT5677_GPIO3 ... RT5677_GPIO6:
4608                 shift = 2 * (9 - offset);
4609                 regmap_update_bits(rt5677->regmap,
4610                         RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4611                         0x3 << shift,
4612                         (value & 0x3) << shift);
4613                 break;
4614 
4615         default:
4616                 break;
4617         }
4618 }
4619 
4620 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4621 {
4622         struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4623         struct regmap_irq_chip_data *data = rt5677->irq_data;
4624         int irq;
4625 
4626         if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4627                 (rt5677->pdata.jd1_gpio == 2 &&
4628                         offset == RT5677_GPIO2) ||
4629                 (rt5677->pdata.jd1_gpio == 3 &&
4630                         offset == RT5677_GPIO3)) {
4631                 irq = RT5677_IRQ_JD1;
4632         } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4633                 (rt5677->pdata.jd2_gpio == 2 &&
4634                         offset == RT5677_GPIO5) ||
4635                 (rt5677->pdata.jd2_gpio == 3 &&
4636                         offset == RT5677_GPIO6)) {
4637                 irq = RT5677_IRQ_JD2;
4638         } else if ((rt5677->pdata.jd3_gpio == 1 &&
4639                         offset == RT5677_GPIO4) ||
4640                 (rt5677->pdata.jd3_gpio == 2 &&
4641                         offset == RT5677_GPIO5) ||
4642                 (rt5677->pdata.jd3_gpio == 3 &&
4643                         offset == RT5677_GPIO6)) {
4644                 irq = RT5677_IRQ_JD3;
4645         } else {
4646                 return -ENXIO;
4647         }
4648 
4649         return regmap_irq_get_virq(data, irq);
4650 }
4651 
4652 static const struct gpio_chip rt5677_template_chip = {
4653         .label                  = "rt5677",
4654         .owner                  = THIS_MODULE,
4655         .direction_output       = rt5677_gpio_direction_out,
4656         .set                    = rt5677_gpio_set,
4657         .direction_input        = rt5677_gpio_direction_in,
4658         .get                    = rt5677_gpio_get,
4659         .to_irq                 = rt5677_to_irq,
4660         .can_sleep              = 1,
4661 };
4662 
4663 static void rt5677_init_gpio(struct i2c_client *i2c)
4664 {
4665         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4666         int ret;
4667 
4668         rt5677->gpio_chip = rt5677_template_chip;
4669         rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4670         rt5677->gpio_chip.parent = &i2c->dev;
4671         rt5677->gpio_chip.base = -1;
4672 
4673         ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4674         if (ret != 0)
4675                 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4676 }
4677 
4678 static void rt5677_free_gpio(struct i2c_client *i2c)
4679 {
4680         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4681 
4682         gpiochip_remove(&rt5677->gpio_chip);
4683 }
4684 #else
4685 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4686                 int value)
4687 {
4688 }
4689 
4690 static void rt5677_init_gpio(struct i2c_client *i2c)
4691 {
4692 }
4693 
4694 static void rt5677_free_gpio(struct i2c_client *i2c)
4695 {
4696 }
4697 #endif
4698 
4699 static int rt5677_probe(struct snd_soc_component *component)
4700 {
4701         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4702         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4703         int i;
4704 
4705         rt5677->component = component;
4706 
4707         if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4708                 snd_soc_dapm_add_routes(dapm,
4709                         rt5677_dmic2_clk_2,
4710                         ARRAY_SIZE(rt5677_dmic2_clk_2));
4711         } else { /*use dmic1 clock by default*/
4712                 snd_soc_dapm_add_routes(dapm,
4713                         rt5677_dmic2_clk_1,
4714                         ARRAY_SIZE(rt5677_dmic2_clk_1));
4715         }
4716 
4717         snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
4718 
4719         regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4720         regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4721 
4722         for (i = 0; i < RT5677_GPIO_NUM; i++)
4723                 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4724 
4725         if (rt5677->irq_data) {
4726                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4727                         0x8000);
4728                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4729                         0x0008);
4730 
4731                 if (rt5677->pdata.jd1_gpio)
4732                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4733                                 RT5677_SEL_GPIO_JD1_MASK,
4734                                 rt5677->pdata.jd1_gpio <<
4735                                 RT5677_SEL_GPIO_JD1_SFT);
4736 
4737                 if (rt5677->pdata.jd2_gpio)
4738                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4739                                 RT5677_SEL_GPIO_JD2_MASK,
4740                                 rt5677->pdata.jd2_gpio <<
4741                                 RT5677_SEL_GPIO_JD2_SFT);
4742 
4743                 if (rt5677->pdata.jd3_gpio)
4744                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4745                                 RT5677_SEL_GPIO_JD3_MASK,
4746                                 rt5677->pdata.jd3_gpio <<
4747                                 RT5677_SEL_GPIO_JD3_SFT);
4748         }
4749 
4750         mutex_init(&rt5677->dsp_cmd_lock);
4751         mutex_init(&rt5677->dsp_pri_lock);
4752 
4753         return 0;
4754 }
4755 
4756 static void rt5677_remove(struct snd_soc_component *component)
4757 {
4758         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4759 
4760         regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4761         gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4762         gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4763 }
4764 
4765 #ifdef CONFIG_PM
4766 static int rt5677_suspend(struct snd_soc_component *component)
4767 {
4768         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4769 
4770         if (!rt5677->dsp_vad_en) {
4771                 regcache_cache_only(rt5677->regmap, true);
4772                 regcache_mark_dirty(rt5677->regmap);
4773 
4774                 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4775                 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4776         }
4777 
4778         return 0;
4779 }
4780 
4781 static int rt5677_resume(struct snd_soc_component *component)
4782 {
4783         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4784 
4785         if (!rt5677->dsp_vad_en) {
4786                 rt5677->pll_src = 0;
4787                 rt5677->pll_in = 0;
4788                 rt5677->pll_out = 0;
4789                 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4790                 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4791                 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4792                         msleep(10);
4793 
4794                 regcache_cache_only(rt5677->regmap, false);
4795                 regcache_sync(rt5677->regmap);
4796         }
4797 
4798         return 0;
4799 }
4800 #else
4801 #define rt5677_suspend NULL
4802 #define rt5677_resume NULL
4803 #endif
4804 
4805 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4806 {
4807         struct i2c_client *client = context;
4808         struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4809 
4810         if (rt5677->is_dsp_mode) {
4811                 if (reg > 0xff) {
4812                         mutex_lock(&rt5677->dsp_pri_lock);
4813                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4814                                 reg & 0xff);
4815                         rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4816                         mutex_unlock(&rt5677->dsp_pri_lock);
4817                 } else {
4818                         rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4819                 }
4820         } else {
4821                 regmap_read(rt5677->regmap_physical, reg, val);
4822         }
4823 
4824         return 0;
4825 }
4826 
4827 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4828 {
4829         struct i2c_client *client = context;
4830         struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4831 
4832         if (rt5677->is_dsp_mode) {
4833                 if (reg > 0xff) {
4834                         mutex_lock(&rt5677->dsp_pri_lock);
4835                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4836                                 reg & 0xff);
4837                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4838                                 val);
4839                         mutex_unlock(&rt5677->dsp_pri_lock);
4840                 } else {
4841                         rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4842                 }
4843         } else {
4844                 regmap_write(rt5677->regmap_physical, reg, val);
4845         }
4846 
4847         return 0;
4848 }
4849 
4850 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4851 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4852                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4853 
4854 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4855         .hw_params = rt5677_hw_params,
4856         .set_fmt = rt5677_set_dai_fmt,
4857         .set_sysclk = rt5677_set_dai_sysclk,
4858         .set_pll = rt5677_set_dai_pll,
4859         .set_tdm_slot = rt5677_set_tdm_slot,
4860 };
4861 
4862 static struct snd_soc_dai_driver rt5677_dai[] = {
4863         {
4864                 .name = "rt5677-aif1",
4865                 .id = RT5677_AIF1,
4866                 .playback = {
4867                         .stream_name = "AIF1 Playback",
4868                         .channels_min = 1,
4869                         .channels_max = 2,
4870                         .rates = RT5677_STEREO_RATES,
4871                         .formats = RT5677_FORMATS,
4872                 },
4873                 .capture = {
4874                         .stream_name = "AIF1 Capture",
4875                         .channels_min = 1,
4876                         .channels_max = 2,
4877                         .rates = RT5677_STEREO_RATES,
4878                         .formats = RT5677_FORMATS,
4879                 },
4880                 .ops = &rt5677_aif_dai_ops,
4881         },
4882         {
4883                 .name = "rt5677-aif2",
4884                 .id = RT5677_AIF2,
4885                 .playback = {
4886                         .stream_name = "AIF2 Playback",
4887                         .channels_min = 1,
4888                         .channels_max = 2,
4889                         .rates = RT5677_STEREO_RATES,
4890                         .formats = RT5677_FORMATS,
4891                 },
4892                 .capture = {
4893                         .stream_name = "AIF2 Capture",
4894                         .channels_min = 1,
4895                         .channels_max = 2,
4896                         .rates = RT5677_STEREO_RATES,
4897                         .formats = RT5677_FORMATS,
4898                 },
4899                 .ops = &rt5677_aif_dai_ops,
4900         },
4901         {
4902                 .name = "rt5677-aif3",
4903                 .id = RT5677_AIF3,
4904                 .playback = {
4905                         .stream_name = "AIF3 Playback",
4906                         .channels_min = 1,
4907                         .channels_max = 2,
4908                         .rates = RT5677_STEREO_RATES,
4909                         .formats = RT5677_FORMATS,
4910                 },
4911                 .capture = {
4912                         .stream_name = "AIF3 Capture",
4913                         .channels_min = 1,
4914                         .channels_max = 2,
4915                         .rates = RT5677_STEREO_RATES,
4916                         .formats = RT5677_FORMATS,
4917                 },
4918                 .ops = &rt5677_aif_dai_ops,
4919         },
4920         {
4921                 .name = "rt5677-aif4",
4922                 .id = RT5677_AIF4,
4923                 .playback = {
4924                         .stream_name = "AIF4 Playback",
4925                         .channels_min = 1,
4926                         .channels_max = 2,
4927                         .rates = RT5677_STEREO_RATES,
4928                         .formats = RT5677_FORMATS,
4929                 },
4930                 .capture = {
4931                         .stream_name = "AIF4 Capture",
4932                         .channels_min = 1,
4933                         .channels_max = 2,
4934                         .rates = RT5677_STEREO_RATES,
4935                         .formats = RT5677_FORMATS,
4936                 },
4937                 .ops = &rt5677_aif_dai_ops,
4938         },
4939         {
4940                 .name = "rt5677-slimbus",
4941                 .id = RT5677_AIF5,
4942                 .playback = {
4943                         .stream_name = "SLIMBus Playback",
4944                         .channels_min = 1,
4945                         .channels_max = 2,
4946                         .rates = RT5677_STEREO_RATES,
4947                         .formats = RT5677_FORMATS,
4948                 },
4949                 .capture = {
4950                         .stream_name = "SLIMBus Capture",
4951                         .channels_min = 1,
4952                         .channels_max = 2,
4953                         .rates = RT5677_STEREO_RATES,
4954                         .formats = RT5677_FORMATS,
4955                 },
4956                 .ops = &rt5677_aif_dai_ops,
4957         },
4958 };
4959 
4960 static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
4961         .probe                  = rt5677_probe,
4962         .remove                 = rt5677_remove,
4963         .suspend                = rt5677_suspend,
4964         .resume                 = rt5677_resume,
4965         .set_bias_level         = rt5677_set_bias_level,
4966         .controls               = rt5677_snd_controls,
4967         .num_controls           = ARRAY_SIZE(rt5677_snd_controls),
4968         .dapm_widgets           = rt5677_dapm_widgets,
4969         .num_dapm_widgets       = ARRAY_SIZE(rt5677_dapm_widgets),
4970         .dapm_routes            = rt5677_dapm_routes,
4971         .num_dapm_routes        = ARRAY_SIZE(rt5677_dapm_routes),
4972         .use_pmdown_time        = 1,
4973         .endianness             = 1,
4974         .non_legacy_dai_naming  = 1,
4975 };
4976 
4977 static const struct regmap_config rt5677_regmap_physical = {
4978         .name = "physical",
4979         .reg_bits = 8,
4980         .val_bits = 16,
4981 
4982         .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4983                                                 RT5677_PR_SPACING),
4984         .readable_reg = rt5677_readable_register,
4985 
4986         .cache_type = REGCACHE_NONE,
4987         .ranges = rt5677_ranges,
4988         .num_ranges = ARRAY_SIZE(rt5677_ranges),
4989 };
4990 
4991 static const struct regmap_config rt5677_regmap = {
4992         .reg_bits = 8,
4993         .val_bits = 16,
4994 
4995         .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4996                                                 RT5677_PR_SPACING),
4997 
4998         .volatile_reg = rt5677_volatile_register,
4999         .readable_reg = rt5677_readable_register,
5000         .reg_read = rt5677_read,
5001         .reg_write = rt5677_write,
5002 
5003         .cache_type = REGCACHE_RBTREE,
5004         .reg_defaults = rt5677_reg,
5005         .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5006         .ranges = rt5677_ranges,
5007         .num_ranges = ARRAY_SIZE(rt5677_ranges),
5008 };
5009 
5010 static const struct of_device_id rt5677_of_match[] = {
5011         { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
5012         { }
5013 };
5014 MODULE_DEVICE_TABLE(of, rt5677_of_match);
5015 
5016 static const struct acpi_device_id rt5677_acpi_match[] = {
5017         { "RT5677CE", RT5677 },
5018         { }
5019 };
5020 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
5021 
5022 static void rt5677_read_acpi_properties(struct rt5677_priv *rt5677,
5023                 struct device *dev)
5024 {
5025         u32 val;
5026 
5027         if (!device_property_read_u32(dev, "DCLK", &val))
5028                 rt5677->pdata.dmic2_clk_pin = val;
5029 
5030         rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1");
5031         rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2");
5032         rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1");
5033         rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2");
5034         rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3");
5035 
5036         device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio);
5037         device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio);
5038         device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio);
5039 }
5040 
5041 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5042                 struct device *dev)
5043 {
5044         rt5677->pdata.in1_diff = device_property_read_bool(dev,
5045                         "realtek,in1-differential");
5046         rt5677->pdata.in2_diff = device_property_read_bool(dev,
5047                         "realtek,in2-differential");
5048         rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5049                         "realtek,lout1-differential");
5050         rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5051                         "realtek,lout2-differential");
5052         rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5053                         "realtek,lout3-differential");
5054 
5055         device_property_read_u8_array(dev, "realtek,gpio-config",
5056                         rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5057 
5058         device_property_read_u32(dev, "realtek,jd1-gpio",
5059                         &rt5677->pdata.jd1_gpio);
5060         device_property_read_u32(dev, "realtek,jd2-gpio",
5061                         &rt5677->pdata.jd2_gpio);
5062         device_property_read_u32(dev, "realtek,jd3-gpio",
5063                         &rt5677->pdata.jd3_gpio);
5064 }
5065 
5066 static struct regmap_irq rt5677_irqs[] = {
5067         [RT5677_IRQ_JD1] = {
5068                 .reg_offset = 0,
5069                 .mask = RT5677_EN_IRQ_GPIO_JD1,
5070         },
5071         [RT5677_IRQ_JD2] = {
5072                 .reg_offset = 0,
5073                 .mask = RT5677_EN_IRQ_GPIO_JD2,
5074         },
5075         [RT5677_IRQ_JD3] = {
5076                 .reg_offset = 0,
5077                 .mask = RT5677_EN_IRQ_GPIO_JD3,
5078         },
5079 };
5080 
5081 static struct regmap_irq_chip rt5677_irq_chip = {
5082         .name = "rt5677",
5083         .irqs = rt5677_irqs,
5084         .num_irqs = ARRAY_SIZE(rt5677_irqs),
5085 
5086         .num_regs = 1,
5087         .status_base = RT5677_IRQ_CTRL1,
5088         .mask_base = RT5677_IRQ_CTRL1,
5089         .mask_invert = 1,
5090 };
5091 
5092 static int rt5677_init_irq(struct i2c_client *i2c)
5093 {
5094         int ret;
5095         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5096 
5097         if (!rt5677->pdata.jd1_gpio &&
5098                 !rt5677->pdata.jd2_gpio &&
5099                 !rt5677->pdata.jd3_gpio)
5100                 return 0;
5101 
5102         if (!i2c->irq) {
5103                 dev_err(&i2c->dev, "No interrupt specified\n");
5104                 return -EINVAL;
5105         }
5106 
5107         ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5108                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5109                 &rt5677_irq_chip, &rt5677->irq_data);
5110 
5111         if (ret != 0) {
5112                 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5113                 return ret;
5114         }
5115 
5116         return 0;
5117 }
5118 
5119 static void rt5677_free_irq(struct i2c_client *i2c)
5120 {
5121         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5122 
5123         if (rt5677->irq_data)
5124                 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5125 }
5126 
5127 static int rt5677_i2c_probe(struct i2c_client *i2c)
5128 {
5129         struct rt5677_priv *rt5677;
5130         int ret;
5131         unsigned int val;
5132 
5133         rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5134                                 GFP_KERNEL);
5135         if (rt5677 == NULL)
5136                 return -ENOMEM;
5137 
5138         i2c_set_clientdata(i2c, rt5677);
5139 
5140         if (i2c->dev.of_node) {
5141                 const struct of_device_id *match_id;
5142 
5143                 match_id = of_match_device(rt5677_of_match, &i2c->dev);
5144                 if (match_id)
5145                         rt5677->type = (enum rt5677_type)match_id->data;
5146 
5147                 rt5677_read_device_properties(rt5677, &i2c->dev);
5148         } else if (ACPI_HANDLE(&i2c->dev)) {
5149                 const struct acpi_device_id *acpi_id;
5150 
5151                 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
5152                 if (acpi_id)
5153                         rt5677->type = (enum rt5677_type)acpi_id->driver_data;
5154 
5155                 rt5677_read_acpi_properties(rt5677, &i2c->dev);
5156         } else {
5157                 return -EINVAL;
5158         }
5159 
5160         /* pow-ldo2 and reset are optional. The codec pins may be statically
5161          * connected on the board without gpios. If the gpio device property
5162          * isn't specified, devm_gpiod_get_optional returns NULL.
5163          */
5164         rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5165                         "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5166         if (IS_ERR(rt5677->pow_ldo2)) {
5167                 ret = PTR_ERR(rt5677->pow_ldo2);
5168                 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5169                 return ret;
5170         }
5171         rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5172                         "realtek,reset", GPIOD_OUT_LOW);
5173         if (IS_ERR(rt5677->reset_pin)) {
5174                 ret = PTR_ERR(rt5677->reset_pin);
5175                 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5176                 return ret;
5177         }
5178 
5179         if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5180                 /* Wait a while until I2C bus becomes available. The datasheet
5181                  * does not specify the exact we should wait but startup
5182                  * sequence mentiones at least a few milliseconds.
5183                  */
5184                 msleep(10);
5185         }
5186 
5187         rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5188                                         &rt5677_regmap_physical);
5189         if (IS_ERR(rt5677->regmap_physical)) {
5190                 ret = PTR_ERR(rt5677->regmap_physical);
5191                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5192                         ret);
5193                 return ret;
5194         }
5195 
5196         rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5197         if (IS_ERR(rt5677->regmap)) {
5198                 ret = PTR_ERR(rt5677->regmap);
5199                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5200                         ret);
5201                 return ret;
5202         }
5203 
5204         regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5205         if (val != RT5677_DEVICE_ID) {
5206                 dev_err(&i2c->dev,
5207                         "Device with ID register %#x is not rt5677\n", val);
5208                 return -ENODEV;
5209         }
5210 
5211         regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5212 
5213         ret = regmap_register_patch(rt5677->regmap, init_list,
5214                                     ARRAY_SIZE(init_list));
5215         if (ret != 0)
5216                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5217 
5218         if (rt5677->pdata.in1_diff)
5219                 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5220                                         RT5677_IN_DF1, RT5677_IN_DF1);
5221 
5222         if (rt5677->pdata.in2_diff)
5223                 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5224                                         RT5677_IN_DF2, RT5677_IN_DF2);
5225 
5226         if (rt5677->pdata.lout1_diff)
5227                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5228                                         RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5229 
5230         if (rt5677->pdata.lout2_diff)
5231                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5232                                         RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5233 
5234         if (rt5677->pdata.lout3_diff)
5235                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5236                                         RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5237 
5238         if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5239                 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5240                                         RT5677_GPIO5_FUNC_MASK,
5241                                         RT5677_GPIO5_FUNC_DMIC);
5242                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5243                                         RT5677_GPIO5_DIR_MASK,
5244                                         RT5677_GPIO5_DIR_OUT);
5245         }
5246 
5247         if (rt5677->pdata.micbias1_vdd_3v3)
5248                 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5249                         RT5677_MICBIAS1_CTRL_VDD_MASK,
5250                         RT5677_MICBIAS1_CTRL_VDD_3_3V);
5251 
5252         rt5677_init_gpio(i2c);
5253         rt5677_init_irq(i2c);
5254 
5255         return devm_snd_soc_register_component(&i2c->dev,
5256                                       &soc_component_dev_rt5677,
5257                                       rt5677_dai, ARRAY_SIZE(rt5677_dai));
5258 }
5259 
5260 static int rt5677_i2c_remove(struct i2c_client *i2c)
5261 {
5262         rt5677_free_irq(i2c);
5263         rt5677_free_gpio(i2c);
5264 
5265         return 0;
5266 }
5267 
5268 static struct i2c_driver rt5677_i2c_driver = {
5269         .driver = {
5270                 .name = "rt5677",
5271                 .of_match_table = rt5677_of_match,
5272                 .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
5273         },
5274         .probe_new = rt5677_i2c_probe,
5275         .remove   = rt5677_i2c_remove,
5276 };
5277 module_i2c_driver(rt5677_i2c_driver);
5278 
5279 MODULE_DESCRIPTION("ASoC RT5677 driver");
5280 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5281 MODULE_LICENSE("GPL v2");
5282 

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