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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/rt5677.c

Version: ~ [ linux-5.12-rc7 ] ~ [ linux-5.11.13 ] ~ [ linux-5.10.29 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.111 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.186 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.230 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.266 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.266 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * rt5677.c  --  RT5677 ALSA SoC audio codec driver
  3  *
  4  * Copyright 2013 Realtek Semiconductor Corp.
  5  * Author: Oder Chiou <oder_chiou@realtek.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 
 12 #include <linux/fs.h>
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/init.h>
 16 #include <linux/delay.h>
 17 #include <linux/pm.h>
 18 #include <linux/regmap.h>
 19 #include <linux/i2c.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/spi/spi.h>
 22 #include <linux/firmware.h>
 23 #include <linux/property.h>
 24 #include <sound/core.h>
 25 #include <sound/pcm.h>
 26 #include <sound/pcm_params.h>
 27 #include <sound/soc.h>
 28 #include <sound/soc-dapm.h>
 29 #include <sound/initval.h>
 30 #include <sound/tlv.h>
 31 
 32 #include "rl6231.h"
 33 #include "rt5677.h"
 34 #include "rt5677-spi.h"
 35 
 36 #define RT5677_DEVICE_ID 0x6327
 37 
 38 #define RT5677_PR_RANGE_BASE (0xff + 1)
 39 #define RT5677_PR_SPACING 0x100
 40 
 41 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
 42 
 43 static const struct regmap_range_cfg rt5677_ranges[] = {
 44         {
 45                 .name = "PR",
 46                 .range_min = RT5677_PR_BASE,
 47                 .range_max = RT5677_PR_BASE + 0xfd,
 48                 .selector_reg = RT5677_PRIV_INDEX,
 49                 .selector_mask = 0xff,
 50                 .selector_shift = 0x0,
 51                 .window_start = RT5677_PRIV_DATA,
 52                 .window_len = 0x1,
 53         },
 54 };
 55 
 56 static const struct reg_sequence init_list[] = {
 57         {RT5677_ASRC_12,        0x0018},
 58         {RT5677_PR_BASE + 0x3d, 0x364d},
 59         {RT5677_PR_BASE + 0x17, 0x4fc0},
 60         {RT5677_PR_BASE + 0x13, 0x0312},
 61         {RT5677_PR_BASE + 0x1e, 0x0000},
 62         {RT5677_PR_BASE + 0x12, 0x0eaa},
 63         {RT5677_PR_BASE + 0x14, 0x018a},
 64         {RT5677_PR_BASE + 0x15, 0x0490},
 65         {RT5677_PR_BASE + 0x38, 0x0f71},
 66         {RT5677_PR_BASE + 0x39, 0x0f71},
 67 };
 68 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
 69 
 70 static const struct reg_default rt5677_reg[] = {
 71         {RT5677_RESET                   , 0x0000},
 72         {RT5677_LOUT1                   , 0xa800},
 73         {RT5677_IN1                     , 0x0000},
 74         {RT5677_MICBIAS                 , 0x0000},
 75         {RT5677_SLIMBUS_PARAM           , 0x0000},
 76         {RT5677_SLIMBUS_RX              , 0x0000},
 77         {RT5677_SLIMBUS_CTRL            , 0x0000},
 78         {RT5677_SIDETONE_CTRL           , 0x000b},
 79         {RT5677_ANA_DAC1_2_3_SRC        , 0x0000},
 80         {RT5677_IF_DSP_DAC3_4_MIXER     , 0x1111},
 81         {RT5677_DAC4_DIG_VOL            , 0xafaf},
 82         {RT5677_DAC3_DIG_VOL            , 0xafaf},
 83         {RT5677_DAC1_DIG_VOL            , 0xafaf},
 84         {RT5677_DAC2_DIG_VOL            , 0xafaf},
 85         {RT5677_IF_DSP_DAC2_MIXER       , 0x0011},
 86         {RT5677_STO1_ADC_DIG_VOL        , 0x2f2f},
 87         {RT5677_MONO_ADC_DIG_VOL        , 0x2f2f},
 88         {RT5677_STO1_2_ADC_BST          , 0x0000},
 89         {RT5677_STO2_ADC_DIG_VOL        , 0x2f2f},
 90         {RT5677_ADC_BST_CTRL2           , 0x0000},
 91         {RT5677_STO3_4_ADC_BST          , 0x0000},
 92         {RT5677_STO3_ADC_DIG_VOL        , 0x2f2f},
 93         {RT5677_STO4_ADC_DIG_VOL        , 0x2f2f},
 94         {RT5677_STO4_ADC_MIXER          , 0xd4c0},
 95         {RT5677_STO3_ADC_MIXER          , 0xd4c0},
 96         {RT5677_STO2_ADC_MIXER          , 0xd4c0},
 97         {RT5677_STO1_ADC_MIXER          , 0xd4c0},
 98         {RT5677_MONO_ADC_MIXER          , 0xd4d1},
 99         {RT5677_ADC_IF_DSP_DAC1_MIXER   , 0x8080},
100         {RT5677_STO1_DAC_MIXER          , 0xaaaa},
101         {RT5677_MONO_DAC_MIXER          , 0xaaaa},
102         {RT5677_DD1_MIXER               , 0xaaaa},
103         {RT5677_DD2_MIXER               , 0xaaaa},
104         {RT5677_IF3_DATA                , 0x0000},
105         {RT5677_IF4_DATA                , 0x0000},
106         {RT5677_PDM_OUT_CTRL            , 0x8888},
107         {RT5677_PDM_DATA_CTRL1          , 0x0000},
108         {RT5677_PDM_DATA_CTRL2          , 0x0000},
109         {RT5677_PDM1_DATA_CTRL2         , 0x0000},
110         {RT5677_PDM1_DATA_CTRL3         , 0x0000},
111         {RT5677_PDM1_DATA_CTRL4         , 0x0000},
112         {RT5677_PDM2_DATA_CTRL2         , 0x0000},
113         {RT5677_PDM2_DATA_CTRL3         , 0x0000},
114         {RT5677_PDM2_DATA_CTRL4         , 0x0000},
115         {RT5677_TDM1_CTRL1              , 0x0300},
116         {RT5677_TDM1_CTRL2              , 0x0000},
117         {RT5677_TDM1_CTRL3              , 0x4000},
118         {RT5677_TDM1_CTRL4              , 0x0123},
119         {RT5677_TDM1_CTRL5              , 0x4567},
120         {RT5677_TDM2_CTRL1              , 0x0300},
121         {RT5677_TDM2_CTRL2              , 0x0000},
122         {RT5677_TDM2_CTRL3              , 0x4000},
123         {RT5677_TDM2_CTRL4              , 0x0123},
124         {RT5677_TDM2_CTRL5              , 0x4567},
125         {RT5677_I2C_MASTER_CTRL1        , 0x0001},
126         {RT5677_I2C_MASTER_CTRL2        , 0x0000},
127         {RT5677_I2C_MASTER_CTRL3        , 0x0000},
128         {RT5677_I2C_MASTER_CTRL4        , 0x0000},
129         {RT5677_I2C_MASTER_CTRL5        , 0x0000},
130         {RT5677_I2C_MASTER_CTRL6        , 0x0000},
131         {RT5677_I2C_MASTER_CTRL7        , 0x0000},
132         {RT5677_I2C_MASTER_CTRL8        , 0x0000},
133         {RT5677_DMIC_CTRL1              , 0x1505},
134         {RT5677_DMIC_CTRL2              , 0x0055},
135         {RT5677_HAP_GENE_CTRL1          , 0x0111},
136         {RT5677_HAP_GENE_CTRL2          , 0x0064},
137         {RT5677_HAP_GENE_CTRL3          , 0xef0e},
138         {RT5677_HAP_GENE_CTRL4          , 0xf0f0},
139         {RT5677_HAP_GENE_CTRL5          , 0xef0e},
140         {RT5677_HAP_GENE_CTRL6          , 0xf0f0},
141         {RT5677_HAP_GENE_CTRL7          , 0xef0e},
142         {RT5677_HAP_GENE_CTRL8          , 0xf0f0},
143         {RT5677_HAP_GENE_CTRL9          , 0xf000},
144         {RT5677_HAP_GENE_CTRL10         , 0x0000},
145         {RT5677_PWR_DIG1                , 0x0000},
146         {RT5677_PWR_DIG2                , 0x0000},
147         {RT5677_PWR_ANLG1               , 0x0055},
148         {RT5677_PWR_ANLG2               , 0x0000},
149         {RT5677_PWR_DSP1                , 0x0001},
150         {RT5677_PWR_DSP_ST              , 0x0000},
151         {RT5677_PWR_DSP2                , 0x0000},
152         {RT5677_ADC_DAC_HPF_CTRL1       , 0x0e00},
153         {RT5677_PRIV_INDEX              , 0x0000},
154         {RT5677_PRIV_DATA               , 0x0000},
155         {RT5677_I2S4_SDP                , 0x8000},
156         {RT5677_I2S1_SDP                , 0x8000},
157         {RT5677_I2S2_SDP                , 0x8000},
158         {RT5677_I2S3_SDP                , 0x8000},
159         {RT5677_CLK_TREE_CTRL1          , 0x1111},
160         {RT5677_CLK_TREE_CTRL2          , 0x1111},
161         {RT5677_CLK_TREE_CTRL3          , 0x0000},
162         {RT5677_PLL1_CTRL1              , 0x0000},
163         {RT5677_PLL1_CTRL2              , 0x0000},
164         {RT5677_PLL2_CTRL1              , 0x0c60},
165         {RT5677_PLL2_CTRL2              , 0x2000},
166         {RT5677_GLB_CLK1                , 0x0000},
167         {RT5677_GLB_CLK2                , 0x0000},
168         {RT5677_ASRC_1                  , 0x0000},
169         {RT5677_ASRC_2                  , 0x0000},
170         {RT5677_ASRC_3                  , 0x0000},
171         {RT5677_ASRC_4                  , 0x0000},
172         {RT5677_ASRC_5                  , 0x0000},
173         {RT5677_ASRC_6                  , 0x0000},
174         {RT5677_ASRC_7                  , 0x0000},
175         {RT5677_ASRC_8                  , 0x0000},
176         {RT5677_ASRC_9                  , 0x0000},
177         {RT5677_ASRC_10                 , 0x0000},
178         {RT5677_ASRC_11                 , 0x0000},
179         {RT5677_ASRC_12                 , 0x0018},
180         {RT5677_ASRC_13                 , 0x0000},
181         {RT5677_ASRC_14                 , 0x0000},
182         {RT5677_ASRC_15                 , 0x0000},
183         {RT5677_ASRC_16                 , 0x0000},
184         {RT5677_ASRC_17                 , 0x0000},
185         {RT5677_ASRC_18                 , 0x0000},
186         {RT5677_ASRC_19                 , 0x0000},
187         {RT5677_ASRC_20                 , 0x0000},
188         {RT5677_ASRC_21                 , 0x000c},
189         {RT5677_ASRC_22                 , 0x0000},
190         {RT5677_ASRC_23                 , 0x0000},
191         {RT5677_VAD_CTRL1               , 0x2184},
192         {RT5677_VAD_CTRL2               , 0x010a},
193         {RT5677_VAD_CTRL3               , 0x0aea},
194         {RT5677_VAD_CTRL4               , 0x000c},
195         {RT5677_VAD_CTRL5               , 0x0000},
196         {RT5677_DSP_INB_CTRL1           , 0x0000},
197         {RT5677_DSP_INB_CTRL2           , 0x0000},
198         {RT5677_DSP_IN_OUTB_CTRL        , 0x0000},
199         {RT5677_DSP_OUTB0_1_DIG_VOL     , 0x2f2f},
200         {RT5677_DSP_OUTB2_3_DIG_VOL     , 0x2f2f},
201         {RT5677_DSP_OUTB4_5_DIG_VOL     , 0x2f2f},
202         {RT5677_DSP_OUTB6_7_DIG_VOL     , 0x2f2f},
203         {RT5677_ADC_EQ_CTRL1            , 0x6000},
204         {RT5677_ADC_EQ_CTRL2            , 0x0000},
205         {RT5677_EQ_CTRL1                , 0xc000},
206         {RT5677_EQ_CTRL2                , 0x0000},
207         {RT5677_EQ_CTRL3                , 0x0000},
208         {RT5677_SOFT_VOL_ZERO_CROSS1    , 0x0009},
209         {RT5677_JD_CTRL1                , 0x0000},
210         {RT5677_JD_CTRL2                , 0x0000},
211         {RT5677_JD_CTRL3                , 0x0000},
212         {RT5677_IRQ_CTRL1               , 0x0000},
213         {RT5677_IRQ_CTRL2               , 0x0000},
214         {RT5677_GPIO_ST                 , 0x0000},
215         {RT5677_GPIO_CTRL1              , 0x0000},
216         {RT5677_GPIO_CTRL2              , 0x0000},
217         {RT5677_GPIO_CTRL3              , 0x0000},
218         {RT5677_STO1_ADC_HI_FILTER1     , 0xb320},
219         {RT5677_STO1_ADC_HI_FILTER2     , 0x0000},
220         {RT5677_MONO_ADC_HI_FILTER1     , 0xb300},
221         {RT5677_MONO_ADC_HI_FILTER2     , 0x0000},
222         {RT5677_STO2_ADC_HI_FILTER1     , 0xb300},
223         {RT5677_STO2_ADC_HI_FILTER2     , 0x0000},
224         {RT5677_STO3_ADC_HI_FILTER1     , 0xb300},
225         {RT5677_STO3_ADC_HI_FILTER2     , 0x0000},
226         {RT5677_STO4_ADC_HI_FILTER1     , 0xb300},
227         {RT5677_STO4_ADC_HI_FILTER2     , 0x0000},
228         {RT5677_MB_DRC_CTRL1            , 0x0f20},
229         {RT5677_DRC1_CTRL1              , 0x001f},
230         {RT5677_DRC1_CTRL2              , 0x020c},
231         {RT5677_DRC1_CTRL3              , 0x1f00},
232         {RT5677_DRC1_CTRL4              , 0x0000},
233         {RT5677_DRC1_CTRL5              , 0x0000},
234         {RT5677_DRC1_CTRL6              , 0x0029},
235         {RT5677_DRC2_CTRL1              , 0x001f},
236         {RT5677_DRC2_CTRL2              , 0x020c},
237         {RT5677_DRC2_CTRL3              , 0x1f00},
238         {RT5677_DRC2_CTRL4              , 0x0000},
239         {RT5677_DRC2_CTRL5              , 0x0000},
240         {RT5677_DRC2_CTRL6              , 0x0029},
241         {RT5677_DRC1_HL_CTRL1           , 0x8000},
242         {RT5677_DRC1_HL_CTRL2           , 0x0200},
243         {RT5677_DRC2_HL_CTRL1           , 0x8000},
244         {RT5677_DRC2_HL_CTRL2           , 0x0200},
245         {RT5677_DSP_INB1_SRC_CTRL1      , 0x5800},
246         {RT5677_DSP_INB1_SRC_CTRL2      , 0x0000},
247         {RT5677_DSP_INB1_SRC_CTRL3      , 0x0000},
248         {RT5677_DSP_INB1_SRC_CTRL4      , 0x0800},
249         {RT5677_DSP_INB2_SRC_CTRL1      , 0x5800},
250         {RT5677_DSP_INB2_SRC_CTRL2      , 0x0000},
251         {RT5677_DSP_INB2_SRC_CTRL3      , 0x0000},
252         {RT5677_DSP_INB2_SRC_CTRL4      , 0x0800},
253         {RT5677_DSP_INB3_SRC_CTRL1      , 0x5800},
254         {RT5677_DSP_INB3_SRC_CTRL2      , 0x0000},
255         {RT5677_DSP_INB3_SRC_CTRL3      , 0x0000},
256         {RT5677_DSP_INB3_SRC_CTRL4      , 0x0800},
257         {RT5677_DSP_OUTB1_SRC_CTRL1     , 0x5800},
258         {RT5677_DSP_OUTB1_SRC_CTRL2     , 0x0000},
259         {RT5677_DSP_OUTB1_SRC_CTRL3     , 0x0000},
260         {RT5677_DSP_OUTB1_SRC_CTRL4     , 0x0800},
261         {RT5677_DSP_OUTB2_SRC_CTRL1     , 0x5800},
262         {RT5677_DSP_OUTB2_SRC_CTRL2     , 0x0000},
263         {RT5677_DSP_OUTB2_SRC_CTRL3     , 0x0000},
264         {RT5677_DSP_OUTB2_SRC_CTRL4     , 0x0800},
265         {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266         {RT5677_DSP_OUTB_45_MIXER_CTRL  , 0xfefe},
267         {RT5677_DSP_OUTB_67_MIXER_CTRL  , 0xfefe},
268         {RT5677_DIG_MISC                , 0x0000},
269         {RT5677_GEN_CTRL1               , 0x0000},
270         {RT5677_GEN_CTRL2               , 0x0000},
271         {RT5677_VENDOR_ID               , 0x0000},
272         {RT5677_VENDOR_ID1              , 0x10ec},
273         {RT5677_VENDOR_ID2              , 0x6327},
274 };
275 
276 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
277 {
278         int i;
279 
280         for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281                 if (reg >= rt5677_ranges[i].range_min &&
282                         reg <= rt5677_ranges[i].range_max) {
283                         return true;
284                 }
285         }
286 
287         switch (reg) {
288         case RT5677_RESET:
289         case RT5677_SLIMBUS_PARAM:
290         case RT5677_PDM_DATA_CTRL1:
291         case RT5677_PDM_DATA_CTRL2:
292         case RT5677_PDM1_DATA_CTRL4:
293         case RT5677_PDM2_DATA_CTRL4:
294         case RT5677_I2C_MASTER_CTRL1:
295         case RT5677_I2C_MASTER_CTRL7:
296         case RT5677_I2C_MASTER_CTRL8:
297         case RT5677_HAP_GENE_CTRL2:
298         case RT5677_PWR_DSP_ST:
299         case RT5677_PRIV_DATA:
300         case RT5677_PLL1_CTRL2:
301         case RT5677_PLL2_CTRL2:
302         case RT5677_ASRC_22:
303         case RT5677_ASRC_23:
304         case RT5677_VAD_CTRL5:
305         case RT5677_ADC_EQ_CTRL1:
306         case RT5677_EQ_CTRL1:
307         case RT5677_IRQ_CTRL1:
308         case RT5677_IRQ_CTRL2:
309         case RT5677_GPIO_ST:
310         case RT5677_DSP_INB1_SRC_CTRL4:
311         case RT5677_DSP_INB2_SRC_CTRL4:
312         case RT5677_DSP_INB3_SRC_CTRL4:
313         case RT5677_DSP_OUTB1_SRC_CTRL4:
314         case RT5677_DSP_OUTB2_SRC_CTRL4:
315         case RT5677_VENDOR_ID:
316         case RT5677_VENDOR_ID1:
317         case RT5677_VENDOR_ID2:
318                 return true;
319         default:
320                 return false;
321         }
322 }
323 
324 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
325 {
326         int i;
327 
328         for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
329                 if (reg >= rt5677_ranges[i].range_min &&
330                         reg <= rt5677_ranges[i].range_max) {
331                         return true;
332                 }
333         }
334 
335         switch (reg) {
336         case RT5677_RESET:
337         case RT5677_LOUT1:
338         case RT5677_IN1:
339         case RT5677_MICBIAS:
340         case RT5677_SLIMBUS_PARAM:
341         case RT5677_SLIMBUS_RX:
342         case RT5677_SLIMBUS_CTRL:
343         case RT5677_SIDETONE_CTRL:
344         case RT5677_ANA_DAC1_2_3_SRC:
345         case RT5677_IF_DSP_DAC3_4_MIXER:
346         case RT5677_DAC4_DIG_VOL:
347         case RT5677_DAC3_DIG_VOL:
348         case RT5677_DAC1_DIG_VOL:
349         case RT5677_DAC2_DIG_VOL:
350         case RT5677_IF_DSP_DAC2_MIXER:
351         case RT5677_STO1_ADC_DIG_VOL:
352         case RT5677_MONO_ADC_DIG_VOL:
353         case RT5677_STO1_2_ADC_BST:
354         case RT5677_STO2_ADC_DIG_VOL:
355         case RT5677_ADC_BST_CTRL2:
356         case RT5677_STO3_4_ADC_BST:
357         case RT5677_STO3_ADC_DIG_VOL:
358         case RT5677_STO4_ADC_DIG_VOL:
359         case RT5677_STO4_ADC_MIXER:
360         case RT5677_STO3_ADC_MIXER:
361         case RT5677_STO2_ADC_MIXER:
362         case RT5677_STO1_ADC_MIXER:
363         case RT5677_MONO_ADC_MIXER:
364         case RT5677_ADC_IF_DSP_DAC1_MIXER:
365         case RT5677_STO1_DAC_MIXER:
366         case RT5677_MONO_DAC_MIXER:
367         case RT5677_DD1_MIXER:
368         case RT5677_DD2_MIXER:
369         case RT5677_IF3_DATA:
370         case RT5677_IF4_DATA:
371         case RT5677_PDM_OUT_CTRL:
372         case RT5677_PDM_DATA_CTRL1:
373         case RT5677_PDM_DATA_CTRL2:
374         case RT5677_PDM1_DATA_CTRL2:
375         case RT5677_PDM1_DATA_CTRL3:
376         case RT5677_PDM1_DATA_CTRL4:
377         case RT5677_PDM2_DATA_CTRL2:
378         case RT5677_PDM2_DATA_CTRL3:
379         case RT5677_PDM2_DATA_CTRL4:
380         case RT5677_TDM1_CTRL1:
381         case RT5677_TDM1_CTRL2:
382         case RT5677_TDM1_CTRL3:
383         case RT5677_TDM1_CTRL4:
384         case RT5677_TDM1_CTRL5:
385         case RT5677_TDM2_CTRL1:
386         case RT5677_TDM2_CTRL2:
387         case RT5677_TDM2_CTRL3:
388         case RT5677_TDM2_CTRL4:
389         case RT5677_TDM2_CTRL5:
390         case RT5677_I2C_MASTER_CTRL1:
391         case RT5677_I2C_MASTER_CTRL2:
392         case RT5677_I2C_MASTER_CTRL3:
393         case RT5677_I2C_MASTER_CTRL4:
394         case RT5677_I2C_MASTER_CTRL5:
395         case RT5677_I2C_MASTER_CTRL6:
396         case RT5677_I2C_MASTER_CTRL7:
397         case RT5677_I2C_MASTER_CTRL8:
398         case RT5677_DMIC_CTRL1:
399         case RT5677_DMIC_CTRL2:
400         case RT5677_HAP_GENE_CTRL1:
401         case RT5677_HAP_GENE_CTRL2:
402         case RT5677_HAP_GENE_CTRL3:
403         case RT5677_HAP_GENE_CTRL4:
404         case RT5677_HAP_GENE_CTRL5:
405         case RT5677_HAP_GENE_CTRL6:
406         case RT5677_HAP_GENE_CTRL7:
407         case RT5677_HAP_GENE_CTRL8:
408         case RT5677_HAP_GENE_CTRL9:
409         case RT5677_HAP_GENE_CTRL10:
410         case RT5677_PWR_DIG1:
411         case RT5677_PWR_DIG2:
412         case RT5677_PWR_ANLG1:
413         case RT5677_PWR_ANLG2:
414         case RT5677_PWR_DSP1:
415         case RT5677_PWR_DSP_ST:
416         case RT5677_PWR_DSP2:
417         case RT5677_ADC_DAC_HPF_CTRL1:
418         case RT5677_PRIV_INDEX:
419         case RT5677_PRIV_DATA:
420         case RT5677_I2S4_SDP:
421         case RT5677_I2S1_SDP:
422         case RT5677_I2S2_SDP:
423         case RT5677_I2S3_SDP:
424         case RT5677_CLK_TREE_CTRL1:
425         case RT5677_CLK_TREE_CTRL2:
426         case RT5677_CLK_TREE_CTRL3:
427         case RT5677_PLL1_CTRL1:
428         case RT5677_PLL1_CTRL2:
429         case RT5677_PLL2_CTRL1:
430         case RT5677_PLL2_CTRL2:
431         case RT5677_GLB_CLK1:
432         case RT5677_GLB_CLK2:
433         case RT5677_ASRC_1:
434         case RT5677_ASRC_2:
435         case RT5677_ASRC_3:
436         case RT5677_ASRC_4:
437         case RT5677_ASRC_5:
438         case RT5677_ASRC_6:
439         case RT5677_ASRC_7:
440         case RT5677_ASRC_8:
441         case RT5677_ASRC_9:
442         case RT5677_ASRC_10:
443         case RT5677_ASRC_11:
444         case RT5677_ASRC_12:
445         case RT5677_ASRC_13:
446         case RT5677_ASRC_14:
447         case RT5677_ASRC_15:
448         case RT5677_ASRC_16:
449         case RT5677_ASRC_17:
450         case RT5677_ASRC_18:
451         case RT5677_ASRC_19:
452         case RT5677_ASRC_20:
453         case RT5677_ASRC_21:
454         case RT5677_ASRC_22:
455         case RT5677_ASRC_23:
456         case RT5677_VAD_CTRL1:
457         case RT5677_VAD_CTRL2:
458         case RT5677_VAD_CTRL3:
459         case RT5677_VAD_CTRL4:
460         case RT5677_VAD_CTRL5:
461         case RT5677_DSP_INB_CTRL1:
462         case RT5677_DSP_INB_CTRL2:
463         case RT5677_DSP_IN_OUTB_CTRL:
464         case RT5677_DSP_OUTB0_1_DIG_VOL:
465         case RT5677_DSP_OUTB2_3_DIG_VOL:
466         case RT5677_DSP_OUTB4_5_DIG_VOL:
467         case RT5677_DSP_OUTB6_7_DIG_VOL:
468         case RT5677_ADC_EQ_CTRL1:
469         case RT5677_ADC_EQ_CTRL2:
470         case RT5677_EQ_CTRL1:
471         case RT5677_EQ_CTRL2:
472         case RT5677_EQ_CTRL3:
473         case RT5677_SOFT_VOL_ZERO_CROSS1:
474         case RT5677_JD_CTRL1:
475         case RT5677_JD_CTRL2:
476         case RT5677_JD_CTRL3:
477         case RT5677_IRQ_CTRL1:
478         case RT5677_IRQ_CTRL2:
479         case RT5677_GPIO_ST:
480         case RT5677_GPIO_CTRL1:
481         case RT5677_GPIO_CTRL2:
482         case RT5677_GPIO_CTRL3:
483         case RT5677_STO1_ADC_HI_FILTER1:
484         case RT5677_STO1_ADC_HI_FILTER2:
485         case RT5677_MONO_ADC_HI_FILTER1:
486         case RT5677_MONO_ADC_HI_FILTER2:
487         case RT5677_STO2_ADC_HI_FILTER1:
488         case RT5677_STO2_ADC_HI_FILTER2:
489         case RT5677_STO3_ADC_HI_FILTER1:
490         case RT5677_STO3_ADC_HI_FILTER2:
491         case RT5677_STO4_ADC_HI_FILTER1:
492         case RT5677_STO4_ADC_HI_FILTER2:
493         case RT5677_MB_DRC_CTRL1:
494         case RT5677_DRC1_CTRL1:
495         case RT5677_DRC1_CTRL2:
496         case RT5677_DRC1_CTRL3:
497         case RT5677_DRC1_CTRL4:
498         case RT5677_DRC1_CTRL5:
499         case RT5677_DRC1_CTRL6:
500         case RT5677_DRC2_CTRL1:
501         case RT5677_DRC2_CTRL2:
502         case RT5677_DRC2_CTRL3:
503         case RT5677_DRC2_CTRL4:
504         case RT5677_DRC2_CTRL5:
505         case RT5677_DRC2_CTRL6:
506         case RT5677_DRC1_HL_CTRL1:
507         case RT5677_DRC1_HL_CTRL2:
508         case RT5677_DRC2_HL_CTRL1:
509         case RT5677_DRC2_HL_CTRL2:
510         case RT5677_DSP_INB1_SRC_CTRL1:
511         case RT5677_DSP_INB1_SRC_CTRL2:
512         case RT5677_DSP_INB1_SRC_CTRL3:
513         case RT5677_DSP_INB1_SRC_CTRL4:
514         case RT5677_DSP_INB2_SRC_CTRL1:
515         case RT5677_DSP_INB2_SRC_CTRL2:
516         case RT5677_DSP_INB2_SRC_CTRL3:
517         case RT5677_DSP_INB2_SRC_CTRL4:
518         case RT5677_DSP_INB3_SRC_CTRL1:
519         case RT5677_DSP_INB3_SRC_CTRL2:
520         case RT5677_DSP_INB3_SRC_CTRL3:
521         case RT5677_DSP_INB3_SRC_CTRL4:
522         case RT5677_DSP_OUTB1_SRC_CTRL1:
523         case RT5677_DSP_OUTB1_SRC_CTRL2:
524         case RT5677_DSP_OUTB1_SRC_CTRL3:
525         case RT5677_DSP_OUTB1_SRC_CTRL4:
526         case RT5677_DSP_OUTB2_SRC_CTRL1:
527         case RT5677_DSP_OUTB2_SRC_CTRL2:
528         case RT5677_DSP_OUTB2_SRC_CTRL3:
529         case RT5677_DSP_OUTB2_SRC_CTRL4:
530         case RT5677_DSP_OUTB_0123_MIXER_CTRL:
531         case RT5677_DSP_OUTB_45_MIXER_CTRL:
532         case RT5677_DSP_OUTB_67_MIXER_CTRL:
533         case RT5677_DIG_MISC:
534         case RT5677_GEN_CTRL1:
535         case RT5677_GEN_CTRL2:
536         case RT5677_VENDOR_ID:
537         case RT5677_VENDOR_ID1:
538         case RT5677_VENDOR_ID2:
539                 return true;
540         default:
541                 return false;
542         }
543 }
544 
545 /**
546  * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
547  * @rt5677: Private Data.
548  * @addr: Address index.
549  * @value: Address data.
550  *
551  *
552  * Returns 0 for success or negative error code.
553  */
554 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
555                 unsigned int addr, unsigned int value, unsigned int opcode)
556 {
557         struct snd_soc_codec *codec = rt5677->codec;
558         int ret;
559 
560         mutex_lock(&rt5677->dsp_cmd_lock);
561 
562         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563                 addr >> 16);
564         if (ret < 0) {
565                 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
566                 goto err;
567         }
568 
569         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570                 addr & 0xffff);
571         if (ret < 0) {
572                 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
573                 goto err;
574         }
575 
576         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577                 value >> 16);
578         if (ret < 0) {
579                 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
580                 goto err;
581         }
582 
583         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584                 value & 0xffff);
585         if (ret < 0) {
586                 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
587                 goto err;
588         }
589 
590         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591                 opcode);
592         if (ret < 0) {
593                 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
594                 goto err;
595         }
596 
597 err:
598         mutex_unlock(&rt5677->dsp_cmd_lock);
599 
600         return ret;
601 }
602 
603 /**
604  * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
605  * rt5677: Private Data.
606  * @addr: Address index.
607  * @value: Address data.
608  *
609  *
610  * Returns 0 for success or negative error code.
611  */
612 static int rt5677_dsp_mode_i2c_read_addr(
613         struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
614 {
615         struct snd_soc_codec *codec = rt5677->codec;
616         int ret;
617         unsigned int msb, lsb;
618 
619         mutex_lock(&rt5677->dsp_cmd_lock);
620 
621         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622                 addr >> 16);
623         if (ret < 0) {
624                 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
625                 goto err;
626         }
627 
628         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629                 addr & 0xffff);
630         if (ret < 0) {
631                 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
632                 goto err;
633         }
634 
635         ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636                 0x0002);
637         if (ret < 0) {
638                 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
639                 goto err;
640         }
641 
642         regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
643         regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
644         *value = (msb << 16) | lsb;
645 
646 err:
647         mutex_unlock(&rt5677->dsp_cmd_lock);
648 
649         return ret;
650 }
651 
652 /**
653  * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
654  * rt5677: Private Data.
655  * @reg: Register index.
656  * @value: Register data.
657  *
658  *
659  * Returns 0 for success or negative error code.
660  */
661 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
662                 unsigned int reg, unsigned int value)
663 {
664         return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
665                 value, 0x0001);
666 }
667 
668 /**
669  * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
670  * @codec: SoC audio codec device.
671  * @reg: Register index.
672  * @value: Register data.
673  *
674  *
675  * Returns 0 for success or negative error code.
676  */
677 static int rt5677_dsp_mode_i2c_read(
678         struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
679 {
680         int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
681                 value);
682 
683         *value &= 0xffff;
684 
685         return ret;
686 }
687 
688 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
689 {
690         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
691 
692         if (on) {
693                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
694                 rt5677->is_dsp_mode = true;
695         } else {
696                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
697                 rt5677->is_dsp_mode = false;
698         }
699 }
700 
701 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
702 {
703         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
704         static bool activity;
705         int ret;
706 
707         if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
708                 return -ENXIO;
709 
710         if (on && !activity) {
711                 activity = true;
712 
713                 regcache_cache_only(rt5677->regmap, false);
714                 regcache_cache_bypass(rt5677->regmap, true);
715 
716                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
717                 regmap_update_bits(rt5677->regmap,
718                         RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
719                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
720                         RT5677_LDO1_SEL_MASK, 0x0);
721                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
722                         RT5677_PWR_LDO1, RT5677_PWR_LDO1);
723                 switch (rt5677->type) {
724                 case RT5677:
725                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
726                                 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
727                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
728                                 RT5677_PLL2_PR_SRC_MASK |
729                                 RT5677_DSP_CLK_SRC_MASK,
730                                 RT5677_PLL2_PR_SRC_MCLK2 |
731                                 RT5677_DSP_CLK_SRC_BYPASS);
732                         break;
733                 case RT5676:
734                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
735                                 RT5677_DSP_CLK_SRC_MASK,
736                                 RT5677_DSP_CLK_SRC_BYPASS);
737                         break;
738                 default:
739                         break;
740                 }
741                 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
742                 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
743                 rt5677_set_dsp_mode(codec, true);
744 
745                 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
746                         codec->dev);
747                 if (ret == 0) {
748                         rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
749                         release_firmware(rt5677->fw1);
750                 }
751 
752                 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
753                         codec->dev);
754                 if (ret == 0) {
755                         rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
756                         release_firmware(rt5677->fw2);
757                 }
758 
759                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
760 
761                 regcache_cache_bypass(rt5677->regmap, false);
762                 regcache_cache_only(rt5677->regmap, true);
763         } else if (!on && activity) {
764                 activity = false;
765 
766                 regcache_cache_only(rt5677->regmap, false);
767                 regcache_cache_bypass(rt5677->regmap, true);
768 
769                 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
770                 rt5677_set_dsp_mode(codec, false);
771                 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
772 
773                 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
774 
775                 regcache_cache_bypass(rt5677->regmap, false);
776                 regcache_mark_dirty(rt5677->regmap);
777                 regcache_sync(rt5677->regmap);
778         }
779 
780         return 0;
781 }
782 
783 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
784 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
786 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
787 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
788 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
789 
790 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
791 static const DECLARE_TLV_DB_RANGE(bst_tlv,
792         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
793         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
794         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
795         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
796         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
797         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
798         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
799 );
800 
801 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
802                 struct snd_ctl_elem_value *ucontrol)
803 {
804         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
805         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
806 
807         ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
808 
809         return 0;
810 }
811 
812 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
813                 struct snd_ctl_elem_value *ucontrol)
814 {
815         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
816         struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
817         struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
818 
819         rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
820 
821         if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
822                 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
823 
824         return 0;
825 }
826 
827 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
828         /* OUTPUT Control */
829         SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
830                 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
831         SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
832                 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
833         SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
834                 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
835 
836         /* DAC Digital Volume */
837         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
838                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
839         SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
840                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
841         SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
842                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
843         SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
844                 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
845 
846         /* IN1/IN2 Control */
847         SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
848         SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
849 
850         /* ADC Digital Volume Control */
851         SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
852                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853         SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
854                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855         SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
856                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857         SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
858                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859         SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
860                 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
861 
862         SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
863                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
864                 adc_vol_tlv),
865         SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
866                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
867                 adc_vol_tlv),
868         SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
869                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
870                 adc_vol_tlv),
871         SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
872                 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
873                 adc_vol_tlv),
874         SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
875                 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
876                 adc_vol_tlv),
877 
878         /* Sidetone Control */
879         SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
880                 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
881 
882         /* ADC Boost Volume Control */
883         SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
884                 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
885                 adc_bst_tlv),
886         SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
887                 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
888                 adc_bst_tlv),
889         SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
890                 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
891                 adc_bst_tlv),
892         SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
893                 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
894                 adc_bst_tlv),
895         SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
896                 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
897                 adc_bst_tlv),
898 
899         SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
900                 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
901 };
902 
903 /**
904  * set_dmic_clk - Set parameter of dmic.
905  *
906  * @w: DAPM widget.
907  * @kcontrol: The kcontrol of this widget.
908  * @event: Event id.
909  *
910  * Choose dmic clock between 1MHz and 3MHz.
911  * It is better for clock to approximate 3MHz.
912  */
913 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
914         struct snd_kcontrol *kcontrol, int event)
915 {
916         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
917         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
918         int idx, rate;
919 
920         rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
921                 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
922         idx = rl6231_calc_dmic_clk(rate);
923         if (idx < 0)
924                 dev_err(codec->dev, "Failed to set DMIC clock\n");
925         else
926                 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
927                         RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
928         return idx;
929 }
930 
931 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
932                          struct snd_soc_dapm_widget *sink)
933 {
934         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
935         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
936         unsigned int val;
937 
938         regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
939         val &= RT5677_SCLK_SRC_MASK;
940         if (val == RT5677_SCLK_SRC_PLL1)
941                 return 1;
942         else
943                 return 0;
944 }
945 
946 static int is_using_asrc(struct snd_soc_dapm_widget *source,
947                          struct snd_soc_dapm_widget *sink)
948 {
949         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
950         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
951         unsigned int reg, shift, val;
952 
953         if (source->reg == RT5677_ASRC_1) {
954                 switch (source->shift) {
955                 case 12:
956                         reg = RT5677_ASRC_4;
957                         shift = 0;
958                         break;
959                 case 13:
960                         reg = RT5677_ASRC_4;
961                         shift = 4;
962                         break;
963                 case 14:
964                         reg = RT5677_ASRC_4;
965                         shift = 8;
966                         break;
967                 case 15:
968                         reg = RT5677_ASRC_4;
969                         shift = 12;
970                         break;
971                 default:
972                         return 0;
973                 }
974         } else {
975                 switch (source->shift) {
976                 case 0:
977                         reg = RT5677_ASRC_6;
978                         shift = 8;
979                         break;
980                 case 1:
981                         reg = RT5677_ASRC_6;
982                         shift = 12;
983                         break;
984                 case 2:
985                         reg = RT5677_ASRC_5;
986                         shift = 0;
987                         break;
988                 case 3:
989                         reg = RT5677_ASRC_5;
990                         shift = 4;
991                         break;
992                 case 4:
993                         reg = RT5677_ASRC_5;
994                         shift = 8;
995                         break;
996                 case 5:
997                         reg = RT5677_ASRC_5;
998                         shift = 12;
999                         break;
1000                 case 12:
1001                         reg = RT5677_ASRC_3;
1002                         shift = 0;
1003                         break;
1004                 case 13:
1005                         reg = RT5677_ASRC_3;
1006                         shift = 4;
1007                         break;
1008                 case 14:
1009                         reg = RT5677_ASRC_3;
1010                         shift = 12;
1011                         break;
1012                 default:
1013                         return 0;
1014                 }
1015         }
1016 
1017         regmap_read(rt5677->regmap, reg, &val);
1018         val = (val >> shift) & 0xf;
1019 
1020         switch (val) {
1021         case 1 ... 6:
1022                 return 1;
1023         default:
1024                 return 0;
1025         }
1026 
1027 }
1028 
1029 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1030                          struct snd_soc_dapm_widget *sink)
1031 {
1032         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1033         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1034 
1035         if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1036                 return 1;
1037 
1038         return 0;
1039 }
1040 
1041 /**
1042  * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1043  * @codec: SoC audio codec device.
1044  * @filter_mask: mask of filters.
1045  * @clk_src: clock source
1046  *
1047  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1048  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1049  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1050  * ASRC function will track i2s clock and generate a corresponding system clock
1051  * for codec. This function provides an API to select the clock source for a
1052  * set of filters specified by the mask. And the codec driver will turn on ASRC
1053  * for these filters if ASRC is selected as their clock source.
1054  */
1055 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1056                 unsigned int filter_mask, unsigned int clk_src)
1057 {
1058         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1059         unsigned int asrc3_mask = 0, asrc3_value = 0;
1060         unsigned int asrc4_mask = 0, asrc4_value = 0;
1061         unsigned int asrc5_mask = 0, asrc5_value = 0;
1062         unsigned int asrc6_mask = 0, asrc6_value = 0;
1063         unsigned int asrc7_mask = 0, asrc7_value = 0;
1064         unsigned int asrc8_mask = 0, asrc8_value = 0;
1065 
1066         switch (clk_src) {
1067         case RT5677_CLK_SEL_SYS:
1068         case RT5677_CLK_SEL_I2S1_ASRC:
1069         case RT5677_CLK_SEL_I2S2_ASRC:
1070         case RT5677_CLK_SEL_I2S3_ASRC:
1071         case RT5677_CLK_SEL_I2S4_ASRC:
1072         case RT5677_CLK_SEL_I2S5_ASRC:
1073         case RT5677_CLK_SEL_I2S6_ASRC:
1074         case RT5677_CLK_SEL_SYS2:
1075         case RT5677_CLK_SEL_SYS3:
1076         case RT5677_CLK_SEL_SYS4:
1077         case RT5677_CLK_SEL_SYS5:
1078         case RT5677_CLK_SEL_SYS6:
1079         case RT5677_CLK_SEL_SYS7:
1080                 break;
1081 
1082         default:
1083                 return -EINVAL;
1084         }
1085 
1086         /* ASRC 3 */
1087         if (filter_mask & RT5677_DA_STEREO_FILTER) {
1088                 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1089                 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1090                         | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1091         }
1092 
1093         if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1094                 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1095                 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1096                         | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1097         }
1098 
1099         if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1100                 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1101                 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1102                         | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1103         }
1104 
1105         if (asrc3_mask)
1106                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1107                         asrc3_value);
1108 
1109         /* ASRC 4 */
1110         if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1111                 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1112                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1113                         | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1114         }
1115 
1116         if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1117                 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1118                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1119                         | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1120         }
1121 
1122         if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1123                 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1124                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1125                         | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1126         }
1127 
1128         if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1129                 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1130                 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1131                         | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1132         }
1133 
1134         if (asrc4_mask)
1135                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1136                         asrc4_value);
1137 
1138         /* ASRC 5 */
1139         if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1140                 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1141                 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1142                         | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1143         }
1144 
1145         if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1146                 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1147                 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1148                         | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1149         }
1150 
1151         if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1152                 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1153                 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1154                         | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1155         }
1156 
1157         if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1158                 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1159                 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1160                         | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1161         }
1162 
1163         if (asrc5_mask)
1164                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1165                         asrc5_value);
1166 
1167         /* ASRC 6 */
1168         if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1169                 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1170                 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1171                         | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1172         }
1173 
1174         if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1175                 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1176                 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1177                         | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1178         }
1179 
1180         if (asrc6_mask)
1181                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1182                         asrc6_value);
1183 
1184         /* ASRC 7 */
1185         if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1186                 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1187                 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1188                         | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1189         }
1190 
1191         if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1192                 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1193                 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1194                         | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1195         }
1196 
1197         if (asrc7_mask)
1198                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1199                         asrc7_value);
1200 
1201         /* ASRC 8 */
1202         if (filter_mask & RT5677_I2S1_SOURCE) {
1203                 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1204                 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1205                         | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1206         }
1207 
1208         if (filter_mask & RT5677_I2S2_SOURCE) {
1209                 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1210                 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1211                         | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1212         }
1213 
1214         if (filter_mask & RT5677_I2S3_SOURCE) {
1215                 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1216                 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1217                         | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1218         }
1219 
1220         if (filter_mask & RT5677_I2S4_SOURCE) {
1221                 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1222                 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1223                         | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1224         }
1225 
1226         if (asrc8_mask)
1227                 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1228                         asrc8_value);
1229 
1230         return 0;
1231 }
1232 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1233 
1234 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1235                          struct snd_soc_dapm_widget *sink)
1236 {
1237         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1238         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1239         unsigned int asrc_setting;
1240 
1241         switch (source->shift) {
1242         case 11:
1243                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1244                 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1245                                 RT5677_AD_STO1_CLK_SEL_SFT;
1246                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1247                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1248                         return 1;
1249                 break;
1250 
1251         case 10:
1252                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1253                 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1254                                 RT5677_AD_STO2_CLK_SEL_SFT;
1255                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1256                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1257                         return 1;
1258                 break;
1259 
1260         case 9:
1261                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1262                 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1263                                 RT5677_AD_STO3_CLK_SEL_SFT;
1264                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1265                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1266                         return 1;
1267                 break;
1268 
1269         case 8:
1270                 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1271                 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1272                         RT5677_AD_STO4_CLK_SEL_SFT;
1273                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1274                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1275                         return 1;
1276                 break;
1277 
1278         case 7:
1279                 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1280                 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1281                         RT5677_AD_MONOL_CLK_SEL_SFT;
1282                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1283                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1284                         return 1;
1285                 break;
1286 
1287         case 6:
1288                 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1289                 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1290                         RT5677_AD_MONOR_CLK_SEL_SFT;
1291                 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1292                         asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1293                         return 1;
1294                 break;
1295 
1296         default:
1297                 break;
1298         }
1299 
1300         return 0;
1301 }
1302 
1303 /* Digital Mixer */
1304 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1305         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1306                         RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1307         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1308                         RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1309 };
1310 
1311 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1312         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1313                         RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1314         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1315                         RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1316 };
1317 
1318 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1319         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1320                         RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1321         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1322                         RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1323 };
1324 
1325 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1326         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1327                         RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1328         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1329                         RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1330 };
1331 
1332 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1333         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1334                         RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1335         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1336                         RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1337 };
1338 
1339 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1340         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1341                         RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1342         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1343                         RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1344 };
1345 
1346 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1347         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1348                         RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1349         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1350                         RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1351 };
1352 
1353 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1354         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1355                         RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1356         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1357                         RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1358 };
1359 
1360 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1361         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1362                         RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1363         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1364                         RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1365 };
1366 
1367 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1368         SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1369                         RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1370         SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1371                         RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1372 };
1373 
1374 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1375         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1376                         RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1377         SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1378                         RT5677_M_DAC1_L_SFT, 1, 1),
1379 };
1380 
1381 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1382         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1383                         RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1384         SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1385                         RT5677_M_DAC1_R_SFT, 1, 1),
1386 };
1387 
1388 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1389         SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1390                         RT5677_M_ST_DAC1_L_SFT, 1, 1),
1391         SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1392                         RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1393         SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1394                         RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1395         SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1396                         RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1397 };
1398 
1399 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1400         SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1401                         RT5677_M_ST_DAC1_R_SFT, 1, 1),
1402         SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1403                         RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1404         SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1405                         RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1406         SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1407                         RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1408 };
1409 
1410 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1411         SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1412                         RT5677_M_ST_DAC2_L_SFT, 1, 1),
1413         SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1414                         RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1415         SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1416                         RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1417         SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1418                         RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1419 };
1420 
1421 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1422         SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1423                         RT5677_M_ST_DAC2_R_SFT, 1, 1),
1424         SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1425                         RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1426         SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1427                         RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1428         SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1429                         RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1430 };
1431 
1432 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1433         SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1434                         RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1435         SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1436                         RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1437         SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1438                         RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1439         SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1440                         RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1441 };
1442 
1443 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1444         SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1445                         RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1446         SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1447                         RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1448         SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1449                         RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1450         SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1451                         RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1452 };
1453 
1454 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1455         SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1456                         RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1457         SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1458                         RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1459         SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1460                         RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1461         SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1462                         RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1463 };
1464 
1465 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1466         SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1467                         RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1468         SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1469                         RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1470         SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1471                         RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1472         SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1473                         RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1474 };
1475 
1476 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1477         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1478                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1479         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1481         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1483         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1485         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1487         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1489         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1491 };
1492 
1493 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1494         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1495                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1496         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1497                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1498         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1499                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1500         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1501                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1502         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1503                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1504         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1505                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1506         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1507                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1508 };
1509 
1510 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1511         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1512                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1513         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1515         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1517         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1519         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1521         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1523         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1525 };
1526 
1527 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1528         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1529                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1530         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1531                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1532         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1533                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1534         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1535                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1536         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1537                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1538         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1539                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1540         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1541                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1542 };
1543 
1544 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1545         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1546                         RT5677_DSP_IB_01_H_SFT, 1, 1),
1547         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548                         RT5677_DSP_IB_23_H_SFT, 1, 1),
1549         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550                         RT5677_DSP_IB_45_H_SFT, 1, 1),
1551         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552                         RT5677_DSP_IB_6_H_SFT, 1, 1),
1553         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554                         RT5677_DSP_IB_7_H_SFT, 1, 1),
1555         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556                         RT5677_DSP_IB_8_H_SFT, 1, 1),
1557         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558                         RT5677_DSP_IB_9_H_SFT, 1, 1),
1559 };
1560 
1561 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1562         SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1563                         RT5677_DSP_IB_01_L_SFT, 1, 1),
1564         SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1565                         RT5677_DSP_IB_23_L_SFT, 1, 1),
1566         SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1567                         RT5677_DSP_IB_45_L_SFT, 1, 1),
1568         SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1569                         RT5677_DSP_IB_6_L_SFT, 1, 1),
1570         SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1571                         RT5677_DSP_IB_7_L_SFT, 1, 1),
1572         SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1573                         RT5677_DSP_IB_8_L_SFT, 1, 1),
1574         SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1575                         RT5677_DSP_IB_9_L_SFT, 1, 1),
1576 };
1577 
1578 
1579 /* Mux */
1580 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1581 static const char * const rt5677_dac1_src[] = {
1582         "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1583         "OB 01"
1584 };
1585 
1586 static SOC_ENUM_SINGLE_DECL(
1587         rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1588         RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1589 
1590 static const struct snd_kcontrol_new rt5677_dac1_mux =
1591         SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1592 
1593 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1594 static const char * const rt5677_adda1_src[] = {
1595         "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1596 };
1597 
1598 static SOC_ENUM_SINGLE_DECL(
1599         rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1600         RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1601 
1602 static const struct snd_kcontrol_new rt5677_adda1_mux =
1603         SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1604 
1605 
1606 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1607 static const char * const rt5677_dac2l_src[] = {
1608         "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1609         "OB 2",
1610 };
1611 
1612 static SOC_ENUM_SINGLE_DECL(
1613         rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1614         RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1615 
1616 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1617         SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1618 
1619 static const char * const rt5677_dac2r_src[] = {
1620         "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1621         "OB 3", "Haptic Generator", "VAD ADC"
1622 };
1623 
1624 static SOC_ENUM_SINGLE_DECL(
1625         rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1626         RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1627 
1628 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1629         SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1630 
1631 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1632 static const char * const rt5677_dac3l_src[] = {
1633         "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1634         "SLB DAC 4", "OB 4"
1635 };
1636 
1637 static SOC_ENUM_SINGLE_DECL(
1638         rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1639         RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1640 
1641 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1642         SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1643 
1644 static const char * const rt5677_dac3r_src[] = {
1645         "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1646         "SLB DAC 5", "OB 5"
1647 };
1648 
1649 static SOC_ENUM_SINGLE_DECL(
1650         rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1651         RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1652 
1653 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1654         SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1655 
1656 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1657 static const char * const rt5677_dac4l_src[] = {
1658         "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1659         "SLB DAC 6", "OB 6"
1660 };
1661 
1662 static SOC_ENUM_SINGLE_DECL(
1663         rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1664         RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1665 
1666 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1667         SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1668 
1669 static const char * const rt5677_dac4r_src[] = {
1670         "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1671         "SLB DAC 7", "OB 7"
1672 };
1673 
1674 static SOC_ENUM_SINGLE_DECL(
1675         rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1676         RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1677 
1678 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1679         SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1680 
1681 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1682 static const char * const rt5677_iob_bypass_src[] = {
1683         "Bypass", "Pass SRC"
1684 };
1685 
1686 static SOC_ENUM_SINGLE_DECL(
1687         rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1688         RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1689 
1690 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1691         SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1692 
1693 static SOC_ENUM_SINGLE_DECL(
1694         rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1695         RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1696 
1697 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1698         SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1699 
1700 static SOC_ENUM_SINGLE_DECL(
1701         rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1702         RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1703 
1704 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1705         SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1706 
1707 static SOC_ENUM_SINGLE_DECL(
1708         rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1709         RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1710 
1711 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1712         SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1713 
1714 static SOC_ENUM_SINGLE_DECL(
1715         rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1716         RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1717 
1718 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1719         SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1720 
1721 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1722 static const char * const rt5677_stereo_adc2_src[] = {
1723         "DD MIX1", "DMIC", "Stereo DAC MIX"
1724 };
1725 
1726 static SOC_ENUM_SINGLE_DECL(
1727         rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1728         RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1729 
1730 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1731         SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1732 
1733 static SOC_ENUM_SINGLE_DECL(
1734         rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1735         RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1736 
1737 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1738         SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1739 
1740 static SOC_ENUM_SINGLE_DECL(
1741         rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1742         RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1743 
1744 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1745         SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1746 
1747 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1748 static const char * const rt5677_dmic_src[] = {
1749         "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1750 };
1751 
1752 static SOC_ENUM_SINGLE_DECL(
1753         rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1754         RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1755 
1756 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1757         SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1758 
1759 static SOC_ENUM_SINGLE_DECL(
1760         rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1761         RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1762 
1763 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1764         SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1765 
1766 static SOC_ENUM_SINGLE_DECL(
1767         rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1768         RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1769 
1770 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1771         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1772 
1773 static SOC_ENUM_SINGLE_DECL(
1774         rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1775         RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1776 
1777 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1778         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1779 
1780 static SOC_ENUM_SINGLE_DECL(
1781         rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1782         RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1783 
1784 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1785         SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1786 
1787 static SOC_ENUM_SINGLE_DECL(
1788         rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1789         RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1790 
1791 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1792         SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1793 
1794 /* Stereo2 ADC Source */ /* MX-26 [0] */
1795 static const char * const rt5677_stereo2_adc_lr_src[] = {
1796         "L", "LR"
1797 };
1798 
1799 static SOC_ENUM_SINGLE_DECL(
1800         rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1801         RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1802 
1803 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1804         SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1805 
1806 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1807 static const char * const rt5677_stereo_adc1_src[] = {
1808         "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1809 };
1810 
1811 static SOC_ENUM_SINGLE_DECL(
1812         rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1813         RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1814 
1815 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1816         SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1817 
1818 static SOC_ENUM_SINGLE_DECL(
1819         rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1820         RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1821 
1822 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1823         SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1824 
1825 static SOC_ENUM_SINGLE_DECL(
1826         rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1827         RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1828 
1829 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1830         SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1831 
1832 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1833 static const char * const rt5677_mono_adc2_l_src[] = {
1834         "DD MIX1L", "DMIC", "MONO DAC MIXL"
1835 };
1836 
1837 static SOC_ENUM_SINGLE_DECL(
1838         rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1839         RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1840 
1841 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1842         SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1843 
1844 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1845 static const char * const rt5677_mono_adc1_l_src[] = {
1846         "DD MIX1L", "ADC1", "MONO DAC MIXL"
1847 };
1848 
1849 static SOC_ENUM_SINGLE_DECL(
1850         rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1851         RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1852 
1853 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1854         SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1855 
1856 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1857 static const char * const rt5677_mono_adc2_r_src[] = {
1858         "DD MIX1R", "DMIC", "MONO DAC MIXR"
1859 };
1860 
1861 static SOC_ENUM_SINGLE_DECL(
1862         rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1863         RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1864 
1865 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1866         SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1867 
1868 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1869 static const char * const rt5677_mono_adc1_r_src[] = {
1870         "DD MIX1R", "ADC2", "MONO DAC MIXR"
1871 };
1872 
1873 static SOC_ENUM_SINGLE_DECL(
1874         rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1875         RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1876 
1877 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1878         SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1879 
1880 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1881 static const char * const rt5677_stereo4_adc2_src[] = {
1882         "DD MIX1", "DMIC", "DD MIX2"
1883 };
1884 
1885 static SOC_ENUM_SINGLE_DECL(
1886         rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1887         RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1888 
1889 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1890         SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1891 
1892 
1893 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1894 static const char * const rt5677_stereo4_adc1_src[] = {
1895         "DD MIX1", "ADC1/2", "DD MIX2"
1896 };
1897 
1898 static SOC_ENUM_SINGLE_DECL(
1899         rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1900         RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1901 
1902 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1903         SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1904 
1905 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1906 static const char * const rt5677_inbound01_src[] = {
1907         "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1908         "VAD ADC/DAC1 FS"
1909 };
1910 
1911 static SOC_ENUM_SINGLE_DECL(
1912         rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1913         RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1914 
1915 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1916         SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1917 
1918 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1919 static const char * const rt5677_inbound23_src[] = {
1920         "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1921         "DAC1 FS", "IF4 DAC"
1922 };
1923 
1924 static SOC_ENUM_SINGLE_DECL(
1925         rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1926         RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1927 
1928 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1929         SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1930 
1931 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1932 static const char * const rt5677_inbound45_src[] = {
1933         "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1934         "IF3 DAC"
1935 };
1936 
1937 static SOC_ENUM_SINGLE_DECL(
1938         rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1939         RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1940 
1941 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1942         SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1943 
1944 /* InBound6 Source */ /* MX-A3 [2:0] */
1945 static const char * const rt5677_inbound6_src[] = {
1946         "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1947         "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1948 };
1949 
1950 static SOC_ENUM_SINGLE_DECL(
1951         rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1952         RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1953 
1954 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1955         SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1956 
1957 /* InBound7 Source */ /* MX-A4 [14:12] */
1958 static const char * const rt5677_inbound7_src[] = {
1959         "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1960         "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1961 };
1962 
1963 static SOC_ENUM_SINGLE_DECL(
1964         rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1965         RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1966 
1967 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1968         SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1969 
1970 /* InBound8 Source */ /* MX-A4 [10:8] */
1971 static const char * const rt5677_inbound8_src[] = {
1972         "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1973         "MONO ADC MIX L", "DACL1 FS"
1974 };
1975 
1976 static SOC_ENUM_SINGLE_DECL(
1977         rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1978         RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1979 
1980 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1981         SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1982 
1983 /* InBound9 Source */ /* MX-A4 [6:4] */
1984 static const char * const rt5677_inbound9_src[] = {
1985         "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1986         "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1987 };
1988 
1989 static SOC_ENUM_SINGLE_DECL(
1990         rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1991         RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1992 
1993 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1994         SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1995 
1996 /* VAD Source */ /* MX-9F [6:4] */
1997 static const char * const rt5677_vad_src[] = {
1998         "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1999         "STO3 ADC MIX L"
2000 };
2001 
2002 static SOC_ENUM_SINGLE_DECL(
2003         rt5677_vad_enum, RT5677_VAD_CTRL4,
2004         RT5677_VAD_SRC_SFT, rt5677_vad_src);
2005 
2006 static const struct snd_kcontrol_new rt5677_vad_src_mux =
2007         SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2008 
2009 /* Sidetone Source */ /* MX-13 [11:9] */
2010 static const char * const rt5677_sidetone_src[] = {
2011         "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2012 };
2013 
2014 static SOC_ENUM_SINGLE_DECL(
2015         rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2016         RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2017 
2018 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2019         SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2020 
2021 /* DAC1/2 Source */ /* MX-15 [1:0] */
2022 static const char * const rt5677_dac12_src[] = {
2023         "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2024 };
2025 
2026 static SOC_ENUM_SINGLE_DECL(
2027         rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2028         RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2029 
2030 static const struct snd_kcontrol_new rt5677_dac12_mux =
2031         SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2032 
2033 /* DAC3 Source */ /* MX-15 [5:4] */
2034 static const char * const rt5677_dac3_src[] = {
2035         "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2036 };
2037 
2038 static SOC_ENUM_SINGLE_DECL(
2039         rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2040         RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2041 
2042 static const struct snd_kcontrol_new rt5677_dac3_mux =
2043         SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2044 
2045 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2046 static const char * const rt5677_pdm_src[] = {
2047         "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2048 };
2049 
2050 static SOC_ENUM_SINGLE_DECL(
2051         rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2052         RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2053 
2054 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2055         SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2056 
2057 static SOC_ENUM_SINGLE_DECL(
2058         rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2059         RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2060 
2061 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2062         SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2063 
2064 static SOC_ENUM_SINGLE_DECL(
2065         rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2066         RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2067 
2068 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2069         SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2070 
2071 static SOC_ENUM_SINGLE_DECL(
2072         rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2073         RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2074 
2075 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2076         SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2077 
2078 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2079 static const char * const rt5677_if12_adc1_src[] = {
2080         "STO1 ADC MIX", "OB01", "VAD ADC"
2081 };
2082 
2083 static SOC_ENUM_SINGLE_DECL(
2084         rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2085         RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2086 
2087 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2088         SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2089 
2090 static SOC_ENUM_SINGLE_DECL(
2091         rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2092         RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2093 
2094 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2095         SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2096 
2097 static SOC_ENUM_SINGLE_DECL(
2098         rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2099         RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2100 
2101 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2102         SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2103 
2104 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2105 static const char * const rt5677_if12_adc2_src[] = {
2106         "STO2 ADC MIX", "OB23"
2107 };
2108 
2109 static SOC_ENUM_SINGLE_DECL(
2110         rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2111         RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2112 
2113 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2114         SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2115 
2116 static SOC_ENUM_SINGLE_DECL(
2117         rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2118         RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2119 
2120 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2121         SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2122 
2123 static SOC_ENUM_SINGLE_DECL(
2124         rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2125         RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2126 
2127 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2128         SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2129 
2130 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2131 static const char * const rt5677_if12_adc3_src[] = {
2132         "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2133 };
2134 
2135 static SOC_ENUM_SINGLE_DECL(
2136         rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2137         RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2138 
2139 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2140         SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2141 
2142 static SOC_ENUM_SINGLE_DECL(
2143         rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2144         RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2145 
2146 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2147         SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2148 
2149 static SOC_ENUM_SINGLE_DECL(
2150         rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2151         RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2152 
2153 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2154         SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2155 
2156 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2157 static const char * const rt5677_if12_adc4_src[] = {
2158         "STO4 ADC MIX", "OB67", "OB01"
2159 };
2160 
2161 static SOC_ENUM_SINGLE_DECL(
2162         rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2163         RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2164 
2165 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2166         SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2167 
2168 static SOC_ENUM_SINGLE_DECL(
2169         rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2170         RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2171 
2172 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2173         SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2174 
2175 static SOC_ENUM_SINGLE_DECL(
2176         rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2177         RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2178 
2179 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2180         SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2181 
2182 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2183 static const char * const rt5677_if34_adc_src[] = {
2184         "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2185         "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2186 };
2187 
2188 static SOC_ENUM_SINGLE_DECL(
2189         rt5677_if3_adc_enum, RT5677_IF3_DATA,
2190         RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2191 
2192 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2193         SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2194 
2195 static SOC_ENUM_SINGLE_DECL(
2196         rt5677_if4_adc_enum, RT5677_IF4_DATA,
2197         RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2198 
2199 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2200         SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2201 
2202 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2203 static const char * const rt5677_if12_adc_swap_src[] = {
2204         "L/R", "R/L", "L/L", "R/R"
2205 };
2206 
2207 static SOC_ENUM_SINGLE_DECL(
2208         rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2209         RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2210 
2211 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2212         SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2213 
2214 static SOC_ENUM_SINGLE_DECL(
2215         rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2216         RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2217 
2218 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2219         SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2220 
2221 static SOC_ENUM_SINGLE_DECL(
2222         rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2223         RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2224 
2225 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2226         SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2227 
2228 static SOC_ENUM_SINGLE_DECL(
2229         rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2230         RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2231 
2232 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2233         SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2234 
2235 static SOC_ENUM_SINGLE_DECL(
2236         rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2237         RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2238 
2239 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2240         SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2241 
2242 static SOC_ENUM_SINGLE_DECL(
2243         rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2244         RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2245 
2246 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2247         SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2248 
2249 static SOC_ENUM_SINGLE_DECL(
2250         rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2251         RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2252 
2253 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2254         SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2255 
2256 static SOC_ENUM_SINGLE_DECL(
2257         rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2258         RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2259 
2260 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2261         SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2262 
2263 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2264 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2265         "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2266         "3/1/2/4", "3/4/1/2"
2267 };
2268 
2269 static SOC_ENUM_SINGLE_DECL(
2270         rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2271         RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2272 
2273 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2274         SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2275 
2276 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2277 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2278         "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2279         "2/3/1/4", "3/4/1/2"
2280 };
2281 
2282 static SOC_ENUM_SINGLE_DECL(
2283         rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2284         RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2285 
2286 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2287         SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2288 
2289 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2290                                         MX-3F[14:12][10:8][6:4][2:0]
2291                                         MX-43[14:12][10:8][6:4][2:0]
2292                                         MX-44[14:12][10:8][6:4][2:0] */
2293 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2294         "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2295 };
2296 
2297 static SOC_ENUM_SINGLE_DECL(
2298         rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2299         RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2300 
2301 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2302         SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2303 
2304 static SOC_ENUM_SINGLE_DECL(
2305         rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2306         RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2307 
2308 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2309         SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2310 
2311 static SOC_ENUM_SINGLE_DECL(
2312         rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2313         RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2314 
2315 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2316         SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2317 
2318 static SOC_ENUM_SINGLE_DECL(
2319         rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2320         RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2321 
2322 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2323         SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2324 
2325 static SOC_ENUM_SINGLE_DECL(
2326         rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2327         RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2328 
2329 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2330         SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2331 
2332 static SOC_ENUM_SINGLE_DECL(
2333         rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2334         RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2335 
2336 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2337         SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2338 
2339 static SOC_ENUM_SINGLE_DECL(
2340         rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2341         RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2342 
2343 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2344         SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2345 
2346 static SOC_ENUM_SINGLE_DECL(
2347         rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2348         RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2349 
2350 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2351         SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2352 
2353 static SOC_ENUM_SINGLE_DECL(
2354         rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2355         RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2356 
2357 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2358         SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2359 
2360 static SOC_ENUM_SINGLE_DECL(
2361         rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2362         RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2363 
2364 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2365         SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2366 
2367 static SOC_ENUM_SINGLE_DECL(
2368         rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2369         RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2370 
2371 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2372         SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2373 
2374 static SOC_ENUM_SINGLE_DECL(
2375         rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2376         RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2377 
2378 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2379         SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2380 
2381 static SOC_ENUM_SINGLE_DECL(
2382         rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2383         RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2384 
2385 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2386         SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2387 
2388 static SOC_ENUM_SINGLE_DECL(
2389         rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2390         RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2391 
2392 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2393         SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2394 
2395 static SOC_ENUM_SINGLE_DECL(
2396         rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2397         RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2398 
2399 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2400         SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2401 
2402 static SOC_ENUM_SINGLE_DECL(
2403         rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2404         RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2405 
2406 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2407         SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2408 
2409 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2410         struct snd_kcontrol *kcontrol, int event)
2411 {
2412         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2413         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2414 
2415         switch (event) {
2416         case SND_SOC_DAPM_POST_PMU:
2417                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2418                         RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2419                 break;
2420 
2421         case SND_SOC_DAPM_PRE_PMD:
2422                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2423                         RT5677_PWR_BST1_P, 0);
2424                 break;
2425 
2426         default:
2427                 return 0;
2428         }
2429 
2430         return 0;
2431 }
2432 
2433 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2434         struct snd_kcontrol *kcontrol, int event)
2435 {
2436         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2437         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2438 
2439         switch (event) {
2440         case SND_SOC_DAPM_POST_PMU:
2441                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2442                         RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2443                 break;
2444 
2445         case SND_SOC_DAPM_PRE_PMD:
2446                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2447                         RT5677_PWR_BST2_P, 0);
2448                 break;
2449 
2450         default:
2451                 return 0;
2452         }
2453 
2454         return 0;
2455 }
2456 
2457 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2458         struct snd_kcontrol *kcontrol, int event)
2459 {
2460         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2461         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2462 
2463         switch (event) {
2464         case SND_SOC_DAPM_PRE_PMU:
2465                 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2466                 break;
2467 
2468         case SND_SOC_DAPM_POST_PMU:
2469                 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2470                 break;
2471 
2472         default:
2473                 return 0;
2474         }
2475 
2476         return 0;
2477 }
2478 
2479 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2480         struct snd_kcontrol *kcontrol, int event)
2481 {
2482         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2483         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2484 
2485         switch (event) {
2486         case SND_SOC_DAPM_PRE_PMU:
2487                 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2488                 break;
2489 
2490         case SND_SOC_DAPM_POST_PMU:
2491                 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2492                 break;
2493 
2494         default:
2495                 return 0;
2496         }
2497 
2498         return 0;
2499 }
2500 
2501 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2502         struct snd_kcontrol *kcontrol, int event)
2503 {
2504         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2505         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2506 
2507         switch (event) {
2508         case SND_SOC_DAPM_POST_PMU:
2509                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2510                         RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2511                         RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2512                         RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2513                 break;
2514 
2515         case SND_SOC_DAPM_PRE_PMD:
2516                 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2517                         RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2518                         RT5677_PWR_CLK_MB, 0);
2519                 break;
2520 
2521         default:
2522                 return 0;
2523         }
2524 
2525         return 0;
2526 }
2527 
2528 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2529         struct snd_kcontrol *kcontrol, int event)
2530 {
2531         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2532         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2533         unsigned int value;
2534 
2535         switch (event) {
2536         case SND_SOC_DAPM_PRE_PMU:
2537                 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2538                 if (value & RT5677_IF1_ADC_CTRL_MASK)
2539                         regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2540                                 RT5677_IF1_ADC_MODE_MASK,
2541                                 RT5677_IF1_ADC_MODE_TDM);
2542                 break;
2543 
2544         default:
2545                 return 0;
2546         }
2547 
2548         return 0;
2549 }
2550 
2551 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2552         struct snd_kcontrol *kcontrol, int event)
2553 {
2554         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2555         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2556         unsigned int value;
2557 
2558         switch (event) {
2559         case SND_SOC_DAPM_PRE_PMU:
2560                 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2561                 if (value & RT5677_IF2_ADC_CTRL_MASK)
2562                         regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2563                                 RT5677_IF2_ADC_MODE_MASK,
2564                                 RT5677_IF2_ADC_MODE_TDM);
2565                 break;
2566 
2567         default:
2568                 return 0;
2569         }
2570 
2571         return 0;
2572 }
2573 
2574 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2575         struct snd_kcontrol *kcontrol, int event)
2576 {
2577         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2578         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2579 
2580         switch (event) {
2581         case SND_SOC_DAPM_POST_PMU:
2582                 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2583                         !rt5677->is_vref_slow) {
2584                         mdelay(20);
2585                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2586                                 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2587                                 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2588                         rt5677->is_vref_slow = true;
2589                 }
2590                 break;
2591 
2592         default:
2593                 return 0;
2594         }
2595 
2596         return 0;
2597 }
2598 
2599 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2600         SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2601                 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2602                 SND_SOC_DAPM_POST_PMU),
2603         SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2604                 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2605                 SND_SOC_DAPM_POST_PMU),
2606 
2607         /* ASRC */
2608         SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2609         SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2610         SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2611         SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2612         SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2613         SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2614                 0),
2615         SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2616                 0),
2617         SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2618                 0),
2619         SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2620                 0),
2621         SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2622                 0),
2623         SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2624                 0),
2625         SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2626                 0),
2627         SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2628                 0),
2629         SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2630                 0),
2631         SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2632                 0),
2633         SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2634                 0),
2635         SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2636                 0),
2637         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2638         SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2639         SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2640         SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2641         SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2642                 0),
2643         SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2644                 0),
2645 
2646         /* Input Side */
2647         /* micbias */
2648         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2649                 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2650                 SND_SOC_DAPM_POST_PMU),
2651 
2652         /* Input Lines */
2653         SND_SOC_DAPM_INPUT("DMIC L1"),
2654         SND_SOC_DAPM_INPUT("DMIC R1"),
2655         SND_SOC_DAPM_INPUT("DMIC L2"),
2656         SND_SOC_DAPM_INPUT("DMIC R2"),
2657         SND_SOC_DAPM_INPUT("DMIC L3"),
2658         SND_SOC_DAPM_INPUT("DMIC R3"),
2659         SND_SOC_DAPM_INPUT("DMIC L4"),
2660         SND_SOC_DAPM_INPUT("DMIC R4"),
2661 
2662         SND_SOC_DAPM_INPUT("IN1P"),
2663         SND_SOC_DAPM_INPUT("IN1N"),
2664         SND_SOC_DAPM_INPUT("IN2P"),
2665         SND_SOC_DAPM_INPUT("IN2N"),
2666 
2667         SND_SOC_DAPM_INPUT("Haptic Generator"),
2668 
2669         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2670         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2671         SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2672         SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 
2674         SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2675                 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2676         SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2677                 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2678         SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2679                 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2680         SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2681                 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2682 
2683         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2684                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2685 
2686         /* Boost */
2687         SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2688                 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2689                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2690         SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2691                 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2692                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2693 
2694         /* ADCs */
2695         SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2696                 0, 0),
2697         SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2698                 0, 0),
2699         SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2700 
2701         SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2702                 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2703         SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2704                 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2705         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2706                 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2707         SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2708                 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2709 
2710         /* ADC Mux */
2711         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2712                                 &rt5677_sto1_dmic_mux),
2713         SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2714                                 &rt5677_sto1_adc1_mux),
2715         SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2716                                 &rt5677_sto1_adc2_mux),
2717         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2718                                 &rt5677_sto2_dmic_mux),
2719         SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2720                                 &rt5677_sto2_adc1_mux),
2721         SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2722                                 &rt5677_sto2_adc2_mux),
2723         SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2724                                 &rt5677_sto2_adc_lr_mux),
2725         SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2726                                 &rt5677_sto3_dmic_mux),
2727         SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2728                                 &rt5677_sto3_adc1_mux),
2729         SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2730                                 &rt5677_sto3_adc2_mux),
2731         SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2732                                 &rt5677_sto4_dmic_mux),
2733         SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2734                                 &rt5677_sto4_adc1_mux),
2735         SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2736                                 &rt5677_sto4_adc2_mux),
2737         SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2738                                 &rt5677_mono_dmic_l_mux),
2739         SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2740                                 &rt5677_mono_dmic_r_mux),
2741         SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2742                                 &rt5677_mono_adc2_l_mux),
2743         SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2744                                 &rt5677_mono_adc1_l_mux),
2745         SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2746                                 &rt5677_mono_adc1_r_mux),
2747         SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2748                                 &rt5677_mono_adc2_r_mux),
2749 
2750         /* ADC Mixer */
2751         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2752                 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2753         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2754                 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2755         SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2756                 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2757         SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2758                 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2759         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2760                 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2761         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2762                 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2763         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2764                 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2765         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2766                 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2767         SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2768                 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2769         SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2770                 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2771         SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2772                 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2773         SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2774                 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2775         SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2776                 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2777         SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2778                 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2779         SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2780                 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2781         SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2782                 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2783 
2784         /* ADC PGA */
2785         SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2786         SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2787         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2788         SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2789         SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2790         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2791         SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2792         SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2793         SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2794         SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2795         SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2796         SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797         SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798         SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2799         SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2800         SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 
2802         /* DSP */
2803         SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2804                         &rt5677_ib9_src_mux),
2805         SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2806                         &rt5677_ib8_src_mux),
2807         SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2808                         &rt5677_ib7_src_mux),
2809         SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2810                         &rt5677_ib6_src_mux),
2811         SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2812                         &rt5677_ib45_src_mux),
2813         SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2814                         &rt5677_ib23_src_mux),
2815         SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2816                         &rt5677_ib01_src_mux),
2817         SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2818                         &rt5677_ib45_bypass_src_mux),
2819         SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2820                         &rt5677_ib23_bypass_src_mux),
2821         SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2822                         &rt5677_ib01_bypass_src_mux),
2823         SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2824                         &rt5677_ob23_bypass_src_mux),
2825         SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2826                         &rt5677_ob01_bypass_src_mux),
2827 
2828         SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2829         SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 
2831         SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2832         SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2833         SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2834         SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2835         SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2836         SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 
2838         /* Digital Interface */
2839         SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2840                 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2841         SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2842         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2843         SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2844         SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2845         SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2846         SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2847         SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2848         SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2849         SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2850         SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2851         SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2852         SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2853         SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2854         SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2855         SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2856         SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 
2858         SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2859                 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2860         SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2861         SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2862         SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2863         SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2864         SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2865         SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2866         SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2867         SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2868         SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2869         SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2870         SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2871         SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2872         SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2873         SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2874         SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2875         SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 
2877         SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2878                 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2879         SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2880         SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2881         SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2882         SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2883         SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2884         SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 
2886         SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2887                 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2888         SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2889         SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2890         SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2891         SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2892         SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2893         SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 
2895         SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2896                 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2897         SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2898         SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2899         SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2900         SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2901         SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2902         SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2903         SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2904         SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2905         SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2906         SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2907         SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2908         SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2909         SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2910         SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2911         SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2912         SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 
2914         /* Digital Interface Select */
2915         SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2916                         &rt5677_if1_adc1_mux),
2917         SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2918                         &rt5677_if1_adc2_mux),
2919         SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2920                         &rt5677_if1_adc3_mux),
2921         SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2922                         &rt5677_if1_adc4_mux),
2923         SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2924                         &rt5677_if1_adc1_swap_mux),
2925         SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2926                         &rt5677_if1_adc2_swap_mux),
2927         SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2928                         &rt5677_if1_adc3_swap_mux),
2929         SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2930                         &rt5677_if1_adc4_swap_mux),
2931         SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2932                         &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2933                         SND_SOC_DAPM_PRE_PMU),
2934         SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2935                         &rt5677_if2_adc1_mux),
2936         SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2937                         &rt5677_if2_adc2_mux),
2938         SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2939                         &rt5677_if2_adc3_mux),
2940         SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2941                         &rt5677_if2_adc4_mux),
2942         SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2943                         &rt5677_if2_adc1_swap_mux),
2944         SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2945                         &rt5677_if2_adc2_swap_mux),
2946         SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2947                         &rt5677_if2_adc3_swap_mux),
2948         SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2949                         &rt5677_if2_adc4_swap_mux),
2950         SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2951                         &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2952                         SND_SOC_DAPM_PRE_PMU),
2953         SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2954                         &rt5677_if3_adc_mux),
2955         SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2956                         &rt5677_if4_adc_mux),
2957         SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2958                         &rt5677_slb_adc1_mux),
2959         SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2960                         &rt5677_slb_adc2_mux),
2961         SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2962                         &rt5677_slb_adc3_mux),
2963         SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2964                         &rt5677_slb_adc4_mux),
2965 
2966         SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2967                         &rt5677_if1_dac0_tdm_sel_mux),
2968         SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2969                         &rt5677_if1_dac1_tdm_sel_mux),
2970         SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2971                         &rt5677_if1_dac2_tdm_sel_mux),
2972         SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2973                         &rt5677_if1_dac3_tdm_sel_mux),
2974         SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2975                         &rt5677_if1_dac4_tdm_sel_mux),
2976         SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2977                         &rt5677_if1_dac5_tdm_sel_mux),
2978         SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2979                         &rt5677_if1_dac6_tdm_sel_mux),
2980         SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2981                         &rt5677_if1_dac7_tdm_sel_mux),
2982 
2983         SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2984                         &rt5677_if2_dac0_tdm_sel_mux),
2985         SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2986                         &rt5677_if2_dac1_tdm_sel_mux),
2987         SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2988                         &rt5677_if2_dac2_tdm_sel_mux),
2989         SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2990                         &rt5677_if2_dac3_tdm_sel_mux),
2991         SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2992                         &rt5677_if2_dac4_tdm_sel_mux),
2993         SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2994                         &rt5677_if2_dac5_tdm_sel_mux),
2995         SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2996                         &rt5677_if2_dac6_tdm_sel_mux),
2997         SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2998                         &rt5677_if2_dac7_tdm_sel_mux),
2999 
3000         /* Audio Interface */
3001         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3002         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3003         SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3004         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3005         SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3006         SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3007         SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3008         SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3009         SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3010         SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3011 
3012         /* Sidetone Mux */
3013         SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3014                         &rt5677_sidetone_mux),
3015         SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3016                 RT5677_ST_EN_SFT, 0, NULL, 0),
3017 
3018         /* VAD Mux*/
3019         SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3020                         &rt5677_vad_src_mux),
3021 
3022         /* Tensilica DSP */
3023         SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3024         SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3025                 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3026         SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3027                 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3028         SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3029                 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3030         SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3031                 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3032         SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3033                 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3034         SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3035                 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3036 
3037         /* Output Side */
3038         /* DAC mixer before sound effect */
3039         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3040                 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3041         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3042                 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3043         SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3044 
3045         /* DAC Mux */
3046         SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3047                                 &rt5677_dac1_mux),
3048         SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3049                                 &rt5677_adda1_mux),
3050         SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3051                                 &rt5677_dac12_mux),
3052         SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3053                                 &rt5677_dac3_mux),
3054 
3055         /* DAC2 channel Mux */
3056         SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3057                                 &rt5677_dac2_l_mux),
3058         SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3059                                 &rt5677_dac2_r_mux),
3060 
3061         /* DAC3 channel Mux */
3062         SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3063                         &rt5677_dac3_l_mux),
3064         SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3065                         &rt5677_dac3_r_mux),
3066 
3067         /* DAC4 channel Mux */
3068         SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3069                         &rt5677_dac4_l_mux),
3070         SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3071                         &rt5677_dac4_r_mux),
3072 
3073         /* DAC Mixer */
3074         SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3075                 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
3076         SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3077                 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
3078         SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3079                 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
3080         SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3081                 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
3082         SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3083                 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
3084         SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3085                 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
3086         SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3087                 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
3088 
3089         SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3090                 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3091         SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3092                 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3093         SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3094                 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3095         SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3096                 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3097         SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3098                 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3099         SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3100                 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3101         SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3102                 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3103         SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3104                 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3105         SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3106         SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3107         SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3108         SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3109 
3110         /* DACs */
3111         SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3112                 RT5677_PWR_DAC1_BIT, 0),
3113         SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3114                 RT5677_PWR_DAC2_BIT, 0),
3115         SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3116                 RT5677_PWR_DAC3_BIT, 0),
3117 
3118         /* PDM */
3119         SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3120                 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3121         SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3122                 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3123 
3124         SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3125                 1, &rt5677_pdm1_l_mux),
3126         SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3127                 1, &rt5677_pdm1_r_mux),
3128         SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3129                 1, &rt5677_pdm2_l_mux),
3130         SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3131                 1, &rt5677_pdm2_r_mux),
3132 
3133         SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3134                 0, NULL, 0),
3135         SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3136                 0, NULL, 0),
3137         SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3138                 0, NULL, 0),
3139 
3140         SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3141                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3142         SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3143                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3144         SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3145                 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3146 
3147         /* Output Lines */
3148         SND_SOC_DAPM_OUTPUT("LOUT1"),
3149         SND_SOC_DAPM_OUTPUT("LOUT2"),
3150         SND_SOC_DAPM_OUTPUT("LOUT3"),
3151         SND_SOC_DAPM_OUTPUT("PDM1L"),
3152         SND_SOC_DAPM_OUTPUT("PDM1R"),
3153         SND_SOC_DAPM_OUTPUT("PDM2L"),
3154         SND_SOC_DAPM_OUTPUT("PDM2R"),
3155 
3156         SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3157 };
3158 
3159 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3160         { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3161         { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3162         { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3163         { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3164         { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3165         { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3166         { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3167         { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3168         { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3169         { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3170 
3171         { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3172         { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3173         { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3174         { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3175         { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3176         { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3177         { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3178         { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3179         { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3180         { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3181         { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3182         { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3183         { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3184 
3185         { "DMIC1", NULL, "DMIC L1" },
3186         { "DMIC1", NULL, "DMIC R1" },
3187         { "DMIC2", NULL, "DMIC L2" },
3188         { "DMIC2", NULL, "DMIC R2" },
3189         { "DMIC3", NULL, "DMIC L3" },
3190         { "DMIC3", NULL, "DMIC R3" },
3191         { "DMIC4", NULL, "DMIC L4" },
3192         { "DMIC4", NULL, "DMIC R4" },
3193 
3194         { "DMIC L1", NULL, "DMIC CLK" },
3195         { "DMIC R1", NULL, "DMIC CLK" },
3196         { "DMIC L2", NULL, "DMIC CLK" },
3197         { "DMIC R2", NULL, "DMIC CLK" },
3198         { "DMIC L3", NULL, "DMIC CLK" },
3199         { "DMIC R3", NULL, "DMIC CLK" },
3200         { "DMIC L4", NULL, "DMIC CLK" },
3201         { "DMIC R4", NULL, "DMIC CLK" },
3202 
3203         { "DMIC L1", NULL, "DMIC1 power" },
3204         { "DMIC R1", NULL, "DMIC1 power" },
3205         { "DMIC L3", NULL, "DMIC3 power" },
3206         { "DMIC R3", NULL, "DMIC3 power" },
3207         { "DMIC L4", NULL, "DMIC4 power" },
3208         { "DMIC R4", NULL, "DMIC4 power" },
3209 
3210         { "BST1", NULL, "IN1P" },
3211         { "BST1", NULL, "IN1N" },
3212         { "BST2", NULL, "IN2P" },
3213         { "BST2", NULL, "IN2N" },
3214 
3215         { "IN1P", NULL, "MICBIAS1" },
3216         { "IN1N", NULL, "MICBIAS1" },
3217         { "IN2P", NULL, "MICBIAS1" },
3218         { "IN2N", NULL, "MICBIAS1" },
3219 
3220         { "ADC 1", NULL, "BST1" },
3221         { "ADC 1", NULL, "ADC 1 power" },
3222         { "ADC 1", NULL, "ADC1 clock" },
3223         { "ADC 2", NULL, "BST2" },
3224         { "ADC 2", NULL, "ADC 2 power" },
3225         { "ADC 2", NULL, "ADC2 clock" },
3226 
3227         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3228         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3229         { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3230         { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3231 
3232         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3233         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3234         { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3235         { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3236 
3237         { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3238         { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3239         { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3240         { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3241 
3242         { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3243         { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3244         { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3245         { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3246 
3247         { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3248         { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3249         { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3250         { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3251 
3252         { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3253         { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3254         { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3255         { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3256 
3257         { "ADC 1_2", NULL, "ADC 1" },
3258         { "ADC 1_2", NULL, "ADC 2" },
3259 
3260         { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3261         { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3262         { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3263 
3264         { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3265         { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3266         { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3267 
3268         { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3269         { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3270         { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3271 
3272         { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3273         { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3274         { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3275 
3276         { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3277         { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3278         { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3279 
3280         { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3281         { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3282         { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3283 
3284         { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3285         { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3286         { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3287 
3288         { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3289         { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3290         { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3291 
3292         { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3293         { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3294         { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3295 
3296         { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3297         { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3298         { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3299 
3300         { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3301         { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3302         { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3303 
3304         { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3305         { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3306         { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3307 
3308         { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3309         { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3310         { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3311         { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3312 
3313         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3314         { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3315         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3316         { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3317         { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3318 
3319         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3320         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3321 
3322         { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3323         { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3324         { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3325         { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3326 
3327         { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3328         { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3329 
3330         { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3331         { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3332 
3333         { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3334         { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3335         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3336         { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3337         { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3338 
3339         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3340         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3341 
3342         { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3343         { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3344         { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3345         { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3346 
3347         { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3348         { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3349         { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3350         { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3351         { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3352 
3353         { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3354         { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3355 
3356         { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3357         { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3358         { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3359         { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3360 
3361         { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3362         { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3363         { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3364         { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3365         { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3366 
3367         { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3368         { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3369 
3370         { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3371         { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3372         { "Mono ADC MIXL", NULL, "adc mono left filter" },
3373         { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3374 
3375         { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3376         { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3377         { "Mono ADC MIXR", NULL, "adc mono right filter" },
3378         { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3379 
3380         { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3381         { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3382 
3383         { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3384         { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3385         { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3386         { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3387         { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3388 
3389         { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3390         { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3391         { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3392 
3393         { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3394         { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3395 
3396         { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3397         { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3398         { "IF1 ADC3 Mux", "OB45", "OB45" },
3399 
3400         { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3401         { "IF1 ADC4 Mux", "OB67", "OB67" },
3402         { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3403 
3404         { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3405         { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3406         { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3407         { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3408 
3409         { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3410         { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3411         { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3412         { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3413 
3414         { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3415         { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3416         { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3417         { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3418 
3419         { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3420         { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3421         { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3422         { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3423 
3424         { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3425         { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3426         { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3427         { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3428 
3429         { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3430         { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3431         { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3432         { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3433         { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3434         { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3435         { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3436         { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3437 
3438         { "AIF1TX", NULL, "I2S1" },
3439         { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3440 
3441         { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3442         { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3443         { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3444 
3445         { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3446         { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3447 
3448         { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3449         { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3450         { "IF2 ADC3 Mux", "OB45", "OB45" },
3451 
3452         { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3453         { "IF2 ADC4 Mux", "OB67", "OB67" },
3454         { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3455 
3456         { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3457         { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3458         { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3459         { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3460 
3461         { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3462         { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3463         { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3464         { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3465 
3466         { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3467         { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3468         { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3469         { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3470 
3471         { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3472         { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3473         { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3474         { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3475 
3476         { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3477         { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3478         { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3479         { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3480 
3481         { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3482         { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3483         { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3484         { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3485         { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3486         { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3487         { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3488         { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3489 
3490         { "AIF2TX", NULL, "I2S2" },
3491         { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3492 
3493         { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3494         { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3495         { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3496         { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3497         { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3498         { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3499         { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3500         { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3501 
3502         { "AIF3TX", NULL, "I2S3" },
3503         { "AIF3TX", NULL, "IF3 ADC Mux" },
3504 
3505         { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3506         { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3507         { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3508         { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3509         { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3510         { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3511         { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3512         { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3513 
3514         { "AIF4TX", NULL, "I2S4" },
3515         { "AIF4TX", NULL, "IF4 ADC Mux" },
3516 
3517         { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3518         { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3519         { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3520 
3521         { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3522         { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3523 
3524         { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3525         { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3526         { "SLB ADC3 Mux", "OB45", "OB45" },
3527 
3528         { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3529         { "SLB ADC4 Mux", "OB67", "OB67" },
3530         { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3531 
3532         { "SLBTX", NULL, "SLB" },
3533         { "SLBTX", NULL, "SLB ADC1 Mux" },
3534         { "SLBTX", NULL, "SLB ADC2 Mux" },
3535         { "SLBTX", NULL, "SLB ADC3 Mux" },
3536         { "SLBTX", NULL, "SLB ADC4 Mux" },
3537 
3538         { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3539         { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3540         { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3541         { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3542         { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3543 
3544         { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3545         { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3546 
3547         { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3548         { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3549         { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3550         { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3551         { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3552         { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3553 
3554         { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3555         { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3556 
3557         { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3558         { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3559         { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3560         { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3561         { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3562 
3563         { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3564         { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3565 
3566         { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3567         { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3568         { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3569         { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3570         { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3571         { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3572         { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3573         { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3574 
3575         { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3576         { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3577         { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3578         { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3579         { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3580         { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3581         { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3582         { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3583 
3584         { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3585         { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3586         { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3587         { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3588         { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3589         { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3590 
3591         { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3592         { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3593         { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3594         { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3595         { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3596         { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3597         { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3598 
3599         { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3600         { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3601         { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3602         { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3603         { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3604         { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3605         { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3606 
3607         { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3608         { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3609         { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3610         { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3611         { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3612         { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3613         { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3614 
3615         { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3616         { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3617         { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3618         { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3619         { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3620         { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3621         { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3622 
3623         { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3624         { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3625         { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3626         { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3627         { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3628         { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3629         { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3630 
3631         { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3632         { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3633         { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3634         { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3635         { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3636         { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3637         { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3638 
3639         { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3640         { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3641         { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3642         { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3643         { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3644         { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3645         { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3646 
3647         { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3648         { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3649         { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3650         { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3651 
3652         { "OutBound2", NULL, "OB23 Bypass Mux" },
3653         { "OutBound3", NULL, "OB23 Bypass Mux" },
3654         { "OutBound4", NULL, "OB4 MIX" },
3655         { "OutBound5", NULL, "OB5 MIX" },
3656         { "OutBound6", NULL, "OB6 MIX" },
3657         { "OutBound7", NULL, "OB7 MIX" },
3658 
3659         { "OB45", NULL, "OutBound4" },
3660         { "OB45", NULL, "OutBound5" },
3661         { "OB67", NULL, "OutBound6" },
3662         { "OB67", NULL, "OutBound7" },
3663 
3664         { "IF1 DAC0", NULL, "AIF1RX" },
3665         { "IF1 DAC1", NULL, "AIF1RX" },
3666         { "IF1 DAC2", NULL, "AIF1RX" },
3667         { "IF1 DAC3", NULL, "AIF1RX" },
3668         { "IF1 DAC4", NULL, "AIF1RX" },
3669         { "IF1 DAC5", NULL, "AIF1RX" },
3670         { "IF1 DAC6", NULL, "AIF1RX" },
3671         { "IF1 DAC7", NULL, "AIF1RX" },
3672         { "IF1 DAC0", NULL, "I2S1" },
3673         { "IF1 DAC1", NULL, "I2S1" },
3674         { "IF1 DAC2", NULL, "I2S1" },
3675         { "IF1 DAC3", NULL, "I2S1" },
3676         { "IF1 DAC4", NULL, "I2S1" },
3677         { "IF1 DAC5", NULL, "I2S1" },
3678         { "IF1 DAC6", NULL, "I2S1" },
3679         { "IF1 DAC7", NULL, "I2S1" },
3680 
3681         { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3682         { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3683         { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3684         { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3685         { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3686         { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3687         { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3688         { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3689 
3690         { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3691         { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3692         { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3693         { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3694         { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3695         { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3696         { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3697         { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3698 
3699         { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3700         { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3701         { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3702         { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3703         { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3704         { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3705         { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3706         { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3707 
3708         { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3709         { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3710         { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3711         { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3712         { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3713         { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3714         { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3715         { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3716 
3717         { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3718         { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3719         { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3720         { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3721         { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3722         { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3723         { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3724         { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3725 
3726         { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3727         { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3728         { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3729         { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3730         { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3731         { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3732         { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3733         { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3734 
3735         { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3736         { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3737         { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3738         { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3739         { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3740         { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3741         { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3742         { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3743 
3744         { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3745         { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3746         { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3747         { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3748         { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3749         { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3750         { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3751         { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3752 
3753         { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3754         { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3755         { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3756         { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3757         { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3758         { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3759         { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3760         { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3761 
3762         { "IF2 DAC0", NULL, "AIF2RX" },
3763         { "IF2 DAC1", NULL, "AIF2RX" },
3764         { "IF2 DAC2", NULL, "AIF2RX" },
3765         { "IF2 DAC3", NULL, "AIF2RX" },
3766         { "IF2 DAC4", NULL, "AIF2RX" },
3767         { "IF2 DAC5", NULL, "AIF2RX" },
3768         { "IF2 DAC6", NULL, "AIF2RX" },
3769         { "IF2 DAC7", NULL, "AIF2RX" },
3770         { "IF2 DAC0", NULL, "I2S2" },
3771         { "IF2 DAC1", NULL, "I2S2" },
3772         { "IF2 DAC2", NULL, "I2S2" },
3773         { "IF2 DAC3", NULL, "I2S2" },
3774         { "IF2 DAC4", NULL, "I2S2" },
3775         { "IF2 DAC5", NULL, "I2S2" },
3776         { "IF2 DAC6", NULL, "I2S2" },
3777         { "IF2 DAC7", NULL, "I2S2" },
3778 
3779         { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3780         { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3781         { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3782         { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3783         { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3784         { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3785         { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3786         { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3787 
3788         { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3789         { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3790         { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3791         { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3792         { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3793         { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3794         { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3795         { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3796 
3797         { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3798         { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3799         { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3800         { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3801         { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3802         { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3803         { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3804         { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3805 
3806         { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3807         { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3808         { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3809         { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3810         { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3811         { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3812         { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3813         { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3814 
3815         { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3816         { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3817         { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3818         { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3819         { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3820         { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3821         { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3822         { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3823 
3824         { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3825         { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3826         { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3827         { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3828         { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3829         { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3830         { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3831         { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3832 
3833         { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3834         { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3835         { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3836         { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3837         { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3838         { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3839         { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3840         { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3841 
3842         { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3843         { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3844         { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3845         { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3846         { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3847         { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3848         { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3849         { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3850 
3851         { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3852         { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3853         { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3854         { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3855         { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3856         { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3857         { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3858         { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3859 
3860         { "IF3 DAC", NULL, "AIF3RX" },
3861         { "IF3 DAC", NULL, "I2S3" },
3862 
3863         { "IF4 DAC", NULL, "AIF4RX" },
3864         { "IF4 DAC", NULL, "I2S4" },
3865 
3866         { "IF3 DAC L", NULL, "IF3 DAC" },
3867         { "IF3 DAC R", NULL, "IF3 DAC" },
3868 
3869         { "IF4 DAC L", NULL, "IF4 DAC" },
3870         { "IF4 DAC R", NULL, "IF4 DAC" },
3871 
3872         { "SLB DAC0", NULL, "SLBRX" },
3873         { "SLB DAC1", NULL, "SLBRX" },
3874         { "SLB DAC2", NULL, "SLBRX" },
3875         { "SLB DAC3", NULL, "SLBRX" },
3876         { "SLB DAC4", NULL, "SLBRX" },
3877         { "SLB DAC5", NULL, "SLBRX" },
3878         { "SLB DAC6", NULL, "SLBRX" },
3879         { "SLB DAC7", NULL, "SLBRX" },
3880         { "SLB DAC0", NULL, "SLB" },
3881         { "SLB DAC1", NULL, "SLB" },
3882         { "SLB DAC2", NULL, "SLB" },
3883         { "SLB DAC3", NULL, "SLB" },
3884         { "SLB DAC4", NULL, "SLB" },
3885         { "SLB DAC5", NULL, "SLB" },
3886         { "SLB DAC6", NULL, "SLB" },
3887         { "SLB DAC7", NULL, "SLB" },
3888 
3889         { "SLB DAC01", NULL, "SLB DAC0" },
3890         { "SLB DAC01", NULL, "SLB DAC1" },
3891         { "SLB DAC23", NULL, "SLB DAC2" },
3892         { "SLB DAC23", NULL, "SLB DAC3" },
3893         { "SLB DAC45", NULL, "SLB DAC4" },
3894         { "SLB DAC45", NULL, "SLB DAC5" },
3895         { "SLB DAC67", NULL, "SLB DAC6" },
3896         { "SLB DAC67", NULL, "SLB DAC7" },
3897 
3898         { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3899         { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3900         { "ADDA1 Mux", "OB 67", "OB67" },
3901 
3902         { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3903         { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3904         { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3905         { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3906         { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3907         { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3908 
3909         { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3910         { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3911         { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3912         { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3913 
3914         { "DAC1 FS", NULL, "DAC1 MIXL" },
3915         { "DAC1 FS", NULL, "DAC1 MIXR" },
3916 
3917         { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3918         { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3919         { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3920         { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3921         { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3922         { "DAC2 L Mux", "OB 2", "OutBound2" },
3923 
3924         { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3925         { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3926         { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3927         { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3928         { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3929         { "DAC2 R Mux", "OB 3", "OutBound3" },
3930         { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3931         { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3932 
3933         { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3934         { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3935         { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3936         { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3937         { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3938         { "DAC3 L Mux", "OB 4", "OutBound4" },
3939 
3940         { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3941         { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3942         { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3943         { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3944         { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3945         { "DAC3 R Mux", "OB 5", "OutBound5" },
3946 
3947         { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3948         { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3949         { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3950         { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3951         { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3952         { "DAC4 L Mux", "OB 6", "OutBound6" },
3953 
3954         { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3955         { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3956         { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3957         { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3958         { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3959         { "DAC4 R Mux", "OB 7", "OutBound7" },
3960 
3961         { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3962         { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3963         { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3964         { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3965         { "Sidetone Mux", "ADC1", "ADC 1" },
3966         { "Sidetone Mux", "ADC2", "ADC 2" },
3967         { "Sidetone Mux", NULL, "Sidetone Power" },
3968 
3969         { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3970         { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3971         { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3972         { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3973         { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3974         { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3975         { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3976         { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3977         { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3978         { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3979         { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3980 
3981         { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3982         { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3983         { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3984         { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3985         { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3986         { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3987         { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3988         { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3989         { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3990         { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3991         { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3992         { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3993 
3994         { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3995         { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3996         { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3997         { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3998         { "DD1 MIXL", NULL, "dac mono3 left filter" },
3999         { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4000         { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4001         { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4002         { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4003         { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4004         { "DD1 MIXR", NULL, "dac mono3 right filter" },
4005         { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4006 
4007         { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4008         { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4009         { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4010         { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4011         { "DD2 MIXL", NULL, "dac mono4 left filter" },
4012         { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4013         { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4014         { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4015         { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4016         { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4017         { "DD2 MIXR", NULL, "dac mono4 right filter" },
4018         { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4019 
4020         { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4021         { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4022         { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4023         { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4024         { "DD1 MIX", NULL, "DD1 MIXL" },
4025         { "DD1 MIX", NULL, "DD1 MIXR" },
4026         { "DD2 MIX", NULL, "DD2 MIXL" },
4027         { "DD2 MIX", NULL, "DD2 MIXR" },
4028 
4029         { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4030         { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4031         { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4032         { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4033 
4034         { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4035         { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4036         { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4037         { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4038 
4039         { "DAC 1", NULL, "DAC12 SRC Mux" },
4040         { "DAC 2", NULL, "DAC12 SRC Mux" },
4041         { "DAC 3", NULL, "DAC3 SRC Mux" },
4042 
4043         { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4044         { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4045         { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4046         { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4047         { "PDM1 L Mux", NULL, "PDM1 Power" },
4048         { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4049         { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4050         { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4051         { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4052         { "PDM1 R Mux", NULL, "PDM1 Power" },
4053         { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4054         { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4055         { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4056         { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4057         { "PDM2 L Mux", NULL, "PDM2 Power" },
4058         { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4059         { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4060         { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4061         { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4062         { "PDM2 R Mux", NULL, "PDM2 Power" },
4063 
4064         { "LOUT1 amp", NULL, "DAC 1" },
4065         { "LOUT2 amp", NULL, "DAC 2" },
4066         { "LOUT3 amp", NULL, "DAC 3" },
4067 
4068         { "LOUT1 vref", NULL, "LOUT1 amp" },
4069         { "LOUT2 vref", NULL, "LOUT2 amp" },
4070         { "LOUT3 vref", NULL, "LOUT3 amp" },
4071 
4072         { "LOUT1", NULL, "LOUT1 vref" },
4073         { "LOUT2", NULL, "LOUT2 vref" },
4074         { "LOUT3", NULL, "LOUT3 vref" },
4075 
4076         { "PDM1L", NULL, "PDM1 L Mux" },
4077         { "PDM1R", NULL, "PDM1 R Mux" },
4078         { "PDM2L", NULL, "PDM2 L Mux" },
4079         { "PDM2R", NULL, "PDM2 R Mux" },
4080 };
4081 
4082 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4083         { "DMIC L2", NULL, "DMIC1 power" },
4084         { "DMIC R2", NULL, "DMIC1 power" },
4085 };
4086 
4087 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4088         { "DMIC L2", NULL, "DMIC2 power" },
4089         { "DMIC R2", NULL, "DMIC2 power" },
4090 };
4091 
4092 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4093         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4094 {
4095         struct snd_soc_codec *codec = dai->codec;
4096         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4097         unsigned int val_len = 0, val_clk, mask_clk;
4098         int pre_div, bclk_ms, frame_size;
4099 
4100         rt5677->lrck[dai->id] = params_rate(params);
4101         pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4102         if (pre_div < 0) {
4103                 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4104                         rt5677->sysclk, rt5677->lrck[dai->id]);
4105                 return -EINVAL;
4106         }
4107         frame_size = snd_soc_params_to_frame_size(params);
4108         if (frame_size < 0) {
4109                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4110                 return -EINVAL;
4111         }
4112         bclk_ms = frame_size > 32;
4113         rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4114 
4115         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4116                 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4117         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4118                                 bclk_ms, pre_div, dai->id);
4119 
4120         switch (params_width(params)) {
4121         case 16:
4122                 break;
4123         case 20:
4124                 val_len |= RT5677_I2S_DL_20;
4125                 break;
4126         case 24:
4127                 val_len |= RT5677_I2S_DL_24;
4128                 break;
4129         case 8:
4130                 val_len |= RT5677_I2S_DL_8;
4131                 break;
4132         default:
4133                 return -EINVAL;
4134         }
4135 
4136         switch (dai->id) {
4137         case RT5677_AIF1:
4138                 mask_clk = RT5677_I2S_PD1_MASK;
4139                 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4140                 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4141                         RT5677_I2S_DL_MASK, val_len);
4142                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4143                         mask_clk, val_clk);
4144                 break;
4145         case RT5677_AIF2:
4146                 mask_clk = RT5677_I2S_PD2_MASK;
4147                 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4148                 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4149                         RT5677_I2S_DL_MASK, val_len);
4150                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4151                         mask_clk, val_clk);
4152                 break;
4153         case RT5677_AIF3:
4154                 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4155                 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4156                         pre_div << RT5677_I2S_PD3_SFT;
4157                 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4158                         RT5677_I2S_DL_MASK, val_len);
4159                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4160                         mask_clk, val_clk);
4161                 break;
4162         case RT5677_AIF4:
4163                 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4164                 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4165                         pre_div << RT5677_I2S_PD4_SFT;
4166                 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4167                         RT5677_I2S_DL_MASK, val_len);
4168                 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4169                         mask_clk, val_clk);
4170                 break;
4171         default:
4172                 break;
4173         }
4174 
4175         return 0;
4176 }
4177 
4178 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4179 {
4180         struct snd_soc_codec *codec = dai->codec;
4181         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4182         unsigned int reg_val = 0;
4183 
4184         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4185         case SND_SOC_DAIFMT_CBM_CFM:
4186                 rt5677->master[dai->id] = 1;
4187                 break;
4188         case SND_SOC_DAIFMT_CBS_CFS:
4189                 reg_val |= RT5677_I2S_MS_S;
4190                 rt5677->master[dai->id] = 0;
4191                 break;
4192         default:
4193                 return -EINVAL;
4194         }
4195 
4196         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4197         case SND_SOC_DAIFMT_NB_NF:
4198                 break;
4199         case SND_SOC_DAIFMT_IB_NF:
4200                 reg_val |= RT5677_I2S_BP_INV;
4201                 break;
4202         default:
4203                 return -EINVAL;
4204         }
4205 
4206         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4207         case SND_SOC_DAIFMT_I2S:
4208                 break;
4209         case SND_SOC_DAIFMT_LEFT_J:
4210                 reg_val |= RT5677_I2S_DF_LEFT;
4211                 break;
4212         case SND_SOC_DAIFMT_DSP_A:
4213                 reg_val |= RT5677_I2S_DF_PCM_A;
4214                 break;
4215         case SND_SOC_DAIFMT_DSP_B:
4216                 reg_val |= RT5677_I2S_DF_PCM_B;
4217                 break;
4218         default:
4219                 return -EINVAL;
4220         }
4221 
4222         switch (dai->id) {
4223         case RT5677_AIF1:
4224                 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4225                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4226                         RT5677_I2S_DF_MASK, reg_val);
4227                 break;
4228         case RT5677_AIF2:
4229                 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4230                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4231                         RT5677_I2S_DF_MASK, reg_val);
4232                 break;
4233         case RT5677_AIF3:
4234                 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4235                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4236                         RT5677_I2S_DF_MASK, reg_val);
4237                 break;
4238         case RT5677_AIF4:
4239                 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4240                         RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4241                         RT5677_I2S_DF_MASK, reg_val);
4242                 break;
4243         default:
4244                 break;
4245         }
4246 
4247 
4248         return 0;
4249 }
4250 
4251 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4252                 int clk_id, unsigned int freq, int dir)
4253 {
4254         struct snd_soc_codec *codec = dai->codec;
4255         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4256         unsigned int reg_val = 0;
4257 
4258         if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4259                 return 0;
4260 
4261         switch (clk_id) {
4262         case RT5677_SCLK_S_MCLK:
4263                 reg_val |= RT5677_SCLK_SRC_MCLK;
4264                 break;
4265         case RT5677_SCLK_S_PLL1:
4266                 reg_val |= RT5677_SCLK_SRC_PLL1;
4267                 break;
4268         case RT5677_SCLK_S_RCCLK:
4269                 reg_val |= RT5677_SCLK_SRC_RCCLK;
4270                 break;
4271         default:
4272                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4273                 return -EINVAL;
4274         }
4275         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4276                 RT5677_SCLK_SRC_MASK, reg_val);
4277         rt5677->sysclk = freq;
4278         rt5677->sysclk_src = clk_id;
4279 
4280         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4281 
4282         return 0;
4283 }
4284 
4285 /**
4286  * rt5677_pll_calc - Calcualte PLL M/N/K code.
4287  * @freq_in: external clock provided to codec.
4288  * @freq_out: target clock which codec works on.
4289  * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4290  *
4291  * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4292  *
4293  * Returns 0 for success or negative error code.
4294  */
4295 static int rt5677_pll_calc(const unsigned int freq_in,
4296         const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4297 {
4298         if (RT5677_PLL_INP_MIN > freq_in)
4299                 return -EINVAL;
4300 
4301         return rl6231_pll_calc(freq_in, freq_out, pll_code);
4302 }
4303 
4304 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4305                         unsigned int freq_in, unsigned int freq_out)
4306 {
4307         struct snd_soc_codec *codec = dai->codec;
4308         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4309         struct rl6231_pll_code pll_code;
4310         int ret;
4311 
4312         if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4313             freq_out == rt5677->pll_out)
4314                 return 0;
4315 
4316         if (!freq_in || !freq_out) {
4317                 dev_dbg(codec->dev, "PLL disabled\n");
4318 
4319                 rt5677->pll_in = 0;
4320                 rt5677->pll_out = 0;
4321                 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4322                         RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4323                 return 0;
4324         }
4325 
4326         switch (source) {
4327         case RT5677_PLL1_S_MCLK:
4328                 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4329                         RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4330                 break;
4331         case RT5677_PLL1_S_BCLK1:
4332         case RT5677_PLL1_S_BCLK2:
4333         case RT5677_PLL1_S_BCLK3:
4334         case RT5677_PLL1_S_BCLK4:
4335                 switch (dai->id) {
4336                 case RT5677_AIF1:
4337                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4338                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4339                         break;
4340                 case RT5677_AIF2:
4341                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4342                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4343                         break;
4344                 case RT5677_AIF3:
4345                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4346                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4347                         break;
4348                 case RT5677_AIF4:
4349                         regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4350                                 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4351                         break;
4352                 default:
4353                         break;
4354                 }
4355                 break;
4356         default:
4357                 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4358                 return -EINVAL;
4359         }
4360 
4361         ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4362         if (ret < 0) {
4363                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4364                 return ret;
4365         }
4366 
4367         dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4368                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4369                 pll_code.n_code, pll_code.k_code);
4370 
4371         regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4372                 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4373         regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4374                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4375                 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4376 
4377         rt5677->pll_in = freq_in;
4378         rt5677->pll_out = freq_out;
4379         rt5677->pll_src = source;
4380 
4381         return 0;
4382 }
4383 
4384 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4385                         unsigned int rx_mask, int slots, int slot_width)
4386 {
4387         struct snd_soc_codec *codec = dai->codec;
4388         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4389         unsigned int val = 0, slot_width_25 = 0;
4390 
4391         if (rx_mask || tx_mask)
4392                 val |= (1 << 12);
4393 
4394         switch (slots) {
4395         case 4:
4396                 val |= (1 << 10);
4397                 break;
4398         case 6:
4399                 val |= (2 << 10);
4400                 break;
4401         case 8:
4402                 val |= (3 << 10);
4403                 break;
4404         case 2:
4405         default:
4406                 break;
4407         }
4408 
4409         switch (slot_width) {
4410         case 20:
4411                 val |= (1 << 8);
4412                 break;
4413         case 25:
4414                 slot_width_25 = 0x8080;
4415         case 24:
4416                 val |= (2 << 8);
4417                 break;
4418         case 32:
4419                 val |= (3 << 8);
4420                 break;
4421         case 16:
4422         default:
4423                 break;
4424         }
4425 
4426         switch (dai->id) {
4427         case RT5677_AIF1:
4428                 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4429                         val);
4430                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4431                         slot_width_25);
4432                 break;
4433         case RT5677_AIF2:
4434                 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4435                         val);
4436                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4437                         slot_width_25);
4438                 break;
4439         default:
4440                 break;
4441         }
4442 
4443         return 0;
4444 }
4445 
4446 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4447                         enum snd_soc_bias_level level)
4448 {
4449         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4450 
4451         switch (level) {
4452         case SND_SOC_BIAS_ON:
4453                 break;
4454 
4455         case SND_SOC_BIAS_PREPARE:
4456                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4457                         rt5677_set_dsp_vad(codec, false);
4458 
4459                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4460                                 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4461                                 0x0055);
4462                         regmap_update_bits(rt5677->regmap,
4463                                 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4464                                 0x0f00, 0x0f00);
4465                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4466                                 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4467                                 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4468                                 RT5677_PWR_BG | RT5677_PWR_VREF2,
4469                                 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4470                                 RT5677_PWR_BG | RT5677_PWR_VREF2);
4471                         rt5677->is_vref_slow = false;
4472                         regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4473                                 RT5677_PWR_CORE, RT5677_PWR_CORE);
4474                         regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4475                                 0x1, 0x1);
4476                 }
4477                 break;
4478 
4479         case SND_SOC_BIAS_STANDBY:
4480                 break;
4481 
4482         case SND_SOC_BIAS_OFF:
4483                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4484                 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4485                 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4486                 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4487                 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4488                 regmap_update_bits(rt5677->regmap,
4489                         RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4490 
4491                 if (rt5677->dsp_vad_en)
4492                         rt5677_set_dsp_vad(codec, true);
4493                 break;
4494 
4495         default:
4496                 break;
4497         }
4498 
4499         return 0;
4500 }
4501 
4502 #ifdef CONFIG_GPIOLIB
4503 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4504 {
4505         return container_of(chip, struct rt5677_priv, gpio_chip);
4506 }
4507 
4508 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4509 {
4510         struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4511 
4512         switch (offset) {
4513         case RT5677_GPIO1 ... RT5677_GPIO5:
4514                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4515                         0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4516                 break;
4517 
4518         case RT5677_GPIO6:
4519                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4520                         RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4521                 break;
4522 
4523         default:
4524                 break;
4525         }
4526 }
4527 
4528 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4529                                      unsigned offset, int value)
4530 {
4531         struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4532 
4533         switch (offset) {
4534         case RT5677_GPIO1 ... RT5677_GPIO5:
4535                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4536                         0x3 << (offset * 3 + 1),
4537                         (0x2 | !!value) << (offset * 3 + 1));
4538                 break;
4539 
4540         case RT5677_GPIO6:
4541                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4542                         RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4543                         RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4544                 break;
4545 
4546         default:
4547                 break;
4548         }
4549 
4550         return 0;
4551 }
4552 
4553 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4554 {
4555         struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4556         int value, ret;
4557 
4558         ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4559         if (ret < 0)
4560                 return ret;
4561 
4562         return (value & (0x1 << offset)) >> offset;
4563 }
4564 
4565 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4566 {
4567         struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4568 
4569         switch (offset) {
4570         case RT5677_GPIO1 ... RT5677_GPIO5:
4571                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4572                         0x1 << (offset * 3 + 2), 0x0);
4573                 break;
4574 
4575         case RT5677_GPIO6:
4576                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4577                         RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4578                 break;
4579 
4580         default:
4581                 break;
4582         }
4583 
4584         return 0;
4585 }
4586 
4587 /** Configures the gpio as
4588  *   0 - floating
4589  *   1 - pull down
4590  *   2 - pull up
4591  */
4592 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4593                 int value)
4594 {
4595         int shift;
4596 
4597         switch (offset) {
4598         case RT5677_GPIO1 ... RT5677_GPIO2:
4599                 shift = 2 * (1 - offset);
4600                 regmap_update_bits(rt5677->regmap,
4601                         RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4602                         0x3 << shift,
4603                         (value & 0x3) << shift);
4604                 break;
4605 
4606         case RT5677_GPIO3 ... RT5677_GPIO6:
4607                 shift = 2 * (9 - offset);
4608                 regmap_update_bits(rt5677->regmap,
4609                         RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4610                         0x3 << shift,
4611                         (value & 0x3) << shift);
4612                 break;
4613 
4614         default:
4615                 break;
4616         }
4617 }
4618 
4619 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4620 {
4621         struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4622         struct regmap_irq_chip_data *data = rt5677->irq_data;
4623         int irq;
4624 
4625         if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4626                 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4627                         (rt5677->pdata.jd1_gpio == 2 &&
4628                                 offset == RT5677_GPIO2) ||
4629                         (rt5677->pdata.jd1_gpio == 3 &&
4630                                 offset == RT5677_GPIO3)) {
4631                         irq = RT5677_IRQ_JD1;
4632                 } else {
4633                         return -ENXIO;
4634                 }
4635         }
4636 
4637         if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4638                 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4639                         (rt5677->pdata.jd2_gpio == 2 &&
4640                                 offset == RT5677_GPIO5) ||
4641                         (rt5677->pdata.jd2_gpio == 3 &&
4642                                 offset == RT5677_GPIO6)) {
4643                         irq = RT5677_IRQ_JD2;
4644                 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4645                                 offset == RT5677_GPIO4) ||
4646                         (rt5677->pdata.jd3_gpio == 2 &&
4647                                 offset == RT5677_GPIO5) ||
4648                         (rt5677->pdata.jd3_gpio == 3 &&
4649                                 offset == RT5677_GPIO6)) {
4650                         irq = RT5677_IRQ_JD3;
4651                 } else {
4652                         return -ENXIO;
4653                 }
4654         }
4655 
4656         return regmap_irq_get_virq(data, irq);
4657 }
4658 
4659 static struct gpio_chip rt5677_template_chip = {
4660         .label                  = "rt5677",
4661         .owner                  = THIS_MODULE,
4662         .direction_output       = rt5677_gpio_direction_out,
4663         .set                    = rt5677_gpio_set,
4664         .direction_input        = rt5677_gpio_direction_in,
4665         .get                    = rt5677_gpio_get,
4666         .to_irq                 = rt5677_to_irq,
4667         .can_sleep              = 1,
4668 };
4669 
4670 static void rt5677_init_gpio(struct i2c_client *i2c)
4671 {
4672         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4673         int ret;
4674 
4675         rt5677->gpio_chip = rt5677_template_chip;
4676         rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4677         rt5677->gpio_chip.dev = &i2c->dev;
4678         rt5677->gpio_chip.base = -1;
4679 
4680         ret = gpiochip_add(&rt5677->gpio_chip);
4681         if (ret != 0)
4682                 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4683 }
4684 
4685 static void rt5677_free_gpio(struct i2c_client *i2c)
4686 {
4687         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4688 
4689         gpiochip_remove(&rt5677->gpio_chip);
4690 }
4691 #else
4692 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4693                 int value)
4694 {
4695 }
4696 
4697 static void rt5677_init_gpio(struct i2c_client *i2c)
4698 {
4699 }
4700 
4701 static void rt5677_free_gpio(struct i2c_client *i2c)
4702 {
4703 }
4704 #endif
4705 
4706 static int rt5677_probe(struct snd_soc_codec *codec)
4707 {
4708         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4709         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4710         int i;
4711 
4712         rt5677->codec = codec;
4713 
4714         if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4715                 snd_soc_dapm_add_routes(dapm,
4716                         rt5677_dmic2_clk_2,
4717                         ARRAY_SIZE(rt5677_dmic2_clk_2));
4718         } else { /*use dmic1 clock by default*/
4719                 snd_soc_dapm_add_routes(dapm,
4720                         rt5677_dmic2_clk_1,
4721                         ARRAY_SIZE(rt5677_dmic2_clk_1));
4722         }
4723 
4724         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4725 
4726         regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4727         regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4728 
4729         for (i = 0; i < RT5677_GPIO_NUM; i++)
4730                 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4731 
4732         if (rt5677->irq_data) {
4733                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4734                         0x8000);
4735                 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4736                         0x0008);
4737 
4738                 if (rt5677->pdata.jd1_gpio)
4739                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4740                                 RT5677_SEL_GPIO_JD1_MASK,
4741                                 rt5677->pdata.jd1_gpio <<
4742                                 RT5677_SEL_GPIO_JD1_SFT);
4743 
4744                 if (rt5677->pdata.jd2_gpio)
4745                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4746                                 RT5677_SEL_GPIO_JD2_MASK,
4747                                 rt5677->pdata.jd2_gpio <<
4748                                 RT5677_SEL_GPIO_JD2_SFT);
4749 
4750                 if (rt5677->pdata.jd3_gpio)
4751                         regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4752                                 RT5677_SEL_GPIO_JD3_MASK,
4753                                 rt5677->pdata.jd3_gpio <<
4754                                 RT5677_SEL_GPIO_JD3_SFT);
4755         }
4756 
4757         mutex_init(&rt5677->dsp_cmd_lock);
4758         mutex_init(&rt5677->dsp_pri_lock);
4759 
4760         return 0;
4761 }
4762 
4763 static int rt5677_remove(struct snd_soc_codec *codec)
4764 {
4765         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4766 
4767         regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4768         gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4769         gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4770 
4771         return 0;
4772 }
4773 
4774 #ifdef CONFIG_PM
4775 static int rt5677_suspend(struct snd_soc_codec *codec)
4776 {
4777         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4778 
4779         if (!rt5677->dsp_vad_en) {
4780                 regcache_cache_only(rt5677->regmap, true);
4781                 regcache_mark_dirty(rt5677->regmap);
4782 
4783                 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4784                 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4785         }
4786 
4787         return 0;
4788 }
4789 
4790 static int rt5677_resume(struct snd_soc_codec *codec)
4791 {
4792         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4793 
4794         if (!rt5677->dsp_vad_en) {
4795                 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4796                 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4797                 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4798                         msleep(10);
4799 
4800                 regcache_cache_only(rt5677->regmap, false);
4801                 regcache_sync(rt5677->regmap);
4802         }
4803 
4804         return 0;
4805 }
4806 #else
4807 #define rt5677_suspend NULL
4808 #define rt5677_resume NULL
4809 #endif
4810 
4811 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4812 {
4813         struct i2c_client *client = context;
4814         struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4815 
4816         if (rt5677->is_dsp_mode) {
4817                 if (reg > 0xff) {
4818                         mutex_lock(&rt5677->dsp_pri_lock);
4819                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4820                                 reg & 0xff);
4821                         rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4822                         mutex_unlock(&rt5677->dsp_pri_lock);
4823                 } else {
4824                         rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4825                 }
4826         } else {
4827                 regmap_read(rt5677->regmap_physical, reg, val);
4828         }
4829 
4830         return 0;
4831 }
4832 
4833 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4834 {
4835         struct i2c_client *client = context;
4836         struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4837 
4838         if (rt5677->is_dsp_mode) {
4839                 if (reg > 0xff) {
4840                         mutex_lock(&rt5677->dsp_pri_lock);
4841                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4842                                 reg & 0xff);
4843                         rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4844                                 val);
4845                         mutex_unlock(&rt5677->dsp_pri_lock);
4846                 } else {
4847                         rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4848                 }
4849         } else {
4850                 regmap_write(rt5677->regmap_physical, reg, val);
4851         }
4852 
4853         return 0;
4854 }
4855 
4856 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4857 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4858                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4859 
4860 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4861         .hw_params = rt5677_hw_params,
4862         .set_fmt = rt5677_set_dai_fmt,
4863         .set_sysclk = rt5677_set_dai_sysclk,
4864         .set_pll = rt5677_set_dai_pll,
4865         .set_tdm_slot = rt5677_set_tdm_slot,
4866 };
4867 
4868 static struct snd_soc_dai_driver rt5677_dai[] = {
4869         {
4870                 .name = "rt5677-aif1",
4871                 .id = RT5677_AIF1,
4872                 .playback = {
4873                         .stream_name = "AIF1 Playback",
4874                         .channels_min = 1,
4875                         .channels_max = 2,
4876                         .rates = RT5677_STEREO_RATES,
4877                         .formats = RT5677_FORMATS,
4878                 },
4879                 .capture = {
4880                         .stream_name = "AIF1 Capture",
4881                         .channels_min = 1,
4882                         .channels_max = 2,
4883                         .rates = RT5677_STEREO_RATES,
4884                         .formats = RT5677_FORMATS,
4885                 },
4886                 .ops = &rt5677_aif_dai_ops,
4887         },
4888         {
4889                 .name = "rt5677-aif2",
4890                 .id = RT5677_AIF2,
4891                 .playback = {
4892                         .stream_name = "AIF2 Playback",
4893                         .channels_min = 1,
4894                         .channels_max = 2,
4895                         .rates = RT5677_STEREO_RATES,
4896                         .formats = RT5677_FORMATS,
4897                 },
4898                 .capture = {
4899                         .stream_name = "AIF2 Capture",
4900                         .channels_min = 1,
4901                         .channels_max = 2,
4902                         .rates = RT5677_STEREO_RATES,
4903                         .formats = RT5677_FORMATS,
4904                 },
4905                 .ops = &rt5677_aif_dai_ops,
4906         },
4907         {
4908                 .name = "rt5677-aif3",
4909                 .id = RT5677_AIF3,
4910                 .playback = {
4911                         .stream_name = "AIF3 Playback",
4912                         .channels_min = 1,
4913                         .channels_max = 2,
4914                         .rates = RT5677_STEREO_RATES,
4915                         .formats = RT5677_FORMATS,
4916                 },
4917                 .capture = {
4918                         .stream_name = "AIF3 Capture",
4919                         .channels_min = 1,
4920                         .channels_max = 2,
4921                         .rates = RT5677_STEREO_RATES,
4922                         .formats = RT5677_FORMATS,
4923                 },
4924                 .ops = &rt5677_aif_dai_ops,
4925         },
4926         {
4927                 .name = "rt5677-aif4",
4928                 .id = RT5677_AIF4,
4929                 .playback = {
4930                         .stream_name = "AIF4 Playback",
4931                         .channels_min = 1,
4932                         .channels_max = 2,
4933                         .rates = RT5677_STEREO_RATES,
4934                         .formats = RT5677_FORMATS,
4935                 },
4936                 .capture = {
4937                         .stream_name = "AIF4 Capture",
4938                         .channels_min = 1,
4939                         .channels_max = 2,
4940                         .rates = RT5677_STEREO_RATES,
4941                         .formats = RT5677_FORMATS,
4942                 },
4943                 .ops = &rt5677_aif_dai_ops,
4944         },
4945         {
4946                 .name = "rt5677-slimbus",
4947                 .id = RT5677_AIF5,
4948                 .playback = {
4949                         .stream_name = "SLIMBus Playback",
4950                         .channels_min = 1,
4951                         .channels_max = 2,
4952                         .rates = RT5677_STEREO_RATES,
4953                         .formats = RT5677_FORMATS,
4954                 },
4955                 .capture = {
4956                         .stream_name = "SLIMBus Capture",
4957                         .channels_min = 1,
4958                         .channels_max = 2,
4959                         .rates = RT5677_STEREO_RATES,
4960                         .formats = RT5677_FORMATS,
4961                 },
4962                 .ops = &rt5677_aif_dai_ops,
4963         },
4964 };
4965 
4966 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4967         .probe = rt5677_probe,
4968         .remove = rt5677_remove,
4969         .suspend = rt5677_suspend,
4970         .resume = rt5677_resume,
4971         .set_bias_level = rt5677_set_bias_level,
4972         .idle_bias_off = true,
4973         .controls = rt5677_snd_controls,
4974         .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4975         .dapm_widgets = rt5677_dapm_widgets,
4976         .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4977         .dapm_routes = rt5677_dapm_routes,
4978         .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4979 };
4980 
4981 static const struct regmap_config rt5677_regmap_physical = {
4982         .name = "physical",
4983         .reg_bits = 8,
4984         .val_bits = 16,
4985 
4986         .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4987                                                 RT5677_PR_SPACING),
4988         .readable_reg = rt5677_readable_register,
4989 
4990         .cache_type = REGCACHE_NONE,
4991         .ranges = rt5677_ranges,
4992         .num_ranges = ARRAY_SIZE(rt5677_ranges),
4993 };
4994 
4995 static const struct regmap_config rt5677_regmap = {
4996         .reg_bits = 8,
4997         .val_bits = 16,
4998 
4999         .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5000                                                 RT5677_PR_SPACING),
5001 
5002         .volatile_reg = rt5677_volatile_register,
5003         .readable_reg = rt5677_readable_register,
5004         .reg_read = rt5677_read,
5005         .reg_write = rt5677_write,
5006 
5007         .cache_type = REGCACHE_RBTREE,
5008         .reg_defaults = rt5677_reg,
5009         .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5010         .ranges = rt5677_ranges,
5011         .num_ranges = ARRAY_SIZE(rt5677_ranges),
5012 };
5013 
5014 static const struct i2c_device_id rt5677_i2c_id[] = {
5015         { "rt5677", RT5677 },
5016         { "rt5676", RT5676 },
5017         { }
5018 };
5019 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5020 
5021 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5022                 struct device *dev)
5023 {
5024         rt5677->pdata.in1_diff = device_property_read_bool(dev,
5025                         "realtek,in1-differential");
5026         rt5677->pdata.in2_diff = device_property_read_bool(dev,
5027                         "realtek,in2-differential");
5028         rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5029                         "realtek,lout1-differential");
5030         rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5031                         "realtek,lout2-differential");
5032         rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5033                         "realtek,lout3-differential");
5034 
5035         device_property_read_u8_array(dev, "realtek,gpio-config",
5036                         rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5037 
5038         device_property_read_u32(dev, "realtek,jd1-gpio",
5039                         &rt5677->pdata.jd1_gpio);
5040         device_property_read_u32(dev, "realtek,jd2-gpio",
5041                         &rt5677->pdata.jd2_gpio);
5042         device_property_read_u32(dev, "realtek,jd3-gpio",
5043                         &rt5677->pdata.jd3_gpio);
5044 }
5045 
5046 static struct regmap_irq rt5677_irqs[] = {
5047         [RT5677_IRQ_JD1] = {
5048                 .reg_offset = 0,
5049                 .mask = RT5677_EN_IRQ_GPIO_JD1,
5050         },
5051         [RT5677_IRQ_JD2] = {
5052                 .reg_offset = 0,
5053                 .mask = RT5677_EN_IRQ_GPIO_JD2,
5054         },
5055         [RT5677_IRQ_JD3] = {
5056                 .reg_offset = 0,
5057                 .mask = RT5677_EN_IRQ_GPIO_JD3,
5058         },
5059 };
5060 
5061 static struct regmap_irq_chip rt5677_irq_chip = {
5062         .name = "rt5677",
5063         .irqs = rt5677_irqs,
5064         .num_irqs = ARRAY_SIZE(rt5677_irqs),
5065 
5066         .num_regs = 1,
5067         .status_base = RT5677_IRQ_CTRL1,
5068         .mask_base = RT5677_IRQ_CTRL1,
5069         .mask_invert = 1,
5070 };
5071 
5072 static int rt5677_init_irq(struct i2c_client *i2c)
5073 {
5074         int ret;
5075         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5076 
5077         if (!rt5677->pdata.jd1_gpio &&
5078                 !rt5677->pdata.jd2_gpio &&
5079                 !rt5677->pdata.jd3_gpio)
5080                 return 0;
5081 
5082         if (!i2c->irq) {
5083                 dev_err(&i2c->dev, "No interrupt specified\n");
5084                 return -EINVAL;
5085         }
5086 
5087         ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5088                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5089                 &rt5677_irq_chip, &rt5677->irq_data);
5090 
5091         if (ret != 0) {
5092                 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5093                 return ret;
5094         }
5095 
5096         return 0;
5097 }
5098 
5099 static void rt5677_free_irq(struct i2c_client *i2c)
5100 {
5101         struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5102 
5103         if (rt5677->irq_data)
5104                 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5105 }
5106 
5107 static int rt5677_i2c_probe(struct i2c_client *i2c,
5108                     const struct i2c_device_id *id)
5109 {
5110         struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5111         struct rt5677_priv *rt5677;
5112         int ret;
5113         unsigned int val;
5114 
5115         rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5116                                 GFP_KERNEL);
5117         if (rt5677 == NULL)
5118                 return -ENOMEM;
5119 
5120         i2c_set_clientdata(i2c, rt5677);
5121 
5122         rt5677->type = id->driver_data;
5123 
5124         if (pdata)
5125                 rt5677->pdata = *pdata;
5126         else
5127                 rt5677_read_device_properties(rt5677, &i2c->dev);
5128 
5129         /* pow-ldo2 and reset are optional. The codec pins may be statically
5130          * connected on the board without gpios. If the gpio device property
5131          * isn't specified, devm_gpiod_get_optional returns NULL.
5132          */
5133         rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5134                         "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5135         if (IS_ERR(rt5677->pow_ldo2)) {
5136                 ret = PTR_ERR(rt5677->pow_ldo2);
5137                 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5138                 return ret;
5139         }
5140         rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5141                         "realtek,reset", GPIOD_OUT_HIGH);
5142         if (IS_ERR(rt5677->reset_pin)) {
5143                 ret = PTR_ERR(rt5677->reset_pin);
5144                 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5145                 return ret;
5146         }
5147 
5148         if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5149                 /* Wait a while until I2C bus becomes available. The datasheet
5150                  * does not specify the exact we should wait but startup
5151                  * sequence mentiones at least a few milliseconds.
5152                  */
5153                 msleep(10);
5154         }
5155 
5156         rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5157                                         &rt5677_regmap_physical);
5158         if (IS_ERR(rt5677->regmap_physical)) {
5159                 ret = PTR_ERR(rt5677->regmap_physical);
5160                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5161                         ret);
5162                 return ret;
5163         }
5164 
5165         rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5166         if (IS_ERR(rt5677->regmap)) {
5167                 ret = PTR_ERR(rt5677->regmap);
5168                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5169                         ret);
5170                 return ret;
5171         }
5172 
5173         regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5174         if (val != RT5677_DEVICE_ID) {
5175                 dev_err(&i2c->dev,
5176                         "Device with ID register %#x is not rt5677\n", val);
5177                 return -ENODEV;
5178         }
5179 
5180         regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5181 
5182         ret = regmap_register_patch(rt5677->regmap, init_list,
5183                                     ARRAY_SIZE(init_list));
5184         if (ret != 0)
5185                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5186 
5187         if (rt5677->pdata.in1_diff)
5188                 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5189                                         RT5677_IN_DF1, RT5677_IN_DF1);
5190 
5191         if (rt5677->pdata.in2_diff)
5192                 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5193                                         RT5677_IN_DF2, RT5677_IN_DF2);
5194 
5195         if (rt5677->pdata.lout1_diff)
5196                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5197                                         RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5198 
5199         if (rt5677->pdata.lout2_diff)
5200                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5201                                         RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5202 
5203         if (rt5677->pdata.lout3_diff)
5204                 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5205                                         RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5206 
5207         if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5208                 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5209                                         RT5677_GPIO5_FUNC_MASK,
5210                                         RT5677_GPIO5_FUNC_DMIC);
5211                 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5212                                         RT5677_GPIO5_DIR_MASK,
5213                                         RT5677_GPIO5_DIR_OUT);
5214         }
5215 
5216         if (rt5677->pdata.micbias1_vdd_3v3)
5217                 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5218                         RT5677_MICBIAS1_CTRL_VDD_MASK,
5219                         RT5677_MICBIAS1_CTRL_VDD_3_3V);
5220 
5221         rt5677_init_gpio(i2c);
5222         rt5677_init_irq(i2c);
5223 
5224         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5225                                       rt5677_dai, ARRAY_SIZE(rt5677_dai));
5226 }
5227 
5228 static int rt5677_i2c_remove(struct i2c_client *i2c)
5229 {
5230         snd_soc_unregister_codec(&i2c->dev);
5231         rt5677_free_irq(i2c);
5232         rt5677_free_gpio(i2c);
5233 
5234         return 0;
5235 }
5236 
5237 static struct i2c_driver rt5677_i2c_driver = {
5238         .driver = {
5239                 .name = "rt5677",
5240         },
5241         .probe = rt5677_i2c_probe,
5242         .remove   = rt5677_i2c_remove,
5243         .id_table = rt5677_i2c_id,
5244 };
5245 module_i2c_driver(rt5677_i2c_driver);
5246 
5247 MODULE_DESCRIPTION("ASoC RT5677 driver");
5248 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5249 MODULE_LICENSE("GPL v2");
5250 

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