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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/rt5677.h

Version: ~ [ linux-5.18-rc6 ] ~ [ linux-5.17.6 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.38 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.114 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.192 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.241 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.277 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.312 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * rt5677.h  --  RT5677 ALSA SoC audio driver
  3  *
  4  * Copyright 2013 Realtek Semiconductor Corp.
  5  * Author: Oder Chiou <oder_chiou@realtek.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 
 12 #ifndef __RT5677_H__
 13 #define __RT5677_H__
 14 
 15 #include <sound/rt5677.h>
 16 #include <linux/gpio/driver.h>
 17 #include <linux/gpio/consumer.h>
 18 
 19 /* Info */
 20 #define RT5677_RESET                            0x00
 21 #define RT5677_VENDOR_ID                        0xfd
 22 #define RT5677_VENDOR_ID1                       0xfe
 23 #define RT5677_VENDOR_ID2                       0xff
 24 /*  I/O - Output */
 25 #define RT5677_LOUT1                            0x01
 26 /* I/O - Input */
 27 #define RT5677_IN1                              0x03
 28 #define RT5677_MICBIAS                          0x04
 29 /* I/O - SLIMBus */
 30 #define RT5677_SLIMBUS_PARAM                    0x07
 31 #define RT5677_SLIMBUS_RX                       0x08
 32 #define RT5677_SLIMBUS_CTRL                     0x09
 33 /* I/O */
 34 #define RT5677_SIDETONE_CTRL                    0x13
 35 /* I/O - ADC/DAC */
 36 #define RT5677_ANA_DAC1_2_3_SRC                 0x15
 37 #define RT5677_IF_DSP_DAC3_4_MIXER              0x16
 38 #define RT5677_DAC4_DIG_VOL                     0x17
 39 #define RT5677_DAC3_DIG_VOL                     0x18
 40 #define RT5677_DAC1_DIG_VOL                     0x19
 41 #define RT5677_DAC2_DIG_VOL                     0x1a
 42 #define RT5677_IF_DSP_DAC2_MIXER                0x1b
 43 #define RT5677_STO1_ADC_DIG_VOL                 0x1c
 44 #define RT5677_MONO_ADC_DIG_VOL                 0x1d
 45 #define RT5677_STO1_2_ADC_BST                   0x1e
 46 #define RT5677_STO2_ADC_DIG_VOL                 0x1f
 47 /* Mixer - D-D */
 48 #define RT5677_ADC_BST_CTRL2                    0x20
 49 #define RT5677_STO3_4_ADC_BST                   0x21
 50 #define RT5677_STO3_ADC_DIG_VOL                 0x22
 51 #define RT5677_STO4_ADC_DIG_VOL                 0x23
 52 #define RT5677_STO4_ADC_MIXER                   0x24
 53 #define RT5677_STO3_ADC_MIXER                   0x25
 54 #define RT5677_STO2_ADC_MIXER                   0x26
 55 #define RT5677_STO1_ADC_MIXER                   0x27
 56 #define RT5677_MONO_ADC_MIXER                   0x28
 57 #define RT5677_ADC_IF_DSP_DAC1_MIXER            0x29
 58 #define RT5677_STO1_DAC_MIXER                   0x2a
 59 #define RT5677_MONO_DAC_MIXER                   0x2b
 60 #define RT5677_DD1_MIXER                        0x2c
 61 #define RT5677_DD2_MIXER                        0x2d
 62 #define RT5677_IF3_DATA                         0x2f
 63 #define RT5677_IF4_DATA                         0x30
 64 /* Mixer - PDM */
 65 #define RT5677_PDM_OUT_CTRL                     0x31
 66 #define RT5677_PDM_DATA_CTRL1                   0x32
 67 #define RT5677_PDM_DATA_CTRL2                   0x33
 68 #define RT5677_PDM1_DATA_CTRL2                  0x34
 69 #define RT5677_PDM1_DATA_CTRL3                  0x35
 70 #define RT5677_PDM1_DATA_CTRL4                  0x36
 71 #define RT5677_PDM2_DATA_CTRL2                  0x37
 72 #define RT5677_PDM2_DATA_CTRL3                  0x38
 73 #define RT5677_PDM2_DATA_CTRL4                  0x39
 74 /* TDM */
 75 #define RT5677_TDM1_CTRL1                       0x3b
 76 #define RT5677_TDM1_CTRL2                       0x3c
 77 #define RT5677_TDM1_CTRL3                       0x3d
 78 #define RT5677_TDM1_CTRL4                       0x3e
 79 #define RT5677_TDM1_CTRL5                       0x3f
 80 #define RT5677_TDM2_CTRL1                       0x40
 81 #define RT5677_TDM2_CTRL2                       0x41
 82 #define RT5677_TDM2_CTRL3                       0x42
 83 #define RT5677_TDM2_CTRL4                       0x43
 84 #define RT5677_TDM2_CTRL5                       0x44
 85 /* I2C_MASTER_CTRL */
 86 #define RT5677_I2C_MASTER_CTRL1                 0x47
 87 #define RT5677_I2C_MASTER_CTRL2                 0x48
 88 #define RT5677_I2C_MASTER_CTRL3                 0x49
 89 #define RT5677_I2C_MASTER_CTRL4                 0x4a
 90 #define RT5677_I2C_MASTER_CTRL5                 0x4b
 91 #define RT5677_I2C_MASTER_CTRL6                 0x4c
 92 #define RT5677_I2C_MASTER_CTRL7                 0x4d
 93 #define RT5677_I2C_MASTER_CTRL8                 0x4e
 94 /* DMIC */
 95 #define RT5677_DMIC_CTRL1                       0x50
 96 #define RT5677_DMIC_CTRL2                       0x51
 97 /* Haptic Generator */
 98 #define RT5677_HAP_GENE_CTRL1                   0x56
 99 #define RT5677_HAP_GENE_CTRL2                   0x57
100 #define RT5677_HAP_GENE_CTRL3                   0x58
101 #define RT5677_HAP_GENE_CTRL4                   0x59
102 #define RT5677_HAP_GENE_CTRL5                   0x5a
103 #define RT5677_HAP_GENE_CTRL6                   0x5b
104 #define RT5677_HAP_GENE_CTRL7                   0x5c
105 #define RT5677_HAP_GENE_CTRL8                   0x5d
106 #define RT5677_HAP_GENE_CTRL9                   0x5e
107 #define RT5677_HAP_GENE_CTRL10                  0x5f
108 /* Power */
109 #define RT5677_PWR_DIG1                         0x61
110 #define RT5677_PWR_DIG2                         0x62
111 #define RT5677_PWR_ANLG1                        0x63
112 #define RT5677_PWR_ANLG2                        0x64
113 #define RT5677_PWR_DSP1                         0x65
114 #define RT5677_PWR_DSP_ST                       0x66
115 #define RT5677_PWR_DSP2                         0x67
116 #define RT5677_ADC_DAC_HPF_CTRL1                0x68
117 /* Private Register Control */
118 #define RT5677_PRIV_INDEX                       0x6a
119 #define RT5677_PRIV_DATA                        0x6c
120 /* Format - ADC/DAC */
121 #define RT5677_I2S4_SDP                         0x6f
122 #define RT5677_I2S1_SDP                         0x70
123 #define RT5677_I2S2_SDP                         0x71
124 #define RT5677_I2S3_SDP                         0x72
125 #define RT5677_CLK_TREE_CTRL1                   0x73
126 #define RT5677_CLK_TREE_CTRL2                   0x74
127 #define RT5677_CLK_TREE_CTRL3                   0x75
128 /* Function - Analog */
129 #define RT5677_PLL1_CTRL1                       0x7a
130 #define RT5677_PLL1_CTRL2                       0x7b
131 #define RT5677_PLL2_CTRL1                       0x7c
132 #define RT5677_PLL2_CTRL2                       0x7d
133 #define RT5677_GLB_CLK1                         0x80
134 #define RT5677_GLB_CLK2                         0x81
135 #define RT5677_ASRC_1                           0x83
136 #define RT5677_ASRC_2                           0x84
137 #define RT5677_ASRC_3                           0x85
138 #define RT5677_ASRC_4                           0x86
139 #define RT5677_ASRC_5                           0x87
140 #define RT5677_ASRC_6                           0x88
141 #define RT5677_ASRC_7                           0x89
142 #define RT5677_ASRC_8                           0x8a
143 #define RT5677_ASRC_9                           0x8b
144 #define RT5677_ASRC_10                          0x8c
145 #define RT5677_ASRC_11                          0x8d
146 #define RT5677_ASRC_12                          0x8e
147 #define RT5677_ASRC_13                          0x8f
148 #define RT5677_ASRC_14                          0x90
149 #define RT5677_ASRC_15                          0x91
150 #define RT5677_ASRC_16                          0x92
151 #define RT5677_ASRC_17                          0x93
152 #define RT5677_ASRC_18                          0x94
153 #define RT5677_ASRC_19                          0x95
154 #define RT5677_ASRC_20                          0x97
155 #define RT5677_ASRC_21                          0x98
156 #define RT5677_ASRC_22                          0x99
157 #define RT5677_ASRC_23                          0x9a
158 #define RT5677_VAD_CTRL1                        0x9c
159 #define RT5677_VAD_CTRL2                        0x9d
160 #define RT5677_VAD_CTRL3                        0x9e
161 #define RT5677_VAD_CTRL4                        0x9f
162 #define RT5677_VAD_CTRL5                        0xa0
163 /* Function - Digital */
164 #define RT5677_DSP_INB_CTRL1                    0xa3
165 #define RT5677_DSP_INB_CTRL2                    0xa4
166 #define RT5677_DSP_IN_OUTB_CTRL                 0xa5
167 #define RT5677_DSP_OUTB0_1_DIG_VOL              0xa6
168 #define RT5677_DSP_OUTB2_3_DIG_VOL              0xa7
169 #define RT5677_DSP_OUTB4_5_DIG_VOL              0xa8
170 #define RT5677_DSP_OUTB6_7_DIG_VOL              0xa9
171 #define RT5677_ADC_EQ_CTRL1                     0xae
172 #define RT5677_ADC_EQ_CTRL2                     0xaf
173 #define RT5677_EQ_CTRL1                         0xb0
174 #define RT5677_EQ_CTRL2                         0xb1
175 #define RT5677_EQ_CTRL3                         0xb2
176 #define RT5677_SOFT_VOL_ZERO_CROSS1             0xb3
177 #define RT5677_JD_CTRL1                         0xb5
178 #define RT5677_JD_CTRL2                         0xb6
179 #define RT5677_JD_CTRL3                         0xb8
180 #define RT5677_IRQ_CTRL1                        0xbd
181 #define RT5677_IRQ_CTRL2                        0xbe
182 #define RT5677_GPIO_ST                          0xbf
183 #define RT5677_GPIO_CTRL1                       0xc0
184 #define RT5677_GPIO_CTRL2                       0xc1
185 #define RT5677_GPIO_CTRL3                       0xc2
186 #define RT5677_STO1_ADC_HI_FILTER1              0xc5
187 #define RT5677_STO1_ADC_HI_FILTER2              0xc6
188 #define RT5677_MONO_ADC_HI_FILTER1              0xc7
189 #define RT5677_MONO_ADC_HI_FILTER2              0xc8
190 #define RT5677_STO2_ADC_HI_FILTER1              0xc9
191 #define RT5677_STO2_ADC_HI_FILTER2              0xca
192 #define RT5677_STO3_ADC_HI_FILTER1              0xcb
193 #define RT5677_STO3_ADC_HI_FILTER2              0xcc
194 #define RT5677_STO4_ADC_HI_FILTER1              0xcd
195 #define RT5677_STO4_ADC_HI_FILTER2              0xce
196 #define RT5677_MB_DRC_CTRL1                     0xd0
197 #define RT5677_DRC1_CTRL1                       0xd2
198 #define RT5677_DRC1_CTRL2                       0xd3
199 #define RT5677_DRC1_CTRL3                       0xd4
200 #define RT5677_DRC1_CTRL4                       0xd5
201 #define RT5677_DRC1_CTRL5                       0xd6
202 #define RT5677_DRC1_CTRL6                       0xd7
203 #define RT5677_DRC2_CTRL1                       0xd8
204 #define RT5677_DRC2_CTRL2                       0xd9
205 #define RT5677_DRC2_CTRL3                       0xda
206 #define RT5677_DRC2_CTRL4                       0xdb
207 #define RT5677_DRC2_CTRL5                       0xdc
208 #define RT5677_DRC2_CTRL6                       0xdd
209 #define RT5677_DRC1_HL_CTRL1                    0xde
210 #define RT5677_DRC1_HL_CTRL2                    0xdf
211 #define RT5677_DRC2_HL_CTRL1                    0xe0
212 #define RT5677_DRC2_HL_CTRL2                    0xe1
213 #define RT5677_DSP_INB1_SRC_CTRL1               0xe3
214 #define RT5677_DSP_INB1_SRC_CTRL2               0xe4
215 #define RT5677_DSP_INB1_SRC_CTRL3               0xe5
216 #define RT5677_DSP_INB1_SRC_CTRL4               0xe6
217 #define RT5677_DSP_INB2_SRC_CTRL1               0xe7
218 #define RT5677_DSP_INB2_SRC_CTRL2               0xe8
219 #define RT5677_DSP_INB2_SRC_CTRL3               0xe9
220 #define RT5677_DSP_INB2_SRC_CTRL4               0xea
221 #define RT5677_DSP_INB3_SRC_CTRL1               0xeb
222 #define RT5677_DSP_INB3_SRC_CTRL2               0xec
223 #define RT5677_DSP_INB3_SRC_CTRL3               0xed
224 #define RT5677_DSP_INB3_SRC_CTRL4               0xee
225 #define RT5677_DSP_OUTB1_SRC_CTRL1              0xef
226 #define RT5677_DSP_OUTB1_SRC_CTRL2              0xf0
227 #define RT5677_DSP_OUTB1_SRC_CTRL3              0xf1
228 #define RT5677_DSP_OUTB1_SRC_CTRL4              0xf2
229 #define RT5677_DSP_OUTB2_SRC_CTRL1              0xf3
230 #define RT5677_DSP_OUTB2_SRC_CTRL2              0xf4
231 #define RT5677_DSP_OUTB2_SRC_CTRL3              0xf5
232 #define RT5677_DSP_OUTB2_SRC_CTRL4              0xf6
233 
234 /* Virtual DSP Mixer Control */
235 #define RT5677_DSP_OUTB_0123_MIXER_CTRL         0xf7
236 #define RT5677_DSP_OUTB_45_MIXER_CTRL           0xf8
237 #define RT5677_DSP_OUTB_67_MIXER_CTRL           0xf9
238 
239 /* General Control */
240 #define RT5677_DIG_MISC                         0xfa
241 #define RT5677_GEN_CTRL1                        0xfb
242 #define RT5677_GEN_CTRL2                        0xfc
243 
244 /* DSP Mode I2C Control*/
245 #define RT5677_DSP_I2C_OP_CODE                  0x00
246 #define RT5677_DSP_I2C_ADDR_LSB                 0x01
247 #define RT5677_DSP_I2C_ADDR_MSB                 0x02
248 #define RT5677_DSP_I2C_DATA_LSB                 0x03
249 #define RT5677_DSP_I2C_DATA_MSB                 0x04
250 
251 /* Index of Codec Private Register definition */
252 #define RT5677_PR_DRC1_CTRL_1                   0x01
253 #define RT5677_PR_DRC1_CTRL_2                   0x02
254 #define RT5677_PR_DRC1_CTRL_3                   0x03
255 #define RT5677_PR_DRC1_CTRL_4                   0x04
256 #define RT5677_PR_DRC1_CTRL_5                   0x05
257 #define RT5677_PR_DRC1_CTRL_6                   0x06
258 #define RT5677_PR_DRC1_CTRL_7                   0x07
259 #define RT5677_PR_DRC2_CTRL_1                   0x08
260 #define RT5677_PR_DRC2_CTRL_2                   0x09
261 #define RT5677_PR_DRC2_CTRL_3                   0x0a
262 #define RT5677_PR_DRC2_CTRL_4                   0x0b
263 #define RT5677_PR_DRC2_CTRL_5                   0x0c
264 #define RT5677_PR_DRC2_CTRL_6                   0x0d
265 #define RT5677_PR_DRC2_CTRL_7                   0x0e
266 #define RT5677_BIAS_CUR1                        0x10
267 #define RT5677_BIAS_CUR2                        0x12
268 #define RT5677_BIAS_CUR3                        0x13
269 #define RT5677_BIAS_CUR4                        0x14
270 #define RT5677_BIAS_CUR5                        0x15
271 #define RT5677_VREF_LOUT_CTRL                   0x17
272 #define RT5677_DIG_VOL_CTRL1                    0x1a
273 #define RT5677_DIG_VOL_CTRL2                    0x1b
274 #define RT5677_ANA_ADC_GAIN_CTRL                0x1e
275 #define RT5677_VAD_SRAM_TEST1                   0x20
276 #define RT5677_VAD_SRAM_TEST2                   0x21
277 #define RT5677_VAD_SRAM_TEST3                   0x22
278 #define RT5677_VAD_SRAM_TEST4                   0x23
279 #define RT5677_PAD_DRV_CTRL                     0x26
280 #define RT5677_DIG_IN_PIN_ST_CTRL1              0x29
281 #define RT5677_DIG_IN_PIN_ST_CTRL2              0x2a
282 #define RT5677_DIG_IN_PIN_ST_CTRL3              0x2b
283 #define RT5677_PLL1_INT                         0x38
284 #define RT5677_PLL2_INT                         0x39
285 #define RT5677_TEST_CTRL1                       0x3a
286 #define RT5677_TEST_CTRL2                       0x3b
287 #define RT5677_TEST_CTRL3                       0x3c
288 #define RT5677_CHOP_DAC_ADC                     0x3d
289 #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL          0x3e
290 #define RT5677_CROSS_OVER_FILTER1               0x90
291 #define RT5677_CROSS_OVER_FILTER2               0x91
292 #define RT5677_CROSS_OVER_FILTER3               0x92
293 #define RT5677_CROSS_OVER_FILTER4               0x93
294 #define RT5677_CROSS_OVER_FILTER5               0x94
295 #define RT5677_CROSS_OVER_FILTER6               0x95
296 #define RT5677_CROSS_OVER_FILTER7               0x96
297 #define RT5677_CROSS_OVER_FILTER8               0x97
298 #define RT5677_CROSS_OVER_FILTER9               0x98
299 #define RT5677_CROSS_OVER_FILTER10              0x99
300 
301 /* global definition */
302 #define RT5677_L_MUTE                           (0x1 << 15)
303 #define RT5677_L_MUTE_SFT                       15
304 #define RT5677_VOL_L_MUTE                       (0x1 << 14)
305 #define RT5677_VOL_L_SFT                        14
306 #define RT5677_R_MUTE                           (0x1 << 7)
307 #define RT5677_R_MUTE_SFT                       7
308 #define RT5677_VOL_R_MUTE                       (0x1 << 6)
309 #define RT5677_VOL_R_SFT                        6
310 #define RT5677_L_VOL_MASK                       (0x7f << 9)
311 #define RT5677_L_VOL_SFT                        9
312 #define RT5677_R_VOL_MASK                       (0x7f << 1)
313 #define RT5677_R_VOL_SFT                        1
314 
315 /* LOUT1 Control (0x01) */
316 #define RT5677_LOUT1_L_MUTE                     (0x1 << 15)
317 #define RT5677_LOUT1_L_MUTE_SFT                 (15)
318 #define RT5677_LOUT1_L_DF                       (0x1 << 14)
319 #define RT5677_LOUT1_L_DF_SFT                   (14)
320 #define RT5677_LOUT2_L_MUTE                     (0x1 << 13)
321 #define RT5677_LOUT2_L_MUTE_SFT                 (13)
322 #define RT5677_LOUT2_L_DF                       (0x1 << 12)
323 #define RT5677_LOUT2_L_DF_SFT                   (12)
324 #define RT5677_LOUT3_L_MUTE                     (0x1 << 11)
325 #define RT5677_LOUT3_L_MUTE_SFT                 (11)
326 #define RT5677_LOUT3_L_DF                       (0x1 << 10)
327 #define RT5677_LOUT3_L_DF_SFT                   (10)
328 #define RT5677_LOUT1_ENH_DRV                    (0x1 << 9)
329 #define RT5677_LOUT1_ENH_DRV_SFT                (9)
330 #define RT5677_LOUT2_ENH_DRV                    (0x1 << 8)
331 #define RT5677_LOUT2_ENH_DRV_SFT                (8)
332 #define RT5677_LOUT3_ENH_DRV                    (0x1 << 7)
333 #define RT5677_LOUT3_ENH_DRV_SFT                (7)
334 
335 /* IN1 Control (0x03) */
336 #define RT5677_BST_MASK1                        (0xf << 12)
337 #define RT5677_BST_SFT1                         12
338 #define RT5677_BST_MASK2                        (0xf << 8)
339 #define RT5677_BST_SFT2                         8
340 #define RT5677_IN_DF1                           (0x1 << 7)
341 #define RT5677_IN_DF1_SFT                       7
342 #define RT5677_IN_DF2                           (0x1 << 6)
343 #define RT5677_IN_DF2_SFT                       6
344 
345 /* Micbias Control (0x04) */
346 #define RT5677_MICBIAS1_OUTVOLT_MASK            (0x1 << 15)
347 #define RT5677_MICBIAS1_OUTVOLT_SFT             (15)
348 #define RT5677_MICBIAS1_OUTVOLT_2_7V            (0x0 << 15)
349 #define RT5677_MICBIAS1_OUTVOLT_2_25V           (0x1 << 15)
350 #define RT5677_MICBIAS1_CTRL_VDD_MASK           (0x1 << 14)
351 #define RT5677_MICBIAS1_CTRL_VDD_SFT            (14)
352 #define RT5677_MICBIAS1_CTRL_VDD_1_8V           (0x0 << 14)
353 #define RT5677_MICBIAS1_CTRL_VDD_3_3V           (0x1 << 14)
354 #define RT5677_MICBIAS1_OVCD_MASK               (0x1 << 11)
355 #define RT5677_MICBIAS1_OVCD_SHIFT              (11)
356 #define RT5677_MICBIAS1_OVCD_DIS                (0x0 << 11)
357 #define RT5677_MICBIAS1_OVCD_EN                 (0x1 << 11)
358 #define RT5677_MICBIAS1_OVTH_MASK               (0x3 << 9)
359 #define RT5677_MICBIAS1_OVTH_SFT                9
360 #define RT5677_MICBIAS1_OVTH_640UA              (0x0 << 9)
361 #define RT5677_MICBIAS1_OVTH_1280UA             (0x1 << 9)
362 #define RT5677_MICBIAS1_OVTH_1920UA             (0x2 << 9)
363 
364 /* SLIMbus Parameter (0x07) */
365 
366 /* SLIMbus Rx (0x08) */
367 #define RT5677_SLB_ADC4_MASK                    (0x3 << 6)
368 #define RT5677_SLB_ADC4_SFT                     6
369 #define RT5677_SLB_ADC3_MASK                    (0x3 << 4)
370 #define RT5677_SLB_ADC3_SFT                     4
371 #define RT5677_SLB_ADC2_MASK                    (0x3 << 2)
372 #define RT5677_SLB_ADC2_SFT                     2
373 #define RT5677_SLB_ADC1_MASK                    (0x3 << 0)
374 #define RT5677_SLB_ADC1_SFT                     0
375 
376 /* SLIMBus control (0x09) */
377 
378 /* Sidetone Control (0x13) */
379 #define RT5677_ST_HPF_SEL_MASK                  (0x7 << 13)
380 #define RT5677_ST_HPF_SEL_SFT                   13
381 #define RT5677_ST_HPF_PATH                      (0x1 << 12)
382 #define RT5677_ST_HPF_PATH_SFT                  12
383 #define RT5677_ST_SEL_MASK                      (0x7 << 9)
384 #define RT5677_ST_SEL_SFT                       9
385 #define RT5677_ST_EN                            (0x1 << 6)
386 #define RT5677_ST_EN_SFT                        6
387 #define RT5677_ST_GAIN                          (0x1 << 5)
388 #define RT5677_ST_GAIN_SFT                      5
389 #define RT5677_ST_VOL_MASK                      (0x1f << 0)
390 #define RT5677_ST_VOL_SFT                       0
391 
392 /* Analog DAC1/2/3 Source Control (0x15) */
393 #define RT5677_ANA_DAC3_SRC_SEL_MASK            (0x3 << 4)
394 #define RT5677_ANA_DAC3_SRC_SEL_SFT             4
395 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK          (0x3 << 0)
396 #define RT5677_ANA_DAC1_2_SRC_SEL_SFT           0
397 
398 /* IF/DSP to DAC3/4 Mixer Control (0x16) */
399 #define RT5677_M_DAC4_L_VOL                     (0x1 << 15)
400 #define RT5677_M_DAC4_L_VOL_SFT                 15
401 #define RT5677_SEL_DAC4_L_SRC_MASK              (0x7 << 12)
402 #define RT5677_SEL_DAC4_L_SRC_SFT               12
403 #define RT5677_M_DAC4_R_VOL                     (0x1 << 11)
404 #define RT5677_M_DAC4_R_VOL_SFT                 11
405 #define RT5677_SEL_DAC4_R_SRC_MASK              (0x7 << 8)
406 #define RT5677_SEL_DAC4_R_SRC_SFT               8
407 #define RT5677_M_DAC3_L_VOL                     (0x1 << 7)
408 #define RT5677_M_DAC3_L_VOL_SFT                 7
409 #define RT5677_SEL_DAC3_L_SRC_MASK              (0x7 << 4)
410 #define RT5677_SEL_DAC3_L_SRC_SFT               4
411 #define RT5677_M_DAC3_R_VOL                     (0x1 << 3)
412 #define RT5677_M_DAC3_R_VOL_SFT                 3
413 #define RT5677_SEL_DAC3_R_SRC_MASK              (0x7 << 0)
414 #define RT5677_SEL_DAC3_R_SRC_SFT               0
415 
416 /* DAC4 Digital Volume (0x17) */
417 #define RT5677_DAC4_L_VOL_MASK                  (0xff << 8)
418 #define RT5677_DAC4_L_VOL_SFT                   8
419 #define RT5677_DAC4_R_VOL_MASK                  (0xff)
420 #define RT5677_DAC4_R_VOL_SFT                   0
421 
422 /* DAC3 Digital Volume (0x18) */
423 #define RT5677_DAC3_L_VOL_MASK                  (0xff << 8)
424 #define RT5677_DAC3_L_VOL_SFT                   8
425 #define RT5677_DAC3_R_VOL_MASK                  (0xff)
426 #define RT5677_DAC3_R_VOL_SFT                   0
427 
428 /* DAC3 Digital Volume (0x19) */
429 #define RT5677_DAC1_L_VOL_MASK                  (0xff << 8)
430 #define RT5677_DAC1_L_VOL_SFT                   8
431 #define RT5677_DAC1_R_VOL_MASK                  (0xff)
432 #define RT5677_DAC1_R_VOL_SFT                   0
433 
434 /* DAC2 Digital Volume (0x1a) */
435 #define RT5677_DAC2_L_VOL_MASK                  (0xff << 8)
436 #define RT5677_DAC2_L_VOL_SFT                   8
437 #define RT5677_DAC2_R_VOL_MASK                  (0xff)
438 #define RT5677_DAC2_R_VOL_SFT                   0
439 
440 /* IF/DSP to DAC2 Mixer Control (0x1b) */
441 #define RT5677_M_DAC2_L_VOL                     (0x1 << 7)
442 #define RT5677_M_DAC2_L_VOL_SFT                 7
443 #define RT5677_SEL_DAC2_L_SRC_MASK              (0x7 << 4)
444 #define RT5677_SEL_DAC2_L_SRC_SFT               4
445 #define RT5677_M_DAC2_R_VOL                     (0x1 << 3)
446 #define RT5677_M_DAC2_R_VOL_SFT                 3
447 #define RT5677_SEL_DAC2_R_SRC_MASK              (0x7 << 0)
448 #define RT5677_SEL_DAC2_R_SRC_SFT               0
449 
450 /* Stereo1 ADC Digital Volume Control (0x1c) */
451 #define RT5677_STO1_ADC_L_VOL_MASK              (0x3f << 9)
452 #define RT5677_STO1_ADC_L_VOL_SFT               9
453 #define RT5677_STO1_ADC_R_VOL_MASK              (0x3f << 1)
454 #define RT5677_STO1_ADC_R_VOL_SFT               1
455 
456 /* Mono ADC Digital Volume Control (0x1d) */
457 #define RT5677_MONO_ADC_L_VOL_MASK              (0x3f << 9)
458 #define RT5677_MONO_ADC_L_VOL_SFT               9
459 #define RT5677_MONO_ADC_R_VOL_MASK              (0x3f << 1)
460 #define RT5677_MONO_ADC_R_VOL_SFT               1
461 
462 /* Stereo 1/2 ADC Boost Gain Control (0x1e) */
463 #define RT5677_STO1_ADC_L_BST_MASK              (0x3 << 14)
464 #define RT5677_STO1_ADC_L_BST_SFT               14
465 #define RT5677_STO1_ADC_R_BST_MASK              (0x3 << 12)
466 #define RT5677_STO1_ADC_R_BST_SFT               12
467 #define RT5677_STO1_ADC_COMP_MASK               (0x3 << 10)
468 #define RT5677_STO1_ADC_COMP_SFT                10
469 #define RT5677_STO2_ADC_L_BST_MASK              (0x3 << 8)
470 #define RT5677_STO2_ADC_L_BST_SFT               8
471 #define RT5677_STO2_ADC_R_BST_MASK              (0x3 << 6)
472 #define RT5677_STO2_ADC_R_BST_SFT               6
473 #define RT5677_STO2_ADC_COMP_MASK               (0x3 << 4)
474 #define RT5677_STO2_ADC_COMP_SFT                4
475 
476 /* Stereo2 ADC Digital Volume Control (0x1f) */
477 #define RT5677_STO2_ADC_L_VOL_MASK              (0x7f << 8)
478 #define RT5677_STO2_ADC_L_VOL_SFT               8
479 #define RT5677_STO2_ADC_R_VOL_MASK              (0x7f)
480 #define RT5677_STO2_ADC_R_VOL_SFT               0
481 
482 /* ADC Boost Gain Control 2 (0x20) */
483 #define RT5677_MONO_ADC_L_BST_MASK              (0x3 << 14)
484 #define RT5677_MONO_ADC_L_BST_SFT               14
485 #define RT5677_MONO_ADC_R_BST_MASK              (0x3 << 12)
486 #define RT5677_MONO_ADC_R_BST_SFT               12
487 #define RT5677_MONO_ADC_COMP_MASK               (0x3 << 10)
488 #define RT5677_MONO_ADC_COMP_SFT                10
489 
490 /* Stereo 3/4 ADC Boost Gain Control (0x21) */
491 #define RT5677_STO3_ADC_L_BST_MASK              (0x3 << 14)
492 #define RT5677_STO3_ADC_L_BST_SFT               14
493 #define RT5677_STO3_ADC_R_BST_MASK              (0x3 << 12)
494 #define RT5677_STO3_ADC_R_BST_SFT               12
495 #define RT5677_STO3_ADC_COMP_MASK               (0x3 << 10)
496 #define RT5677_STO3_ADC_COMP_SFT                10
497 #define RT5677_STO4_ADC_L_BST_MASK              (0x3 << 8)
498 #define RT5677_STO4_ADC_L_BST_SFT               8
499 #define RT5677_STO4_ADC_R_BST_MASK              (0x3 << 6)
500 #define RT5677_STO4_ADC_R_BST_SFT               6
501 #define RT5677_STO4_ADC_COMP_MASK               (0x3 << 4)
502 #define RT5677_STO4_ADC_COMP_SFT                4
503 
504 /* Stereo3 ADC Digital Volume Control (0x22) */
505 #define RT5677_STO3_ADC_L_VOL_MASK              (0x7f << 8)
506 #define RT5677_STO3_ADC_L_VOL_SFT               8
507 #define RT5677_STO3_ADC_R_VOL_MASK              (0x7f)
508 #define RT5677_STO3_ADC_R_VOL_SFT               0
509 
510 /* Stereo4 ADC Digital Volume Control (0x23) */
511 #define RT5677_STO4_ADC_L_VOL_MASK              (0x7f << 8)
512 #define RT5677_STO4_ADC_L_VOL_SFT               8
513 #define RT5677_STO4_ADC_R_VOL_MASK              (0x7f)
514 #define RT5677_STO4_ADC_R_VOL_SFT               0
515 
516 /* Stereo4 ADC Mixer control (0x24) */
517 #define RT5677_M_STO4_ADC_L2                    (0x1 << 15)
518 #define RT5677_M_STO4_ADC_L2_SFT                15
519 #define RT5677_M_STO4_ADC_L1                    (0x1 << 14)
520 #define RT5677_M_STO4_ADC_L1_SFT                14
521 #define RT5677_SEL_STO4_ADC1_MASK               (0x3 << 12)
522 #define RT5677_SEL_STO4_ADC1_SFT                12
523 #define RT5677_SEL_STO4_ADC2_MASK               (0x3 << 10)
524 #define RT5677_SEL_STO4_ADC2_SFT                10
525 #define RT5677_SEL_STO4_DMIC_MASK               (0x3 << 8)
526 #define RT5677_SEL_STO4_DMIC_SFT                8
527 #define RT5677_M_STO4_ADC_R1                    (0x1 << 7)
528 #define RT5677_M_STO4_ADC_R1_SFT                7
529 #define RT5677_M_STO4_ADC_R2                    (0x1 << 6)
530 #define RT5677_M_STO4_ADC_R2_SFT                6
531 
532 /* Stereo3 ADC Mixer control (0x25) */
533 #define RT5677_M_STO3_ADC_L2                    (0x1 << 15)
534 #define RT5677_M_STO3_ADC_L2_SFT                15
535 #define RT5677_M_STO3_ADC_L1                    (0x1 << 14)
536 #define RT5677_M_STO3_ADC_L1_SFT                14
537 #define RT5677_SEL_STO3_ADC1_MASK               (0x3 << 12)
538 #define RT5677_SEL_STO3_ADC1_SFT                12
539 #define RT5677_SEL_STO3_ADC2_MASK               (0x3 << 10)
540 #define RT5677_SEL_STO3_ADC2_SFT                10
541 #define RT5677_SEL_STO3_DMIC_MASK               (0x3 << 8)
542 #define RT5677_SEL_STO3_DMIC_SFT                8
543 #define RT5677_M_STO3_ADC_R1                    (0x1 << 7)
544 #define RT5677_M_STO3_ADC_R1_SFT                7
545 #define RT5677_M_STO3_ADC_R2                    (0x1 << 6)
546 #define RT5677_M_STO3_ADC_R2_SFT                6
547 
548 /* Stereo2 ADC Mixer Control (0x26) */
549 #define RT5677_M_STO2_ADC_L2                    (0x1 << 15)
550 #define RT5677_M_STO2_ADC_L2_SFT                15
551 #define RT5677_M_STO2_ADC_L1                    (0x1 << 14)
552 #define RT5677_M_STO2_ADC_L1_SFT                14
553 #define RT5677_SEL_STO2_ADC1_MASK               (0x3 << 12)
554 #define RT5677_SEL_STO2_ADC1_SFT                12
555 #define RT5677_SEL_STO2_ADC2_MASK               (0x3 << 10)
556 #define RT5677_SEL_STO2_ADC2_SFT                10
557 #define RT5677_SEL_STO2_DMIC_MASK               (0x3 << 8)
558 #define RT5677_SEL_STO2_DMIC_SFT                8
559 #define RT5677_M_STO2_ADC_R1                    (0x1 << 7)
560 #define RT5677_M_STO2_ADC_R1_SFT                7
561 #define RT5677_M_STO2_ADC_R2                    (0x1 << 6)
562 #define RT5677_M_STO2_ADC_R2_SFT                6
563 #define RT5677_SEL_STO2_LR_MIX_MASK             (0x1 << 0)
564 #define RT5677_SEL_STO2_LR_MIX_SFT              0
565 #define RT5677_SEL_STO2_LR_MIX_L                (0x0 << 0)
566 #define RT5677_SEL_STO2_LR_MIX_LR               (0x1 << 0)
567 
568 /* Stereo1 ADC Mixer control (0x27) */
569 #define RT5677_M_STO1_ADC_L2                    (0x1 << 15)
570 #define RT5677_M_STO1_ADC_L2_SFT                15
571 #define RT5677_M_STO1_ADC_L1                    (0x1 << 14)
572 #define RT5677_M_STO1_ADC_L1_SFT                14
573 #define RT5677_SEL_STO1_ADC1_MASK               (0x3 << 12)
574 #define RT5677_SEL_STO1_ADC1_SFT                12
575 #define RT5677_SEL_STO1_ADC2_MASK               (0x3 << 10)
576 #define RT5677_SEL_STO1_ADC2_SFT                10
577 #define RT5677_SEL_STO1_DMIC_MASK               (0x3 << 8)
578 #define RT5677_SEL_STO1_DMIC_SFT                8
579 #define RT5677_M_STO1_ADC_R1                    (0x1 << 7)
580 #define RT5677_M_STO1_ADC_R1_SFT                7
581 #define RT5677_M_STO1_ADC_R2                    (0x1 << 6)
582 #define RT5677_M_STO1_ADC_R2_SFT                6
583 
584 /* Mono ADC Mixer control (0x28) */
585 #define RT5677_M_MONO_ADC_L2                    (0x1 << 15)
586 #define RT5677_M_MONO_ADC_L2_SFT                15
587 #define RT5677_M_MONO_ADC_L1                    (0x1 << 14)
588 #define RT5677_M_MONO_ADC_L1_SFT                14
589 #define RT5677_SEL_MONO_ADC_L1_MASK             (0x3 << 12)
590 #define RT5677_SEL_MONO_ADC_L1_SFT              12
591 #define RT5677_SEL_MONO_ADC_L2_MASK             (0x3 << 10)
592 #define RT5677_SEL_MONO_ADC_L2_SFT              10
593 #define RT5677_SEL_MONO_DMIC_L_MASK             (0x3 << 8)
594 #define RT5677_SEL_MONO_DMIC_L_SFT              8
595 #define RT5677_M_MONO_ADC_R1                    (0x1 << 7)
596 #define RT5677_M_MONO_ADC_R1_SFT                7
597 #define RT5677_M_MONO_ADC_R2                    (0x1 << 6)
598 #define RT5677_M_MONO_ADC_R2_SFT                6
599 #define RT5677_SEL_MONO_ADC_R1_MASK             (0x3 << 4)
600 #define RT5677_SEL_MONO_ADC_R1_SFT              4
601 #define RT5677_SEL_MONO_ADC_R2_MASK             (0x3 << 2)
602 #define RT5677_SEL_MONO_ADC_R2_SFT              2
603 #define RT5677_SEL_MONO_DMIC_R_MASK             (0x3 << 0)
604 #define RT5677_SEL_MONO_DMIC_R_SFT              0
605 
606 /* ADC/IF/DSP to DAC1 Mixer control (0x29) */
607 #define RT5677_M_ADDA_MIXER1_L                  (0x1 << 15)
608 #define RT5677_M_ADDA_MIXER1_L_SFT              15
609 #define RT5677_M_DAC1_L                         (0x1 << 14)
610 #define RT5677_M_DAC1_L_SFT                     14
611 #define RT5677_DAC1_L_SEL_MASK                  (0x7 << 8)
612 #define RT5677_DAC1_L_SEL_SFT                   8
613 #define RT5677_M_ADDA_MIXER1_R                  (0x1 << 7)
614 #define RT5677_M_ADDA_MIXER1_R_SFT              7
615 #define RT5677_M_DAC1_R                         (0x1 << 6)
616 #define RT5677_M_DAC1_R_SFT                     6
617 #define RT5677_ADDA1_SEL_MASK                   (0x3 << 0)
618 #define RT5677_ADDA1_SEL_SFT                    0
619 
620 /* Stereo1 DAC Mixer L/R Control (0x2a) */
621 #define RT5677_M_ST_DAC1_L                      (0x1 << 15)
622 #define RT5677_M_ST_DAC1_L_SFT                  15
623 #define RT5677_M_DAC1_L_STO_L                   (0x1 << 13)
624 #define RT5677_M_DAC1_L_STO_L_SFT               13
625 #define RT5677_DAC1_L_STO_L_VOL_MASK            (0x1 << 12)
626 #define RT5677_DAC1_L_STO_L_VOL_SFT             12
627 #define RT5677_M_DAC2_L_STO_L                   (0x1 << 11)
628 #define RT5677_M_DAC2_L_STO_L_SFT               11
629 #define RT5677_DAC2_L_STO_L_VOL_MASK            (0x1 << 10)
630 #define RT5677_DAC2_L_STO_L_VOL_SFT             10
631 #define RT5677_M_DAC1_R_STO_L                   (0x1 << 9)
632 #define RT5677_M_DAC1_R_STO_L_SFT               9
633 #define RT5677_DAC1_R_STO_L_VOL_MASK            (0x1 << 8)
634 #define RT5677_DAC1_R_STO_L_VOL_SFT             8
635 #define RT5677_M_ST_DAC1_R                      (0x1 << 7)
636 #define RT5677_M_ST_DAC1_R_SFT                  7
637 #define RT5677_M_DAC1_R_STO_R                   (0x1 << 5)
638 #define RT5677_M_DAC1_R_STO_R_SFT               5
639 #define RT5677_DAC1_R_STO_R_VOL_MASK            (0x1 << 4)
640 #define RT5677_DAC1_R_STO_R_VOL_SFT             4
641 #define RT5677_M_DAC2_R_STO_R                   (0x1 << 3)
642 #define RT5677_M_DAC2_R_STO_R_SFT               3
643 #define RT5677_DAC2_R_STO_R_VOL_MASK            (0x1 << 2)
644 #define RT5677_DAC2_R_STO_R_VOL_SFT             2
645 #define RT5677_M_DAC1_L_STO_R                   (0x1 << 1)
646 #define RT5677_M_DAC1_L_STO_R_SFT               1
647 #define RT5677_DAC1_L_STO_R_VOL_MASK            (0x1 << 0)
648 #define RT5677_DAC1_L_STO_R_VOL_SFT             0
649 
650 /* Mono DAC Mixer L/R Control (0x2b) */
651 #define RT5677_M_ST_DAC2_L                      (0x1 << 15)
652 #define RT5677_M_ST_DAC2_L_SFT                  15
653 #define RT5677_M_DAC2_L_MONO_L                  (0x1 << 13)
654 #define RT5677_M_DAC2_L_MONO_L_SFT              13
655 #define RT5677_DAC2_L_MONO_L_VOL_MASK           (0x1 << 12)
656 #define RT5677_DAC2_L_MONO_L_VOL_SFT            12
657 #define RT5677_M_DAC2_R_MONO_L                  (0x1 << 11)
658 #define RT5677_M_DAC2_R_MONO_L_SFT              11
659 #define RT5677_DAC2_R_MONO_L_VOL_MASK           (0x1 << 10)
660 #define RT5677_DAC2_R_MONO_L_VOL_SFT            10
661 #define RT5677_M_DAC1_L_MONO_L                  (0x1 << 9)
662 #define RT5677_M_DAC1_L_MONO_L_SFT              9
663 #define RT5677_DAC1_L_MONO_L_VOL_MASK           (0x1 << 8)
664 #define RT5677_DAC1_L_MONO_L_VOL_SFT            8
665 #define RT5677_M_ST_DAC2_R                      (0x1 << 7)
666 #define RT5677_M_ST_DAC2_R_SFT                  7
667 #define RT5677_M_DAC2_R_MONO_R                  (0x1 << 5)
668 #define RT5677_M_DAC2_R_MONO_R_SFT              5
669 #define RT5677_DAC2_R_MONO_R_VOL_MASK           (0x1 << 4)
670 #define RT5677_DAC2_R_MONO_R_VOL_SFT            4
671 #define RT5677_M_DAC1_R_MONO_R                  (0x1 << 3)
672 #define RT5677_M_DAC1_R_MONO_R_SFT              3
673 #define RT5677_DAC1_R_MONO_R_VOL_MASK           (0x1 << 2)
674 #define RT5677_DAC1_R_MONO_R_VOL_SFT            2
675 #define RT5677_M_DAC2_L_MONO_R                  (0x1 << 1)
676 #define RT5677_M_DAC2_L_MONO_R_SFT              1
677 #define RT5677_DAC2_L_MONO_R_VOL_MASK           (0x1 << 0)
678 #define RT5677_DAC2_L_MONO_R_VOL_SFT            0
679 
680 /* DD Mixer 1 Control (0x2c) */
681 #define RT5677_M_STO_L_DD1_L                    (0x1 << 15)
682 #define RT5677_M_STO_L_DD1_L_SFT                15
683 #define RT5677_STO_L_DD1_L_VOL_MASK             (0x1 << 14)
684 #define RT5677_STO_L_DD1_L_VOL_SFT              14
685 #define RT5677_M_MONO_L_DD1_L                   (0x1 << 13)
686 #define RT5677_M_MONO_L_DD1_L_SFT               13
687 #define RT5677_MONO_L_DD1_L_VOL_MASK            (0x1 << 12)
688 #define RT5677_MONO_L_DD1_L_VOL_SFT             12
689 #define RT5677_M_DAC3_L_DD1_L                   (0x1 << 11)
690 #define RT5677_M_DAC3_L_DD1_L_SFT               11
691 #define RT5677_DAC3_L_DD1_L_VOL_MASK            (0x1 << 10)
692 #define RT5677_DAC3_L_DD1_L_VOL_SFT             10
693 #define RT5677_M_DAC3_R_DD1_L                   (0x1 << 9)
694 #define RT5677_M_DAC3_R_DD1_L_SFT               9
695 #define RT5677_DAC3_R_DD1_L_VOL_MASK            (0x1 << 8)
696 #define RT5677_DAC3_R_DD1_L_VOL_SFT             8
697 #define RT5677_M_STO_R_DD1_R                    (0x1 << 7)
698 #define RT5677_M_STO_R_DD1_R_SFT                7
699 #define RT5677_STO_R_DD1_R_VOL_MASK             (0x1 << 6)
700 #define RT5677_STO_R_DD1_R_VOL_SFT              6
701 #define RT5677_M_MONO_R_DD1_R                   (0x1 << 5)
702 #define RT5677_M_MONO_R_DD1_R_SFT               5
703 #define RT5677_MONO_R_DD1_R_VOL_MASK            (0x1 << 4)
704 #define RT5677_MONO_R_DD1_R_VOL_SFT             4
705 #define RT5677_M_DAC3_R_DD1_R                   (0x1 << 3)
706 #define RT5677_M_DAC3_R_DD1_R_SFT               3
707 #define RT5677_DAC3_R_DD1_R_VOL_MASK            (0x1 << 2)
708 #define RT5677_DAC3_R_DD1_R_VOL_SFT             2
709 #define RT5677_M_DAC3_L_DD1_R                   (0x1 << 1)
710 #define RT5677_M_DAC3_L_DD1_R_SFT               1
711 #define RT5677_DAC3_L_DD1_R_VOL_MASK            (0x1 << 0)
712 #define RT5677_DAC3_L_DD1_R_VOL_SFT             0
713 
714 /* DD Mixer 2 Control (0x2d) */
715 #define RT5677_M_STO_L_DD2_L                    (0x1 << 15)
716 #define RT5677_M_STO_L_DD2_L_SFT                15
717 #define RT5677_STO_L_DD2_L_VOL_MASK             (0x1 << 14)
718 #define RT5677_STO_L_DD2_L_VOL_SFT              14
719 #define RT5677_M_MONO_L_DD2_L                   (0x1 << 13)
720 #define RT5677_M_MONO_L_DD2_L_SFT               13
721 #define RT5677_MONO_L_DD2_L_VOL_MASK            (0x1 << 12)
722 #define RT5677_MONO_L_DD2_L_VOL_SFT             12
723 #define RT5677_M_DAC4_L_DD2_L                   (0x1 << 11)
724 #define RT5677_M_DAC4_L_DD2_L_SFT               11
725 #define RT5677_DAC4_L_DD2_L_VOL_MASK            (0x1 << 10)
726 #define RT5677_DAC4_L_DD2_L_VOL_SFT             10
727 #define RT5677_M_DAC4_R_DD2_L                   (0x1 << 9)
728 #define RT5677_M_DAC4_R_DD2_L_SFT               9
729 #define RT5677_DAC4_R_DD2_L_VOL_MASK            (0x1 << 8)
730 #define RT5677_DAC4_R_DD2_L_VOL_SFT             8
731 #define RT5677_M_STO_R_DD2_R                    (0x1 << 7)
732 #define RT5677_M_STO_R_DD2_R_SFT                7
733 #define RT5677_STO_R_DD2_R_VOL_MASK             (0x1 << 6)
734 #define RT5677_STO_R_DD2_R_VOL_SFT              6
735 #define RT5677_M_MONO_R_DD2_R                   (0x1 << 5)
736 #define RT5677_M_MONO_R_DD2_R_SFT               5
737 #define RT5677_MONO_R_DD2_R_VOL_MASK            (0x1 << 4)
738 #define RT5677_MONO_R_DD2_R_VOL_SFT             4
739 #define RT5677_M_DAC4_R_DD2_R                   (0x1 << 3)
740 #define RT5677_M_DAC4_R_DD2_R_SFT               3
741 #define RT5677_DAC4_R_DD2_R_VOL_MASK            (0x1 << 2)
742 #define RT5677_DAC4_R_DD2_R_VOL_SFT             2
743 #define RT5677_M_DAC4_L_DD2_R                   (0x1 << 1)
744 #define RT5677_M_DAC4_L_DD2_R_SFT               1
745 #define RT5677_DAC4_L_DD2_R_VOL_MASK            (0x1 << 0)
746 #define RT5677_DAC4_L_DD2_R_VOL_SFT             0
747 
748 /* IF3 data control (0x2f) */
749 #define RT5677_IF3_DAC_SEL_MASK                 (0x3 << 6)
750 #define RT5677_IF3_DAC_SEL_SFT                  6
751 #define RT5677_IF3_ADC_SEL_MASK                 (0x3 << 4)
752 #define RT5677_IF3_ADC_SEL_SFT                  4
753 #define RT5677_IF3_ADC_IN_MASK                  (0xf << 0)
754 #define RT5677_IF3_ADC_IN_SFT                   0
755 
756 /* IF4 data control (0x30) */
757 #define RT5677_IF4_ADC_IN_MASK                  (0xf << 4)
758 #define RT5677_IF4_ADC_IN_SFT                   4
759 #define RT5677_IF4_DAC_SEL_MASK                 (0x3 << 2)
760 #define RT5677_IF4_DAC_SEL_SFT                  2
761 #define RT5677_IF4_ADC_SEL_MASK                 (0x3 << 0)
762 #define RT5677_IF4_ADC_SEL_SFT                  0
763 
764 /* PDM Output Control (0x31) */
765 #define RT5677_M_PDM1_L                         (0x1 << 15)
766 #define RT5677_M_PDM1_L_SFT                     15
767 #define RT5677_SEL_PDM1_L_MASK                  (0x3 << 12)
768 #define RT5677_SEL_PDM1_L_SFT                   12
769 #define RT5677_M_PDM1_R                         (0x1 << 11)
770 #define RT5677_M_PDM1_R_SFT                     11
771 #define RT5677_SEL_PDM1_R_MASK                  (0x3 << 8)
772 #define RT5677_SEL_PDM1_R_SFT                   8
773 #define RT5677_M_PDM2_L                         (0x1 << 7)
774 #define RT5677_M_PDM2_L_SFT                     7
775 #define RT5677_SEL_PDM2_L_MASK                  (0x3 << 4)
776 #define RT5677_SEL_PDM2_L_SFT                   4
777 #define RT5677_M_PDM2_R                         (0x1 << 3)
778 #define RT5677_M_PDM2_R_SFT                     3
779 #define RT5677_SEL_PDM2_R_MASK                  (0x3 << 0)
780 #define RT5677_SEL_PDM2_R_SFT                   0
781 
782 /* PDM I2C / Data Control 1 (0x32) */
783 #define RT5677_PDM2_PW_DOWN                     (0x1 << 7)
784 #define RT5677_PDM1_PW_DOWN                     (0x1 << 6)
785 #define RT5677_PDM2_BUSY                        (0x1 << 5)
786 #define RT5677_PDM1_BUSY                        (0x1 << 4)
787 #define RT5677_PDM_PATTERN                      (0x1 << 3)
788 #define RT5677_PDM_GAIN                         (0x1 << 2)
789 #define RT5677_PDM_DIV_MASK                     (0x3 << 0)
790 
791 /* PDM I2C / Data Control 2 (0x33) */
792 #define RT5677_PDM1_I2C_ID                      (0xf << 12)
793 #define RT5677_PDM1_EXE                         (0x1 << 11)
794 #define RT5677_PDM1_I2C_CMD                     (0x1 << 10)
795 #define RT5677_PDM1_I2C_EXE                     (0x1 << 9)
796 #define RT5677_PDM1_I2C_BUSY                    (0x1 << 8)
797 #define RT5677_PDM2_I2C_ID                      (0xf << 4)
798 #define RT5677_PDM2_EXE                         (0x1 << 3)
799 #define RT5677_PDM2_I2C_CMD                     (0x1 << 2)
800 #define RT5677_PDM2_I2C_EXE                     (0x1 << 1)
801 #define RT5677_PDM2_I2C_BUSY                    (0x1 << 0)
802 
803 /* TDM1 control 1 (0x3b) */
804 #define RT5677_IF1_ADC_MODE_MASK                (0x1 << 12)
805 #define RT5677_IF1_ADC_MODE_SFT                 12
806 #define RT5677_IF1_ADC_MODE_I2S                 (0x0 << 12)
807 #define RT5677_IF1_ADC_MODE_TDM                 (0x1 << 12)
808 #define RT5677_IF1_ADC1_SWAP_MASK               (0x3 << 6)
809 #define RT5677_IF1_ADC1_SWAP_SFT                6
810 #define RT5677_IF1_ADC2_SWAP_MASK               (0x3 << 4)
811 #define RT5677_IF1_ADC2_SWAP_SFT                4
812 #define RT5677_IF1_ADC3_SWAP_MASK               (0x3 << 2)
813 #define RT5677_IF1_ADC3_SWAP_SFT                2
814 #define RT5677_IF1_ADC4_SWAP_MASK               (0x3 << 0)
815 #define RT5677_IF1_ADC4_SWAP_SFT                0
816 
817 /* TDM1 control 2 (0x3c) */
818 #define RT5677_IF1_ADC4_MASK                    (0x3 << 10)
819 #define RT5677_IF1_ADC4_SFT                     10
820 #define RT5677_IF1_ADC3_MASK                    (0x3 << 8)
821 #define RT5677_IF1_ADC3_SFT                     8
822 #define RT5677_IF1_ADC2_MASK                    (0x3 << 6)
823 #define RT5677_IF1_ADC2_SFT                     6
824 #define RT5677_IF1_ADC1_MASK                    (0x3 << 4)
825 #define RT5677_IF1_ADC1_SFT                     4
826 #define RT5677_IF1_ADC_CTRL_MASK                (0x7 << 0)
827 #define RT5677_IF1_ADC_CTRL_SFT                 0
828 
829 /* TDM1 control 4 (0x3e) */
830 #define RT5677_IF1_DAC0_MASK                    (0x7 << 12)
831 #define RT5677_IF1_DAC0_SFT                     12
832 #define RT5677_IF1_DAC1_MASK                    (0x7 << 8)
833 #define RT5677_IF1_DAC1_SFT                     8
834 #define RT5677_IF1_DAC2_MASK                    (0x7 << 4)
835 #define RT5677_IF1_DAC2_SFT                     4
836 #define RT5677_IF1_DAC3_MASK                    (0x7 << 0)
837 #define RT5677_IF1_DAC3_SFT                     0
838 
839 /* TDM1 control 5 (0x3f) */
840 #define RT5677_IF1_DAC4_MASK                    (0x7 << 12)
841 #define RT5677_IF1_DAC4_SFT                     12
842 #define RT5677_IF1_DAC5_MASK                    (0x7 << 8)
843 #define RT5677_IF1_DAC5_SFT                     8
844 #define RT5677_IF1_DAC6_MASK                    (0x7 << 4)
845 #define RT5677_IF1_DAC6_SFT                     4
846 #define RT5677_IF1_DAC7_MASK                    (0x7 << 0)
847 #define RT5677_IF1_DAC7_SFT                     0
848 
849 /* TDM2 control 1 (0x40) */
850 #define RT5677_IF2_ADC_MODE_MASK                (0x1 << 12)
851 #define RT5677_IF2_ADC_MODE_SFT                 12
852 #define RT5677_IF2_ADC_MODE_I2S                 (0x0 << 12)
853 #define RT5677_IF2_ADC_MODE_TDM                 (0x1 << 12)
854 #define RT5677_IF2_ADC1_SWAP_MASK               (0x3 << 6)
855 #define RT5677_IF2_ADC1_SWAP_SFT                6
856 #define RT5677_IF2_ADC2_SWAP_MASK               (0x3 << 4)
857 #define RT5677_IF2_ADC2_SWAP_SFT                4
858 #define RT5677_IF2_ADC3_SWAP_MASK               (0x3 << 2)
859 #define RT5677_IF2_ADC3_SWAP_SFT                2
860 #define RT5677_IF2_ADC4_SWAP_MASK               (0x3 << 0)
861 #define RT5677_IF2_ADC4_SWAP_SFT                0
862 
863 /* TDM2 control 2 (0x41) */
864 #define RT5677_IF2_ADC4_MASK                    (0x3 << 10)
865 #define RT5677_IF2_ADC4_SFT                     10
866 #define RT5677_IF2_ADC3_MASK                    (0x3 << 8)
867 #define RT5677_IF2_ADC3_SFT                     8
868 #define RT5677_IF2_ADC2_MASK                    (0x3 << 6)
869 #define RT5677_IF2_ADC2_SFT                     6
870 #define RT5677_IF2_ADC1_MASK                    (0x3 << 4)
871 #define RT5677_IF2_ADC1_SFT                     4
872 #define RT5677_IF2_ADC_CTRL_MASK                (0x7 << 0)
873 #define RT5677_IF2_ADC_CTRL_SFT                 0
874 
875 /* TDM2 control 4 (0x43) */
876 #define RT5677_IF2_DAC0_MASK                    (0x7 << 12)
877 #define RT5677_IF2_DAC0_SFT                     12
878 #define RT5677_IF2_DAC1_MASK                    (0x7 << 8)
879 #define RT5677_IF2_DAC1_SFT                     8
880 #define RT5677_IF2_DAC2_MASK                    (0x7 << 4)
881 #define RT5677_IF2_DAC2_SFT                     4
882 #define RT5677_IF2_DAC3_MASK                    (0x7 << 0)
883 #define RT5677_IF2_DAC3_SFT                     0
884 
885 /* TDM2 control 5 (0x44) */
886 #define RT5677_IF2_DAC4_MASK                    (0x7 << 12)
887 #define RT5677_IF2_DAC4_SFT                     12
888 #define RT5677_IF2_DAC5_MASK                    (0x7 << 8)
889 #define RT5677_IF2_DAC5_SFT                     8
890 #define RT5677_IF2_DAC6_MASK                    (0x7 << 4)
891 #define RT5677_IF2_DAC6_SFT                     4
892 #define RT5677_IF2_DAC7_MASK                    (0x7 << 0)
893 #define RT5677_IF2_DAC7_SFT                     0
894 
895 /* Digital Microphone Control 1 (0x50) */
896 #define RT5677_DMIC_1_EN_MASK                   (0x1 << 15)
897 #define RT5677_DMIC_1_EN_SFT                    15
898 #define RT5677_DMIC_1_DIS                       (0x0 << 15)
899 #define RT5677_DMIC_1_EN                        (0x1 << 15)
900 #define RT5677_DMIC_2_EN_MASK                   (0x1 << 14)
901 #define RT5677_DMIC_2_EN_SFT                    14
902 #define RT5677_DMIC_2_DIS                       (0x0 << 14)
903 #define RT5677_DMIC_2_EN                        (0x1 << 14)
904 #define RT5677_DMIC_L_STO1_LH_MASK              (0x1 << 13)
905 #define RT5677_DMIC_L_STO1_LH_SFT               13
906 #define RT5677_DMIC_L_STO1_LH_FALLING           (0x0 << 13)
907 #define RT5677_DMIC_L_STO1_LH_RISING            (0x1 << 13)
908 #define RT5677_DMIC_R_STO1_LH_MASK              (0x1 << 12)
909 #define RT5677_DMIC_R_STO1_LH_SFT               12
910 #define RT5677_DMIC_R_STO1_LH_FALLING           (0x0 << 12)
911 #define RT5677_DMIC_R_STO1_LH_RISING            (0x1 << 12)
912 #define RT5677_DMIC_L_STO3_LH_MASK              (0x1 << 11)
913 #define RT5677_DMIC_L_STO3_LH_SFT               11
914 #define RT5677_DMIC_L_STO3_LH_FALLING           (0x0 << 11)
915 #define RT5677_DMIC_L_STO3_LH_RISING            (0x1 << 11)
916 #define RT5677_DMIC_R_STO3_LH_MASK              (0x1 << 10)
917 #define RT5677_DMIC_R_STO3_LH_SFT               10
918 #define RT5677_DMIC_R_STO3_LH_FALLING           (0x0 << 10)
919 #define RT5677_DMIC_R_STO3_LH_RISING            (0x1 << 10)
920 #define RT5677_DMIC_L_STO2_LH_MASK              (0x1 << 9)
921 #define RT5677_DMIC_L_STO2_LH_SFT               9
922 #define RT5677_DMIC_L_STO2_LH_FALLING           (0x0 << 9)
923 #define RT5677_DMIC_L_STO2_LH_RISING            (0x1 << 9)
924 #define RT5677_DMIC_R_STO2_LH_MASK              (0x1 << 8)
925 #define RT5677_DMIC_R_STO2_LH_SFT               8
926 #define RT5677_DMIC_R_STO2_LH_FALLING           (0x0 << 8)
927 #define RT5677_DMIC_R_STO2_LH_RISING            (0x1 << 8)
928 #define RT5677_DMIC_CLK_MASK                    (0x7 << 5)
929 #define RT5677_DMIC_CLK_SFT                     5
930 #define RT5677_DMIC_3_EN_MASK                   (0x1 << 4)
931 #define RT5677_DMIC_3_EN_SFT                    4
932 #define RT5677_DMIC_3_DIS                       (0x0 << 4)
933 #define RT5677_DMIC_3_EN                        (0x1 << 4)
934 #define RT5677_DMIC_R_MONO_LH_MASK              (0x1 << 2)
935 #define RT5677_DMIC_R_MONO_LH_SFT               2
936 #define RT5677_DMIC_R_MONO_LH_FALLING           (0x0 << 2)
937 #define RT5677_DMIC_R_MONO_LH_RISING            (0x1 << 2)
938 #define RT5677_DMIC_L_STO4_LH_MASK              (0x1 << 1)
939 #define RT5677_DMIC_L_STO4_LH_SFT               1
940 #define RT5677_DMIC_L_STO4_LH_FALLING           (0x0 << 1)
941 #define RT5677_DMIC_L_STO4_LH_RISING            (0x1 << 1)
942 #define RT5677_DMIC_R_STO4_LH_MASK              (0x1 << 0)
943 #define RT5677_DMIC_R_STO4_LH_SFT               0
944 #define RT5677_DMIC_R_STO4_LH_FALLING           (0x0 << 0)
945 #define RT5677_DMIC_R_STO4_LH_RISING            (0x1 << 0)
946 
947 /* Digital Microphone Control 2 (0x51) */
948 #define RT5677_DMIC_4_EN_MASK                   (0x1 << 15)
949 #define RT5677_DMIC_4_EN_SFT                    15
950 #define RT5677_DMIC_4_DIS                       (0x0 << 15)
951 #define RT5677_DMIC_4_EN                        (0x1 << 15)
952 #define RT5677_DMIC_4L_LH_MASK                  (0x1 << 7)
953 #define RT5677_DMIC_4L_LH_SFT                   7
954 #define RT5677_DMIC_4L_LH_FALLING               (0x0 << 7)
955 #define RT5677_DMIC_4L_LH_RISING                (0x1 << 7)
956 #define RT5677_DMIC_4R_LH_MASK                  (0x1 << 6)
957 #define RT5677_DMIC_4R_LH_SFT                   6
958 #define RT5677_DMIC_4R_LH_FALLING               (0x0 << 6)
959 #define RT5677_DMIC_4R_LH_RISING                (0x1 << 6)
960 #define RT5677_DMIC_3L_LH_MASK                  (0x1 << 5)
961 #define RT5677_DMIC_3L_LH_SFT                   5
962 #define RT5677_DMIC_3L_LH_FALLING               (0x0 << 5)
963 #define RT5677_DMIC_3L_LH_RISING                (0x1 << 5)
964 #define RT5677_DMIC_3R_LH_MASK                  (0x1 << 4)
965 #define RT5677_DMIC_3R_LH_SFT                   4
966 #define RT5677_DMIC_3R_LH_FALLING               (0x0 << 4)
967 #define RT5677_DMIC_3R_LH_RISING                (0x1 << 4)
968 #define RT5677_DMIC_2L_LH_MASK                  (0x1 << 3)
969 #define RT5677_DMIC_2L_LH_SFT                   3
970 #define RT5677_DMIC_2L_LH_FALLING               (0x0 << 3)
971 #define RT5677_DMIC_2L_LH_RISING                (0x1 << 3)
972 #define RT5677_DMIC_2R_LH_MASK                  (0x1 << 2)
973 #define RT5677_DMIC_2R_LH_SFT                   2
974 #define RT5677_DMIC_2R_LH_FALLING               (0x0 << 2)
975 #define RT5677_DMIC_2R_LH_RISING                (0x1 << 2)
976 #define RT5677_DMIC_1L_LH_MASK                  (0x1 << 1)
977 #define RT5677_DMIC_1L_LH_SFT                   1
978 #define RT5677_DMIC_1L_LH_FALLING               (0x0 << 1)
979 #define RT5677_DMIC_1L_LH_RISING                (0x1 << 1)
980 #define RT5677_DMIC_1R_LH_MASK                  (0x1 << 0)
981 #define RT5677_DMIC_1R_LH_SFT                   0
982 #define RT5677_DMIC_1R_LH_FALLING               (0x0 << 0)
983 #define RT5677_DMIC_1R_LH_RISING                (0x1 << 0)
984 
985 /* Power Management for Digital 1 (0x61) */
986 #define RT5677_PWR_I2S1                         (0x1 << 15)
987 #define RT5677_PWR_I2S1_BIT                     15
988 #define RT5677_PWR_I2S2                         (0x1 << 14)
989 #define RT5677_PWR_I2S2_BIT                     14
990 #define RT5677_PWR_I2S3                         (0x1 << 13)
991 #define RT5677_PWR_I2S3_BIT                     13
992 #define RT5677_PWR_DAC1                         (0x1 << 12)
993 #define RT5677_PWR_DAC1_BIT                     12
994 #define RT5677_PWR_DAC2                         (0x1 << 11)
995 #define RT5677_PWR_DAC2_BIT                     11
996 #define RT5677_PWR_I2S4                         (0x1 << 10)
997 #define RT5677_PWR_I2S4_BIT                     10
998 #define RT5677_PWR_SLB                          (0x1 << 9)
999 #define RT5677_PWR_SLB_BIT                      9
1000 #define RT5677_PWR_DAC3                         (0x1 << 7)
1001 #define RT5677_PWR_DAC3_BIT                     7
1002 #define RT5677_PWR_ADCFED2                      (0x1 << 4)
1003 #define RT5677_PWR_ADCFED2_BIT                  4
1004 #define RT5677_PWR_ADCFED1                      (0x1 << 3)
1005 #define RT5677_PWR_ADCFED1_BIT                  3
1006 #define RT5677_PWR_ADC_L                        (0x1 << 2)
1007 #define RT5677_PWR_ADC_L_BIT                    2
1008 #define RT5677_PWR_ADC_R                        (0x1 << 1)
1009 #define RT5677_PWR_ADC_R_BIT                    1
1010 #define RT5677_PWR_I2C_MASTER                   (0x1 << 0)
1011 #define RT5677_PWR_I2C_MASTER_BIT               0
1012 
1013 /* Power Management for Digital 2 (0x62) */
1014 #define RT5677_PWR_ADC_S1F                      (0x1 << 15)
1015 #define RT5677_PWR_ADC_S1F_BIT                  15
1016 #define RT5677_PWR_ADC_MF_L                     (0x1 << 14)
1017 #define RT5677_PWR_ADC_MF_L_BIT                 14
1018 #define RT5677_PWR_ADC_MF_R                     (0x1 << 13)
1019 #define RT5677_PWR_ADC_MF_R_BIT                 13
1020 #define RT5677_PWR_DAC_S1F                      (0x1 << 12)
1021 #define RT5677_PWR_DAC_S1F_BIT                  12
1022 #define RT5677_PWR_DAC_M2F_L                    (0x1 << 11)
1023 #define RT5677_PWR_DAC_M2F_L_BIT                11
1024 #define RT5677_PWR_DAC_M2F_R                    (0x1 << 10)
1025 #define RT5677_PWR_DAC_M2F_R_BIT                10
1026 #define RT5677_PWR_DAC_M3F_L                    (0x1 << 9)
1027 #define RT5677_PWR_DAC_M3F_L_BIT                9
1028 #define RT5677_PWR_DAC_M3F_R                    (0x1 << 8)
1029 #define RT5677_PWR_DAC_M3F_R_BIT                8
1030 #define RT5677_PWR_DAC_M4F_L                    (0x1 << 7)
1031 #define RT5677_PWR_DAC_M4F_L_BIT                7
1032 #define RT5677_PWR_DAC_M4F_R                    (0x1 << 6)
1033 #define RT5677_PWR_DAC_M4F_R_BIT                6
1034 #define RT5677_PWR_ADC_S2F                      (0x1 << 5)
1035 #define RT5677_PWR_ADC_S2F_BIT                  5
1036 #define RT5677_PWR_ADC_S3F                      (0x1 << 4)
1037 #define RT5677_PWR_ADC_S3F_BIT                  4
1038 #define RT5677_PWR_ADC_S4F                      (0x1 << 3)
1039 #define RT5677_PWR_ADC_S4F_BIT                  3
1040 #define RT5677_PWR_PDM1                         (0x1 << 2)
1041 #define RT5677_PWR_PDM1_BIT                     2
1042 #define RT5677_PWR_PDM2                         (0x1 << 1)
1043 #define RT5677_PWR_PDM2_BIT                     1
1044 
1045 /* Power Management for Analog 1 (0x63) */
1046 #define RT5677_PWR_VREF1                        (0x1 << 15)
1047 #define RT5677_PWR_VREF1_BIT                    15
1048 #define RT5677_PWR_FV1                          (0x1 << 14)
1049 #define RT5677_PWR_FV1_BIT                      14
1050 #define RT5677_PWR_MB                           (0x1 << 13)
1051 #define RT5677_PWR_MB_BIT                       13
1052 #define RT5677_PWR_LO1                          (0x1 << 12)
1053 #define RT5677_PWR_LO1_BIT                      12
1054 #define RT5677_PWR_BG                           (0x1 << 11)
1055 #define RT5677_PWR_BG_BIT                       11
1056 #define RT5677_PWR_LO2                          (0x1 << 10)
1057 #define RT5677_PWR_LO2_BIT                      10
1058 #define RT5677_PWR_LO3                          (0x1 << 9)
1059 #define RT5677_PWR_LO3_BIT                      9
1060 #define RT5677_PWR_VREF2                        (0x1 << 8)
1061 #define RT5677_PWR_VREF2_BIT                    8
1062 #define RT5677_PWR_FV2                          (0x1 << 7)
1063 #define RT5677_PWR_FV2_BIT                      7
1064 #define RT5677_LDO2_SEL_MASK                    (0x7 << 4)
1065 #define RT5677_LDO2_SEL_SFT                     4
1066 #define RT5677_LDO1_SEL_MASK                    (0x7 << 0)
1067 #define RT5677_LDO1_SEL_SFT                     0
1068 
1069 /* Power Management for Analog 2 (0x64) */
1070 #define RT5677_PWR_BST1                         (0x1 << 15)
1071 #define RT5677_PWR_BST1_BIT                     15
1072 #define RT5677_PWR_BST2                         (0x1 << 14)
1073 #define RT5677_PWR_BST2_BIT                     14
1074 #define RT5677_PWR_CLK_MB1                      (0x1 << 13)
1075 #define RT5677_PWR_CLK_MB1_BIT                  13
1076 #define RT5677_PWR_SLIM                         (0x1 << 12)
1077 #define RT5677_PWR_SLIM_BIT                     12
1078 #define RT5677_PWR_MB1                          (0x1 << 11)
1079 #define RT5677_PWR_MB1_BIT                      11
1080 #define RT5677_PWR_PP_MB1                       (0x1 << 10)
1081 #define RT5677_PWR_PP_MB1_BIT                   10
1082 #define RT5677_PWR_PLL1                         (0x1 << 9)
1083 #define RT5677_PWR_PLL1_BIT                     9
1084 #define RT5677_PWR_PLL2                         (0x1 << 8)
1085 #define RT5677_PWR_PLL2_BIT                     8
1086 #define RT5677_PWR_CORE                         (0x1 << 7)
1087 #define RT5677_PWR_CORE_BIT                     7
1088 #define RT5677_PWR_CLK_MB                       (0x1 << 6)
1089 #define RT5677_PWR_CLK_MB_BIT                   6
1090 #define RT5677_PWR_BST1_P                       (0x1 << 5)
1091 #define RT5677_PWR_BST1_P_BIT                   5
1092 #define RT5677_PWR_BST2_P                       (0x1 << 4)
1093 #define RT5677_PWR_BST2_P_BIT                   4
1094 #define RT5677_PWR_IPTV                         (0x1 << 3)
1095 #define RT5677_PWR_IPTV_BIT                     3
1096 #define RT5677_PWR_25M_CLK                      (0x1 << 1)
1097 #define RT5677_PWR_25M_CLK_BIT                  1
1098 #define RT5677_PWR_LDO1                         (0x1 << 0)
1099 #define RT5677_PWR_LDO1_BIT                     0
1100 
1101 /* Power Management for DSP (0x65) */
1102 #define RT5677_PWR_SR7                          (0x1 << 10)
1103 #define RT5677_PWR_SR7_BIT                      10
1104 #define RT5677_PWR_SR6                          (0x1 << 9)
1105 #define RT5677_PWR_SR6_BIT                      9
1106 #define RT5677_PWR_SR5                          (0x1 << 8)
1107 #define RT5677_PWR_SR5_BIT                      8
1108 #define RT5677_PWR_SR4                          (0x1 << 7)
1109 #define RT5677_PWR_SR4_BIT                      7
1110 #define RT5677_PWR_SR3                          (0x1 << 6)
1111 #define RT5677_PWR_SR3_BIT                      6
1112 #define RT5677_PWR_SR2                          (0x1 << 5)
1113 #define RT5677_PWR_SR2_BIT                      5
1114 #define RT5677_PWR_SR1                          (0x1 << 4)
1115 #define RT5677_PWR_SR1_BIT                      4
1116 #define RT5677_PWR_SR0                          (0x1 << 3)
1117 #define RT5677_PWR_SR0_BIT                      3
1118 #define RT5677_PWR_MLT                          (0x1 << 2)
1119 #define RT5677_PWR_MLT_BIT                      2
1120 #define RT5677_PWR_DSP                          (0x1 << 1)
1121 #define RT5677_PWR_DSP_BIT                      1
1122 #define RT5677_PWR_DSP_CPU                      (0x1 << 0)
1123 #define RT5677_PWR_DSP_CPU_BIT                  0
1124 
1125 /* Power Status for DSP (0x66) */
1126 #define RT5677_PWR_SR7_RDY                      (0x1 << 9)
1127 #define RT5677_PWR_SR7_RDY_BIT                  9
1128 #define RT5677_PWR_SR6_RDY                      (0x1 << 8)
1129 #define RT5677_PWR_SR6_RDY_BIT                  8
1130 #define RT5677_PWR_SR5_RDY                      (0x1 << 7)
1131 #define RT5677_PWR_SR5_RDY_BIT                  7
1132 #define RT5677_PWR_SR4_RDY                      (0x1 << 6)
1133 #define RT5677_PWR_SR4_RDY_BIT                  6
1134 #define RT5677_PWR_SR3_RDY                      (0x1 << 5)
1135 #define RT5677_PWR_SR3_RDY_BIT                  5
1136 #define RT5677_PWR_SR2_RDY                      (0x1 << 4)
1137 #define RT5677_PWR_SR2_RDY_BIT                  4
1138 #define RT5677_PWR_SR1_RDY                      (0x1 << 3)
1139 #define RT5677_PWR_SR1_RDY_BIT                  3
1140 #define RT5677_PWR_SR0_RDY                      (0x1 << 2)
1141 #define RT5677_PWR_SR0_RDY_BIT                  2
1142 #define RT5677_PWR_MLT_RDY                      (0x1 << 1)
1143 #define RT5677_PWR_MLT_RDY_BIT                  1
1144 #define RT5677_PWR_DSP_RDY                      (0x1 << 0)
1145 #define RT5677_PWR_DSP_RDY_BIT                  0
1146 
1147 /* Power Management for DSP (0x67) */
1148 #define RT5677_PWR_SLIM_ISO                     (0x1 << 11)
1149 #define RT5677_PWR_SLIM_ISO_BIT                 11
1150 #define RT5677_PWR_CORE_ISO                     (0x1 << 10)
1151 #define RT5677_PWR_CORE_ISO_BIT                 10
1152 #define RT5677_PWR_DSP_ISO                      (0x1 << 9)
1153 #define RT5677_PWR_DSP_ISO_BIT                  9
1154 #define RT5677_PWR_SR7_ISO                      (0x1 << 8)
1155 #define RT5677_PWR_SR7_ISO_BIT                  8
1156 #define RT5677_PWR_SR6_ISO                      (0x1 << 7)
1157 #define RT5677_PWR_SR6_ISO_BIT                  7
1158 #define RT5677_PWR_SR5_ISO                      (0x1 << 6)
1159 #define RT5677_PWR_SR5_ISO_BIT                  6
1160 #define RT5677_PWR_SR4_ISO                      (0x1 << 5)
1161 #define RT5677_PWR_SR4_ISO_BIT                  5
1162 #define RT5677_PWR_SR3_ISO                      (0x1 << 4)
1163 #define RT5677_PWR_SR3_ISO_BIT                  4
1164 #define RT5677_PWR_SR2_ISO                      (0x1 << 3)
1165 #define RT5677_PWR_SR2_ISO_BIT                  3
1166 #define RT5677_PWR_SR1_ISO                      (0x1 << 2)
1167 #define RT5677_PWR_SR1_ISO_BIT                  2
1168 #define RT5677_PWR_SR0_ISO                      (0x1 << 1)
1169 #define RT5677_PWR_SR0_ISO_BIT                  1
1170 #define RT5677_PWR_MLT_ISO                      (0x1 << 0)
1171 #define RT5677_PWR_MLT_ISO_BIT                  0
1172 
1173 /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
1174 #define RT5677_I2S_MS_MASK                      (0x1 << 15)
1175 #define RT5677_I2S_MS_SFT                       15
1176 #define RT5677_I2S_MS_M                         (0x0 << 15)
1177 #define RT5677_I2S_MS_S                         (0x1 << 15)
1178 #define RT5677_I2S_O_CP_MASK                    (0x3 << 10)
1179 #define RT5677_I2S_O_CP_SFT                     10
1180 #define RT5677_I2S_O_CP_OFF                     (0x0 << 10)
1181 #define RT5677_I2S_O_CP_U_LAW                   (0x1 << 10)
1182 #define RT5677_I2S_O_CP_A_LAW                   (0x2 << 10)
1183 #define RT5677_I2S_I_CP_MASK                    (0x3 << 8)
1184 #define RT5677_I2S_I_CP_SFT                     8
1185 #define RT5677_I2S_I_CP_OFF                     (0x0 << 8)
1186 #define RT5677_I2S_I_CP_U_LAW                   (0x1 << 8)
1187 #define RT5677_I2S_I_CP_A_LAW                   (0x2 << 8)
1188 #define RT5677_I2S_BP_MASK                      (0x1 << 7)
1189 #define RT5677_I2S_BP_SFT                       7
1190 #define RT5677_I2S_BP_NOR                       (0x0 << 7)
1191 #define RT5677_I2S_BP_INV                       (0x1 << 7)
1192 #define RT5677_I2S_DL_MASK                      (0x3 << 2)
1193 #define RT5677_I2S_DL_SFT                       2
1194 #define RT5677_I2S_DL_16                        (0x0 << 2)
1195 #define RT5677_I2S_DL_20                        (0x1 << 2)
1196 #define RT5677_I2S_DL_24                        (0x2 << 2)
1197 #define RT5677_I2S_DL_8                         (0x3 << 2)
1198 #define RT5677_I2S_DF_MASK                      (0x3 << 0)
1199 #define RT5677_I2S_DF_SFT                       0
1200 #define RT5677_I2S_DF_I2S                       (0x0 << 0)
1201 #define RT5677_I2S_DF_LEFT                      (0x1 << 0)
1202 #define RT5677_I2S_DF_PCM_A                     (0x2 << 0)
1203 #define RT5677_I2S_DF_PCM_B                     (0x3 << 0)
1204 
1205 /* Clock Tree Control 1 (0x73) */
1206 #define RT5677_I2S_PD1_MASK                     (0x7 << 12)
1207 #define RT5677_I2S_PD1_SFT                      12
1208 #define RT5677_I2S_PD1_1                        (0x0 << 12)
1209 #define RT5677_I2S_PD1_2                        (0x1 << 12)
1210 #define RT5677_I2S_PD1_3                        (0x2 << 12)
1211 #define RT5677_I2S_PD1_4                        (0x3 << 12)
1212 #define RT5677_I2S_PD1_6                        (0x4 << 12)
1213 #define RT5677_I2S_PD1_8                        (0x5 << 12)
1214 #define RT5677_I2S_PD1_12                       (0x6 << 12)
1215 #define RT5677_I2S_PD1_16                       (0x7 << 12)
1216 #define RT5677_I2S_BCLK_MS2_MASK                (0x1 << 11)
1217 #define RT5677_I2S_BCLK_MS2_SFT                 11
1218 #define RT5677_I2S_BCLK_MS2_32                  (0x0 << 11)
1219 #define RT5677_I2S_BCLK_MS2_64                  (0x1 << 11)
1220 #define RT5677_I2S_PD2_MASK                     (0x7 << 8)
1221 #define RT5677_I2S_PD2_SFT                      8
1222 #define RT5677_I2S_PD2_1                        (0x0 << 8)
1223 #define RT5677_I2S_PD2_2                        (0x1 << 8)
1224 #define RT5677_I2S_PD2_3                        (0x2 << 8)
1225 #define RT5677_I2S_PD2_4                        (0x3 << 8)
1226 #define RT5677_I2S_PD2_6                        (0x4 << 8)
1227 #define RT5677_I2S_PD2_8                        (0x5 << 8)
1228 #define RT5677_I2S_PD2_12                       (0x6 << 8)
1229 #define RT5677_I2S_PD2_16                       (0x7 << 8)
1230 #define RT5677_I2S_BCLK_MS3_MASK                (0x1 << 7)
1231 #define RT5677_I2S_BCLK_MS3_SFT                 7
1232 #define RT5677_I2S_BCLK_MS3_32                  (0x0 << 7)
1233 #define RT5677_I2S_BCLK_MS3_64                  (0x1 << 7)
1234 #define RT5677_I2S_PD3_MASK                     (0x7 << 4)
1235 #define RT5677_I2S_PD3_SFT                      4
1236 #define RT5677_I2S_PD3_1                        (0x0 << 4)
1237 #define RT5677_I2S_PD3_2                        (0x1 << 4)
1238 #define RT5677_I2S_PD3_3                        (0x2 << 4)
1239 #define RT5677_I2S_PD3_4                        (0x3 << 4)
1240 #define RT5677_I2S_PD3_6                        (0x4 << 4)
1241 #define RT5677_I2S_PD3_8                        (0x5 << 4)
1242 #define RT5677_I2S_PD3_12                       (0x6 << 4)
1243 #define RT5677_I2S_PD3_16                       (0x7 << 4)
1244 #define RT5677_I2S_BCLK_MS4_MASK                (0x1 << 3)
1245 #define RT5677_I2S_BCLK_MS4_SFT                 3
1246 #define RT5677_I2S_BCLK_MS4_32                  (0x0 << 3)
1247 #define RT5677_I2S_BCLK_MS4_64                  (0x1 << 3)
1248 #define RT5677_I2S_PD4_MASK                     (0x7 << 0)
1249 #define RT5677_I2S_PD4_SFT                      0
1250 #define RT5677_I2S_PD4_1                        (0x0 << 0)
1251 #define RT5677_I2S_PD4_2                        (0x1 << 0)
1252 #define RT5677_I2S_PD4_3                        (0x2 << 0)
1253 #define RT5677_I2S_PD4_4                        (0x3 << 0)
1254 #define RT5677_I2S_PD4_6                        (0x4 << 0)
1255 #define RT5677_I2S_PD4_8                        (0x5 << 0)
1256 #define RT5677_I2S_PD4_12                       (0x6 << 0)
1257 #define RT5677_I2S_PD4_16                       (0x7 << 0)
1258 
1259 /* Clock Tree Control 2 (0x74) */
1260 #define RT5677_I2S_PD5_MASK                     (0x7 << 12)
1261 #define RT5677_I2S_PD5_SFT                      12
1262 #define RT5677_I2S_PD5_1                        (0x0 << 12)
1263 #define RT5677_I2S_PD5_2                        (0x1 << 12)
1264 #define RT5677_I2S_PD5_3                        (0x2 << 12)
1265 #define RT5677_I2S_PD5_4                        (0x3 << 12)
1266 #define RT5677_I2S_PD5_6                        (0x4 << 12)
1267 #define RT5677_I2S_PD5_8                        (0x5 << 12)
1268 #define RT5677_I2S_PD5_12                       (0x6 << 12)
1269 #define RT5677_I2S_PD5_16                       (0x7 << 12)
1270 #define RT5677_I2S_PD6_MASK                     (0x7 << 8)
1271 #define RT5677_I2S_PD6_SFT                      8
1272 #define RT5677_I2S_PD6_1                        (0x0 << 8)
1273 #define RT5677_I2S_PD6_2                        (0x1 << 8)
1274 #define RT5677_I2S_PD6_3                        (0x2 << 8)
1275 #define RT5677_I2S_PD6_4                        (0x3 << 8)
1276 #define RT5677_I2S_PD6_6                        (0x4 << 8)
1277 #define RT5677_I2S_PD6_8                        (0x5 << 8)
1278 #define RT5677_I2S_PD6_12                       (0x6 << 8)
1279 #define RT5677_I2S_PD6_16                       (0x7 << 8)
1280 #define RT5677_I2S_PD7_MASK                     (0x7 << 4)
1281 #define RT5677_I2S_PD7_SFT                      4
1282 #define RT5677_I2S_PD7_1                        (0x0 << 4)
1283 #define RT5677_I2S_PD7_2                        (0x1 << 4)
1284 #define RT5677_I2S_PD7_3                        (0x2 << 4)
1285 #define RT5677_I2S_PD7_4                        (0x3 << 4)
1286 #define RT5677_I2S_PD7_6                        (0x4 << 4)
1287 #define RT5677_I2S_PD7_8                        (0x5 << 4)
1288 #define RT5677_I2S_PD7_12                       (0x6 << 4)
1289 #define RT5677_I2S_PD7_16                       (0x7 << 4)
1290 #define RT5677_I2S_PD8_MASK                     (0x7 << 0)
1291 #define RT5677_I2S_PD8_SFT                      0
1292 #define RT5677_I2S_PD8_1                        (0x0 << 0)
1293 #define RT5677_I2S_PD8_2                        (0x1 << 0)
1294 #define RT5677_I2S_PD8_3                        (0x2 << 0)
1295 #define RT5677_I2S_PD8_4                        (0x3 << 0)
1296 #define RT5677_I2S_PD8_6                        (0x4 << 0)
1297 #define RT5677_I2S_PD8_8                        (0x5 << 0)
1298 #define RT5677_I2S_PD8_12                       (0x6 << 0)
1299 #define RT5677_I2S_PD8_16                       (0x7 << 0)
1300 
1301 /* Clock Tree Control 3 (0x75) */
1302 #define RT5677_DSP_ASRC_O_MASK                  (0x3 << 6)
1303 #define RT5677_DSP_ASRC_O_SFT                   6
1304 #define RT5677_DSP_ASRC_O_1_0                   (0x0 << 6)
1305 #define RT5677_DSP_ASRC_O_1_5                   (0x1 << 6)
1306 #define RT5677_DSP_ASRC_O_2_0                   (0x2 << 6)
1307 #define RT5677_DSP_ASRC_O_3_0                   (0x3 << 6)
1308 #define RT5677_DSP_ASRC_I_MASK                  (0x3 << 4)
1309 #define RT5677_DSP_ASRC_I_SFT                   4
1310 #define RT5677_DSP_ASRC_I_1_0                   (0x0 << 4)
1311 #define RT5677_DSP_ASRC_I_1_5                   (0x1 << 4)
1312 #define RT5677_DSP_ASRC_I_2_0                   (0x2 << 4)
1313 #define RT5677_DSP_ASRC_I_3_0                   (0x3 << 4)
1314 #define RT5677_DSP_BUS_PD_MASK                  (0x7 << 0)
1315 #define RT5677_DSP_BUS_PD_SFT                   0
1316 #define RT5677_DSP_BUS_PD_1                     (0x0 << 0)
1317 #define RT5677_DSP_BUS_PD_2                     (0x1 << 0)
1318 #define RT5677_DSP_BUS_PD_3                     (0x2 << 0)
1319 #define RT5677_DSP_BUS_PD_4                     (0x3 << 0)
1320 #define RT5677_DSP_BUS_PD_6                     (0x4 << 0)
1321 #define RT5677_DSP_BUS_PD_8                     (0x5 << 0)
1322 #define RT5677_DSP_BUS_PD_12                    (0x6 << 0)
1323 #define RT5677_DSP_BUS_PD_16                    (0x7 << 0)
1324 
1325 #define RT5677_PLL_INP_MAX                      40000000
1326 #define RT5677_PLL_INP_MIN                      2048000
1327 /* PLL M/N/K Code Control 1 (0x7a 0x7c) */
1328 #define RT5677_PLL_N_MAX                        0x1ff
1329 #define RT5677_PLL_N_MASK                       (RT5677_PLL_N_MAX << 7)
1330 #define RT5677_PLL_N_SFT                        7
1331 #define RT5677_PLL_K_BP                         (0x1 << 5)
1332 #define RT5677_PLL_K_BP_SFT                     5
1333 #define RT5677_PLL_K_MAX                        0x1f
1334 #define RT5677_PLL_K_MASK                       (RT5677_PLL_K_MAX)
1335 #define RT5677_PLL_K_SFT                        0
1336 
1337 /* PLL M/N/K Code Control 2 (0x7b 0x7d) */
1338 #define RT5677_PLL_M_MAX                        0xf
1339 #define RT5677_PLL_M_MASK                       (RT5677_PLL_M_MAX << 12)
1340 #define RT5677_PLL_M_SFT                        12
1341 #define RT5677_PLL_M_BP                         (0x1 << 11)
1342 #define RT5677_PLL_M_BP_SFT                     11
1343 
1344 /* Global Clock Control 1 (0x80) */
1345 #define RT5677_SCLK_SRC_MASK                    (0x3 << 14)
1346 #define RT5677_SCLK_SRC_SFT                     14
1347 #define RT5677_SCLK_SRC_MCLK                    (0x0 << 14)
1348 #define RT5677_SCLK_SRC_PLL1                    (0x1 << 14)
1349 #define RT5677_SCLK_SRC_RCCLK                   (0x2 << 14) /* 25MHz */
1350 #define RT5677_SCLK_SRC_SLIM                    (0x3 << 14)
1351 #define RT5677_PLL1_SRC_MASK                    (0x7 << 11)
1352 #define RT5677_PLL1_SRC_SFT                     11
1353 #define RT5677_PLL1_SRC_MCLK                    (0x0 << 11)
1354 #define RT5677_PLL1_SRC_BCLK1                   (0x1 << 11)
1355 #define RT5677_PLL1_SRC_BCLK2                   (0x2 << 11)
1356 #define RT5677_PLL1_SRC_BCLK3                   (0x3 << 11)
1357 #define RT5677_PLL1_SRC_BCLK4                   (0x4 << 11)
1358 #define RT5677_PLL1_SRC_RCCLK                   (0x5 << 11)
1359 #define RT5677_PLL1_SRC_SLIM                    (0x6 << 11)
1360 #define RT5677_MCLK_SRC_MASK                    (0x1 << 10)
1361 #define RT5677_MCLK_SRC_SFT                     10
1362 #define RT5677_MCLK1_SRC                        (0x0 << 10)
1363 #define RT5677_MCLK2_SRC                        (0x1 << 10)
1364 #define RT5677_PLL1_PD_MASK                     (0x1 << 8)
1365 #define RT5677_PLL1_PD_SFT                      8
1366 #define RT5677_PLL1_PD_1                        (0x0 << 8)
1367 #define RT5677_PLL1_PD_2                        (0x1 << 8)
1368 #define RT5677_DAC_OSR_MASK                     (0x3 << 6)
1369 #define RT5677_DAC_OSR_SFT                      6
1370 #define RT5677_DAC_OSR_128                      (0x0 << 6)
1371 #define RT5677_DAC_OSR_64                       (0x1 << 6)
1372 #define RT5677_DAC_OSR_32                       (0x2 << 6)
1373 #define RT5677_ADC_OSR_MASK                     (0x3 << 4)
1374 #define RT5677_ADC_OSR_SFT                      4
1375 #define RT5677_ADC_OSR_128                      (0x0 << 4)
1376 #define RT5677_ADC_OSR_64                       (0x1 << 4)
1377 #define RT5677_ADC_OSR_32                       (0x2 << 4)
1378 
1379 /* Global Clock Control 2 (0x81) */
1380 #define RT5677_PLL2_PR_SRC_MASK                 (0x1 << 15)
1381 #define RT5677_PLL2_PR_SRC_SFT                  15
1382 #define RT5677_PLL2_PR_SRC_MCLK1                (0x0 << 15)
1383 #define RT5677_PLL2_PR_SRC_MCLK2                (0x1 << 15)
1384 #define RT5677_PLL2_SRC_MASK                    (0x7 << 12)
1385 #define RT5677_PLL2_SRC_SFT                     12
1386 #define RT5677_PLL2_SRC_MCLK                    (0x0 << 12)
1387 #define RT5677_PLL2_SRC_BCLK1                   (0x1 << 12)
1388 #define RT5677_PLL2_SRC_BCLK2                   (0x2 << 12)
1389 #define RT5677_PLL2_SRC_BCLK3                   (0x3 << 12)
1390 #define RT5677_PLL2_SRC_BCLK4                   (0x4 << 12)
1391 #define RT5677_PLL2_SRC_RCCLK                   (0x5 << 12)
1392 #define RT5677_PLL2_SRC_SLIM                    (0x6 << 12)
1393 #define RT5677_DSP_ASRC_O_SRC                   (0x3 << 10)
1394 #define RT5677_DSP_ASRC_O_SRC_SFT               10
1395 #define RT5677_DSP_ASRC_O_MCLK                  (0x0 << 10)
1396 #define RT5677_DSP_ASRC_O_PLL1                  (0x1 << 10)
1397 #define RT5677_DSP_ASRC_O_SLIM                  (0x2 << 10)
1398 #define RT5677_DSP_ASRC_O_RCCLK                 (0x3 << 10)
1399 #define RT5677_DSP_ASRC_I_SRC                   (0x3 << 8)
1400 #define RT5677_DSP_ASRC_I_SRC_SFT               8
1401 #define RT5677_DSP_ASRC_I_MCLK                  (0x0 << 8)
1402 #define RT5677_DSP_ASRC_I_PLL1                  (0x1 << 8)
1403 #define RT5677_DSP_ASRC_I_SLIM                  (0x2 << 8)
1404 #define RT5677_DSP_ASRC_I_RCCLK                 (0x3 << 8)
1405 #define RT5677_DSP_CLK_SRC_MASK                 (0x1 << 7)
1406 #define RT5677_DSP_CLK_SRC_SFT                  7
1407 #define RT5677_DSP_CLK_SRC_PLL2                 (0x0 << 7)
1408 #define RT5677_DSP_CLK_SRC_BYPASS               (0x1 << 7)
1409 
1410 /* ASRC Control 3 (0x85) */
1411 #define RT5677_DA_STO_CLK_SEL_MASK              (0xf << 12)
1412 #define RT5677_DA_STO_CLK_SEL_SFT               12
1413 #define RT5677_DA_MONO2L_CLK_SEL_MASK           (0xf << 4)
1414 #define RT5677_DA_MONO2L_CLK_SEL_SFT            4
1415 #define RT5677_DA_MONO2R_CLK_SEL_MASK           (0xf << 0)
1416 #define RT5677_DA_MONO2R_CLK_SEL_SFT            0
1417 
1418 /* ASRC Control 4 (0x86) */
1419 #define RT5677_DA_MONO3L_CLK_SEL_MASK           (0xf << 12)
1420 #define RT5677_DA_MONO3L_CLK_SEL_SFT            12
1421 #define RT5677_DA_MONO3R_CLK_SEL_MASK           (0xf << 8)
1422 #define RT5677_DA_MONO3R_CLK_SEL_SFT            8
1423 #define RT5677_DA_MONO4L_CLK_SEL_MASK           (0xf << 4)
1424 #define RT5677_DA_MONO4L_CLK_SEL_SFT            4
1425 #define RT5677_DA_MONO4R_CLK_SEL_MASK           (0xf << 0)
1426 #define RT5677_DA_MONO4R_CLK_SEL_SFT            0
1427 
1428 /* ASRC Control 5 (0x87) */
1429 #define RT5677_AD_STO1_CLK_SEL_MASK             (0xf << 12)
1430 #define RT5677_AD_STO1_CLK_SEL_SFT              12
1431 #define RT5677_AD_STO2_CLK_SEL_MASK             (0xf << 8)
1432 #define RT5677_AD_STO2_CLK_SEL_SFT              8
1433 #define RT5677_AD_STO3_CLK_SEL_MASK             (0xf << 4)
1434 #define RT5677_AD_STO3_CLK_SEL_SFT              4
1435 #define RT5677_AD_STO4_CLK_SEL_MASK             (0xf << 0)
1436 #define RT5677_AD_STO4_CLK_SEL_SFT              0
1437 
1438 /* ASRC Control 6 (0x88) */
1439 #define RT5677_AD_MONOL_CLK_SEL_MASK            (0xf << 12)
1440 #define RT5677_AD_MONOL_CLK_SEL_SFT             12
1441 #define RT5677_AD_MONOR_CLK_SEL_MASK            (0xf << 8)
1442 #define RT5677_AD_MONOR_CLK_SEL_SFT             8
1443 
1444 /* ASRC Control 7 (0x89) */
1445 #define RT5677_DSP_OB_0_3_CLK_SEL_MASK          (0xf << 12)
1446 #define RT5677_DSP_OB_0_3_CLK_SEL_SFT           12
1447 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK          (0xf << 8)
1448 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT           8
1449 
1450 /* ASRC Control 8 (0x8a) */
1451 #define RT5677_I2S1_CLK_SEL_MASK                (0xf << 12)
1452 #define RT5677_I2S1_CLK_SEL_SFT                 12
1453 #define RT5677_I2S2_CLK_SEL_MASK                (0xf << 8)
1454 #define RT5677_I2S2_CLK_SEL_SFT                 8
1455 #define RT5677_I2S3_CLK_SEL_MASK                (0xf << 4)
1456 #define RT5677_I2S3_CLK_SEL_SFT                 4
1457 #define RT5677_I2S4_CLK_SEL_MASK                (0xf)
1458 #define RT5677_I2S4_CLK_SEL_SFT                 0
1459 
1460 /* VAD Function Control 4 (0x9f) */
1461 #define RT5677_VAD_SRC_MASK                     (0x7 << 8)
1462 #define RT5677_VAD_SRC_SFT                      8
1463 
1464 /* DSP InBound Control (0xa3) */
1465 #define RT5677_IB01_SRC_MASK                    (0x7 << 12)
1466 #define RT5677_IB01_SRC_SFT                     12
1467 #define RT5677_IB23_SRC_MASK                    (0x7 << 8)
1468 #define RT5677_IB23_SRC_SFT                     8
1469 #define RT5677_IB45_SRC_MASK                    (0x7 << 4)
1470 #define RT5677_IB45_SRC_SFT                     4
1471 #define RT5677_IB6_SRC_MASK                     (0x7 << 0)
1472 #define RT5677_IB6_SRC_SFT                      0
1473 
1474 /* DSP InBound Control (0xa4) */
1475 #define RT5677_IB7_SRC_MASK                     (0x7 << 12)
1476 #define RT5677_IB7_SRC_SFT                      12
1477 #define RT5677_IB8_SRC_MASK                     (0x7 << 8)
1478 #define RT5677_IB8_SRC_SFT                      8
1479 #define RT5677_IB9_SRC_MASK                     (0x7 << 4)
1480 #define RT5677_IB9_SRC_SFT                      4
1481 
1482 /* DSP In/OutBound Control (0xa5) */
1483 #define RT5677_SEL_SRC_OB23                     (0x1 << 4)
1484 #define RT5677_SEL_SRC_OB23_SFT                 4
1485 #define RT5677_SEL_SRC_OB01                     (0x1 << 3)
1486 #define RT5677_SEL_SRC_OB01_SFT                 3
1487 #define RT5677_SEL_SRC_IB45                     (0x1 << 2)
1488 #define RT5677_SEL_SRC_IB45_SFT                 2
1489 #define RT5677_SEL_SRC_IB23                     (0x1 << 1)
1490 #define RT5677_SEL_SRC_IB23_SFT                 1
1491 #define RT5677_SEL_SRC_IB01                     (0x1 << 0)
1492 #define RT5677_SEL_SRC_IB01_SFT                 0
1493 
1494 /* Jack Detect Control 1 (0xb5) */
1495 #define RT5677_SEL_GPIO_JD1_MASK                (0x3 << 14)
1496 #define RT5677_SEL_GPIO_JD1_SFT                 14
1497 #define RT5677_SEL_GPIO_JD2_MASK                (0x3 << 12)
1498 #define RT5677_SEL_GPIO_JD2_SFT                 12
1499 #define RT5677_SEL_GPIO_JD3_MASK                (0x3 << 10)
1500 #define RT5677_SEL_GPIO_JD3_SFT                 10
1501 
1502 /* IRQ Control 1 (0xbd) */
1503 #define RT5677_STA_GPIO_JD1                     (0x1 << 15)
1504 #define RT5677_STA_GPIO_JD1_SFT                 15
1505 #define RT5677_EN_IRQ_GPIO_JD1                  (0x1 << 14)
1506 #define RT5677_EN_IRQ_GPIO_JD1_SFT              14
1507 #define RT5677_EN_GPIO_JD1_STICKY               (0x1 << 13)
1508 #define RT5677_EN_GPIO_JD1_STICKY_SFT           13
1509 #define RT5677_INV_GPIO_JD1                     (0x1 << 12)
1510 #define RT5677_INV_GPIO_JD1_SFT                 12
1511 #define RT5677_STA_GPIO_JD2                     (0x1 << 11)
1512 #define RT5677_STA_GPIO_JD2_SFT                 11
1513 #define RT5677_EN_IRQ_GPIO_JD2                  (0x1 << 10)
1514 #define RT5677_EN_IRQ_GPIO_JD2_SFT              10
1515 #define RT5677_EN_GPIO_JD2_STICKY               (0x1 << 9)
1516 #define RT5677_EN_GPIO_JD2_STICKY_SFT           9
1517 #define RT5677_INV_GPIO_JD2                     (0x1 << 8)
1518 #define RT5677_INV_GPIO_JD2_SFT                 8
1519 #define RT5677_STA_MICBIAS1_OVCD                (0x1 << 7)
1520 #define RT5677_STA_MICBIAS1_OVCD_SFT            7
1521 #define RT5677_EN_IRQ_MICBIAS1_OVCD             (0x1 << 6)
1522 #define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT         6
1523 #define RT5677_EN_MICBIAS1_OVCD_STICKY          (0x1 << 5)
1524 #define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT      5
1525 #define RT5677_INV_MICBIAS1_OVCD                (0x1 << 4)
1526 #define RT5677_INV_MICBIAS1_OVCD_SFT            4
1527 #define RT5677_STA_GPIO_JD3                     (0x1 << 3)
1528 #define RT5677_STA_GPIO_JD3_SFT                 3
1529 #define RT5677_EN_IRQ_GPIO_JD3                  (0x1 << 2)
1530 #define RT5677_EN_IRQ_GPIO_JD3_SFT              2
1531 #define RT5677_EN_GPIO_JD3_STICKY               (0x1 << 1)
1532 #define RT5677_EN_GPIO_JD3_STICKY_SFT           1
1533 #define RT5677_INV_GPIO_JD3                     (0x1 << 0)
1534 #define RT5677_INV_GPIO_JD3_SFT                 0
1535 
1536 /* GPIO status (0xbf) */
1537 #define RT5677_GPIO6_STATUS_MASK                (0x1 << 5)
1538 #define RT5677_GPIO6_STATUS_SFT                 5
1539 #define RT5677_GPIO5_STATUS_MASK                (0x1 << 4)
1540 #define RT5677_GPIO5_STATUS_SFT                 4
1541 #define RT5677_GPIO4_STATUS_MASK                (0x1 << 3)
1542 #define RT5677_GPIO4_STATUS_SFT                 3
1543 #define RT5677_GPIO3_STATUS_MASK                (0x1 << 2)
1544 #define RT5677_GPIO3_STATUS_SFT                 2
1545 #define RT5677_GPIO2_STATUS_MASK                (0x1 << 1)
1546 #define RT5677_GPIO2_STATUS_SFT                 1
1547 #define RT5677_GPIO1_STATUS_MASK                (0x1 << 0)
1548 #define RT5677_GPIO1_STATUS_SFT                 0
1549 
1550 /* GPIO Control 1 (0xc0) */
1551 #define RT5677_GPIO1_PIN_MASK                   (0x1 << 15)
1552 #define RT5677_GPIO1_PIN_SFT                    15
1553 #define RT5677_GPIO1_PIN_GPIO1                  (0x0 << 15)
1554 #define RT5677_GPIO1_PIN_IRQ                    (0x1 << 15)
1555 #define RT5677_IPTV_MODE_MASK                   (0x1 << 14)
1556 #define RT5677_IPTV_MODE_SFT                    14
1557 #define RT5677_IPTV_MODE_GPIO                   (0x0 << 14)
1558 #define RT5677_IPTV_MODE_IPTV                   (0x1 << 14)
1559 #define RT5677_FUNC_MODE_MASK                   (0x1 << 13)
1560 #define RT5677_FUNC_MODE_SFT                    13
1561 #define RT5677_FUNC_MODE_DMIC_GPIO              (0x0 << 13)
1562 #define RT5677_FUNC_MODE_JTAG                   (0x1 << 13)
1563 
1564 /* GPIO Control 2 (0xc1) */
1565 #define RT5677_GPIO5_DIR_MASK                   (0x1 << 14)
1566 #define RT5677_GPIO5_DIR_SFT                    14
1567 #define RT5677_GPIO5_DIR_IN                     (0x0 << 14)
1568 #define RT5677_GPIO5_DIR_OUT                    (0x1 << 14)
1569 #define RT5677_GPIO5_OUT_MASK                   (0x1 << 13)
1570 #define RT5677_GPIO5_OUT_SFT                    13
1571 #define RT5677_GPIO5_OUT_LO                     (0x0 << 13)
1572 #define RT5677_GPIO5_OUT_HI                     (0x1 << 13)
1573 #define RT5677_GPIO5_P_MASK                     (0x1 << 12)
1574 #define RT5677_GPIO5_P_SFT                      12
1575 #define RT5677_GPIO5_P_NOR                      (0x0 << 12)
1576 #define RT5677_GPIO5_P_INV                      (0x1 << 12)
1577 #define RT5677_GPIO4_DIR_MASK                   (0x1 << 11)
1578 #define RT5677_GPIO4_DIR_SFT                    11
1579 #define RT5677_GPIO4_DIR_IN                     (0x0 << 11)
1580 #define RT5677_GPIO4_DIR_OUT                    (0x1 << 11)
1581 #define RT5677_GPIO4_OUT_MASK                   (0x1 << 10)
1582 #define RT5677_GPIO4_OUT_SFT                    10
1583 #define RT5677_GPIO4_OUT_LO                     (0x0 << 10)
1584 #define RT5677_GPIO4_OUT_HI                     (0x1 << 10)
1585 #define RT5677_GPIO4_P_MASK                     (0x1 << 9)
1586 #define RT5677_GPIO4_P_SFT                      9
1587 #define RT5677_GPIO4_P_NOR                      (0x0 << 9)
1588 #define RT5677_GPIO4_P_INV                      (0x1 << 9)
1589 #define RT5677_GPIO3_DIR_MASK                   (0x1 << 8)
1590 #define RT5677_GPIO3_DIR_SFT                    8
1591 #define RT5677_GPIO3_DIR_IN                     (0x0 << 8)
1592 #define RT5677_GPIO3_DIR_OUT                    (0x1 << 8)
1593 #define RT5677_GPIO3_OUT_MASK                   (0x1 << 7)
1594 #define RT5677_GPIO3_OUT_SFT                    7
1595 #define RT5677_GPIO3_OUT_LO                     (0x0 << 7)
1596 #define RT5677_GPIO3_OUT_HI                     (0x1 << 7)
1597 #define RT5677_GPIO3_P_MASK                     (0x1 << 6)
1598 #define RT5677_GPIO3_P_SFT                      6
1599 #define RT5677_GPIO3_P_NOR                      (0x0 << 6)
1600 #define RT5677_GPIO3_P_INV                      (0x1 << 6)
1601 #define RT5677_GPIO2_DIR_MASK                   (0x1 << 5)
1602 #define RT5677_GPIO2_DIR_SFT                    5
1603 #define RT5677_GPIO2_DIR_IN                     (0x0 << 5)
1604 #define RT5677_GPIO2_DIR_OUT                    (0x1 << 5)
1605 #define RT5677_GPIO2_OUT_MASK                   (0x1 << 4)
1606 #define RT5677_GPIO2_OUT_SFT                    4
1607 #define RT5677_GPIO2_OUT_LO                     (0x0 << 4)
1608 #define RT5677_GPIO2_OUT_HI                     (0x1 << 4)
1609 #define RT5677_GPIO2_P_MASK                     (0x1 << 3)
1610 #define RT5677_GPIO2_P_SFT                      3
1611 #define RT5677_GPIO2_P_NOR                      (0x0 << 3)
1612 #define RT5677_GPIO2_P_INV                      (0x1 << 3)
1613 #define RT5677_GPIO1_DIR_MASK                   (0x1 << 2)
1614 #define RT5677_GPIO1_DIR_SFT                    2
1615 #define RT5677_GPIO1_DIR_IN                     (0x0 << 2)
1616 #define RT5677_GPIO1_DIR_OUT                    (0x1 << 2)
1617 #define RT5677_GPIO1_OUT_MASK                   (0x1 << 1)
1618 #define RT5677_GPIO1_OUT_SFT                    1
1619 #define RT5677_GPIO1_OUT_LO                     (0x0 << 1)
1620 #define RT5677_GPIO1_OUT_HI                     (0x1 << 1)
1621 #define RT5677_GPIO1_P_MASK                     (0x1 << 0)
1622 #define RT5677_GPIO1_P_SFT                      0
1623 #define RT5677_GPIO1_P_NOR                      (0x0 << 0)
1624 #define RT5677_GPIO1_P_INV                      (0x1 << 0)
1625 
1626 /* GPIO Control 3 (0xc2) */
1627 #define RT5677_GPIO6_DIR_MASK                   (0x1 << 2)
1628 #define RT5677_GPIO6_DIR_SFT                    2
1629 #define RT5677_GPIO6_DIR_IN                     (0x0 << 2)
1630 #define RT5677_GPIO6_DIR_OUT                    (0x1 << 2)
1631 #define RT5677_GPIO6_OUT_MASK                   (0x1 << 1)
1632 #define RT5677_GPIO6_OUT_SFT                    1
1633 #define RT5677_GPIO6_OUT_LO                     (0x0 << 1)
1634 #define RT5677_GPIO6_OUT_HI                     (0x1 << 1)
1635 #define RT5677_GPIO6_P_MASK                     (0x1 << 0)
1636 #define RT5677_GPIO6_P_SFT                      0
1637 #define RT5677_GPIO6_P_NOR                      (0x0 << 0)
1638 #define RT5677_GPIO6_P_INV                      (0x1 << 0)
1639 
1640 /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
1641 #define RT5677_DSP_IB_01_H                      (0x1 << 15)
1642 #define RT5677_DSP_IB_01_H_SFT                  15
1643 #define RT5677_DSP_IB_23_H                      (0x1 << 14)
1644 #define RT5677_DSP_IB_23_H_SFT                  14
1645 #define RT5677_DSP_IB_45_H                      (0x1 << 13)
1646 #define RT5677_DSP_IB_45_H_SFT                  13
1647 #define RT5677_DSP_IB_6_H                       (0x1 << 12)
1648 #define RT5677_DSP_IB_6_H_SFT                   12
1649 #define RT5677_DSP_IB_7_H                       (0x1 << 11)
1650 #define RT5677_DSP_IB_7_H_SFT                   11
1651 #define RT5677_DSP_IB_8_H                       (0x1 << 10)
1652 #define RT5677_DSP_IB_8_H_SFT                   10
1653 #define RT5677_DSP_IB_9_H                       (0x1 << 9)
1654 #define RT5677_DSP_IB_9_H_SFT                   9
1655 #define RT5677_DSP_IB_01_L                      (0x1 << 7)
1656 #define RT5677_DSP_IB_01_L_SFT                  7
1657 #define RT5677_DSP_IB_23_L                      (0x1 << 6)
1658 #define RT5677_DSP_IB_23_L_SFT                  6
1659 #define RT5677_DSP_IB_45_L                      (0x1 << 5)
1660 #define RT5677_DSP_IB_45_L_SFT                  5
1661 #define RT5677_DSP_IB_6_L                       (0x1 << 4)
1662 #define RT5677_DSP_IB_6_L_SFT                   4
1663 #define RT5677_DSP_IB_7_L                       (0x1 << 3)
1664 #define RT5677_DSP_IB_7_L_SFT                   3
1665 #define RT5677_DSP_IB_8_L                       (0x1 << 2)
1666 #define RT5677_DSP_IB_8_L_SFT                   2
1667 #define RT5677_DSP_IB_9_L                       (0x1 << 1)
1668 #define RT5677_DSP_IB_9_L_SFT                   1
1669 
1670 /* General Control2 (0xfc)*/
1671 #define RT5677_GPIO5_FUNC_MASK                  (0x1 << 9)
1672 #define RT5677_GPIO5_FUNC_GPIO                  (0x0 << 9)
1673 #define RT5677_GPIO5_FUNC_DMIC                  (0x1 << 9)
1674 
1675 #define RT5677_FIRMWARE1        "rt5677_dsp_fw1.bin"
1676 #define RT5677_FIRMWARE2        "rt5677_dsp_fw2.bin"
1677 
1678 /* System Clock Source */
1679 enum {
1680         RT5677_SCLK_S_MCLK,
1681         RT5677_SCLK_S_PLL1,
1682         RT5677_SCLK_S_RCCLK,
1683 };
1684 
1685 /* PLL1 Source */
1686 enum {
1687         RT5677_PLL1_S_MCLK,
1688         RT5677_PLL1_S_BCLK1,
1689         RT5677_PLL1_S_BCLK2,
1690         RT5677_PLL1_S_BCLK3,
1691         RT5677_PLL1_S_BCLK4,
1692 };
1693 
1694 enum {
1695         RT5677_AIF1,
1696         RT5677_AIF2,
1697         RT5677_AIF3,
1698         RT5677_AIF4,
1699         RT5677_AIF5,
1700         RT5677_AIFS,
1701 };
1702 
1703 enum {
1704         RT5677_GPIO1,
1705         RT5677_GPIO2,
1706         RT5677_GPIO3,
1707         RT5677_GPIO4,
1708         RT5677_GPIO5,
1709         RT5677_GPIO6,
1710         RT5677_GPIO_NUM,
1711 };
1712 
1713 enum {
1714         RT5677_IRQ_JD1,
1715         RT5677_IRQ_JD2,
1716         RT5677_IRQ_JD3,
1717 };
1718 
1719 enum rt5677_type {
1720         RT5677,
1721         RT5676,
1722 };
1723 
1724 /* ASRC clock source selection */
1725 enum {
1726         RT5677_CLK_SEL_SYS,
1727         RT5677_CLK_SEL_I2S1_ASRC,
1728         RT5677_CLK_SEL_I2S2_ASRC,
1729         RT5677_CLK_SEL_I2S3_ASRC,
1730         RT5677_CLK_SEL_I2S4_ASRC,
1731         RT5677_CLK_SEL_I2S5_ASRC,
1732         RT5677_CLK_SEL_I2S6_ASRC,
1733         RT5677_CLK_SEL_SYS2,
1734         RT5677_CLK_SEL_SYS3,
1735         RT5677_CLK_SEL_SYS4,
1736         RT5677_CLK_SEL_SYS5,
1737         RT5677_CLK_SEL_SYS6,
1738         RT5677_CLK_SEL_SYS7,
1739 };
1740 
1741 /* filter mask */
1742 enum {
1743         RT5677_DA_STEREO_FILTER = 0x1,
1744         RT5677_DA_MONO2_L_FILTER = (0x1 << 1),
1745         RT5677_DA_MONO2_R_FILTER = (0x1 << 2),
1746         RT5677_DA_MONO3_L_FILTER = (0x1 << 3),
1747         RT5677_DA_MONO3_R_FILTER = (0x1 << 4),
1748         RT5677_DA_MONO4_L_FILTER = (0x1 << 5),
1749         RT5677_DA_MONO4_R_FILTER = (0x1 << 6),
1750         RT5677_AD_STEREO1_FILTER = (0x1 << 7),
1751         RT5677_AD_STEREO2_FILTER = (0x1 << 8),
1752         RT5677_AD_STEREO3_FILTER = (0x1 << 9),
1753         RT5677_AD_STEREO4_FILTER = (0x1 << 10),
1754         RT5677_AD_MONO_L_FILTER = (0x1 << 11),
1755         RT5677_AD_MONO_R_FILTER = (0x1 << 12),
1756         RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
1757         RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
1758         RT5677_I2S1_SOURCE = (0x1 << 15),
1759         RT5677_I2S2_SOURCE = (0x1 << 16),
1760         RT5677_I2S3_SOURCE = (0x1 << 17),
1761         RT5677_I2S4_SOURCE = (0x1 << 18),
1762 };
1763 
1764 struct rt5677_priv {
1765         struct snd_soc_codec *codec;
1766         struct rt5677_platform_data pdata;
1767         struct regmap *regmap, *regmap_physical;
1768         const struct firmware *fw1, *fw2;
1769         struct mutex dsp_cmd_lock, dsp_pri_lock;
1770 
1771         int sysclk;
1772         int sysclk_src;
1773         int lrck[RT5677_AIFS];
1774         int bclk[RT5677_AIFS];
1775         int master[RT5677_AIFS];
1776         int pll_src;
1777         int pll_in;
1778         int pll_out;
1779         struct gpio_desc *pow_ldo2; /* POW_LDO2 pin */
1780         struct gpio_desc *reset_pin; /* RESET pin */
1781         enum rt5677_type type;
1782 #ifdef CONFIG_GPIOLIB
1783         struct gpio_chip gpio_chip;
1784 #endif
1785         bool dsp_vad_en;
1786         struct regmap_irq_chip_data *irq_data;
1787         bool is_dsp_mode;
1788         bool is_vref_slow;
1789 };
1790 
1791 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1792                 unsigned int filter_mask, unsigned int clk_src);
1793 
1794 #endif /* __RT5677_H__ */
1795 

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