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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/sgtl5000.c

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  1 /*
  2  * sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
  3  *
  4  * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #include <linux/module.h>
 12 #include <linux/moduleparam.h>
 13 #include <linux/init.h>
 14 #include <linux/delay.h>
 15 #include <linux/slab.h>
 16 #include <linux/pm.h>
 17 #include <linux/i2c.h>
 18 #include <linux/clk.h>
 19 #include <linux/log2.h>
 20 #include <linux/regmap.h>
 21 #include <linux/regulator/driver.h>
 22 #include <linux/regulator/machine.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/of_device.h>
 25 #include <sound/core.h>
 26 #include <sound/tlv.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/soc-dapm.h>
 31 #include <sound/initval.h>
 32 
 33 #include "sgtl5000.h"
 34 
 35 #define SGTL5000_DAP_REG_OFFSET 0x0100
 36 #define SGTL5000_MAX_REG_OFFSET 0x013A
 37 
 38 /* default value of sgtl5000 registers */
 39 static const struct reg_default sgtl5000_reg_defaults[] = {
 40         { SGTL5000_CHIP_DIG_POWER,              0x0000 },
 41         { SGTL5000_CHIP_I2S_CTRL,               0x0010 },
 42         { SGTL5000_CHIP_SSS_CTRL,               0x0010 },
 43         { SGTL5000_CHIP_ADCDAC_CTRL,            0x020c },
 44         { SGTL5000_CHIP_DAC_VOL,                0x3c3c },
 45         { SGTL5000_CHIP_PAD_STRENGTH,           0x015f },
 46         { SGTL5000_CHIP_ANA_ADC_CTRL,           0x0000 },
 47         { SGTL5000_CHIP_ANA_HP_CTRL,            0x1818 },
 48         { SGTL5000_CHIP_ANA_CTRL,               0x0111 },
 49         { SGTL5000_CHIP_REF_CTRL,               0x0000 },
 50         { SGTL5000_CHIP_MIC_CTRL,               0x0000 },
 51         { SGTL5000_CHIP_LINE_OUT_CTRL,          0x0000 },
 52         { SGTL5000_CHIP_LINE_OUT_VOL,           0x0404 },
 53         { SGTL5000_CHIP_PLL_CTRL,               0x5000 },
 54         { SGTL5000_CHIP_CLK_TOP_CTRL,           0x0000 },
 55         { SGTL5000_CHIP_ANA_STATUS,             0x0000 },
 56         { SGTL5000_CHIP_SHORT_CTRL,             0x0000 },
 57         { SGTL5000_CHIP_ANA_TEST2,              0x0000 },
 58         { SGTL5000_DAP_CTRL,                    0x0000 },
 59         { SGTL5000_DAP_PEQ,                     0x0000 },
 60         { SGTL5000_DAP_BASS_ENHANCE,            0x0040 },
 61         { SGTL5000_DAP_BASS_ENHANCE_CTRL,       0x051f },
 62         { SGTL5000_DAP_AUDIO_EQ,                0x0000 },
 63         { SGTL5000_DAP_SURROUND,                0x0040 },
 64         { SGTL5000_DAP_EQ_BASS_BAND0,           0x002f },
 65         { SGTL5000_DAP_EQ_BASS_BAND1,           0x002f },
 66         { SGTL5000_DAP_EQ_BASS_BAND2,           0x002f },
 67         { SGTL5000_DAP_EQ_BASS_BAND3,           0x002f },
 68         { SGTL5000_DAP_EQ_BASS_BAND4,           0x002f },
 69         { SGTL5000_DAP_MAIN_CHAN,               0x8000 },
 70         { SGTL5000_DAP_MIX_CHAN,                0x0000 },
 71         { SGTL5000_DAP_AVC_CTRL,                0x0510 },
 72         { SGTL5000_DAP_AVC_THRESHOLD,           0x1473 },
 73         { SGTL5000_DAP_AVC_ATTACK,              0x0028 },
 74         { SGTL5000_DAP_AVC_DECAY,               0x0050 },
 75 };
 76 
 77 /* AVC: Threshold dB -> register: pre-calculated values */
 78 static const u16 avc_thr_db2reg[97] = {
 79         0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
 80         0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
 81         0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
 82         0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
 83         0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
 84         0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
 85         0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
 86         0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
 87         0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
 88         0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
 89         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
 90 
 91 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
 92 enum sgtl5000_regulator_supplies {
 93         VDDA,
 94         VDDIO,
 95         VDDD,
 96         SGTL5000_SUPPLY_NUM
 97 };
 98 
 99 /* vddd is optional supply */
100 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
101         "VDDA",
102         "VDDIO",
103         "VDDD"
104 };
105 
106 #define LDO_VOLTAGE             1200000
107 #define LINREG_VDDD     ((1600 - LDO_VOLTAGE / 1000) / 50)
108 
109 enum sgtl5000_micbias_resistor {
110         SGTL5000_MICBIAS_OFF = 0,
111         SGTL5000_MICBIAS_2K = 2,
112         SGTL5000_MICBIAS_4K = 4,
113         SGTL5000_MICBIAS_8K = 8,
114 };
115 
116 enum  {
117         I2S_LRCLK_STRENGTH_DISABLE,
118         I2S_LRCLK_STRENGTH_LOW,
119         I2S_LRCLK_STRENGTH_MEDIUM,
120         I2S_LRCLK_STRENGTH_HIGH,
121 };
122 
123 /* sgtl5000 private structure in codec */
124 struct sgtl5000_priv {
125         int sysclk;     /* sysclk rate */
126         int master;     /* i2s master or not */
127         int fmt;        /* i2s data format */
128         struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
129         int num_supplies;
130         struct regmap *regmap;
131         struct clk *mclk;
132         int revision;
133         u8 micbias_resistor;
134         u8 micbias_voltage;
135         u8 lrclk_strength;
136 };
137 
138 /*
139  * mic_bias power on/off share the same register bits with
140  * output impedance of mic bias, when power on mic bias, we
141  * need reclaim it to impedance value.
142  * 0x0 = Powered off
143  * 0x1 = 2Kohm
144  * 0x2 = 4Kohm
145  * 0x3 = 8Kohm
146  */
147 static int mic_bias_event(struct snd_soc_dapm_widget *w,
148         struct snd_kcontrol *kcontrol, int event)
149 {
150         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
151         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
152 
153         switch (event) {
154         case SND_SOC_DAPM_POST_PMU:
155                 /* change mic bias resistor */
156                 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
157                         SGTL5000_BIAS_R_MASK,
158                         sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
159                 break;
160 
161         case SND_SOC_DAPM_PRE_PMD:
162                 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
163                                 SGTL5000_BIAS_R_MASK, 0);
164                 break;
165         }
166         return 0;
167 }
168 
169 /*
170  * As manual described, ADC/DAC only works when VAG powerup,
171  * So enabled VAG before ADC/DAC up.
172  * In power down case, we need wait 400ms when vag fully ramped down.
173  */
174 static int power_vag_event(struct snd_soc_dapm_widget *w,
175         struct snd_kcontrol *kcontrol, int event)
176 {
177         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
178         const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
179 
180         switch (event) {
181         case SND_SOC_DAPM_POST_PMU:
182                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
183                         SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
184                 msleep(400);
185                 break;
186 
187         case SND_SOC_DAPM_PRE_PMD:
188                 /*
189                  * Don't clear VAG_POWERUP, when both DAC and ADC are
190                  * operational to prevent inadvertently starving the
191                  * other one of them.
192                  */
193                 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
194                                 mask) != mask) {
195                         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
196                                 SGTL5000_VAG_POWERUP, 0);
197                         msleep(400);
198                 }
199                 break;
200         default:
201                 break;
202         }
203 
204         return 0;
205 }
206 
207 /* input sources for ADC */
208 static const char *adc_mux_text[] = {
209         "MIC_IN", "LINE_IN"
210 };
211 
212 static SOC_ENUM_SINGLE_DECL(adc_enum,
213                             SGTL5000_CHIP_ANA_CTRL, 2,
214                             adc_mux_text);
215 
216 static const struct snd_kcontrol_new adc_mux =
217 SOC_DAPM_ENUM("Capture Mux", adc_enum);
218 
219 /* input sources for DAC */
220 static const char *dac_mux_text[] = {
221         "DAC", "LINE_IN"
222 };
223 
224 static SOC_ENUM_SINGLE_DECL(dac_enum,
225                             SGTL5000_CHIP_ANA_CTRL, 6,
226                             dac_mux_text);
227 
228 static const struct snd_kcontrol_new dac_mux =
229 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
230 
231 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
232         SND_SOC_DAPM_INPUT("LINE_IN"),
233         SND_SOC_DAPM_INPUT("MIC_IN"),
234 
235         SND_SOC_DAPM_OUTPUT("HP_OUT"),
236         SND_SOC_DAPM_OUTPUT("LINE_OUT"),
237 
238         SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
239                             mic_bias_event,
240                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
241 
242         SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
243         SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
244 
245         SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
246         SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
247 
248         /* aif for i2s input */
249         SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
250                                 0, SGTL5000_CHIP_DIG_POWER,
251                                 0, 0),
252 
253         /* aif for i2s output */
254         SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
255                                 0, SGTL5000_CHIP_DIG_POWER,
256                                 1, 0),
257 
258         SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
259         SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
260 
261         SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
262         SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
263 };
264 
265 /* routes for sgtl5000 */
266 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
267         {"Capture Mux", "LINE_IN", "LINE_IN"},  /* line_in --> adc_mux */
268         {"Capture Mux", "MIC_IN", "MIC_IN"},    /* mic_in --> adc_mux */
269 
270         {"ADC", NULL, "Capture Mux"},           /* adc_mux --> adc */
271         {"AIFOUT", NULL, "ADC"},                /* adc --> i2s_out */
272 
273         {"DAC", NULL, "AIFIN"},                 /* i2s-->dac,skip audio mux */
274         {"Headphone Mux", "DAC", "DAC"},        /* dac --> hp_mux */
275         {"LO", NULL, "DAC"},                    /* dac --> line_out */
276 
277         {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
278         {"HP", NULL, "Headphone Mux"},          /* hp_mux --> hp */
279 
280         {"LINE_OUT", NULL, "LO"},
281         {"HP_OUT", NULL, "HP"},
282 };
283 
284 /* custom function to fetch info of PCM playback volume */
285 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
286                           struct snd_ctl_elem_info *uinfo)
287 {
288         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
289         uinfo->count = 2;
290         uinfo->value.integer.min = 0;
291         uinfo->value.integer.max = 0xfc - 0x3c;
292         return 0;
293 }
294 
295 /*
296  * custom function to get of PCM playback volume
297  *
298  * dac volume register
299  * 15-------------8-7--------------0
300  * | R channel vol | L channel vol |
301  *  -------------------------------
302  *
303  * PCM volume with 0.5017 dB steps from 0 to -90 dB
304  *
305  * register values map to dB
306  * 0x3B and less = Reserved
307  * 0x3C = 0 dB
308  * 0x3D = -0.5 dB
309  * 0xF0 = -90 dB
310  * 0xFC and greater = Muted
311  *
312  * register value map to userspace value
313  *
314  * register value       0x3c(0dB)         0xf0(-90dB)0xfc
315  *                      ------------------------------
316  * userspace value      0xc0                         0
317  */
318 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
319                          struct snd_ctl_elem_value *ucontrol)
320 {
321         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
322         int reg;
323         int l;
324         int r;
325 
326         reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
327 
328         /* get left channel volume */
329         l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
330 
331         /* get right channel volume */
332         r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
333 
334         /* make sure value fall in (0x3c,0xfc) */
335         l = clamp(l, 0x3c, 0xfc);
336         r = clamp(r, 0x3c, 0xfc);
337 
338         /* invert it and map to userspace value */
339         l = 0xfc - l;
340         r = 0xfc - r;
341 
342         ucontrol->value.integer.value[0] = l;
343         ucontrol->value.integer.value[1] = r;
344 
345         return 0;
346 }
347 
348 /*
349  * custom function to put of PCM playback volume
350  *
351  * dac volume register
352  * 15-------------8-7--------------0
353  * | R channel vol | L channel vol |
354  *  -------------------------------
355  *
356  * PCM volume with 0.5017 dB steps from 0 to -90 dB
357  *
358  * register values map to dB
359  * 0x3B and less = Reserved
360  * 0x3C = 0 dB
361  * 0x3D = -0.5 dB
362  * 0xF0 = -90 dB
363  * 0xFC and greater = Muted
364  *
365  * userspace value map to register value
366  *
367  * userspace value      0xc0                         0
368  *                      ------------------------------
369  * register value       0x3c(0dB)       0xf0(-90dB)0xfc
370  */
371 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
372                          struct snd_ctl_elem_value *ucontrol)
373 {
374         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
375         int reg;
376         int l;
377         int r;
378 
379         l = ucontrol->value.integer.value[0];
380         r = ucontrol->value.integer.value[1];
381 
382         /* make sure userspace volume fall in (0, 0xfc-0x3c) */
383         l = clamp(l, 0, 0xfc - 0x3c);
384         r = clamp(r, 0, 0xfc - 0x3c);
385 
386         /* invert it, get the value can be set to register */
387         l = 0xfc - l;
388         r = 0xfc - r;
389 
390         /* shift to get the register value */
391         reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
392                 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
393 
394         snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
395 
396         return 0;
397 }
398 
399 /*
400  * custom function to get AVC threshold
401  *
402  * The threshold dB is calculated by rearranging the calculation from the
403  * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
404  * dB = ( fls(register_value) - 14.347 ) * 6.02
405  *
406  * As this calculation is expensive and the threshold dB values may not exeed
407  * 0 to 96 we use pre-calculated values.
408  */
409 static int avc_get_threshold(struct snd_kcontrol *kcontrol,
410                              struct snd_ctl_elem_value *ucontrol)
411 {
412         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
413         int db, i;
414         u16 reg = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD);
415 
416         /* register value 0 => -96dB */
417         if (!reg) {
418                 ucontrol->value.integer.value[0] = 96;
419                 ucontrol->value.integer.value[1] = 96;
420                 return 0;
421         }
422 
423         /* get dB from register value (rounded down) */
424         for (i = 0; avc_thr_db2reg[i] > reg; i++)
425                 ;
426         db = i;
427 
428         ucontrol->value.integer.value[0] = db;
429         ucontrol->value.integer.value[1] = db;
430 
431         return 0;
432 }
433 
434 /*
435  * custom function to put AVC threshold
436  *
437  * The register value is calculated by following formula:
438  *                                    register_value = 10^(dB/20) * 0.636 * 2^15
439  * As this calculation is expensive and the threshold dB values may not exeed
440  * 0 to 96 we use pre-calculated values.
441  */
442 static int avc_put_threshold(struct snd_kcontrol *kcontrol,
443                              struct snd_ctl_elem_value *ucontrol)
444 {
445         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
446         int db;
447         u16 reg;
448 
449         db = (int)ucontrol->value.integer.value[0];
450         if (db < 0 || db > 96)
451                 return -EINVAL;
452         reg = avc_thr_db2reg[db];
453         snd_soc_write(codec, SGTL5000_DAP_AVC_THRESHOLD, reg);
454 
455         return 0;
456 }
457 
458 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
459 
460 /* tlv for mic gain, 0db 20db 30db 40db */
461 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
462         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
463         1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
464 );
465 
466 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
467 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
468 
469 /* tlv for lineout volume, 31 steps of .5db each */
470 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
471 
472 /* tlv for dap avc max gain, 0db, 6db, 12db */
473 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
474 
475 /* tlv for dap avc threshold, */
476 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
477 
478 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
479         /* SOC_DOUBLE_S8_TLV with invert */
480         {
481                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
482                 .name = "PCM Playback Volume",
483                 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
484                         SNDRV_CTL_ELEM_ACCESS_READWRITE,
485                 .info = dac_info_volsw,
486                 .get = dac_get_volsw,
487                 .put = dac_put_volsw,
488         },
489 
490         SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
491         SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
492                         SGTL5000_CHIP_ANA_ADC_CTRL,
493                         8, 1, 0, capture_6db_attenuate),
494         SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
495 
496         SOC_DOUBLE_TLV("Headphone Playback Volume",
497                         SGTL5000_CHIP_ANA_HP_CTRL,
498                         0, 8,
499                         0x7f, 1,
500                         headphone_volume),
501         SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
502                         4, 1, 1),
503         SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
504                         5, 1, 0),
505 
506         SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
507                         0, 3, 0, mic_gain_tlv),
508 
509         SOC_DOUBLE_TLV("Lineout Playback Volume",
510                         SGTL5000_CHIP_LINE_OUT_VOL,
511                         SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
512                         SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
513                         0x1f, 1,
514                         lineout_volume),
515         SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
516 
517         /* Automatic Volume Control (DAP AVC) */
518         SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
519         SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
520         SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
521                         avc_max_gain),
522         SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
523         SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
524                         0, 96, 0, avc_get_threshold, avc_put_threshold,
525                         avc_threshold),
526 };
527 
528 /* mute the codec used by alsa core */
529 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
530 {
531         struct snd_soc_codec *codec = codec_dai->codec;
532         u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
533 
534         snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
535                         adcdac_ctrl, mute ? adcdac_ctrl : 0);
536 
537         return 0;
538 }
539 
540 /* set codec format */
541 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
542 {
543         struct snd_soc_codec *codec = codec_dai->codec;
544         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
545         u16 i2sctl = 0;
546 
547         sgtl5000->master = 0;
548         /*
549          * i2s clock and frame master setting.
550          * ONLY support:
551          *  - clock and frame slave,
552          *  - clock and frame master
553          */
554         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
555         case SND_SOC_DAIFMT_CBS_CFS:
556                 break;
557         case SND_SOC_DAIFMT_CBM_CFM:
558                 i2sctl |= SGTL5000_I2S_MASTER;
559                 sgtl5000->master = 1;
560                 break;
561         default:
562                 return -EINVAL;
563         }
564 
565         /* setting i2s data format */
566         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
567         case SND_SOC_DAIFMT_DSP_A:
568                 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
569                 break;
570         case SND_SOC_DAIFMT_DSP_B:
571                 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
572                 i2sctl |= SGTL5000_I2S_LRALIGN;
573                 break;
574         case SND_SOC_DAIFMT_I2S:
575                 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
576                 break;
577         case SND_SOC_DAIFMT_RIGHT_J:
578                 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
579                 i2sctl |= SGTL5000_I2S_LRPOL;
580                 break;
581         case SND_SOC_DAIFMT_LEFT_J:
582                 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
583                 i2sctl |= SGTL5000_I2S_LRALIGN;
584                 break;
585         default:
586                 return -EINVAL;
587         }
588 
589         sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
590 
591         /* Clock inversion */
592         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
593         case SND_SOC_DAIFMT_NB_NF:
594                 break;
595         case SND_SOC_DAIFMT_IB_NF:
596                 i2sctl |= SGTL5000_I2S_SCLK_INV;
597                 break;
598         default:
599                 return -EINVAL;
600         }
601 
602         snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
603 
604         return 0;
605 }
606 
607 /* set codec sysclk */
608 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
609                                    int clk_id, unsigned int freq, int dir)
610 {
611         struct snd_soc_codec *codec = codec_dai->codec;
612         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
613 
614         switch (clk_id) {
615         case SGTL5000_SYSCLK:
616                 sgtl5000->sysclk = freq;
617                 break;
618         default:
619                 return -EINVAL;
620         }
621 
622         return 0;
623 }
624 
625 /*
626  * set clock according to i2s frame clock,
627  * sgtl5000 provides 2 clock sources:
628  * 1. sys_mclk: sample freq can only be configured to
629  *      1/256, 1/384, 1/512 of sys_mclk.
630  * 2. pll: can derive any audio clocks.
631  *
632  * clock setting rules:
633  * 1. in slave mode, only sys_mclk can be used
634  * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
635  * and above.
636  * 3. usage of sys_mclk is preferred over pll to save power.
637  */
638 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
639 {
640         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
641         int clk_ctl = 0;
642         int sys_fs;     /* sample freq */
643 
644         /*
645          * sample freq should be divided by frame clock,
646          * if frame clock is lower than 44.1 kHz, sample freq should be set to
647          * 32 kHz or 44.1 kHz.
648          */
649         switch (frame_rate) {
650         case 8000:
651         case 16000:
652                 sys_fs = 32000;
653                 break;
654         case 11025:
655         case 22050:
656                 sys_fs = 44100;
657                 break;
658         default:
659                 sys_fs = frame_rate;
660                 break;
661         }
662 
663         /* set divided factor of frame clock */
664         switch (sys_fs / frame_rate) {
665         case 4:
666                 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
667                 break;
668         case 2:
669                 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
670                 break;
671         case 1:
672                 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
673                 break;
674         default:
675                 return -EINVAL;
676         }
677 
678         /* set the sys_fs according to frame rate */
679         switch (sys_fs) {
680         case 32000:
681                 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
682                 break;
683         case 44100:
684                 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
685                 break;
686         case 48000:
687                 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
688                 break;
689         case 96000:
690                 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
691                 break;
692         default:
693                 dev_err(codec->dev, "frame rate %d not supported\n",
694                         frame_rate);
695                 return -EINVAL;
696         }
697 
698         /*
699          * calculate the divider of mclk/sample_freq,
700          * factor of freq = 96 kHz can only be 256, since mclk is in the range
701          * of 8 MHz - 27 MHz
702          */
703         switch (sgtl5000->sysclk / frame_rate) {
704         case 256:
705                 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
706                         SGTL5000_MCLK_FREQ_SHIFT;
707                 break;
708         case 384:
709                 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
710                         SGTL5000_MCLK_FREQ_SHIFT;
711                 break;
712         case 512:
713                 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
714                         SGTL5000_MCLK_FREQ_SHIFT;
715                 break;
716         default:
717                 /* if mclk does not satisfy the divider, use pll */
718                 if (sgtl5000->master) {
719                         clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
720                                 SGTL5000_MCLK_FREQ_SHIFT;
721                 } else {
722                         dev_err(codec->dev,
723                                 "PLL not supported in slave mode\n");
724                         dev_err(codec->dev, "%d ratio is not supported. "
725                                 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
726                                 sgtl5000->sysclk / frame_rate);
727                         return -EINVAL;
728                 }
729         }
730 
731         /* if using pll, please check manual 6.4.2 for detail */
732         if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
733                 u64 out, t;
734                 int div2;
735                 int pll_ctl;
736                 unsigned int in, int_div, frac_div;
737 
738                 if (sgtl5000->sysclk > 17000000) {
739                         div2 = 1;
740                         in = sgtl5000->sysclk / 2;
741                 } else {
742                         div2 = 0;
743                         in = sgtl5000->sysclk;
744                 }
745                 if (sys_fs == 44100)
746                         out = 180633600;
747                 else
748                         out = 196608000;
749                 t = do_div(out, in);
750                 int_div = out;
751                 t *= 2048;
752                 do_div(t, in);
753                 frac_div = t;
754                 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
755                     frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
756 
757                 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
758                 if (div2)
759                         snd_soc_update_bits(codec,
760                                 SGTL5000_CHIP_CLK_TOP_CTRL,
761                                 SGTL5000_INPUT_FREQ_DIV2,
762                                 SGTL5000_INPUT_FREQ_DIV2);
763                 else
764                         snd_soc_update_bits(codec,
765                                 SGTL5000_CHIP_CLK_TOP_CTRL,
766                                 SGTL5000_INPUT_FREQ_DIV2,
767                                 0);
768 
769                 /* power up pll */
770                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
771                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
772                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
773 
774                 /* if using pll, clk_ctrl must be set after pll power up */
775                 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
776         } else {
777                 /* otherwise, clk_ctrl must be set before pll power down */
778                 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
779 
780                 /* power down pll */
781                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
782                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
783                         0);
784         }
785 
786         return 0;
787 }
788 
789 /*
790  * Set PCM DAI bit size and sample rate.
791  * input: params_rate, params_fmt
792  */
793 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
794                                   struct snd_pcm_hw_params *params,
795                                   struct snd_soc_dai *dai)
796 {
797         struct snd_soc_codec *codec = dai->codec;
798         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
799         int channels = params_channels(params);
800         int i2s_ctl = 0;
801         int stereo;
802         int ret;
803 
804         /* sysclk should already set */
805         if (!sgtl5000->sysclk) {
806                 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
807                 return -EFAULT;
808         }
809 
810         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
811                 stereo = SGTL5000_DAC_STEREO;
812         else
813                 stereo = SGTL5000_ADC_STEREO;
814 
815         /* set mono to save power */
816         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
817                         channels == 1 ? 0 : stereo);
818 
819         /* set codec clock base on lrclk */
820         ret = sgtl5000_set_clock(codec, params_rate(params));
821         if (ret)
822                 return ret;
823 
824         /* set i2s data format */
825         switch (params_width(params)) {
826         case 16:
827                 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
828                         return -EINVAL;
829                 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
830                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
831                     SGTL5000_I2S_SCLKFREQ_SHIFT;
832                 break;
833         case 20:
834                 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
835                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
836                     SGTL5000_I2S_SCLKFREQ_SHIFT;
837                 break;
838         case 24:
839                 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
840                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
841                     SGTL5000_I2S_SCLKFREQ_SHIFT;
842                 break;
843         case 32:
844                 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
845                         return -EINVAL;
846                 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
847                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
848                     SGTL5000_I2S_SCLKFREQ_SHIFT;
849                 break;
850         default:
851                 return -EINVAL;
852         }
853 
854         snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
855                             SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
856                             i2s_ctl);
857 
858         return 0;
859 }
860 
861 /*
862  * set dac bias
863  * common state changes:
864  * startup:
865  * off --> standby --> prepare --> on
866  * standby --> prepare --> on
867  *
868  * stop:
869  * on --> prepare --> standby
870  */
871 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
872                                    enum snd_soc_bias_level level)
873 {
874         struct sgtl5000_priv *sgtl = snd_soc_codec_get_drvdata(codec);
875         int ret;
876 
877         switch (level) {
878         case SND_SOC_BIAS_ON:
879         case SND_SOC_BIAS_PREPARE:
880         case SND_SOC_BIAS_STANDBY:
881                 regcache_cache_only(sgtl->regmap, false);
882                 ret = regcache_sync(sgtl->regmap);
883                 if (ret) {
884                         regcache_cache_only(sgtl->regmap, true);
885                         return ret;
886                 }
887 
888                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
889                                     SGTL5000_REFTOP_POWERUP,
890                                     SGTL5000_REFTOP_POWERUP);
891                 break;
892         case SND_SOC_BIAS_OFF:
893                 regcache_cache_only(sgtl->regmap, true);
894                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
895                                     SGTL5000_REFTOP_POWERUP, 0);
896                 break;
897         }
898 
899         return 0;
900 }
901 
902 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
903                         SNDRV_PCM_FMTBIT_S20_3LE |\
904                         SNDRV_PCM_FMTBIT_S24_LE |\
905                         SNDRV_PCM_FMTBIT_S32_LE)
906 
907 static const struct snd_soc_dai_ops sgtl5000_ops = {
908         .hw_params = sgtl5000_pcm_hw_params,
909         .digital_mute = sgtl5000_digital_mute,
910         .set_fmt = sgtl5000_set_dai_fmt,
911         .set_sysclk = sgtl5000_set_dai_sysclk,
912 };
913 
914 static struct snd_soc_dai_driver sgtl5000_dai = {
915         .name = "sgtl5000",
916         .playback = {
917                 .stream_name = "Playback",
918                 .channels_min = 1,
919                 .channels_max = 2,
920                 /*
921                  * only support 8~48K + 96K,
922                  * TODO modify hw_param to support more
923                  */
924                 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
925                 .formats = SGTL5000_FORMATS,
926         },
927         .capture = {
928                 .stream_name = "Capture",
929                 .channels_min = 1,
930                 .channels_max = 2,
931                 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
932                 .formats = SGTL5000_FORMATS,
933         },
934         .ops = &sgtl5000_ops,
935         .symmetric_rates = 1,
936 };
937 
938 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
939 {
940         switch (reg) {
941         case SGTL5000_CHIP_ID:
942         case SGTL5000_CHIP_ADCDAC_CTRL:
943         case SGTL5000_CHIP_ANA_STATUS:
944                 return true;
945         }
946 
947         return false;
948 }
949 
950 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
951 {
952         switch (reg) {
953         case SGTL5000_CHIP_ID:
954         case SGTL5000_CHIP_DIG_POWER:
955         case SGTL5000_CHIP_CLK_CTRL:
956         case SGTL5000_CHIP_I2S_CTRL:
957         case SGTL5000_CHIP_SSS_CTRL:
958         case SGTL5000_CHIP_ADCDAC_CTRL:
959         case SGTL5000_CHIP_DAC_VOL:
960         case SGTL5000_CHIP_PAD_STRENGTH:
961         case SGTL5000_CHIP_ANA_ADC_CTRL:
962         case SGTL5000_CHIP_ANA_HP_CTRL:
963         case SGTL5000_CHIP_ANA_CTRL:
964         case SGTL5000_CHIP_LINREG_CTRL:
965         case SGTL5000_CHIP_REF_CTRL:
966         case SGTL5000_CHIP_MIC_CTRL:
967         case SGTL5000_CHIP_LINE_OUT_CTRL:
968         case SGTL5000_CHIP_LINE_OUT_VOL:
969         case SGTL5000_CHIP_ANA_POWER:
970         case SGTL5000_CHIP_PLL_CTRL:
971         case SGTL5000_CHIP_CLK_TOP_CTRL:
972         case SGTL5000_CHIP_ANA_STATUS:
973         case SGTL5000_CHIP_SHORT_CTRL:
974         case SGTL5000_CHIP_ANA_TEST2:
975         case SGTL5000_DAP_CTRL:
976         case SGTL5000_DAP_PEQ:
977         case SGTL5000_DAP_BASS_ENHANCE:
978         case SGTL5000_DAP_BASS_ENHANCE_CTRL:
979         case SGTL5000_DAP_AUDIO_EQ:
980         case SGTL5000_DAP_SURROUND:
981         case SGTL5000_DAP_FLT_COEF_ACCESS:
982         case SGTL5000_DAP_COEF_WR_B0_MSB:
983         case SGTL5000_DAP_COEF_WR_B0_LSB:
984         case SGTL5000_DAP_EQ_BASS_BAND0:
985         case SGTL5000_DAP_EQ_BASS_BAND1:
986         case SGTL5000_DAP_EQ_BASS_BAND2:
987         case SGTL5000_DAP_EQ_BASS_BAND3:
988         case SGTL5000_DAP_EQ_BASS_BAND4:
989         case SGTL5000_DAP_MAIN_CHAN:
990         case SGTL5000_DAP_MIX_CHAN:
991         case SGTL5000_DAP_AVC_CTRL:
992         case SGTL5000_DAP_AVC_THRESHOLD:
993         case SGTL5000_DAP_AVC_ATTACK:
994         case SGTL5000_DAP_AVC_DECAY:
995         case SGTL5000_DAP_COEF_WR_B1_MSB:
996         case SGTL5000_DAP_COEF_WR_B1_LSB:
997         case SGTL5000_DAP_COEF_WR_B2_MSB:
998         case SGTL5000_DAP_COEF_WR_B2_LSB:
999         case SGTL5000_DAP_COEF_WR_A1_MSB:
1000         case SGTL5000_DAP_COEF_WR_A1_LSB:
1001         case SGTL5000_DAP_COEF_WR_A2_MSB:
1002         case SGTL5000_DAP_COEF_WR_A2_LSB:
1003                 return true;
1004 
1005         default:
1006                 return false;
1007         }
1008 }
1009 
1010 /*
1011  * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1012  * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1013  * The calculatation was done for all possible register values which
1014  * is the array index and the following formula: 10^((idx−15)/40) * 100
1015  */
1016 static const u8 vol_quot_table[] = {
1017         42, 45, 47, 50, 53, 56, 60, 63,
1018         67, 71, 75, 79, 84, 89, 94, 100,
1019         106, 112, 119, 126, 133, 141, 150, 158,
1020         168, 178, 188, 200, 211, 224, 237, 251
1021 };
1022 
1023 /*
1024  * sgtl5000 has 3 internal power supplies:
1025  * 1. VAG, normally set to vdda/2
1026  * 2. charge pump, set to different value
1027  *      according to voltage of vdda and vddio
1028  * 3. line out VAG, normally set to vddio/2
1029  *
1030  * and should be set according to:
1031  * 1. vddd provided by external or not
1032  * 2. vdda and vddio voltage value. > 3.1v or not
1033  */
1034 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1035 {
1036         int vddd;
1037         int vdda;
1038         int vddio;
1039         u16 ana_pwr;
1040         u16 lreg_ctrl;
1041         int vag;
1042         int lo_vag;
1043         int vol_quot;
1044         int lo_vol;
1045         size_t i;
1046         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1047 
1048         vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1049         vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1050         vddd  = (sgtl5000->num_supplies > VDDD)
1051                 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1052                 : LDO_VOLTAGE;
1053 
1054         vdda  = vdda / 1000;
1055         vddio = vddio / 1000;
1056         vddd  = vddd / 1000;
1057 
1058         if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1059                 dev_err(codec->dev, "regulator voltage not set correctly\n");
1060 
1061                 return -EINVAL;
1062         }
1063 
1064         /* according to datasheet, maximum voltage of supplies */
1065         if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1066                 dev_err(codec->dev,
1067                         "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1068                         vdda, vddio, vddd);
1069 
1070                 return -EINVAL;
1071         }
1072 
1073         /* reset value */
1074         ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1075         ana_pwr |= SGTL5000_DAC_STEREO |
1076                         SGTL5000_ADC_STEREO |
1077                         SGTL5000_REFTOP_POWERUP;
1078         lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1079 
1080         if (vddio < 3100 && vdda < 3100) {
1081                 /* enable internal oscillator used for charge pump */
1082                 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1083                                         SGTL5000_INT_OSC_EN,
1084                                         SGTL5000_INT_OSC_EN);
1085                 /* Enable VDDC charge pump */
1086                 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1087         } else if (vddio >= 3100 && vdda >= 3100) {
1088                 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1089                 /* VDDC use VDDIO rail */
1090                 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1091                 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1092                             SGTL5000_VDDC_MAN_ASSN_SHIFT;
1093         }
1094 
1095         snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1096 
1097         snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1098 
1099         /*
1100          * set ADC/DAC VAG to vdda / 2,
1101          * should stay in range (0.8v, 1.575v)
1102          */
1103         vag = vdda / 2;
1104         if (vag <= SGTL5000_ANA_GND_BASE)
1105                 vag = 0;
1106         else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1107                  (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1108                 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1109         else
1110                 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1111 
1112         snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1113                         SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1114 
1115         /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1116         lo_vag = vddio / 2;
1117         if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1118                 lo_vag = 0;
1119         else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1120                 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1121                 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1122         else
1123                 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1124                     SGTL5000_LINE_OUT_GND_STP;
1125 
1126         snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1127                         SGTL5000_LINE_OUT_CURRENT_MASK |
1128                         SGTL5000_LINE_OUT_GND_MASK,
1129                         lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1130                         SGTL5000_LINE_OUT_CURRENT_360u <<
1131                                 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1132 
1133         /*
1134          * Set lineout output level in range (0..31)
1135          * the same value is used for right and left channel
1136          *
1137          * Searching for a suitable index solving this formula:
1138          * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1139          */
1140         vol_quot = (vag * 100) / lo_vag;
1141         lo_vol = 0;
1142         for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1143                 if (vol_quot >= vol_quot_table[i])
1144                         lo_vol = i;
1145                 else
1146                         break;
1147         }
1148 
1149         snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1150                 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1151                 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1152                 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1153                 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1154 
1155         return 0;
1156 }
1157 
1158 static int sgtl5000_enable_regulators(struct i2c_client *client)
1159 {
1160         int ret;
1161         int i;
1162         int external_vddd = 0;
1163         struct regulator *vddd;
1164         struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1165 
1166         for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1167                 sgtl5000->supplies[i].supply = supply_names[i];
1168 
1169         vddd = regulator_get_optional(&client->dev, "VDDD");
1170         if (IS_ERR(vddd)) {
1171                 /* See if it's just not registered yet */
1172                 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1173                         return -EPROBE_DEFER;
1174         } else {
1175                 external_vddd = 1;
1176                 regulator_put(vddd);
1177         }
1178 
1179         sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1180                                  - 1 + external_vddd;
1181         ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1182                                  sgtl5000->supplies);
1183         if (ret)
1184                 return ret;
1185 
1186         ret = regulator_bulk_enable(sgtl5000->num_supplies,
1187                                     sgtl5000->supplies);
1188         if (!ret)
1189                 usleep_range(10, 20);
1190         else
1191                 regulator_bulk_free(sgtl5000->num_supplies,
1192                                     sgtl5000->supplies);
1193 
1194         return ret;
1195 }
1196 
1197 static int sgtl5000_probe(struct snd_soc_codec *codec)
1198 {
1199         int ret;
1200         u16 reg;
1201         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1202 
1203         /* power up sgtl5000 */
1204         ret = sgtl5000_set_power_regs(codec);
1205         if (ret)
1206                 goto err;
1207 
1208         /* enable small pop, introduce 400ms delay in turning off */
1209         snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1210                                 SGTL5000_SMALL_POP, 1);
1211 
1212         /* disable short cut detector */
1213         snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1214 
1215         /*
1216          * set i2s as default input of sound switch
1217          * TODO: add sound switch to control and dapm widge.
1218          */
1219         snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1220                         SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1221         snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1222                         SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1223 
1224         /* enable dac volume ramp by default */
1225         snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1226                         SGTL5000_DAC_VOL_RAMP_EN |
1227                         SGTL5000_DAC_MUTE_RIGHT |
1228                         SGTL5000_DAC_MUTE_LEFT);
1229 
1230         reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
1231         snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg);
1232 
1233         snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1234                         SGTL5000_HP_ZCD_EN |
1235                         SGTL5000_ADC_ZCD_EN);
1236 
1237         snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1238                         SGTL5000_BIAS_R_MASK,
1239                         sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1240 
1241         snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1242                         SGTL5000_BIAS_VOLT_MASK,
1243                         sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1244         /*
1245          * disable DAP
1246          * TODO:
1247          * Enable DAP in kcontrol and dapm.
1248          */
1249         snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1250 
1251         return 0;
1252 
1253 err:
1254         return ret;
1255 }
1256 
1257 static int sgtl5000_remove(struct snd_soc_codec *codec)
1258 {
1259         return 0;
1260 }
1261 
1262 static const struct snd_soc_codec_driver sgtl5000_driver = {
1263         .probe = sgtl5000_probe,
1264         .remove = sgtl5000_remove,
1265         .set_bias_level = sgtl5000_set_bias_level,
1266         .suspend_bias_off = true,
1267         .component_driver = {
1268                 .controls               = sgtl5000_snd_controls,
1269                 .num_controls           = ARRAY_SIZE(sgtl5000_snd_controls),
1270                 .dapm_widgets           = sgtl5000_dapm_widgets,
1271                 .num_dapm_widgets       = ARRAY_SIZE(sgtl5000_dapm_widgets),
1272                 .dapm_routes            = sgtl5000_dapm_routes,
1273                 .num_dapm_routes        = ARRAY_SIZE(sgtl5000_dapm_routes),
1274         },
1275 };
1276 
1277 static const struct regmap_config sgtl5000_regmap = {
1278         .reg_bits = 16,
1279         .val_bits = 16,
1280         .reg_stride = 2,
1281 
1282         .max_register = SGTL5000_MAX_REG_OFFSET,
1283         .volatile_reg = sgtl5000_volatile,
1284         .readable_reg = sgtl5000_readable,
1285 
1286         .cache_type = REGCACHE_RBTREE,
1287         .reg_defaults = sgtl5000_reg_defaults,
1288         .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1289 };
1290 
1291 /*
1292  * Write all the default values from sgtl5000_reg_defaults[] array into the
1293  * sgtl5000 registers, to make sure we always start with the sane registers
1294  * values as stated in the datasheet.
1295  *
1296  * Since sgtl5000 does not have a reset line, nor a reset command in software,
1297  * we follow this approach to guarantee we always start from the default values
1298  * and avoid problems like, not being able to probe after an audio playback
1299  * followed by a system reset or a 'reboot' command in Linux
1300  */
1301 static void sgtl5000_fill_defaults(struct i2c_client *client)
1302 {
1303         struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1304         int i, ret, val, index;
1305 
1306         for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1307                 val = sgtl5000_reg_defaults[i].def;
1308                 index = sgtl5000_reg_defaults[i].reg;
1309                 ret = regmap_write(sgtl5000->regmap, index, val);
1310                 if (ret)
1311                         dev_err(&client->dev,
1312                                 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1313                                 __func__, ret, index, val);
1314         }
1315 }
1316 
1317 static int sgtl5000_i2c_probe(struct i2c_client *client,
1318                               const struct i2c_device_id *id)
1319 {
1320         struct sgtl5000_priv *sgtl5000;
1321         int ret, reg, rev;
1322         struct device_node *np = client->dev.of_node;
1323         u32 value;
1324         u16 ana_pwr;
1325 
1326         sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1327         if (!sgtl5000)
1328                 return -ENOMEM;
1329 
1330         i2c_set_clientdata(client, sgtl5000);
1331 
1332         ret = sgtl5000_enable_regulators(client);
1333         if (ret)
1334                 return ret;
1335 
1336         sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1337         if (IS_ERR(sgtl5000->regmap)) {
1338                 ret = PTR_ERR(sgtl5000->regmap);
1339                 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1340                 goto disable_regs;
1341         }
1342 
1343         sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1344         if (IS_ERR(sgtl5000->mclk)) {
1345                 ret = PTR_ERR(sgtl5000->mclk);
1346                 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1347                 /* Defer the probe to see if the clk will be provided later */
1348                 if (ret == -ENOENT)
1349                         ret = -EPROBE_DEFER;
1350                 goto disable_regs;
1351         }
1352 
1353         ret = clk_prepare_enable(sgtl5000->mclk);
1354         if (ret) {
1355                 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1356                 goto disable_regs;
1357         }
1358 
1359         /* Need 8 clocks before I2C accesses */
1360         udelay(1);
1361 
1362         /* read chip information */
1363         ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1364         if (ret) {
1365                 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1366                 goto disable_clk;
1367         }
1368 
1369         if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1370             SGTL5000_PARTID_PART_ID) {
1371                 dev_err(&client->dev,
1372                         "Device with ID register %x is not a sgtl5000\n", reg);
1373                 ret = -ENODEV;
1374                 goto disable_clk;
1375         }
1376 
1377         rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1378         dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1379         sgtl5000->revision = rev;
1380 
1381         /* reconfigure the clocks in case we're using the PLL */
1382         ret = regmap_write(sgtl5000->regmap,
1383                            SGTL5000_CHIP_CLK_CTRL,
1384                            SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1385         if (ret)
1386                 dev_err(&client->dev,
1387                         "Error %d initializing CHIP_CLK_CTRL\n", ret);
1388 
1389         /* Follow section 2.2.1.1 of AN3663 */
1390         ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1391         if (sgtl5000->num_supplies <= VDDD) {
1392                 /* internal VDDD at 1.2V */
1393                 ret = regmap_update_bits(sgtl5000->regmap,
1394                                          SGTL5000_CHIP_LINREG_CTRL,
1395                                          SGTL5000_LINREG_VDDD_MASK,
1396                                          LINREG_VDDD);
1397                 if (ret)
1398                         dev_err(&client->dev,
1399                                 "Error %d setting LINREG_VDDD\n", ret);
1400 
1401                 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1402                 dev_info(&client->dev,
1403                          "Using internal LDO instead of VDDD: check ER1\n");
1404         } else {
1405                 /* using external LDO for VDDD
1406                  * Clear startup powerup and simple powerup
1407                  * bits to save power
1408                  */
1409                 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1410                              | SGTL5000_LINREG_SIMPLE_POWERUP);
1411                 dev_dbg(&client->dev, "Using external VDDD\n");
1412         }
1413         ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1414         if (ret)
1415                 dev_err(&client->dev,
1416                         "Error %d setting CHIP_ANA_POWER to %04x\n",
1417                         ret, ana_pwr);
1418 
1419         if (np) {
1420                 if (!of_property_read_u32(np,
1421                         "micbias-resistor-k-ohms", &value)) {
1422                         switch (value) {
1423                         case SGTL5000_MICBIAS_OFF:
1424                                 sgtl5000->micbias_resistor = 0;
1425                                 break;
1426                         case SGTL5000_MICBIAS_2K:
1427                                 sgtl5000->micbias_resistor = 1;
1428                                 break;
1429                         case SGTL5000_MICBIAS_4K:
1430                                 sgtl5000->micbias_resistor = 2;
1431                                 break;
1432                         case SGTL5000_MICBIAS_8K:
1433                                 sgtl5000->micbias_resistor = 3;
1434                                 break;
1435                         default:
1436                                 sgtl5000->micbias_resistor = 2;
1437                                 dev_err(&client->dev,
1438                                         "Unsuitable MicBias resistor\n");
1439                         }
1440                 } else {
1441                         /* default is 4Kohms */
1442                         sgtl5000->micbias_resistor = 2;
1443                 }
1444                 if (!of_property_read_u32(np,
1445                         "micbias-voltage-m-volts", &value)) {
1446                         /* 1250mV => 0 */
1447                         /* steps of 250mV */
1448                         if ((value >= 1250) && (value <= 3000))
1449                                 sgtl5000->micbias_voltage = (value / 250) - 5;
1450                         else {
1451                                 sgtl5000->micbias_voltage = 0;
1452                                 dev_err(&client->dev,
1453                                         "Unsuitable MicBias voltage\n");
1454                         }
1455                 } else {
1456                         sgtl5000->micbias_voltage = 0;
1457                 }
1458         }
1459 
1460         sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1461         if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1462                 if (value > I2S_LRCLK_STRENGTH_HIGH)
1463                         value = I2S_LRCLK_STRENGTH_LOW;
1464                 sgtl5000->lrclk_strength = value;
1465         }
1466 
1467         /* Ensure sgtl5000 will start with sane register values */
1468         sgtl5000_fill_defaults(client);
1469 
1470         ret = snd_soc_register_codec(&client->dev,
1471                         &sgtl5000_driver, &sgtl5000_dai, 1);
1472         if (ret)
1473                 goto disable_clk;
1474 
1475         return 0;
1476 
1477 disable_clk:
1478         clk_disable_unprepare(sgtl5000->mclk);
1479 
1480 disable_regs:
1481         regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1482         regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1483 
1484         return ret;
1485 }
1486 
1487 static int sgtl5000_i2c_remove(struct i2c_client *client)
1488 {
1489         struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1490 
1491         snd_soc_unregister_codec(&client->dev);
1492         clk_disable_unprepare(sgtl5000->mclk);
1493         regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1494         regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1495 
1496         return 0;
1497 }
1498 
1499 static const struct i2c_device_id sgtl5000_id[] = {
1500         {"sgtl5000", 0},
1501         {},
1502 };
1503 
1504 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1505 
1506 static const struct of_device_id sgtl5000_dt_ids[] = {
1507         { .compatible = "fsl,sgtl5000", },
1508         { /* sentinel */ }
1509 };
1510 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1511 
1512 static struct i2c_driver sgtl5000_i2c_driver = {
1513         .driver = {
1514                    .name = "sgtl5000",
1515                    .of_match_table = sgtl5000_dt_ids,
1516                    },
1517         .probe = sgtl5000_i2c_probe,
1518         .remove = sgtl5000_i2c_remove,
1519         .id_table = sgtl5000_id,
1520 };
1521 
1522 module_i2c_driver(sgtl5000_i2c_driver);
1523 
1524 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1525 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1526 MODULE_LICENSE("GPL");
1527 

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