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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/twl4030.c

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  1 /*
  2  * ALSA SoC TWL4030 codec driver
  3  *
  4  * Author:      Steve Sakoman, <steve@sakoman.com>
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * version 2 as published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope that it will be useful, but
 11  * WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 13  * General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 18  * 02110-1301 USA
 19  *
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/moduleparam.h>
 24 #include <linux/init.h>
 25 #include <linux/delay.h>
 26 #include <linux/pm.h>
 27 #include <linux/i2c.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/of.h>
 30 #include <linux/of_gpio.h>
 31 #include <linux/i2c/twl.h>
 32 #include <linux/slab.h>
 33 #include <linux/gpio.h>
 34 #include <sound/core.h>
 35 #include <sound/pcm.h>
 36 #include <sound/pcm_params.h>
 37 #include <sound/soc.h>
 38 #include <sound/initval.h>
 39 #include <sound/tlv.h>
 40 
 41 /* Register descriptions are here */
 42 #include <linux/mfd/twl4030-audio.h>
 43 
 44 /* TWL4030 PMBR1 Register */
 45 #define TWL4030_PMBR1_REG               0x0D
 46 /* TWL4030 PMBR1 Register GPIO6 mux bits */
 47 #define TWL4030_GPIO6_PWM0_MUTE(value)  ((value & 0x03) << 2)
 48 
 49 /* Shadow register used by the audio driver */
 50 #define TWL4030_REG_SW_SHADOW           0x4A
 51 #define TWL4030_CACHEREGNUM     (TWL4030_REG_SW_SHADOW + 1)
 52 
 53 /* TWL4030_REG_SW_SHADOW (0x4A) Fields */
 54 #define TWL4030_HFL_EN                  0x01
 55 #define TWL4030_HFR_EN                  0x02
 56 
 57 /*
 58  * twl4030 register cache & default register settings
 59  */
 60 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
 61         0x00, /* this register not used         */
 62         0x00, /* REG_CODEC_MODE         (0x1)   */
 63         0x00, /* REG_OPTION             (0x2)   */
 64         0x00, /* REG_UNKNOWN            (0x3)   */
 65         0x00, /* REG_MICBIAS_CTL        (0x4)   */
 66         0x00, /* REG_ANAMICL            (0x5)   */
 67         0x00, /* REG_ANAMICR            (0x6)   */
 68         0x00, /* REG_AVADC_CTL          (0x7)   */
 69         0x00, /* REG_ADCMICSEL          (0x8)   */
 70         0x00, /* REG_DIGMIXING          (0x9)   */
 71         0x0f, /* REG_ATXL1PGA           (0xA)   */
 72         0x0f, /* REG_ATXR1PGA           (0xB)   */
 73         0x0f, /* REG_AVTXL2PGA          (0xC)   */
 74         0x0f, /* REG_AVTXR2PGA          (0xD)   */
 75         0x00, /* REG_AUDIO_IF           (0xE)   */
 76         0x00, /* REG_VOICE_IF           (0xF)   */
 77         0x3f, /* REG_ARXR1PGA           (0x10)  */
 78         0x3f, /* REG_ARXL1PGA           (0x11)  */
 79         0x3f, /* REG_ARXR2PGA           (0x12)  */
 80         0x3f, /* REG_ARXL2PGA           (0x13)  */
 81         0x25, /* REG_VRXPGA             (0x14)  */
 82         0x00, /* REG_VSTPGA             (0x15)  */
 83         0x00, /* REG_VRX2ARXPGA         (0x16)  */
 84         0x00, /* REG_AVDAC_CTL          (0x17)  */
 85         0x00, /* REG_ARX2VTXPGA         (0x18)  */
 86         0x32, /* REG_ARXL1_APGA_CTL     (0x19)  */
 87         0x32, /* REG_ARXR1_APGA_CTL     (0x1A)  */
 88         0x32, /* REG_ARXL2_APGA_CTL     (0x1B)  */
 89         0x32, /* REG_ARXR2_APGA_CTL     (0x1C)  */
 90         0x00, /* REG_ATX2ARXPGA         (0x1D)  */
 91         0x00, /* REG_BT_IF              (0x1E)  */
 92         0x55, /* REG_BTPGA              (0x1F)  */
 93         0x00, /* REG_BTSTPGA            (0x20)  */
 94         0x00, /* REG_EAR_CTL            (0x21)  */
 95         0x00, /* REG_HS_SEL             (0x22)  */
 96         0x00, /* REG_HS_GAIN_SET        (0x23)  */
 97         0x00, /* REG_HS_POPN_SET        (0x24)  */
 98         0x00, /* REG_PREDL_CTL          (0x25)  */
 99         0x00, /* REG_PREDR_CTL          (0x26)  */
100         0x00, /* REG_PRECKL_CTL         (0x27)  */
101         0x00, /* REG_PRECKR_CTL         (0x28)  */
102         0x00, /* REG_HFL_CTL            (0x29)  */
103         0x00, /* REG_HFR_CTL            (0x2A)  */
104         0x05, /* REG_ALC_CTL            (0x2B)  */
105         0x00, /* REG_ALC_SET1           (0x2C)  */
106         0x00, /* REG_ALC_SET2           (0x2D)  */
107         0x00, /* REG_BOOST_CTL          (0x2E)  */
108         0x00, /* REG_SOFTVOL_CTL        (0x2F)  */
109         0x13, /* REG_DTMF_FREQSEL       (0x30)  */
110         0x00, /* REG_DTMF_TONEXT1H      (0x31)  */
111         0x00, /* REG_DTMF_TONEXT1L      (0x32)  */
112         0x00, /* REG_DTMF_TONEXT2H      (0x33)  */
113         0x00, /* REG_DTMF_TONEXT2L      (0x34)  */
114         0x79, /* REG_DTMF_TONOFF        (0x35)  */
115         0x11, /* REG_DTMF_WANONOFF      (0x36)  */
116         0x00, /* REG_I2S_RX_SCRAMBLE_H  (0x37)  */
117         0x00, /* REG_I2S_RX_SCRAMBLE_M  (0x38)  */
118         0x00, /* REG_I2S_RX_SCRAMBLE_L  (0x39)  */
119         0x06, /* REG_APLL_CTL           (0x3A)  */
120         0x00, /* REG_DTMF_CTL           (0x3B)  */
121         0x44, /* REG_DTMF_PGA_CTL2      (0x3C)  */
122         0x69, /* REG_DTMF_PGA_CTL1      (0x3D)  */
123         0x00, /* REG_MISC_SET_1         (0x3E)  */
124         0x00, /* REG_PCMBTMUX           (0x3F)  */
125         0x00, /* not used               (0x40)  */
126         0x00, /* not used               (0x41)  */
127         0x00, /* not used               (0x42)  */
128         0x00, /* REG_RX_PATH_SEL        (0x43)  */
129         0x32, /* REG_VDL_APGA_CTL       (0x44)  */
130         0x00, /* REG_VIBRA_CTL          (0x45)  */
131         0x00, /* REG_VIBRA_SET          (0x46)  */
132         0x00, /* REG_VIBRA_PWM_SET      (0x47)  */
133         0x00, /* REG_ANAMIC_GAIN        (0x48)  */
134         0x00, /* REG_MISC_SET_2         (0x49)  */
135         0x00, /* REG_SW_SHADOW          (0x4A)  - Shadow, non HW register */
136 };
137 
138 /* codec private data */
139 struct twl4030_priv {
140         unsigned int codec_powered;
141 
142         /* reference counts of AIF/APLL users */
143         unsigned int apll_enabled;
144 
145         struct snd_pcm_substream *master_substream;
146         struct snd_pcm_substream *slave_substream;
147 
148         unsigned int configured;
149         unsigned int rate;
150         unsigned int sample_bits;
151         unsigned int channels;
152 
153         unsigned int sysclk;
154 
155         /* Output (with associated amp) states */
156         u8 hsl_enabled, hsr_enabled;
157         u8 earpiece_enabled;
158         u8 predrivel_enabled, predriver_enabled;
159         u8 carkitl_enabled, carkitr_enabled;
160 
161         struct twl4030_codec_data *pdata;
162 };
163 
164 /*
165  * read twl4030 register cache
166  */
167 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
168         unsigned int reg)
169 {
170         u8 *cache = codec->reg_cache;
171 
172         if (reg >= TWL4030_CACHEREGNUM)
173                 return -EIO;
174 
175         return cache[reg];
176 }
177 
178 /*
179  * write twl4030 register cache
180  */
181 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
182                                                 u8 reg, u8 value)
183 {
184         u8 *cache = codec->reg_cache;
185 
186         if (reg >= TWL4030_CACHEREGNUM)
187                 return;
188         cache[reg] = value;
189 }
190 
191 /*
192  * write to the twl4030 register space
193  */
194 static int twl4030_write(struct snd_soc_codec *codec,
195                         unsigned int reg, unsigned int value)
196 {
197         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
198         int write_to_reg = 0;
199 
200         twl4030_write_reg_cache(codec, reg, value);
201         if (likely(reg < TWL4030_REG_SW_SHADOW)) {
202                 /* Decide if the given register can be written */
203                 switch (reg) {
204                 case TWL4030_REG_EAR_CTL:
205                         if (twl4030->earpiece_enabled)
206                                 write_to_reg = 1;
207                         break;
208                 case TWL4030_REG_PREDL_CTL:
209                         if (twl4030->predrivel_enabled)
210                                 write_to_reg = 1;
211                         break;
212                 case TWL4030_REG_PREDR_CTL:
213                         if (twl4030->predriver_enabled)
214                                 write_to_reg = 1;
215                         break;
216                 case TWL4030_REG_PRECKL_CTL:
217                         if (twl4030->carkitl_enabled)
218                                 write_to_reg = 1;
219                         break;
220                 case TWL4030_REG_PRECKR_CTL:
221                         if (twl4030->carkitr_enabled)
222                                 write_to_reg = 1;
223                         break;
224                 case TWL4030_REG_HS_GAIN_SET:
225                         if (twl4030->hsl_enabled || twl4030->hsr_enabled)
226                                 write_to_reg = 1;
227                         break;
228                 default:
229                         /* All other register can be written */
230                         write_to_reg = 1;
231                         break;
232                 }
233                 if (write_to_reg)
234                         return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
235                                                     value, reg);
236         }
237         return 0;
238 }
239 
240 static inline void twl4030_wait_ms(int time)
241 {
242         if (time < 60) {
243                 time *= 1000;
244                 usleep_range(time, time + 500);
245         } else {
246                 msleep(time);
247         }
248 }
249 
250 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
251 {
252         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
253         int mode;
254 
255         if (enable == twl4030->codec_powered)
256                 return;
257 
258         if (enable)
259                 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
260         else
261                 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
262 
263         if (mode >= 0) {
264                 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
265                 twl4030->codec_powered = enable;
266         }
267 
268         /* REVISIT: this delay is present in TI sample drivers */
269         /* but there seems to be no TRM requirement for it     */
270         udelay(10);
271 }
272 
273 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
274 {
275         int i, difference = 0;
276         u8 val;
277 
278         dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
279         for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
280                 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
281                 if (val != twl4030_reg[i]) {
282                         difference++;
283                         dev_dbg(codec->dev,
284                                  "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
285                                  i, val, twl4030_reg[i]);
286                 }
287         }
288         dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
289                  difference, difference ? "Not OK" : "OK");
290 }
291 
292 static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
293 {
294         int i;
295 
296         /* set all audio section registers to reasonable defaults */
297         for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
298                 if (i != TWL4030_REG_APLL_CTL)
299                         twl4030_write(codec, i, twl4030_reg[i]);
300 
301 }
302 
303 static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
304                                    struct device_node *node)
305 {
306         int value;
307 
308         of_property_read_u32(node, "ti,digimic_delay",
309                              &pdata->digimic_delay);
310         of_property_read_u32(node, "ti,ramp_delay_value",
311                              &pdata->ramp_delay_value);
312         of_property_read_u32(node, "ti,offset_cncl_path",
313                              &pdata->offset_cncl_path);
314         if (!of_property_read_u32(node, "ti,hs_extmute", &value))
315                 pdata->hs_extmute = value;
316 
317         pdata->hs_extmute_gpio = of_get_named_gpio(node,
318                                                    "ti,hs_extmute_gpio", 0);
319         if (gpio_is_valid(pdata->hs_extmute_gpio))
320                 pdata->hs_extmute = 1;
321 }
322 
323 static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
324 {
325         struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
326         struct device_node *twl4030_codec_node = NULL;
327 
328         twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
329                                                   "codec");
330 
331         if (!pdata && twl4030_codec_node) {
332                 pdata = devm_kzalloc(codec->dev,
333                                      sizeof(struct twl4030_codec_data),
334                                      GFP_KERNEL);
335                 if (!pdata) {
336                         dev_err(codec->dev, "Can not allocate memory\n");
337                         return NULL;
338                 }
339                 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
340         }
341 
342         return pdata;
343 }
344 
345 static void twl4030_init_chip(struct snd_soc_codec *codec)
346 {
347         struct twl4030_codec_data *pdata;
348         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
349         u8 reg, byte;
350         int i = 0;
351 
352         pdata = twl4030_get_pdata(codec);
353 
354         if (pdata && pdata->hs_extmute) {
355                 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
356                         int ret;
357 
358                         if (!pdata->hs_extmute_gpio)
359                                 dev_warn(codec->dev,
360                                         "Extmute GPIO is 0 is this correct?\n");
361 
362                         ret = gpio_request_one(pdata->hs_extmute_gpio,
363                                                GPIOF_OUT_INIT_LOW,
364                                                "hs_extmute");
365                         if (ret) {
366                                 dev_err(codec->dev,
367                                         "Failed to get hs_extmute GPIO\n");
368                                 pdata->hs_extmute_gpio = -1;
369                         }
370                 } else {
371                         u8 pin_mux;
372 
373                         /* Set TWL4030 GPIO6 as EXTMUTE signal */
374                         twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
375                                         TWL4030_PMBR1_REG);
376                         pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
377                         pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
378                         twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
379                                          TWL4030_PMBR1_REG);
380                 }
381         }
382 
383         /* Check defaults, if instructed before anything else */
384         if (pdata && pdata->check_defaults)
385                 twl4030_check_defaults(codec);
386 
387         /* Reset registers, if no setup data or if instructed to do so */
388         if (!pdata || (pdata && pdata->reset_registers))
389                 twl4030_reset_registers(codec);
390 
391         /* Refresh APLL_CTL register from HW */
392         twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
393                             TWL4030_REG_APLL_CTL);
394         twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
395 
396         /* anti-pop when changing analog gain */
397         reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
398         twl4030_write(codec, TWL4030_REG_MISC_SET_1,
399                 reg | TWL4030_SMOOTH_ANAVOL_EN);
400 
401         twl4030_write(codec, TWL4030_REG_OPTION,
402                 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
403                 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
404 
405         /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
406         twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
407 
408         /* Machine dependent setup */
409         if (!pdata)
410                 return;
411 
412         twl4030->pdata = pdata;
413 
414         reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
415         reg &= ~TWL4030_RAMP_DELAY;
416         reg |= (pdata->ramp_delay_value << 2);
417         twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
418 
419         /* initiate offset cancellation */
420         twl4030_codec_enable(codec, 1);
421 
422         reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
423         reg &= ~TWL4030_OFFSET_CNCL_SEL;
424         reg |= pdata->offset_cncl_path;
425         twl4030_write(codec, TWL4030_REG_ANAMICL,
426                 reg | TWL4030_CNCL_OFFSET_START);
427 
428         /*
429          * Wait for offset cancellation to complete.
430          * Since this takes a while, do not slam the i2c.
431          * Start polling the status after ~20ms.
432          */
433         msleep(20);
434         do {
435                 usleep_range(1000, 2000);
436                 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
437                                     TWL4030_REG_ANAMICL);
438         } while ((i++ < 100) &&
439                  ((byte & TWL4030_CNCL_OFFSET_START) ==
440                   TWL4030_CNCL_OFFSET_START));
441 
442         /* Make sure that the reg_cache has the same value as the HW */
443         twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
444 
445         twl4030_codec_enable(codec, 0);
446 }
447 
448 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
449 {
450         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
451         int status = -1;
452 
453         if (enable) {
454                 twl4030->apll_enabled++;
455                 if (twl4030->apll_enabled == 1)
456                         status = twl4030_audio_enable_resource(
457                                                         TWL4030_AUDIO_RES_APLL);
458         } else {
459                 twl4030->apll_enabled--;
460                 if (!twl4030->apll_enabled)
461                         status = twl4030_audio_disable_resource(
462                                                         TWL4030_AUDIO_RES_APLL);
463         }
464 
465         if (status >= 0)
466                 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
467 }
468 
469 /* Earpiece */
470 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
471         SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
472         SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
473         SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
474         SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
475 };
476 
477 /* PreDrive Left */
478 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
479         SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
480         SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
481         SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
482         SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
483 };
484 
485 /* PreDrive Right */
486 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
487         SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
488         SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
489         SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
490         SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
491 };
492 
493 /* Headset Left */
494 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
495         SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
496         SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
497         SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
498 };
499 
500 /* Headset Right */
501 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
502         SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
503         SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
504         SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
505 };
506 
507 /* Carkit Left */
508 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
509         SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
510         SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
511         SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
512 };
513 
514 /* Carkit Right */
515 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
516         SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
517         SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
518         SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
519 };
520 
521 /* Handsfree Left */
522 static const char *twl4030_handsfreel_texts[] =
523                 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
524 
525 static const struct soc_enum twl4030_handsfreel_enum =
526         SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
527                         ARRAY_SIZE(twl4030_handsfreel_texts),
528                         twl4030_handsfreel_texts);
529 
530 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
531 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
532 
533 /* Handsfree Left virtual mute */
534 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
535         SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
536 
537 /* Handsfree Right */
538 static const char *twl4030_handsfreer_texts[] =
539                 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
540 
541 static const struct soc_enum twl4030_handsfreer_enum =
542         SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
543                         ARRAY_SIZE(twl4030_handsfreer_texts),
544                         twl4030_handsfreer_texts);
545 
546 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
547 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
548 
549 /* Handsfree Right virtual mute */
550 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
551         SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
552 
553 /* Vibra */
554 /* Vibra audio path selection */
555 static const char *twl4030_vibra_texts[] =
556                 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
557 
558 static const struct soc_enum twl4030_vibra_enum =
559         SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
560                         ARRAY_SIZE(twl4030_vibra_texts),
561                         twl4030_vibra_texts);
562 
563 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
564 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
565 
566 /* Vibra path selection: local vibrator (PWM) or audio driven */
567 static const char *twl4030_vibrapath_texts[] =
568                 {"Local vibrator", "Audio"};
569 
570 static const struct soc_enum twl4030_vibrapath_enum =
571         SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
572                         ARRAY_SIZE(twl4030_vibrapath_texts),
573                         twl4030_vibrapath_texts);
574 
575 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
576 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
577 
578 /* Left analog microphone selection */
579 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
580         SOC_DAPM_SINGLE("Main Mic Capture Switch",
581                         TWL4030_REG_ANAMICL, 0, 1, 0),
582         SOC_DAPM_SINGLE("Headset Mic Capture Switch",
583                         TWL4030_REG_ANAMICL, 1, 1, 0),
584         SOC_DAPM_SINGLE("AUXL Capture Switch",
585                         TWL4030_REG_ANAMICL, 2, 1, 0),
586         SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
587                         TWL4030_REG_ANAMICL, 3, 1, 0),
588 };
589 
590 /* Right analog microphone selection */
591 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
592         SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
593         SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
594 };
595 
596 /* TX1 L/R Analog/Digital microphone selection */
597 static const char *twl4030_micpathtx1_texts[] =
598                 {"Analog", "Digimic0"};
599 
600 static const struct soc_enum twl4030_micpathtx1_enum =
601         SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
602                         ARRAY_SIZE(twl4030_micpathtx1_texts),
603                         twl4030_micpathtx1_texts);
604 
605 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
606 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
607 
608 /* TX2 L/R Analog/Digital microphone selection */
609 static const char *twl4030_micpathtx2_texts[] =
610                 {"Analog", "Digimic1"};
611 
612 static const struct soc_enum twl4030_micpathtx2_enum =
613         SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
614                         ARRAY_SIZE(twl4030_micpathtx2_texts),
615                         twl4030_micpathtx2_texts);
616 
617 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
618 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
619 
620 /* Analog bypass for AudioR1 */
621 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
622         SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
623 
624 /* Analog bypass for AudioL1 */
625 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
626         SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
627 
628 /* Analog bypass for AudioR2 */
629 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
630         SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
631 
632 /* Analog bypass for AudioL2 */
633 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
634         SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
635 
636 /* Analog bypass for Voice */
637 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
638         SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
639 
640 /* Digital bypass gain, mute instead of -30dB */
641 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
642         TLV_DB_RANGE_HEAD(3),
643         0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
644         2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
645         4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
646 };
647 
648 /* Digital bypass left (TX1L -> RX2L) */
649 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
650         SOC_DAPM_SINGLE_TLV("Volume",
651                         TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
652                         twl4030_dapm_dbypass_tlv);
653 
654 /* Digital bypass right (TX1R -> RX2R) */
655 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
656         SOC_DAPM_SINGLE_TLV("Volume",
657                         TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
658                         twl4030_dapm_dbypass_tlv);
659 
660 /*
661  * Voice Sidetone GAIN volume control:
662  * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
663  */
664 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
665 
666 /* Digital bypass voice: sidetone (VUL -> VDL)*/
667 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
668         SOC_DAPM_SINGLE_TLV("Volume",
669                         TWL4030_REG_VSTPGA, 0, 0x29, 0,
670                         twl4030_dapm_dbypassv_tlv);
671 
672 /*
673  * Output PGA builder:
674  * Handle the muting and unmuting of the given output (turning off the
675  * amplifier associated with the output pin)
676  * On mute bypass the reg_cache and write 0 to the register
677  * On unmute: restore the register content from the reg_cache
678  * Outputs handled in this way:  Earpiece, PreDrivL/R, CarkitL/R
679  */
680 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask)                         \
681 static int pin_name##pga_event(struct snd_soc_dapm_widget *w,           \
682                 struct snd_kcontrol *kcontrol, int event)               \
683 {                                                                       \
684         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
685                                                                         \
686         switch (event) {                                                \
687         case SND_SOC_DAPM_POST_PMU:                                     \
688                 twl4030->pin_name##_enabled = 1;                        \
689                 twl4030_write(w->codec, reg,                            \
690                         twl4030_read_reg_cache(w->codec, reg));         \
691                 break;                                                  \
692         case SND_SOC_DAPM_POST_PMD:                                     \
693                 twl4030->pin_name##_enabled = 0;                        \
694                 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,            \
695                                         0, reg);                        \
696                 break;                                                  \
697         }                                                               \
698         return 0;                                                       \
699 }
700 
701 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
702 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
703 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
704 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
705 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
706 
707 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
708 {
709         unsigned char hs_ctl;
710 
711         hs_ctl = twl4030_read_reg_cache(codec, reg);
712 
713         if (ramp) {
714                 /* HF ramp-up */
715                 hs_ctl |= TWL4030_HF_CTL_REF_EN;
716                 twl4030_write(codec, reg, hs_ctl);
717                 udelay(10);
718                 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
719                 twl4030_write(codec, reg, hs_ctl);
720                 udelay(40);
721                 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
722                 hs_ctl |= TWL4030_HF_CTL_HB_EN;
723                 twl4030_write(codec, reg, hs_ctl);
724         } else {
725                 /* HF ramp-down */
726                 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
727                 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
728                 twl4030_write(codec, reg, hs_ctl);
729                 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
730                 twl4030_write(codec, reg, hs_ctl);
731                 udelay(40);
732                 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
733                 twl4030_write(codec, reg, hs_ctl);
734         }
735 }
736 
737 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
738                 struct snd_kcontrol *kcontrol, int event)
739 {
740         switch (event) {
741         case SND_SOC_DAPM_POST_PMU:
742                 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
743                 break;
744         case SND_SOC_DAPM_POST_PMD:
745                 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
746                 break;
747         }
748         return 0;
749 }
750 
751 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
752                 struct snd_kcontrol *kcontrol, int event)
753 {
754         switch (event) {
755         case SND_SOC_DAPM_POST_PMU:
756                 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
757                 break;
758         case SND_SOC_DAPM_POST_PMD:
759                 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
760                 break;
761         }
762         return 0;
763 }
764 
765 static int vibramux_event(struct snd_soc_dapm_widget *w,
766                 struct snd_kcontrol *kcontrol, int event)
767 {
768         twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
769         return 0;
770 }
771 
772 static int apll_event(struct snd_soc_dapm_widget *w,
773                 struct snd_kcontrol *kcontrol, int event)
774 {
775         switch (event) {
776         case SND_SOC_DAPM_PRE_PMU:
777                 twl4030_apll_enable(w->codec, 1);
778                 break;
779         case SND_SOC_DAPM_POST_PMD:
780                 twl4030_apll_enable(w->codec, 0);
781                 break;
782         }
783         return 0;
784 }
785 
786 static int aif_event(struct snd_soc_dapm_widget *w,
787                 struct snd_kcontrol *kcontrol, int event)
788 {
789         u8 audio_if;
790 
791         audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
792         switch (event) {
793         case SND_SOC_DAPM_PRE_PMU:
794                 /* Enable AIF */
795                 /* enable the PLL before we use it to clock the DAI */
796                 twl4030_apll_enable(w->codec, 1);
797 
798                 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
799                                                 audio_if | TWL4030_AIF_EN);
800                 break;
801         case SND_SOC_DAPM_POST_PMD:
802                 /* disable the DAI before we stop it's source PLL */
803                 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
804                                                 audio_if &  ~TWL4030_AIF_EN);
805                 twl4030_apll_enable(w->codec, 0);
806                 break;
807         }
808         return 0;
809 }
810 
811 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
812 {
813         unsigned char hs_gain, hs_pop;
814         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
815         struct twl4030_codec_data *pdata = twl4030->pdata;
816         /* Base values for ramp delay calculation: 2^19 - 2^26 */
817         unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
818                                     8388608, 16777216, 33554432, 67108864};
819         unsigned int delay;
820 
821         hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
822         hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
823         delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
824                 twl4030->sysclk) + 1;
825 
826         /* Enable external mute control, this dramatically reduces
827          * the pop-noise */
828         if (pdata && pdata->hs_extmute) {
829                 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
830                         gpio_set_value(pdata->hs_extmute_gpio, 1);
831                 } else {
832                         hs_pop |= TWL4030_EXTMUTE;
833                         twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
834                 }
835         }
836 
837         if (ramp) {
838                 /* Headset ramp-up according to the TRM */
839                 hs_pop |= TWL4030_VMID_EN;
840                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
841                 /* Actually write to the register */
842                 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
843                                         hs_gain,
844                                         TWL4030_REG_HS_GAIN_SET);
845                 hs_pop |= TWL4030_RAMP_EN;
846                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
847                 /* Wait ramp delay time + 1, so the VMID can settle */
848                 twl4030_wait_ms(delay);
849         } else {
850                 /* Headset ramp-down _not_ according to
851                  * the TRM, but in a way that it is working */
852                 hs_pop &= ~TWL4030_RAMP_EN;
853                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
854                 /* Wait ramp delay time + 1, so the VMID can settle */
855                 twl4030_wait_ms(delay);
856                 /* Bypass the reg_cache to mute the headset */
857                 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
858                                         hs_gain & (~0x0f),
859                                         TWL4030_REG_HS_GAIN_SET);
860 
861                 hs_pop &= ~TWL4030_VMID_EN;
862                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
863         }
864 
865         /* Disable external mute */
866         if (pdata && pdata->hs_extmute) {
867                 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
868                         gpio_set_value(pdata->hs_extmute_gpio, 0);
869                 } else {
870                         hs_pop &= ~TWL4030_EXTMUTE;
871                         twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
872                 }
873         }
874 }
875 
876 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
877                 struct snd_kcontrol *kcontrol, int event)
878 {
879         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
880 
881         switch (event) {
882         case SND_SOC_DAPM_POST_PMU:
883                 /* Do the ramp-up only once */
884                 if (!twl4030->hsr_enabled)
885                         headset_ramp(w->codec, 1);
886 
887                 twl4030->hsl_enabled = 1;
888                 break;
889         case SND_SOC_DAPM_POST_PMD:
890                 /* Do the ramp-down only if both headsetL/R is disabled */
891                 if (!twl4030->hsr_enabled)
892                         headset_ramp(w->codec, 0);
893 
894                 twl4030->hsl_enabled = 0;
895                 break;
896         }
897         return 0;
898 }
899 
900 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
901                 struct snd_kcontrol *kcontrol, int event)
902 {
903         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
904 
905         switch (event) {
906         case SND_SOC_DAPM_POST_PMU:
907                 /* Do the ramp-up only once */
908                 if (!twl4030->hsl_enabled)
909                         headset_ramp(w->codec, 1);
910 
911                 twl4030->hsr_enabled = 1;
912                 break;
913         case SND_SOC_DAPM_POST_PMD:
914                 /* Do the ramp-down only if both headsetL/R is disabled */
915                 if (!twl4030->hsl_enabled)
916                         headset_ramp(w->codec, 0);
917 
918                 twl4030->hsr_enabled = 0;
919                 break;
920         }
921         return 0;
922 }
923 
924 static int digimic_event(struct snd_soc_dapm_widget *w,
925                 struct snd_kcontrol *kcontrol, int event)
926 {
927         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
928         struct twl4030_codec_data *pdata = twl4030->pdata;
929 
930         if (pdata && pdata->digimic_delay)
931                 twl4030_wait_ms(pdata->digimic_delay);
932         return 0;
933 }
934 
935 /*
936  * Some of the gain controls in TWL (mostly those which are associated with
937  * the outputs) are implemented in an interesting way:
938  * 0x0 : Power down (mute)
939  * 0x1 : 6dB
940  * 0x2 : 0 dB
941  * 0x3 : -6 dB
942  * Inverting not going to help with these.
943  * Custom volsw and volsw_2r get/put functions to handle these gain bits.
944  */
945 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
946         struct snd_ctl_elem_value *ucontrol)
947 {
948         struct soc_mixer_control *mc =
949                 (struct soc_mixer_control *)kcontrol->private_value;
950         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
951         unsigned int reg = mc->reg;
952         unsigned int shift = mc->shift;
953         unsigned int rshift = mc->rshift;
954         int max = mc->max;
955         int mask = (1 << fls(max)) - 1;
956 
957         ucontrol->value.integer.value[0] =
958                 (snd_soc_read(codec, reg) >> shift) & mask;
959         if (ucontrol->value.integer.value[0])
960                 ucontrol->value.integer.value[0] =
961                         max + 1 - ucontrol->value.integer.value[0];
962 
963         if (shift != rshift) {
964                 ucontrol->value.integer.value[1] =
965                         (snd_soc_read(codec, reg) >> rshift) & mask;
966                 if (ucontrol->value.integer.value[1])
967                         ucontrol->value.integer.value[1] =
968                                 max + 1 - ucontrol->value.integer.value[1];
969         }
970 
971         return 0;
972 }
973 
974 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
975         struct snd_ctl_elem_value *ucontrol)
976 {
977         struct soc_mixer_control *mc =
978                 (struct soc_mixer_control *)kcontrol->private_value;
979         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
980         unsigned int reg = mc->reg;
981         unsigned int shift = mc->shift;
982         unsigned int rshift = mc->rshift;
983         int max = mc->max;
984         int mask = (1 << fls(max)) - 1;
985         unsigned short val, val2, val_mask;
986 
987         val = (ucontrol->value.integer.value[0] & mask);
988 
989         val_mask = mask << shift;
990         if (val)
991                 val = max + 1 - val;
992         val = val << shift;
993         if (shift != rshift) {
994                 val2 = (ucontrol->value.integer.value[1] & mask);
995                 val_mask |= mask << rshift;
996                 if (val2)
997                         val2 = max + 1 - val2;
998                 val |= val2 << rshift;
999         }
1000         return snd_soc_update_bits(codec, reg, val_mask, val);
1001 }
1002 
1003 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1004         struct snd_ctl_elem_value *ucontrol)
1005 {
1006         struct soc_mixer_control *mc =
1007                 (struct soc_mixer_control *)kcontrol->private_value;
1008         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1009         unsigned int reg = mc->reg;
1010         unsigned int reg2 = mc->rreg;
1011         unsigned int shift = mc->shift;
1012         int max = mc->max;
1013         int mask = (1<<fls(max))-1;
1014 
1015         ucontrol->value.integer.value[0] =
1016                 (snd_soc_read(codec, reg) >> shift) & mask;
1017         ucontrol->value.integer.value[1] =
1018                 (snd_soc_read(codec, reg2) >> shift) & mask;
1019 
1020         if (ucontrol->value.integer.value[0])
1021                 ucontrol->value.integer.value[0] =
1022                         max + 1 - ucontrol->value.integer.value[0];
1023         if (ucontrol->value.integer.value[1])
1024                 ucontrol->value.integer.value[1] =
1025                         max + 1 - ucontrol->value.integer.value[1];
1026 
1027         return 0;
1028 }
1029 
1030 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1031         struct snd_ctl_elem_value *ucontrol)
1032 {
1033         struct soc_mixer_control *mc =
1034                 (struct soc_mixer_control *)kcontrol->private_value;
1035         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1036         unsigned int reg = mc->reg;
1037         unsigned int reg2 = mc->rreg;
1038         unsigned int shift = mc->shift;
1039         int max = mc->max;
1040         int mask = (1 << fls(max)) - 1;
1041         int err;
1042         unsigned short val, val2, val_mask;
1043 
1044         val_mask = mask << shift;
1045         val = (ucontrol->value.integer.value[0] & mask);
1046         val2 = (ucontrol->value.integer.value[1] & mask);
1047 
1048         if (val)
1049                 val = max + 1 - val;
1050         if (val2)
1051                 val2 = max + 1 - val2;
1052 
1053         val = val << shift;
1054         val2 = val2 << shift;
1055 
1056         err = snd_soc_update_bits(codec, reg, val_mask, val);
1057         if (err < 0)
1058                 return err;
1059 
1060         err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1061         return err;
1062 }
1063 
1064 /* Codec operation modes */
1065 static const char *twl4030_op_modes_texts[] = {
1066         "Option 2 (voice/audio)", "Option 1 (audio)"
1067 };
1068 
1069 static const struct soc_enum twl4030_op_modes_enum =
1070         SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1071                         ARRAY_SIZE(twl4030_op_modes_texts),
1072                         twl4030_op_modes_texts);
1073 
1074 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1075         struct snd_ctl_elem_value *ucontrol)
1076 {
1077         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1078         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1079         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1080         unsigned short val;
1081         unsigned short mask;
1082 
1083         if (twl4030->configured) {
1084                 dev_err(codec->dev,
1085                         "operation mode cannot be changed on-the-fly\n");
1086                 return -EBUSY;
1087         }
1088 
1089         if (ucontrol->value.enumerated.item[0] > e->max - 1)
1090                 return -EINVAL;
1091 
1092         val = ucontrol->value.enumerated.item[0] << e->shift_l;
1093         mask = e->mask << e->shift_l;
1094         if (e->shift_l != e->shift_r) {
1095                 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1096                         return -EINVAL;
1097                 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1098                 mask |= e->mask << e->shift_r;
1099         }
1100 
1101         return snd_soc_update_bits(codec, e->reg, mask, val);
1102 }
1103 
1104 /*
1105  * FGAIN volume control:
1106  * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1107  */
1108 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1109 
1110 /*
1111  * CGAIN volume control:
1112  * 0 dB to 12 dB in 6 dB steps
1113  * value 2 and 3 means 12 dB
1114  */
1115 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1116 
1117 /*
1118  * Voice Downlink GAIN volume control:
1119  * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1120  */
1121 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1122 
1123 /*
1124  * Analog playback gain
1125  * -24 dB to 12 dB in 2 dB steps
1126  */
1127 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1128 
1129 /*
1130  * Gain controls tied to outputs
1131  * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1132  */
1133 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1134 
1135 /*
1136  * Gain control for earpiece amplifier
1137  * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1138  */
1139 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1140 
1141 /*
1142  * Capture gain after the ADCs
1143  * from 0 dB to 31 dB in 1 dB steps
1144  */
1145 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1146 
1147 /*
1148  * Gain control for input amplifiers
1149  * 0 dB to 30 dB in 6 dB steps
1150  */
1151 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1152 
1153 /* AVADC clock priority */
1154 static const char *twl4030_avadc_clk_priority_texts[] = {
1155         "Voice high priority", "HiFi high priority"
1156 };
1157 
1158 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1159         SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1160                         ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1161                         twl4030_avadc_clk_priority_texts);
1162 
1163 static const char *twl4030_rampdelay_texts[] = {
1164         "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1165         "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1166         "3495/2581/1748 ms"
1167 };
1168 
1169 static const struct soc_enum twl4030_rampdelay_enum =
1170         SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1171                         ARRAY_SIZE(twl4030_rampdelay_texts),
1172                         twl4030_rampdelay_texts);
1173 
1174 /* Vibra H-bridge direction mode */
1175 static const char *twl4030_vibradirmode_texts[] = {
1176         "Vibra H-bridge direction", "Audio data MSB",
1177 };
1178 
1179 static const struct soc_enum twl4030_vibradirmode_enum =
1180         SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1181                         ARRAY_SIZE(twl4030_vibradirmode_texts),
1182                         twl4030_vibradirmode_texts);
1183 
1184 /* Vibra H-bridge direction */
1185 static const char *twl4030_vibradir_texts[] = {
1186         "Positive polarity", "Negative polarity",
1187 };
1188 
1189 static const struct soc_enum twl4030_vibradir_enum =
1190         SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1191                         ARRAY_SIZE(twl4030_vibradir_texts),
1192                         twl4030_vibradir_texts);
1193 
1194 /* Digimic Left and right swapping */
1195 static const char *twl4030_digimicswap_texts[] = {
1196         "Not swapped", "Swapped",
1197 };
1198 
1199 static const struct soc_enum twl4030_digimicswap_enum =
1200         SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1201                         ARRAY_SIZE(twl4030_digimicswap_texts),
1202                         twl4030_digimicswap_texts);
1203 
1204 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1205         /* Codec operation mode control */
1206         SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1207                 snd_soc_get_enum_double,
1208                 snd_soc_put_twl4030_opmode_enum_double),
1209 
1210         /* Common playback gain controls */
1211         SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1212                 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1213                 0, 0x3f, 0, digital_fine_tlv),
1214         SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1215                 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1216                 0, 0x3f, 0, digital_fine_tlv),
1217 
1218         SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1219                 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1220                 6, 0x2, 0, digital_coarse_tlv),
1221         SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1222                 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1223                 6, 0x2, 0, digital_coarse_tlv),
1224 
1225         SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1226                 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1227                 3, 0x12, 1, analog_tlv),
1228         SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1229                 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1230                 3, 0x12, 1, analog_tlv),
1231         SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1232                 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1233                 1, 1, 0),
1234         SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1235                 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1236                 1, 1, 0),
1237 
1238         /* Common voice downlink gain controls */
1239         SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1240                 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1241 
1242         SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1243                 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1244 
1245         SOC_SINGLE("DAC Voice Analog Downlink Switch",
1246                 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1247 
1248         /* Separate output gain controls */
1249         SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
1250                 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1251                 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1252                 snd_soc_put_volsw_r2_twl4030, output_tvl),
1253 
1254         SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1255                 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1256                 snd_soc_put_volsw_twl4030, output_tvl),
1257 
1258         SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
1259                 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1260                 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1261                 snd_soc_put_volsw_r2_twl4030, output_tvl),
1262 
1263         SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1264                 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1265                 snd_soc_put_volsw_twl4030, output_ear_tvl),
1266 
1267         /* Common capture gain controls */
1268         SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1269                 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1270                 0, 0x1f, 0, digital_capture_tlv),
1271         SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1272                 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1273                 0, 0x1f, 0, digital_capture_tlv),
1274 
1275         SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1276                 0, 3, 5, 0, input_gain_tlv),
1277 
1278         SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1279 
1280         SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1281 
1282         SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1283         SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1284 
1285         SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1286 };
1287 
1288 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1289         /* Left channel inputs */
1290         SND_SOC_DAPM_INPUT("MAINMIC"),
1291         SND_SOC_DAPM_INPUT("HSMIC"),
1292         SND_SOC_DAPM_INPUT("AUXL"),
1293         SND_SOC_DAPM_INPUT("CARKITMIC"),
1294         /* Right channel inputs */
1295         SND_SOC_DAPM_INPUT("SUBMIC"),
1296         SND_SOC_DAPM_INPUT("AUXR"),
1297         /* Digital microphones (Stereo) */
1298         SND_SOC_DAPM_INPUT("DIGIMIC0"),
1299         SND_SOC_DAPM_INPUT("DIGIMIC1"),
1300 
1301         /* Outputs */
1302         SND_SOC_DAPM_OUTPUT("EARPIECE"),
1303         SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1304         SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1305         SND_SOC_DAPM_OUTPUT("HSOL"),
1306         SND_SOC_DAPM_OUTPUT("HSOR"),
1307         SND_SOC_DAPM_OUTPUT("CARKITL"),
1308         SND_SOC_DAPM_OUTPUT("CARKITR"),
1309         SND_SOC_DAPM_OUTPUT("HFL"),
1310         SND_SOC_DAPM_OUTPUT("HFR"),
1311         SND_SOC_DAPM_OUTPUT("VIBRA"),
1312 
1313         /* AIF and APLL clocks for running DAIs (including loopback) */
1314         SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1315         SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1316         SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1317 
1318         /* DACs */
1319         SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1320         SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1321         SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1322         SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1323         SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1324 
1325         SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1326                             TWL4030_REG_VOICE_IF, 6, 0),
1327 
1328         /* Analog bypasses */
1329         SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1330                         &twl4030_dapm_abypassr1_control),
1331         SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1332                         &twl4030_dapm_abypassl1_control),
1333         SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1334                         &twl4030_dapm_abypassr2_control),
1335         SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1336                         &twl4030_dapm_abypassl2_control),
1337         SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1338                         &twl4030_dapm_abypassv_control),
1339 
1340         /* Master analog loopback switch */
1341         SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1342                             NULL, 0),
1343 
1344         /* Digital bypasses */
1345         SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1346                         &twl4030_dapm_dbypassl_control),
1347         SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1348                         &twl4030_dapm_dbypassr_control),
1349         SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1350                         &twl4030_dapm_dbypassv_control),
1351 
1352         /* Digital mixers, power control for the physical DACs */
1353         SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1354                         TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1355         SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1356                         TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1357         SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1358                         TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1359         SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1360                         TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1361         SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1362                         TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1363 
1364         /* Analog mixers, power control for the physical PGAs */
1365         SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1366                         TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1367         SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1368                         TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1369         SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1370                         TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1371         SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1372                         TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1373         SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1374                         TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1375 
1376         SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1377                             SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1378 
1379         SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1380                             SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1381 
1382         /* Output MIXER controls */
1383         /* Earpiece */
1384         SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1385                         &twl4030_dapm_earpiece_controls[0],
1386                         ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1387         SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1388                         0, 0, NULL, 0, earpiecepga_event,
1389                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1390         /* PreDrivL/R */
1391         SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1392                         &twl4030_dapm_predrivel_controls[0],
1393                         ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1394         SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1395                         0, 0, NULL, 0, predrivelpga_event,
1396                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1397         SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1398                         &twl4030_dapm_predriver_controls[0],
1399                         ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1400         SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1401                         0, 0, NULL, 0, predriverpga_event,
1402                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1403         /* HeadsetL/R */
1404         SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1405                         &twl4030_dapm_hsol_controls[0],
1406                         ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1407         SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1408                         0, 0, NULL, 0, headsetlpga_event,
1409                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1410         SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1411                         &twl4030_dapm_hsor_controls[0],
1412                         ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1413         SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1414                         0, 0, NULL, 0, headsetrpga_event,
1415                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1416         /* CarkitL/R */
1417         SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1418                         &twl4030_dapm_carkitl_controls[0],
1419                         ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1420         SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1421                         0, 0, NULL, 0, carkitlpga_event,
1422                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1423         SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1424                         &twl4030_dapm_carkitr_controls[0],
1425                         ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1426         SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1427                         0, 0, NULL, 0, carkitrpga_event,
1428                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1429 
1430         /* Output MUX controls */
1431         /* HandsfreeL/R */
1432         SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1433                 &twl4030_dapm_handsfreel_control),
1434         SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1435                         &twl4030_dapm_handsfreelmute_control),
1436         SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1437                         0, 0, NULL, 0, handsfreelpga_event,
1438                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1439         SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1440                 &twl4030_dapm_handsfreer_control),
1441         SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1442                         &twl4030_dapm_handsfreermute_control),
1443         SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1444                         0, 0, NULL, 0, handsfreerpga_event,
1445                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1446         /* Vibra */
1447         SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1448                            &twl4030_dapm_vibra_control, vibramux_event,
1449                            SND_SOC_DAPM_PRE_PMU),
1450         SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1451                 &twl4030_dapm_vibrapath_control),
1452 
1453         /* Introducing four virtual ADC, since TWL4030 have four channel for
1454            capture */
1455         SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1456         SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1457         SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1458         SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1459 
1460         SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1461                              TWL4030_REG_VOICE_IF, 5, 0),
1462 
1463         /* Analog/Digital mic path selection.
1464            TX1 Left/Right: either analog Left/Right or Digimic0
1465            TX2 Left/Right: either analog Left/Right or Digimic1 */
1466         SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1467                 &twl4030_dapm_micpathtx1_control),
1468         SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1469                 &twl4030_dapm_micpathtx2_control),
1470 
1471         /* Analog input mixers for the capture amplifiers */
1472         SND_SOC_DAPM_MIXER("Analog Left",
1473                 TWL4030_REG_ANAMICL, 4, 0,
1474                 &twl4030_dapm_analoglmic_controls[0],
1475                 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1476         SND_SOC_DAPM_MIXER("Analog Right",
1477                 TWL4030_REG_ANAMICR, 4, 0,
1478                 &twl4030_dapm_analogrmic_controls[0],
1479                 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1480 
1481         SND_SOC_DAPM_PGA("ADC Physical Left",
1482                 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1483         SND_SOC_DAPM_PGA("ADC Physical Right",
1484                 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1485 
1486         SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1487                 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1488                 digimic_event, SND_SOC_DAPM_POST_PMU),
1489         SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1490                 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1491                 digimic_event, SND_SOC_DAPM_POST_PMU),
1492 
1493         SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1494                             NULL, 0),
1495         SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1496                             NULL, 0),
1497 
1498         /* Microphone bias */
1499         SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1500                             TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1501         SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1502                             TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1503         SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1504                             TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
1505 
1506         SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
1507 };
1508 
1509 static const struct snd_soc_dapm_route intercon[] = {
1510         /* Stream -> DAC mapping */
1511         {"DAC Right1", NULL, "HiFi Playback"},
1512         {"DAC Left1", NULL, "HiFi Playback"},
1513         {"DAC Right2", NULL, "HiFi Playback"},
1514         {"DAC Left2", NULL, "HiFi Playback"},
1515         {"DAC Voice", NULL, "VAIFIN"},
1516 
1517         /* ADC -> Stream mapping */
1518         {"HiFi Capture", NULL, "ADC Virtual Left1"},
1519         {"HiFi Capture", NULL, "ADC Virtual Right1"},
1520         {"HiFi Capture", NULL, "ADC Virtual Left2"},
1521         {"HiFi Capture", NULL, "ADC Virtual Right2"},
1522         {"VAIFOUT", NULL, "ADC Virtual Left2"},
1523         {"VAIFOUT", NULL, "ADC Virtual Right2"},
1524         {"VAIFOUT", NULL, "VIF Enable"},
1525 
1526         {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1527         {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1528         {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1529         {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1530         {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1531 
1532         /* Supply for the digital part (APLL) */
1533         {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1534 
1535         {"DAC Left1", NULL, "AIF Enable"},
1536         {"DAC Right1", NULL, "AIF Enable"},
1537         {"DAC Left2", NULL, "AIF Enable"},
1538         {"DAC Right1", NULL, "AIF Enable"},
1539         {"DAC Voice", NULL, "VIF Enable"},
1540 
1541         {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1542         {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1543 
1544         {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1545         {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1546         {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1547         {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1548         {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1549 
1550         /* Internal playback routings */
1551         /* Earpiece */
1552         {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1553         {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1554         {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1555         {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1556         {"Earpiece PGA", NULL, "Earpiece Mixer"},
1557         /* PreDrivL */
1558         {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1559         {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1560         {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1561         {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1562         {"PredriveL PGA", NULL, "PredriveL Mixer"},
1563         /* PreDrivR */
1564         {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1565         {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1566         {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1567         {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1568         {"PredriveR PGA", NULL, "PredriveR Mixer"},
1569         /* HeadsetL */
1570         {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1571         {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1572         {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1573         {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1574         /* HeadsetR */
1575         {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1576         {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1577         {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1578         {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1579         /* CarkitL */
1580         {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1581         {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1582         {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1583         {"CarkitL PGA", NULL, "CarkitL Mixer"},
1584         /* CarkitR */
1585         {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1586         {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1587         {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1588         {"CarkitR PGA", NULL, "CarkitR Mixer"},
1589         /* HandsfreeL */
1590         {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1591         {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1592         {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1593         {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1594         {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1595         {"HandsfreeL PGA", NULL, "HandsfreeL"},
1596         /* HandsfreeR */
1597         {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1598         {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1599         {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1600         {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1601         {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1602         {"HandsfreeR PGA", NULL, "HandsfreeR"},
1603         /* Vibra */
1604         {"Vibra Mux", "AudioL1", "DAC Left1"},
1605         {"Vibra Mux", "AudioR1", "DAC Right1"},
1606         {"Vibra Mux", "AudioL2", "DAC Left2"},
1607         {"Vibra Mux", "AudioR2", "DAC Right2"},
1608 
1609         /* outputs */
1610         /* Must be always connected (for AIF and APLL) */
1611         {"Virtual HiFi OUT", NULL, "DAC Left1"},
1612         {"Virtual HiFi OUT", NULL, "DAC Right1"},
1613         {"Virtual HiFi OUT", NULL, "DAC Left2"},
1614         {"Virtual HiFi OUT", NULL, "DAC Right2"},
1615         /* Must be always connected (for APLL) */
1616         {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1617         /* Physical outputs */
1618         {"EARPIECE", NULL, "Earpiece PGA"},
1619         {"PREDRIVEL", NULL, "PredriveL PGA"},
1620         {"PREDRIVER", NULL, "PredriveR PGA"},
1621         {"HSOL", NULL, "HeadsetL PGA"},
1622         {"HSOR", NULL, "HeadsetR PGA"},
1623         {"CARKITL", NULL, "CarkitL PGA"},
1624         {"CARKITR", NULL, "CarkitR PGA"},
1625         {"HFL", NULL, "HandsfreeL PGA"},
1626         {"HFR", NULL, "HandsfreeR PGA"},
1627         {"Vibra Route", "Audio", "Vibra Mux"},
1628         {"VIBRA", NULL, "Vibra Route"},
1629 
1630         /* Capture path */
1631         /* Must be always connected (for AIF and APLL) */
1632         {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1633         {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1634         {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1635         {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1636         /* Physical inputs */
1637         {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1638         {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1639         {"Analog Left", "AUXL Capture Switch", "AUXL"},
1640         {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1641 
1642         {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1643         {"Analog Right", "AUXR Capture Switch", "AUXR"},
1644 
1645         {"ADC Physical Left", NULL, "Analog Left"},
1646         {"ADC Physical Right", NULL, "Analog Right"},
1647 
1648         {"Digimic0 Enable", NULL, "DIGIMIC0"},
1649         {"Digimic1 Enable", NULL, "DIGIMIC1"},
1650 
1651         {"DIGIMIC0", NULL, "micbias1 select"},
1652         {"DIGIMIC1", NULL, "micbias2 select"},
1653 
1654         /* TX1 Left capture path */
1655         {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1656         {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1657         /* TX1 Right capture path */
1658         {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1659         {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1660         /* TX2 Left capture path */
1661         {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1662         {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1663         /* TX2 Right capture path */
1664         {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1665         {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1666 
1667         {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1668         {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1669         {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1670         {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1671 
1672         {"ADC Virtual Left1", NULL, "AIF Enable"},
1673         {"ADC Virtual Right1", NULL, "AIF Enable"},
1674         {"ADC Virtual Left2", NULL, "AIF Enable"},
1675         {"ADC Virtual Right2", NULL, "AIF Enable"},
1676 
1677         /* Analog bypass routes */
1678         {"Right1 Analog Loopback", "Switch", "Analog Right"},
1679         {"Left1 Analog Loopback", "Switch", "Analog Left"},
1680         {"Right2 Analog Loopback", "Switch", "Analog Right"},
1681         {"Left2 Analog Loopback", "Switch", "Analog Left"},
1682         {"Voice Analog Loopback", "Switch", "Analog Left"},
1683 
1684         /* Supply for the Analog loopbacks */
1685         {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1686         {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1687         {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1688         {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1689         {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1690 
1691         {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1692         {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1693         {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1694         {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1695         {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1696 
1697         /* Digital bypass routes */
1698         {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1699         {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1700         {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1701 
1702         {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1703         {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1704         {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1705 
1706 };
1707 
1708 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1709                                   enum snd_soc_bias_level level)
1710 {
1711         switch (level) {
1712         case SND_SOC_BIAS_ON:
1713                 break;
1714         case SND_SOC_BIAS_PREPARE:
1715                 break;
1716         case SND_SOC_BIAS_STANDBY:
1717                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1718                         twl4030_codec_enable(codec, 1);
1719                 break;
1720         case SND_SOC_BIAS_OFF:
1721                 twl4030_codec_enable(codec, 0);
1722                 break;
1723         }
1724         codec->dapm.bias_level = level;
1725 
1726         return 0;
1727 }
1728 
1729 static void twl4030_constraints(struct twl4030_priv *twl4030,
1730                                 struct snd_pcm_substream *mst_substream)
1731 {
1732         struct snd_pcm_substream *slv_substream;
1733 
1734         /* Pick the stream, which need to be constrained */
1735         if (mst_substream == twl4030->master_substream)
1736                 slv_substream = twl4030->slave_substream;
1737         else if (mst_substream == twl4030->slave_substream)
1738                 slv_substream = twl4030->master_substream;
1739         else /* This should not happen.. */
1740                 return;
1741 
1742         /* Set the constraints according to the already configured stream */
1743         snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1744                                 SNDRV_PCM_HW_PARAM_RATE,
1745                                 twl4030->rate,
1746                                 twl4030->rate);
1747 
1748         snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1749                                 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1750                                 twl4030->sample_bits,
1751                                 twl4030->sample_bits);
1752 
1753         snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1754                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1755                                 twl4030->channels,
1756                                 twl4030->channels);
1757 }
1758 
1759 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1760  * capture has to be enabled/disabled. */
1761 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1762                                 int enable)
1763 {
1764         u8 reg, mask;
1765 
1766         reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1767 
1768         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1769                 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1770         else
1771                 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1772 
1773         if (enable)
1774                 reg |= mask;
1775         else
1776                 reg &= ~mask;
1777 
1778         twl4030_write(codec, TWL4030_REG_OPTION, reg);
1779 }
1780 
1781 static int twl4030_startup(struct snd_pcm_substream *substream,
1782                            struct snd_soc_dai *dai)
1783 {
1784         struct snd_soc_codec *codec = dai->codec;
1785         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1786 
1787         if (twl4030->master_substream) {
1788                 twl4030->slave_substream = substream;
1789                 /* The DAI has one configuration for playback and capture, so
1790                  * if the DAI has been already configured then constrain this
1791                  * substream to match it. */
1792                 if (twl4030->configured)
1793                         twl4030_constraints(twl4030, twl4030->master_substream);
1794         } else {
1795                 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1796                         TWL4030_OPTION_1)) {
1797                         /* In option2 4 channel is not supported, set the
1798                          * constraint for the first stream for channels, the
1799                          * second stream will 'inherit' this cosntraint */
1800                         snd_pcm_hw_constraint_minmax(substream->runtime,
1801                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1802                                                 2, 2);
1803                 }
1804                 twl4030->master_substream = substream;
1805         }
1806 
1807         return 0;
1808 }
1809 
1810 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1811                              struct snd_soc_dai *dai)
1812 {
1813         struct snd_soc_codec *codec = dai->codec;
1814         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1815 
1816         if (twl4030->master_substream == substream)
1817                 twl4030->master_substream = twl4030->slave_substream;
1818 
1819         twl4030->slave_substream = NULL;
1820 
1821         /* If all streams are closed, or the remaining stream has not yet
1822          * been configured than set the DAI as not configured. */
1823         if (!twl4030->master_substream)
1824                 twl4030->configured = 0;
1825          else if (!twl4030->master_substream->runtime->channels)
1826                 twl4030->configured = 0;
1827 
1828          /* If the closing substream had 4 channel, do the necessary cleanup */
1829         if (substream->runtime->channels == 4)
1830                 twl4030_tdm_enable(codec, substream->stream, 0);
1831 }
1832 
1833 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1834                            struct snd_pcm_hw_params *params,
1835                            struct snd_soc_dai *dai)
1836 {
1837         struct snd_soc_codec *codec = dai->codec;
1838         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1839         u8 mode, old_mode, format, old_format;
1840 
1841          /* If the substream has 4 channel, do the necessary setup */
1842         if (params_channels(params) == 4) {
1843                 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1844                 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1845 
1846                 /* Safety check: are we in the correct operating mode and
1847                  * the interface is in TDM mode? */
1848                 if ((mode & TWL4030_OPTION_1) &&
1849                     ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1850                         twl4030_tdm_enable(codec, substream->stream, 1);
1851                 else
1852                         return -EINVAL;
1853         }
1854 
1855         if (twl4030->configured)
1856                 /* Ignoring hw_params for already configured DAI */
1857                 return 0;
1858 
1859         /* bit rate */
1860         old_mode = twl4030_read_reg_cache(codec,
1861                         TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1862         mode = old_mode & ~TWL4030_APLL_RATE;
1863 
1864         switch (params_rate(params)) {
1865         case 8000:
1866                 mode |= TWL4030_APLL_RATE_8000;
1867                 break;
1868         case 11025:
1869                 mode |= TWL4030_APLL_RATE_11025;
1870                 break;
1871         case 12000:
1872                 mode |= TWL4030_APLL_RATE_12000;
1873                 break;
1874         case 16000:
1875                 mode |= TWL4030_APLL_RATE_16000;
1876                 break;
1877         case 22050:
1878                 mode |= TWL4030_APLL_RATE_22050;
1879                 break;
1880         case 24000:
1881                 mode |= TWL4030_APLL_RATE_24000;
1882                 break;
1883         case 32000:
1884                 mode |= TWL4030_APLL_RATE_32000;
1885                 break;
1886         case 44100:
1887                 mode |= TWL4030_APLL_RATE_44100;
1888                 break;
1889         case 48000:
1890                 mode |= TWL4030_APLL_RATE_48000;
1891                 break;
1892         case 96000:
1893                 mode |= TWL4030_APLL_RATE_96000;
1894                 break;
1895         default:
1896                 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
1897                         params_rate(params));
1898                 return -EINVAL;
1899         }
1900 
1901         /* sample size */
1902         old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1903         format = old_format;
1904         format &= ~TWL4030_DATA_WIDTH;
1905         switch (params_format(params)) {
1906         case SNDRV_PCM_FORMAT_S16_LE:
1907                 format |= TWL4030_DATA_WIDTH_16S_16W;
1908                 break;
1909         case SNDRV_PCM_FORMAT_S32_LE:
1910                 format |= TWL4030_DATA_WIDTH_32S_24W;
1911                 break;
1912         default:
1913                 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
1914                         params_format(params));
1915                 return -EINVAL;
1916         }
1917 
1918         if (format != old_format || mode != old_mode) {
1919                 if (twl4030->codec_powered) {
1920                         /*
1921                          * If the codec is powered, than we need to toggle the
1922                          * codec power.
1923                          */
1924                         twl4030_codec_enable(codec, 0);
1925                         twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1926                         twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1927                         twl4030_codec_enable(codec, 1);
1928                 } else {
1929                         twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1930                         twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1931                 }
1932         }
1933 
1934         /* Store the important parameters for the DAI configuration and set
1935          * the DAI as configured */
1936         twl4030->configured = 1;
1937         twl4030->rate = params_rate(params);
1938         twl4030->sample_bits = hw_param_interval(params,
1939                                         SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1940         twl4030->channels = params_channels(params);
1941 
1942         /* If both playback and capture streams are open, and one of them
1943          * is setting the hw parameters right now (since we are here), set
1944          * constraints to the other stream to match the current one. */
1945         if (twl4030->slave_substream)
1946                 twl4030_constraints(twl4030, substream);
1947 
1948         return 0;
1949 }
1950 
1951 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1952                 int clk_id, unsigned int freq, int dir)
1953 {
1954         struct snd_soc_codec *codec = codec_dai->codec;
1955         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1956 
1957         switch (freq) {
1958         case 19200000:
1959         case 26000000:
1960         case 38400000:
1961                 break;
1962         default:
1963                 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
1964                 return -EINVAL;
1965         }
1966 
1967         if ((freq / 1000) != twl4030->sysclk) {
1968                 dev_err(codec->dev,
1969                         "Mismatch in HFCLKIN: %u (configured: %u)\n",
1970                         freq, twl4030->sysclk * 1000);
1971                 return -EINVAL;
1972         }
1973 
1974         return 0;
1975 }
1976 
1977 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1978                              unsigned int fmt)
1979 {
1980         struct snd_soc_codec *codec = codec_dai->codec;
1981         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1982         u8 old_format, format;
1983 
1984         /* get format */
1985         old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1986         format = old_format;
1987 
1988         /* set master/slave audio interface */
1989         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1990         case SND_SOC_DAIFMT_CBM_CFM:
1991                 format &= ~(TWL4030_AIF_SLAVE_EN);
1992                 format &= ~(TWL4030_CLK256FS_EN);
1993                 break;
1994         case SND_SOC_DAIFMT_CBS_CFS:
1995                 format |= TWL4030_AIF_SLAVE_EN;
1996                 format |= TWL4030_CLK256FS_EN;
1997                 break;
1998         default:
1999                 return -EINVAL;
2000         }
2001 
2002         /* interface format */
2003         format &= ~TWL4030_AIF_FORMAT;
2004         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2005         case SND_SOC_DAIFMT_I2S:
2006                 format |= TWL4030_AIF_FORMAT_CODEC;
2007                 break;
2008         case SND_SOC_DAIFMT_DSP_A:
2009                 format |= TWL4030_AIF_FORMAT_TDM;
2010                 break;
2011         default:
2012                 return -EINVAL;
2013         }
2014 
2015         if (format != old_format) {
2016                 if (twl4030->codec_powered) {
2017                         /*
2018                          * If the codec is powered, than we need to toggle the
2019                          * codec power.
2020                          */
2021                         twl4030_codec_enable(codec, 0);
2022                         twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2023                         twl4030_codec_enable(codec, 1);
2024                 } else {
2025                         twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2026                 }
2027         }
2028 
2029         return 0;
2030 }
2031 
2032 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
2033 {
2034         struct snd_soc_codec *codec = dai->codec;
2035         u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
2036 
2037         if (tristate)
2038                 reg |= TWL4030_AIF_TRI_EN;
2039         else
2040                 reg &= ~TWL4030_AIF_TRI_EN;
2041 
2042         return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2043 }
2044 
2045 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2046  * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2047 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2048                                 int enable)
2049 {
2050         u8 reg, mask;
2051 
2052         reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2053 
2054         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2055                 mask = TWL4030_ARXL1_VRX_EN;
2056         else
2057                 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2058 
2059         if (enable)
2060                 reg |= mask;
2061         else
2062                 reg &= ~mask;
2063 
2064         twl4030_write(codec, TWL4030_REG_OPTION, reg);
2065 }
2066 
2067 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2068                 struct snd_soc_dai *dai)
2069 {
2070         struct snd_soc_codec *codec = dai->codec;
2071         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2072         u8 mode;
2073 
2074         /* If the system master clock is not 26MHz, the voice PCM interface is
2075          * not available.
2076          */
2077         if (twl4030->sysclk != 26000) {
2078                 dev_err(codec->dev,
2079                         "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2080                         __func__, twl4030->sysclk);
2081                 return -EINVAL;
2082         }
2083 
2084         /* If the codec mode is not option2, the voice PCM interface is not
2085          * available.
2086          */
2087         mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2088                 & TWL4030_OPT_MODE;
2089 
2090         if (mode != TWL4030_OPTION_2) {
2091                 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2092                         __func__);
2093                 return -EINVAL;
2094         }
2095 
2096         return 0;
2097 }
2098 
2099 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2100                                 struct snd_soc_dai *dai)
2101 {
2102         struct snd_soc_codec *codec = dai->codec;
2103 
2104         /* Enable voice digital filters */
2105         twl4030_voice_enable(codec, substream->stream, 0);
2106 }
2107 
2108 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2109                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2110 {
2111         struct snd_soc_codec *codec = dai->codec;
2112         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2113         u8 old_mode, mode;
2114 
2115         /* Enable voice digital filters */
2116         twl4030_voice_enable(codec, substream->stream, 1);
2117 
2118         /* bit rate */
2119         old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2120                 & ~(TWL4030_CODECPDZ);
2121         mode = old_mode;
2122 
2123         switch (params_rate(params)) {
2124         case 8000:
2125                 mode &= ~(TWL4030_SEL_16K);
2126                 break;
2127         case 16000:
2128                 mode |= TWL4030_SEL_16K;
2129                 break;
2130         default:
2131                 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
2132                         params_rate(params));
2133                 return -EINVAL;
2134         }
2135 
2136         if (mode != old_mode) {
2137                 if (twl4030->codec_powered) {
2138                         /*
2139                          * If the codec is powered, than we need to toggle the
2140                          * codec power.
2141                          */
2142                         twl4030_codec_enable(codec, 0);
2143                         twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2144                         twl4030_codec_enable(codec, 1);
2145                 } else {
2146                         twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2147                 }
2148         }
2149 
2150         return 0;
2151 }
2152 
2153 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2154                 int clk_id, unsigned int freq, int dir)
2155 {
2156         struct snd_soc_codec *codec = codec_dai->codec;
2157         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2158 
2159         if (freq != 26000000) {
2160                 dev_err(codec->dev,
2161                         "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2162                         __func__, freq / 1000);
2163                 return -EINVAL;
2164         }
2165         if ((freq / 1000) != twl4030->sysclk) {
2166                 dev_err(codec->dev,
2167                         "Mismatch in HFCLKIN: %u (configured: %u)\n",
2168                         freq, twl4030->sysclk * 1000);
2169                 return -EINVAL;
2170         }
2171         return 0;
2172 }
2173 
2174 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2175                 unsigned int fmt)
2176 {
2177         struct snd_soc_codec *codec = codec_dai->codec;
2178         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2179         u8 old_format, format;
2180 
2181         /* get format */
2182         old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2183         format = old_format;
2184 
2185         /* set master/slave audio interface */
2186         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2187         case SND_SOC_DAIFMT_CBM_CFM:
2188                 format &= ~(TWL4030_VIF_SLAVE_EN);
2189                 break;
2190         case SND_SOC_DAIFMT_CBS_CFS:
2191                 format |= TWL4030_VIF_SLAVE_EN;
2192                 break;
2193         default:
2194                 return -EINVAL;
2195         }
2196 
2197         /* clock inversion */
2198         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2199         case SND_SOC_DAIFMT_IB_NF:
2200                 format &= ~(TWL4030_VIF_FORMAT);
2201                 break;
2202         case SND_SOC_DAIFMT_NB_IF:
2203                 format |= TWL4030_VIF_FORMAT;
2204                 break;
2205         default:
2206                 return -EINVAL;
2207         }
2208 
2209         if (format != old_format) {
2210                 if (twl4030->codec_powered) {
2211                         /*
2212                          * If the codec is powered, than we need to toggle the
2213                          * codec power.
2214                          */
2215                         twl4030_codec_enable(codec, 0);
2216                         twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2217                         twl4030_codec_enable(codec, 1);
2218                 } else {
2219                         twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2220                 }
2221         }
2222 
2223         return 0;
2224 }
2225 
2226 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2227 {
2228         struct snd_soc_codec *codec = dai->codec;
2229         u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2230 
2231         if (tristate)
2232                 reg |= TWL4030_VIF_TRI_EN;
2233         else
2234                 reg &= ~TWL4030_VIF_TRI_EN;
2235 
2236         return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2237 }
2238 
2239 #define TWL4030_RATES    (SNDRV_PCM_RATE_8000_48000)
2240 #define TWL4030_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2241 
2242 static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2243         .startup        = twl4030_startup,
2244         .shutdown       = twl4030_shutdown,
2245         .hw_params      = twl4030_hw_params,
2246         .set_sysclk     = twl4030_set_dai_sysclk,
2247         .set_fmt        = twl4030_set_dai_fmt,
2248         .set_tristate   = twl4030_set_tristate,
2249 };
2250 
2251 static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2252         .startup        = twl4030_voice_startup,
2253         .shutdown       = twl4030_voice_shutdown,
2254         .hw_params      = twl4030_voice_hw_params,
2255         .set_sysclk     = twl4030_voice_set_dai_sysclk,
2256         .set_fmt        = twl4030_voice_set_dai_fmt,
2257         .set_tristate   = twl4030_voice_set_tristate,
2258 };
2259 
2260 static struct snd_soc_dai_driver twl4030_dai[] = {
2261 {
2262         .name = "twl4030-hifi",
2263         .playback = {
2264                 .stream_name = "HiFi Playback",
2265                 .channels_min = 2,
2266                 .channels_max = 4,
2267                 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2268                 .formats = TWL4030_FORMATS,
2269                 .sig_bits = 24,},
2270         .capture = {
2271                 .stream_name = "HiFi Capture",
2272                 .channels_min = 2,
2273                 .channels_max = 4,
2274                 .rates = TWL4030_RATES,
2275                 .formats = TWL4030_FORMATS,
2276                 .sig_bits = 24,},
2277         .ops = &twl4030_dai_hifi_ops,
2278 },
2279 {
2280         .name = "twl4030-voice",
2281         .playback = {
2282                 .stream_name = "Voice Playback",
2283                 .channels_min = 1,
2284                 .channels_max = 1,
2285                 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2286                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2287         .capture = {
2288                 .stream_name = "Voice Capture",
2289                 .channels_min = 1,
2290                 .channels_max = 2,
2291                 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2292                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2293         .ops = &twl4030_dai_voice_ops,
2294 },
2295 };
2296 
2297 static int twl4030_soc_probe(struct snd_soc_codec *codec)
2298 {
2299         struct twl4030_priv *twl4030;
2300 
2301         twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2302                                GFP_KERNEL);
2303         if (twl4030 == NULL) {
2304                 dev_err(codec->dev, "Can not allocate memory\n");
2305                 return -ENOMEM;
2306         }
2307         snd_soc_codec_set_drvdata(codec, twl4030);
2308         /* Set the defaults, and power up the codec */
2309         twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
2310 
2311         twl4030_init_chip(codec);
2312 
2313         return 0;
2314 }
2315 
2316 static int twl4030_soc_remove(struct snd_soc_codec *codec)
2317 {
2318         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2319         struct twl4030_codec_data *pdata = twl4030->pdata;
2320 
2321         /* Reset registers to their chip default before leaving */
2322         twl4030_reset_registers(codec);
2323         twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2324 
2325         if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2326                 gpio_free(pdata->hs_extmute_gpio);
2327 
2328         return 0;
2329 }
2330 
2331 static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2332         .probe = twl4030_soc_probe,
2333         .remove = twl4030_soc_remove,
2334         .read = twl4030_read_reg_cache,
2335         .write = twl4030_write,
2336         .set_bias_level = twl4030_set_bias_level,
2337         .idle_bias_off = true,
2338         .reg_cache_size = sizeof(twl4030_reg),
2339         .reg_word_size = sizeof(u8),
2340         .reg_cache_default = twl4030_reg,
2341 
2342         .controls = twl4030_snd_controls,
2343         .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2344         .dapm_widgets = twl4030_dapm_widgets,
2345         .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2346         .dapm_routes = intercon,
2347         .num_dapm_routes = ARRAY_SIZE(intercon),
2348 };
2349 
2350 static int twl4030_codec_probe(struct platform_device *pdev)
2351 {
2352         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2353                         twl4030_dai, ARRAY_SIZE(twl4030_dai));
2354 }
2355 
2356 static int twl4030_codec_remove(struct platform_device *pdev)
2357 {
2358         snd_soc_unregister_codec(&pdev->dev);
2359         return 0;
2360 }
2361 
2362 MODULE_ALIAS("platform:twl4030-codec");
2363 
2364 static struct platform_driver twl4030_codec_driver = {
2365         .probe          = twl4030_codec_probe,
2366         .remove         = twl4030_codec_remove,
2367         .driver         = {
2368                 .name   = "twl4030-codec",
2369                 .owner  = THIS_MODULE,
2370         },
2371 };
2372 
2373 module_platform_driver(twl4030_codec_driver);
2374 
2375 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2376 MODULE_AUTHOR("Steve Sakoman");
2377 MODULE_LICENSE("GPL");
2378 

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