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Linux/sound/soc/codecs/uda1380.c

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  1 /*
  2  * uda1380.c - Philips UDA1380 ALSA SoC audio driver
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  *
  8  * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
  9  *
 10  * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
 11  * codec model.
 12  *
 13  * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
 14  * Copyright 2005 Openedhand Ltd.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/init.h>
 19 #include <linux/types.h>
 20 #include <linux/slab.h>
 21 #include <linux/errno.h>
 22 #include <linux/gpio.h>
 23 #include <linux/delay.h>
 24 #include <linux/i2c.h>
 25 #include <linux/workqueue.h>
 26 #include <sound/core.h>
 27 #include <sound/control.h>
 28 #include <sound/initval.h>
 29 #include <sound/soc.h>
 30 #include <sound/tlv.h>
 31 #include <sound/uda1380.h>
 32 
 33 #include "uda1380.h"
 34 
 35 /* codec private data */
 36 struct uda1380_priv {
 37         struct snd_soc_codec *codec;
 38         unsigned int dac_clk;
 39         struct work_struct work;
 40         void *control_data;
 41 };
 42 
 43 /*
 44  * uda1380 register cache
 45  */
 46 static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
 47         0x0502, 0x0000, 0x0000, 0x3f3f,
 48         0x0202, 0x0000, 0x0000, 0x0000,
 49         0x0000, 0x0000, 0x0000, 0x0000,
 50         0x0000, 0x0000, 0x0000, 0x0000,
 51         0x0000, 0xff00, 0x0000, 0x4800,
 52         0x0000, 0x0000, 0x0000, 0x0000,
 53         0x0000, 0x0000, 0x0000, 0x0000,
 54         0x0000, 0x0000, 0x0000, 0x0000,
 55         0x0000, 0x8000, 0x0002, 0x0000,
 56 };
 57 
 58 static unsigned long uda1380_cache_dirty;
 59 
 60 /*
 61  * read uda1380 register cache
 62  */
 63 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
 64         unsigned int reg)
 65 {
 66         u16 *cache = codec->reg_cache;
 67         if (reg == UDA1380_RESET)
 68                 return 0;
 69         if (reg >= UDA1380_CACHEREGNUM)
 70                 return -1;
 71         return cache[reg];
 72 }
 73 
 74 /*
 75  * write uda1380 register cache
 76  */
 77 static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
 78         u16 reg, unsigned int value)
 79 {
 80         u16 *cache = codec->reg_cache;
 81 
 82         if (reg >= UDA1380_CACHEREGNUM)
 83                 return;
 84         if ((reg >= 0x10) && (cache[reg] != value))
 85                 set_bit(reg - 0x10, &uda1380_cache_dirty);
 86         cache[reg] = value;
 87 }
 88 
 89 /*
 90  * write to the UDA1380 register space
 91  */
 92 static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
 93         unsigned int value)
 94 {
 95         u8 data[3];
 96 
 97         /* data is
 98          *   data[0] is register offset
 99          *   data[1] is MS byte
100          *   data[2] is LS byte
101          */
102         data[0] = reg;
103         data[1] = (value & 0xff00) >> 8;
104         data[2] = value & 0x00ff;
105 
106         uda1380_write_reg_cache(codec, reg, value);
107 
108         /* the interpolator & decimator regs must only be written when the
109          * codec DAI is active.
110          */
111         if (!snd_soc_codec_is_active(codec) && (reg >= UDA1380_MVOL))
112                 return 0;
113         pr_debug("uda1380: hw write %x val %x\n", reg, value);
114         if (codec->hw_write(codec->control_data, data, 3) == 3) {
115                 unsigned int val;
116                 i2c_master_send(codec->control_data, data, 1);
117                 i2c_master_recv(codec->control_data, data, 2);
118                 val = (data[0]<<8) | data[1];
119                 if (val != value) {
120                         pr_debug("uda1380: READ BACK VAL %x\n",
121                                         (data[0]<<8) | data[1]);
122                         return -EIO;
123                 }
124                 if (reg >= 0x10)
125                         clear_bit(reg - 0x10, &uda1380_cache_dirty);
126                 return 0;
127         } else
128                 return -EIO;
129 }
130 
131 static void uda1380_sync_cache(struct snd_soc_codec *codec)
132 {
133         int reg;
134         u8 data[3];
135         u16 *cache = codec->reg_cache;
136 
137         /* Sync reg_cache with the hardware */
138         for (reg = 0; reg < UDA1380_MVOL; reg++) {
139                 data[0] = reg;
140                 data[1] = (cache[reg] & 0xff00) >> 8;
141                 data[2] = cache[reg] & 0x00ff;
142                 if (codec->hw_write(codec->control_data, data, 3) != 3)
143                         dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
144                                 __func__, reg);
145         }
146 }
147 
148 static int uda1380_reset(struct snd_soc_codec *codec)
149 {
150         struct uda1380_platform_data *pdata = codec->dev->platform_data;
151 
152         if (gpio_is_valid(pdata->gpio_reset)) {
153                 gpio_set_value(pdata->gpio_reset, 1);
154                 mdelay(1);
155                 gpio_set_value(pdata->gpio_reset, 0);
156         } else {
157                 u8 data[3];
158 
159                 data[0] = UDA1380_RESET;
160                 data[1] = 0;
161                 data[2] = 0;
162 
163                 if (codec->hw_write(codec->control_data, data, 3) != 3) {
164                         dev_err(codec->dev, "%s: failed\n", __func__);
165                         return -EIO;
166                 }
167         }
168 
169         return 0;
170 }
171 
172 static void uda1380_flush_work(struct work_struct *work)
173 {
174         struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
175         struct snd_soc_codec *uda1380_codec = uda1380->codec;
176         int bit, reg;
177 
178         for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
179                 reg = 0x10 + bit;
180                 pr_debug("uda1380: flush reg %x val %x:\n", reg,
181                                 uda1380_read_reg_cache(uda1380_codec, reg));
182                 uda1380_write(uda1380_codec, reg,
183                                 uda1380_read_reg_cache(uda1380_codec, reg));
184                 clear_bit(bit, &uda1380_cache_dirty);
185         }
186 
187 }
188 
189 /* declarations of ALSA reg_elem_REAL controls */
190 static const char *uda1380_deemp[] = {
191         "None",
192         "32kHz",
193         "44.1kHz",
194         "48kHz",
195         "96kHz",
196 };
197 static const char *uda1380_input_sel[] = {
198         "Line",
199         "Mic + Line R",
200         "Line L",
201         "Mic",
202 };
203 static const char *uda1380_output_sel[] = {
204         "DAC",
205         "Analog Mixer",
206 };
207 static const char *uda1380_spf_mode[] = {
208         "Flat",
209         "Minimum1",
210         "Minimum2",
211         "Maximum"
212 };
213 static const char *uda1380_capture_sel[] = {
214         "ADC",
215         "Digital Mixer"
216 };
217 static const char *uda1380_sel_ns[] = {
218         "3rd-order",
219         "5th-order"
220 };
221 static const char *uda1380_mix_control[] = {
222         "off",
223         "PCM only",
224         "before sound processing",
225         "after sound processing"
226 };
227 static const char *uda1380_sdet_setting[] = {
228         "3200",
229         "4800",
230         "9600",
231         "19200"
232 };
233 static const char *uda1380_os_setting[] = {
234         "single-speed",
235         "double-speed (no mixing)",
236         "quad-speed (no mixing)"
237 };
238 
239 static const struct soc_enum uda1380_deemp_enum[] = {
240         SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp),
241                         uda1380_deemp),
242         SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp),
243                         uda1380_deemp),
244 };
245 static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum,
246                             UDA1380_ADC, 2, uda1380_input_sel);         /* SEL_MIC, SEL_LNA */
247 static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum,
248                             UDA1380_PM, 7, uda1380_output_sel);         /* R02_EN_AVC */
249 static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum,
250                             UDA1380_MODE, 14, uda1380_spf_mode);                /* M */
251 static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum,
252                             UDA1380_IFACE, 6, uda1380_capture_sel);     /* SEL_SOURCE */
253 static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum,
254                             UDA1380_MIXER, 14, uda1380_sel_ns);         /* SEL_NS */
255 static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum,
256                             UDA1380_MIXER, 12, uda1380_mix_control);    /* MIX, MIX_POS */
257 static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum,
258                             UDA1380_MIXER, 4, uda1380_sdet_setting);    /* SD_VALUE */
259 static SOC_ENUM_SINGLE_DECL(uda1380_os_enum,
260                             UDA1380_MIXER, 0, uda1380_os_setting);      /* OS */
261 
262 /*
263  * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
264  */
265 static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
266 
267 /*
268  * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
269  * from -66 dB in 0.5 dB steps (2 dB steps, really) and
270  * from -52 dB in 0.25 dB steps
271  */
272 static const unsigned int mvol_tlv[] = {
273         TLV_DB_RANGE_HEAD(3),
274         0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
275         16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
276         44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
277 };
278 
279 /*
280  * from -72 dB in 1.5 dB steps (6 dB steps really),
281  * from -66 dB in 0.75 dB steps (3 dB steps really),
282  * from -60 dB in 0.5 dB steps (2 dB steps really) and
283  * from -46 dB in 0.25 dB steps
284  */
285 static const unsigned int vc_tlv[] = {
286         TLV_DB_RANGE_HEAD(4),
287         0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
288         8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
289         16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
290         44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
291 };
292 
293 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
294 static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
295 
296 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
297  * off at 18 dB max) */
298 static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
299 
300 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
301 static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
302 
303 /* from 0 to 24 dB in 3 dB steps */
304 static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
305 
306 /* from 0 to 30 dB in 2 dB steps */
307 static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
308 
309 static const struct snd_kcontrol_new uda1380_snd_controls[] = {
310         SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv),     /* AVCR, AVCL */
311         SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
312         SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv),       /* VC2 */
313         SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv),       /* VC1 */
314         SOC_ENUM("Sound Processing Filter", uda1380_spf_enum),                          /* M */
315         SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv),     /* TRL, TRR */
316         SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv),       /* BBL, BBR */
317 /**/    SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1),          /* MTM */
318         SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1),             /* MT2 from decimation filter */
319         SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]),            /* DE2 */
320         SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1),              /* MT1, from digital data input */
321         SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]),            /* DE1 */
322         SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0),   /* DA_POL_INV */
323         SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum),                          /* SEL_NS */
324         SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum),             /* MIX_POS, MIX */
325         SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0),          /* SDET_ON */
326         SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum),                /* SD_VALUE */
327         SOC_ENUM("Oversampling Input", uda1380_os_enum),                        /* OS */
328         SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv),        /* ML_DEC, MR_DEC */
329 /**/    SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1),                /* MT_ADC */
330         SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
331         SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0),     /* ADCPOL_INV */
332         SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv),   /* VGA_CTRL */
333         SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0),            /* SKIP_DCFIL (before decimator) */
334         SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0),            /* EN_DCFIL (at output of decimator) */
335         SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0),                 /* TODO: enum, see table 62 */
336         SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1),                   /* AGC_LEVEL */
337         /* -5.5, -8, -11.5, -14 dBFS */
338         SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
339 };
340 
341 /* Input mux */
342 static const struct snd_kcontrol_new uda1380_input_mux_control =
343         SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
344 
345 /* Output mux */
346 static const struct snd_kcontrol_new uda1380_output_mux_control =
347         SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
348 
349 /* Capture mux */
350 static const struct snd_kcontrol_new uda1380_capture_mux_control =
351         SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
352 
353 
354 static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
355         SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
356                 &uda1380_input_mux_control),
357         SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
358                 &uda1380_output_mux_control),
359         SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
360                 &uda1380_capture_mux_control),
361         SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
362         SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
363         SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
364         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
365         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
366         SND_SOC_DAPM_INPUT("VINM"),
367         SND_SOC_DAPM_INPUT("VINL"),
368         SND_SOC_DAPM_INPUT("VINR"),
369         SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
370         SND_SOC_DAPM_OUTPUT("VOUTLHP"),
371         SND_SOC_DAPM_OUTPUT("VOUTRHP"),
372         SND_SOC_DAPM_OUTPUT("VOUTL"),
373         SND_SOC_DAPM_OUTPUT("VOUTR"),
374         SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
375         SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
376 };
377 
378 static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {
379 
380         /* output mux */
381         {"HeadPhone Driver", NULL, "Output Mux"},
382         {"VOUTR", NULL, "Output Mux"},
383         {"VOUTL", NULL, "Output Mux"},
384 
385         {"Analog Mixer", NULL, "VINR"},
386         {"Analog Mixer", NULL, "VINL"},
387         {"Analog Mixer", NULL, "DAC"},
388 
389         {"Output Mux", "DAC", "DAC"},
390         {"Output Mux", "Analog Mixer", "Analog Mixer"},
391 
392         /* {"DAC", "Digital Mixer", "I2S" } */
393 
394         /* headphone driver */
395         {"VOUTLHP", NULL, "HeadPhone Driver"},
396         {"VOUTRHP", NULL, "HeadPhone Driver"},
397 
398         /* input mux */
399         {"Left ADC", NULL, "Input Mux"},
400         {"Input Mux", "Mic", "Mic LNA"},
401         {"Input Mux", "Mic + Line R", "Mic LNA"},
402         {"Input Mux", "Line L", "Left PGA"},
403         {"Input Mux", "Line", "Left PGA"},
404 
405         /* right input */
406         {"Right ADC", "Mic + Line R", "Right PGA"},
407         {"Right ADC", "Line", "Right PGA"},
408 
409         /* inputs */
410         {"Mic LNA", NULL, "VINM"},
411         {"Left PGA", NULL, "VINL"},
412         {"Right PGA", NULL, "VINR"},
413 };
414 
415 static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
416                 unsigned int fmt)
417 {
418         struct snd_soc_codec *codec = codec_dai->codec;
419         int iface;
420 
421         /* set up DAI based upon fmt */
422         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
423         iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
424 
425         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
426         case SND_SOC_DAIFMT_I2S:
427                 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
428                 break;
429         case SND_SOC_DAIFMT_LSB:
430                 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
431                 break;
432         case SND_SOC_DAIFMT_MSB:
433                 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
434         }
435 
436         /* DATAI is slave only, so in single-link mode, this has to be slave */
437         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
438                 return -EINVAL;
439 
440         uda1380_write(codec, UDA1380_IFACE, iface);
441 
442         return 0;
443 }
444 
445 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
446                 unsigned int fmt)
447 {
448         struct snd_soc_codec *codec = codec_dai->codec;
449         int iface;
450 
451         /* set up DAI based upon fmt */
452         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
453         iface &= ~R01_SFORI_MASK;
454 
455         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
456         case SND_SOC_DAIFMT_I2S:
457                 iface |= R01_SFORI_I2S;
458                 break;
459         case SND_SOC_DAIFMT_LSB:
460                 iface |= R01_SFORI_LSB16;
461                 break;
462         case SND_SOC_DAIFMT_MSB:
463                 iface |= R01_SFORI_MSB;
464         }
465 
466         /* DATAI is slave only, so this has to be slave */
467         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
468                 return -EINVAL;
469 
470         uda1380_write(codec, UDA1380_IFACE, iface);
471 
472         return 0;
473 }
474 
475 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
476                 unsigned int fmt)
477 {
478         struct snd_soc_codec *codec = codec_dai->codec;
479         int iface;
480 
481         /* set up DAI based upon fmt */
482         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
483         iface &= ~(R01_SIM | R01_SFORO_MASK);
484 
485         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
486         case SND_SOC_DAIFMT_I2S:
487                 iface |= R01_SFORO_I2S;
488                 break;
489         case SND_SOC_DAIFMT_LSB:
490                 iface |= R01_SFORO_LSB16;
491                 break;
492         case SND_SOC_DAIFMT_MSB:
493                 iface |= R01_SFORO_MSB;
494         }
495 
496         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
497                 iface |= R01_SIM;
498 
499         uda1380_write(codec, UDA1380_IFACE, iface);
500 
501         return 0;
502 }
503 
504 static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
505                 struct snd_soc_dai *dai)
506 {
507         struct snd_soc_codec *codec = dai->codec;
508         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
509         int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
510 
511         switch (cmd) {
512         case SNDRV_PCM_TRIGGER_START:
513         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
514                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
515                                         mixer & ~R14_SILENCE);
516                 schedule_work(&uda1380->work);
517                 break;
518         case SNDRV_PCM_TRIGGER_STOP:
519         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
520                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
521                                         mixer | R14_SILENCE);
522                 schedule_work(&uda1380->work);
523                 break;
524         }
525         return 0;
526 }
527 
528 static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
529                                  struct snd_pcm_hw_params *params,
530                                  struct snd_soc_dai *dai)
531 {
532         struct snd_soc_codec *codec = dai->codec;
533         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
534 
535         /* set WSPLL power and divider if running from this clock */
536         if (clk & R00_DAC_CLK) {
537                 int rate = params_rate(params);
538                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
539                 clk &= ~0x3; /* clear SEL_LOOP_DIV */
540                 switch (rate) {
541                 case 6250 ... 12500:
542                         clk |= 0x0;
543                         break;
544                 case 12501 ... 25000:
545                         clk |= 0x1;
546                         break;
547                 case 25001 ... 50000:
548                         clk |= 0x2;
549                         break;
550                 case 50001 ... 100000:
551                         clk |= 0x3;
552                         break;
553                 }
554                 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
555         }
556 
557         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
558                 clk |= R00_EN_DAC | R00_EN_INT;
559         else
560                 clk |= R00_EN_ADC | R00_EN_DEC;
561 
562         uda1380_write(codec, UDA1380_CLK, clk);
563         return 0;
564 }
565 
566 static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
567                                  struct snd_soc_dai *dai)
568 {
569         struct snd_soc_codec *codec = dai->codec;
570         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
571 
572         /* shut down WSPLL power if running from this clock */
573         if (clk & R00_DAC_CLK) {
574                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
575                 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
576         }
577 
578         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
579                 clk &= ~(R00_EN_DAC | R00_EN_INT);
580         else
581                 clk &= ~(R00_EN_ADC | R00_EN_DEC);
582 
583         uda1380_write(codec, UDA1380_CLK, clk);
584 }
585 
586 static int uda1380_set_bias_level(struct snd_soc_codec *codec,
587         enum snd_soc_bias_level level)
588 {
589         int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
590         int reg;
591         struct uda1380_platform_data *pdata = codec->dev->platform_data;
592 
593         if (codec->dapm.bias_level == level)
594                 return 0;
595 
596         switch (level) {
597         case SND_SOC_BIAS_ON:
598         case SND_SOC_BIAS_PREPARE:
599                 /* ADC, DAC on */
600                 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
601                 break;
602         case SND_SOC_BIAS_STANDBY:
603                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
604                         if (gpio_is_valid(pdata->gpio_power)) {
605                                 gpio_set_value(pdata->gpio_power, 1);
606                                 mdelay(1);
607                                 uda1380_reset(codec);
608                         }
609 
610                         uda1380_sync_cache(codec);
611                 }
612                 uda1380_write(codec, UDA1380_PM, 0x0);
613                 break;
614         case SND_SOC_BIAS_OFF:
615                 if (!gpio_is_valid(pdata->gpio_power))
616                         break;
617 
618                 gpio_set_value(pdata->gpio_power, 0);
619 
620                 /* Mark mixer regs cache dirty to sync them with
621                  * codec regs on power on.
622                  */
623                 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
624                         set_bit(reg - 0x10, &uda1380_cache_dirty);
625         }
626         codec->dapm.bias_level = level;
627         return 0;
628 }
629 
630 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
631                        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
632                        SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
633 
634 static const struct snd_soc_dai_ops uda1380_dai_ops = {
635         .hw_params      = uda1380_pcm_hw_params,
636         .shutdown       = uda1380_pcm_shutdown,
637         .trigger        = uda1380_trigger,
638         .set_fmt        = uda1380_set_dai_fmt_both,
639 };
640 
641 static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {
642         .hw_params      = uda1380_pcm_hw_params,
643         .shutdown       = uda1380_pcm_shutdown,
644         .trigger        = uda1380_trigger,
645         .set_fmt        = uda1380_set_dai_fmt_playback,
646 };
647 
648 static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {
649         .hw_params      = uda1380_pcm_hw_params,
650         .shutdown       = uda1380_pcm_shutdown,
651         .trigger        = uda1380_trigger,
652         .set_fmt        = uda1380_set_dai_fmt_capture,
653 };
654 
655 static struct snd_soc_dai_driver uda1380_dai[] = {
656 {
657         .name = "uda1380-hifi",
658         .playback = {
659                 .stream_name = "Playback",
660                 .channels_min = 1,
661                 .channels_max = 2,
662                 .rates = UDA1380_RATES,
663                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
664         .capture = {
665                 .stream_name = "Capture",
666                 .channels_min = 1,
667                 .channels_max = 2,
668                 .rates = UDA1380_RATES,
669                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
670         .ops = &uda1380_dai_ops,
671 },
672 { /* playback only - dual interface */
673         .name = "uda1380-hifi-playback",
674         .playback = {
675                 .stream_name = "Playback",
676                 .channels_min = 1,
677                 .channels_max = 2,
678                 .rates = UDA1380_RATES,
679                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
680         },
681         .ops = &uda1380_dai_ops_playback,
682 },
683 { /* capture only - dual interface*/
684         .name = "uda1380-hifi-capture",
685         .capture = {
686                 .stream_name = "Capture",
687                 .channels_min = 1,
688                 .channels_max = 2,
689                 .rates = UDA1380_RATES,
690                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
691         },
692         .ops = &uda1380_dai_ops_capture,
693 },
694 };
695 
696 static int uda1380_suspend(struct snd_soc_codec *codec)
697 {
698         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
699         return 0;
700 }
701 
702 static int uda1380_resume(struct snd_soc_codec *codec)
703 {
704         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
705         return 0;
706 }
707 
708 static int uda1380_probe(struct snd_soc_codec *codec)
709 {
710         struct uda1380_platform_data *pdata =codec->dev->platform_data;
711         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
712         int ret;
713 
714         uda1380->codec = codec;
715 
716         codec->hw_write = (hw_write_t)i2c_master_send;
717         codec->control_data = uda1380->control_data;
718 
719         if (!pdata)
720                 return -EINVAL;
721 
722         if (gpio_is_valid(pdata->gpio_reset)) {
723                 ret = gpio_request_one(pdata->gpio_reset, GPIOF_OUT_INIT_LOW,
724                                        "uda1380 reset");
725                 if (ret)
726                         goto err_out;
727         }
728 
729         if (gpio_is_valid(pdata->gpio_power)) {
730                 ret = gpio_request_one(pdata->gpio_power, GPIOF_OUT_INIT_LOW,
731                                    "uda1380 power");
732                 if (ret)
733                         goto err_free_gpio;
734         } else {
735                 ret = uda1380_reset(codec);
736                 if (ret)
737                         goto err_free_gpio;
738         }
739 
740         INIT_WORK(&uda1380->work, uda1380_flush_work);
741 
742         /* power on device */
743         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
744         /* set clock input */
745         switch (pdata->dac_clk) {
746         case UDA1380_DAC_CLK_SYSCLK:
747                 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
748                 break;
749         case UDA1380_DAC_CLK_WSPLL:
750                 uda1380_write_reg_cache(codec, UDA1380_CLK,
751                         R00_DAC_CLK);
752                 break;
753         }
754 
755         return 0;
756 
757 err_free_gpio:
758         if (gpio_is_valid(pdata->gpio_reset))
759                 gpio_free(pdata->gpio_reset);
760 err_out:
761         return ret;
762 }
763 
764 /* power down chip */
765 static int uda1380_remove(struct snd_soc_codec *codec)
766 {
767         struct uda1380_platform_data *pdata =codec->dev->platform_data;
768 
769         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
770 
771         gpio_free(pdata->gpio_reset);
772         gpio_free(pdata->gpio_power);
773 
774         return 0;
775 }
776 
777 static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
778         .probe =        uda1380_probe,
779         .remove =       uda1380_remove,
780         .suspend =      uda1380_suspend,
781         .resume =       uda1380_resume,
782         .read =         uda1380_read_reg_cache,
783         .write =        uda1380_write,
784         .set_bias_level = uda1380_set_bias_level,
785         .reg_cache_size = ARRAY_SIZE(uda1380_reg),
786         .reg_word_size = sizeof(u16),
787         .reg_cache_default = uda1380_reg,
788         .reg_cache_step = 1,
789 
790         .controls = uda1380_snd_controls,
791         .num_controls = ARRAY_SIZE(uda1380_snd_controls),
792         .dapm_widgets = uda1380_dapm_widgets,
793         .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
794         .dapm_routes = uda1380_dapm_routes,
795         .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
796 };
797 
798 #if IS_ENABLED(CONFIG_I2C)
799 static int uda1380_i2c_probe(struct i2c_client *i2c,
800                              const struct i2c_device_id *id)
801 {
802         struct uda1380_priv *uda1380;
803         int ret;
804 
805         uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),
806                                GFP_KERNEL);
807         if (uda1380 == NULL)
808                 return -ENOMEM;
809 
810         i2c_set_clientdata(i2c, uda1380);
811         uda1380->control_data = i2c;
812 
813         ret =  snd_soc_register_codec(&i2c->dev,
814                         &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
815         return ret;
816 }
817 
818 static int uda1380_i2c_remove(struct i2c_client *i2c)
819 {
820         snd_soc_unregister_codec(&i2c->dev);
821         return 0;
822 }
823 
824 static const struct i2c_device_id uda1380_i2c_id[] = {
825         { "uda1380", 0 },
826         { }
827 };
828 MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
829 
830 static struct i2c_driver uda1380_i2c_driver = {
831         .driver = {
832                 .name =  "uda1380-codec",
833                 .owner = THIS_MODULE,
834         },
835         .probe =    uda1380_i2c_probe,
836         .remove =   uda1380_i2c_remove,
837         .id_table = uda1380_i2c_id,
838 };
839 #endif
840 
841 static int __init uda1380_modinit(void)
842 {
843         int ret = 0;
844 #if IS_ENABLED(CONFIG_I2C)
845         ret = i2c_add_driver(&uda1380_i2c_driver);
846         if (ret != 0)
847                 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
848 #endif
849         return ret;
850 }
851 module_init(uda1380_modinit);
852 
853 static void __exit uda1380_exit(void)
854 {
855 #if IS_ENABLED(CONFIG_I2C)
856         i2c_del_driver(&uda1380_i2c_driver);
857 #endif
858 }
859 module_exit(uda1380_exit);
860 
861 MODULE_AUTHOR("Giorgio Padrin");
862 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
863 MODULE_LICENSE("GPL");
864 

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