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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wcd938x.c

Version: ~ [ linux-6.0 ] ~ [ linux-5.19.12 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.71 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.146 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.215 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.260 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.295 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.330 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  3 
  4 #include <linux/module.h>
  5 #include <linux/slab.h>
  6 #include <linux/platform_device.h>
  7 #include <linux/device.h>
  8 #include <linux/delay.h>
  9 #include <linux/kernel.h>
 10 #include <linux/pm_runtime.h>
 11 #include <linux/component.h>
 12 #include <sound/tlv.h>
 13 #include <linux/of_gpio.h>
 14 #include <linux/of.h>
 15 #include <sound/jack.h>
 16 #include <sound/pcm.h>
 17 #include <sound/pcm_params.h>
 18 #include <linux/regmap.h>
 19 #include <sound/soc.h>
 20 #include <sound/soc-dapm.h>
 21 #include <linux/regulator/consumer.h>
 22 
 23 #include "wcd-clsh-v2.h"
 24 #include "wcd-mbhc-v2.h"
 25 #include "wcd938x.h"
 26 
 27 #define WCD938X_MAX_MICBIAS             (4)
 28 #define WCD938X_MAX_SUPPLY              (4)
 29 #define WCD938X_MBHC_MAX_BUTTONS        (8)
 30 #define TX_ADC_MAX                      (4)
 31 #define WCD938X_TX_MAX_SWR_PORTS        (5)
 32 
 33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 34                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 35                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
 36 /* Fractional Rates */
 37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
 38                                  SNDRV_PCM_RATE_176400)
 39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
 40                                     SNDRV_PCM_FMTBIT_S24_LE)
 41 /* Convert from vout ctl to micbias voltage in mV */
 42 #define  WCD_VOUT_CTL_TO_MICB(v)        (1000 + v * 50)
 43 #define SWR_CLK_RATE_0P6MHZ             (600000)
 44 #define SWR_CLK_RATE_1P2MHZ             (1200000)
 45 #define SWR_CLK_RATE_2P4MHZ             (2400000)
 46 #define SWR_CLK_RATE_4P8MHZ             (4800000)
 47 #define SWR_CLK_RATE_9P6MHZ             (9600000)
 48 #define SWR_CLK_RATE_11P2896MHZ         (1128960)
 49 
 50 #define WCD938X_DRV_NAME "wcd938x_codec"
 51 #define WCD938X_VERSION_1_0             (1)
 52 #define EAR_RX_PATH_AUX                 (1)
 53 
 54 #define ADC_MODE_VAL_HIFI               0x01
 55 #define ADC_MODE_VAL_LO_HIF             0x02
 56 #define ADC_MODE_VAL_NORMAL             0x03
 57 #define ADC_MODE_VAL_LP                 0x05
 58 #define ADC_MODE_VAL_ULP1               0x09
 59 #define ADC_MODE_VAL_ULP2               0x0B
 60 
 61 /* Z value defined in milliohm */
 62 #define WCD938X_ZDET_VAL_32             (32000)
 63 #define WCD938X_ZDET_VAL_400            (400000)
 64 #define WCD938X_ZDET_VAL_1200           (1200000)
 65 #define WCD938X_ZDET_VAL_100K           (100000000)
 66 /* Z floating defined in ohms */
 67 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
 68 #define WCD938X_ZDET_NUM_MEASUREMENTS   (900)
 69 #define WCD938X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
 70 #define WCD938X_MBHC_GET_X1(x)          (x & 0x3FFF)
 71 /* Z value compared in milliOhm */
 72 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
 73 #define WCD938X_MBHC_ZDET_CONST         (86 * 16384)
 74 #define WCD938X_MBHC_MOISTURE_RREF      R_24_KOHM
 75 #define WCD_MBHC_HS_V_MAX           1600
 76 
 77 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
 78 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 79         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 80                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 81         .tlv.p = (tlv_array), \
 82         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 83         .put = wcd938x_ear_pa_put_gain, \
 84         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
 85 
 86 enum {
 87         WCD9380 = 0,
 88         WCD9385 = 5,
 89 };
 90 
 91 enum {
 92         TX_HDR12 = 0,
 93         TX_HDR34,
 94         TX_HDR_MAX,
 95 };
 96 
 97 enum {
 98         WCD_RX1,
 99         WCD_RX2,
100         WCD_RX3
101 };
102 
103 enum {
104         /* INTR_CTRL_INT_MASK_0 */
105         WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
106         WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
107         WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
108         WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
109         WCD938X_IRQ_MBHC_SW_DET,
110         WCD938X_IRQ_HPHR_OCP_INT,
111         WCD938X_IRQ_HPHR_CNP_INT,
112         WCD938X_IRQ_HPHL_OCP_INT,
113 
114         /* INTR_CTRL_INT_MASK_1 */
115         WCD938X_IRQ_HPHL_CNP_INT,
116         WCD938X_IRQ_EAR_CNP_INT,
117         WCD938X_IRQ_EAR_SCD_INT,
118         WCD938X_IRQ_AUX_CNP_INT,
119         WCD938X_IRQ_AUX_SCD_INT,
120         WCD938X_IRQ_HPHL_PDM_WD_INT,
121         WCD938X_IRQ_HPHR_PDM_WD_INT,
122         WCD938X_IRQ_AUX_PDM_WD_INT,
123 
124         /* INTR_CTRL_INT_MASK_2 */
125         WCD938X_IRQ_LDORT_SCD_INT,
126         WCD938X_IRQ_MBHC_MOISTURE_INT,
127         WCD938X_IRQ_HPHL_SURGE_DET_INT,
128         WCD938X_IRQ_HPHR_SURGE_DET_INT,
129         WCD938X_NUM_IRQS,
130 };
131 
132 enum {
133         WCD_ADC1 = 0,
134         WCD_ADC2,
135         WCD_ADC3,
136         WCD_ADC4,
137         ALLOW_BUCK_DISABLE,
138         HPH_COMP_DELAY,
139         HPH_PA_DELAY,
140         AMIC2_BCS_ENABLE,
141         WCD_SUPPLIES_LPM_MODE,
142 };
143 
144 enum {
145         ADC_MODE_INVALID = 0,
146         ADC_MODE_HIFI,
147         ADC_MODE_LO_HIF,
148         ADC_MODE_NORMAL,
149         ADC_MODE_LP,
150         ADC_MODE_ULP1,
151         ADC_MODE_ULP2,
152 };
153 
154 enum {
155         AIF1_PB = 0,
156         AIF1_CAP,
157         NUM_CODEC_DAIS,
158 };
159 
160 static u8 tx_mode_bit[] = {
161         [ADC_MODE_INVALID] = 0x00,
162         [ADC_MODE_HIFI] = 0x01,
163         [ADC_MODE_LO_HIF] = 0x02,
164         [ADC_MODE_NORMAL] = 0x04,
165         [ADC_MODE_LP] = 0x08,
166         [ADC_MODE_ULP1] = 0x10,
167         [ADC_MODE_ULP2] = 0x20,
168 };
169 
170 struct wcd938x_priv {
171         struct sdw_slave *tx_sdw_dev;
172         struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
173         struct device *txdev;
174         struct device *rxdev;
175         struct device_node *rxnode, *txnode;
176         struct regmap *regmap;
177         struct mutex micb_lock;
178         /* mbhc module */
179         struct wcd_mbhc *wcd_mbhc;
180         struct wcd_mbhc_config mbhc_cfg;
181         struct wcd_mbhc_intr intr_ids;
182         struct wcd_clsh_ctrl *clsh_info;
183         struct irq_domain *virq;
184         struct regmap_irq_chip *wcd_regmap_irq_chip;
185         struct regmap_irq_chip_data *irq_chip;
186         struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
187         struct snd_soc_jack *jack;
188         unsigned long status_mask;
189         s32 micb_ref[WCD938X_MAX_MICBIAS];
190         s32 pullup_ref[WCD938X_MAX_MICBIAS];
191         u32 hph_mode;
192         u32 tx_mode[TX_ADC_MAX];
193         int flyback_cur_det_disable;
194         int ear_rx_path;
195         int variant;
196         int reset_gpio;
197         u32 micb1_mv;
198         u32 micb2_mv;
199         u32 micb3_mv;
200         u32 micb4_mv;
201         int hphr_pdm_wd_int;
202         int hphl_pdm_wd_int;
203         int aux_pdm_wd_int;
204         bool comp1_enable;
205         bool comp2_enable;
206         bool ldoh;
207         bool bcs_dis;
208 };
209 
210 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
211 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
213 
214 struct wcd938x_mbhc_zdet_param {
215         u16 ldo_ctl;
216         u16 noff;
217         u16 nshift;
218         u16 btn5;
219         u16 btn6;
220         u16 btn7;
221 };
222 
223 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
224         WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
225         WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
226         WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
227         WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
228         WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
229         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
230         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
231         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
232         WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
233         WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
234         WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
235         WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
236         WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
237         WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
238         WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
239         WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
240         WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
241         WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
242         WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
243         WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
244         WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
245         WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
246         WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
247         WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
248         WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
249         WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
250         WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
251         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
252         WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
253         WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
254         WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
255         WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
256         WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
257         WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
258         WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
259         WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
260         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
261         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
262         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
263         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
264         WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
265         WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
266         WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
267         WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
268         WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
269         WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
270         WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
271         WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
272 };
273 
274 static const struct reg_default wcd938x_defaults[] = {
275         {WCD938X_ANA_PAGE_REGISTER,                            0x00},
276         {WCD938X_ANA_BIAS,                                     0x00},
277         {WCD938X_ANA_RX_SUPPLIES,                              0x00},
278         {WCD938X_ANA_HPH,                                      0x0C},
279         {WCD938X_ANA_EAR,                                      0x00},
280         {WCD938X_ANA_EAR_COMPANDER_CTL,                        0x02},
281         {WCD938X_ANA_TX_CH1,                                   0x20},
282         {WCD938X_ANA_TX_CH2,                                   0x00},
283         {WCD938X_ANA_TX_CH3,                                   0x20},
284         {WCD938X_ANA_TX_CH4,                                   0x00},
285         {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC,                 0x00},
286         {WCD938X_ANA_MICB3_DSP_EN_LOGIC,                       0x00},
287         {WCD938X_ANA_MBHC_MECH,                                0x39},
288         {WCD938X_ANA_MBHC_ELECT,                               0x08},
289         {WCD938X_ANA_MBHC_ZDET,                                0x00},
290         {WCD938X_ANA_MBHC_RESULT_1,                            0x00},
291         {WCD938X_ANA_MBHC_RESULT_2,                            0x00},
292         {WCD938X_ANA_MBHC_RESULT_3,                            0x00},
293         {WCD938X_ANA_MBHC_BTN0,                                0x00},
294         {WCD938X_ANA_MBHC_BTN1,                                0x10},
295         {WCD938X_ANA_MBHC_BTN2,                                0x20},
296         {WCD938X_ANA_MBHC_BTN3,                                0x30},
297         {WCD938X_ANA_MBHC_BTN4,                                0x40},
298         {WCD938X_ANA_MBHC_BTN5,                                0x50},
299         {WCD938X_ANA_MBHC_BTN6,                                0x60},
300         {WCD938X_ANA_MBHC_BTN7,                                0x70},
301         {WCD938X_ANA_MICB1,                                    0x10},
302         {WCD938X_ANA_MICB2,                                    0x10},
303         {WCD938X_ANA_MICB2_RAMP,                               0x00},
304         {WCD938X_ANA_MICB3,                                    0x10},
305         {WCD938X_ANA_MICB4,                                    0x10},
306         {WCD938X_BIAS_CTL,                                     0x2A},
307         {WCD938X_BIAS_VBG_FINE_ADJ,                            0x55},
308         {WCD938X_LDOL_VDDCX_ADJUST,                            0x01},
309         {WCD938X_LDOL_DISABLE_LDOL,                            0x00},
310         {WCD938X_MBHC_CTL_CLK,                                 0x00},
311         {WCD938X_MBHC_CTL_ANA,                                 0x00},
312         {WCD938X_MBHC_CTL_SPARE_1,                             0x00},
313         {WCD938X_MBHC_CTL_SPARE_2,                             0x00},
314         {WCD938X_MBHC_CTL_BCS,                                 0x00},
315         {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS,                 0x00},
316         {WCD938X_MBHC_TEST_CTL,                                0x00},
317         {WCD938X_LDOH_MODE,                                    0x2B},
318         {WCD938X_LDOH_BIAS,                                    0x68},
319         {WCD938X_LDOH_STB_LOADS,                               0x00},
320         {WCD938X_LDOH_SLOWRAMP,                                0x50},
321         {WCD938X_MICB1_TEST_CTL_1,                             0x1A},
322         {WCD938X_MICB1_TEST_CTL_2,                             0x00},
323         {WCD938X_MICB1_TEST_CTL_3,                             0xA4},
324         {WCD938X_MICB2_TEST_CTL_1,                             0x1A},
325         {WCD938X_MICB2_TEST_CTL_2,                             0x00},
326         {WCD938X_MICB2_TEST_CTL_3,                             0x24},
327         {WCD938X_MICB3_TEST_CTL_1,                             0x1A},
328         {WCD938X_MICB3_TEST_CTL_2,                             0x00},
329         {WCD938X_MICB3_TEST_CTL_3,                             0xA4},
330         {WCD938X_MICB4_TEST_CTL_1,                             0x1A},
331         {WCD938X_MICB4_TEST_CTL_2,                             0x00},
332         {WCD938X_MICB4_TEST_CTL_3,                             0xA4},
333         {WCD938X_TX_COM_ADC_VCM,                               0x39},
334         {WCD938X_TX_COM_BIAS_ATEST,                            0xE0},
335         {WCD938X_TX_COM_SPARE1,                                0x00},
336         {WCD938X_TX_COM_SPARE2,                                0x00},
337         {WCD938X_TX_COM_TXFE_DIV_CTL,                          0x22},
338         {WCD938X_TX_COM_TXFE_DIV_START,                        0x00},
339         {WCD938X_TX_COM_SPARE3,                                0x00},
340         {WCD938X_TX_COM_SPARE4,                                0x00},
341         {WCD938X_TX_1_2_TEST_EN,                               0xCC},
342         {WCD938X_TX_1_2_ADC_IB,                                0xE9},
343         {WCD938X_TX_1_2_ATEST_REFCTL,                          0x0A},
344         {WCD938X_TX_1_2_TEST_CTL,                              0x38},
345         {WCD938X_TX_1_2_TEST_BLK_EN1,                          0xFF},
346         {WCD938X_TX_1_2_TXFE1_CLKDIV,                          0x00},
347         {WCD938X_TX_1_2_SAR2_ERR,                              0x00},
348         {WCD938X_TX_1_2_SAR1_ERR,                              0x00},
349         {WCD938X_TX_3_4_TEST_EN,                               0xCC},
350         {WCD938X_TX_3_4_ADC_IB,                                0xE9},
351         {WCD938X_TX_3_4_ATEST_REFCTL,                          0x0A},
352         {WCD938X_TX_3_4_TEST_CTL,                              0x38},
353         {WCD938X_TX_3_4_TEST_BLK_EN3,                          0xFF},
354         {WCD938X_TX_3_4_TXFE3_CLKDIV,                          0x00},
355         {WCD938X_TX_3_4_SAR4_ERR,                              0x00},
356         {WCD938X_TX_3_4_SAR3_ERR,                              0x00},
357         {WCD938X_TX_3_4_TEST_BLK_EN2,                          0xFB},
358         {WCD938X_TX_3_4_TXFE2_CLKDIV,                          0x00},
359         {WCD938X_TX_3_4_SPARE1,                                0x00},
360         {WCD938X_TX_3_4_TEST_BLK_EN4,                          0xFB},
361         {WCD938X_TX_3_4_TXFE4_CLKDIV,                          0x00},
362         {WCD938X_TX_3_4_SPARE2,                                0x00},
363         {WCD938X_CLASSH_MODE_1,                                0x40},
364         {WCD938X_CLASSH_MODE_2,                                0x3A},
365         {WCD938X_CLASSH_MODE_3,                                0x00},
366         {WCD938X_CLASSH_CTRL_VCL_1,                            0x70},
367         {WCD938X_CLASSH_CTRL_VCL_2,                            0x82},
368         {WCD938X_CLASSH_CTRL_CCL_1,                            0x31},
369         {WCD938X_CLASSH_CTRL_CCL_2,                            0x80},
370         {WCD938X_CLASSH_CTRL_CCL_3,                            0x80},
371         {WCD938X_CLASSH_CTRL_CCL_4,                            0x51},
372         {WCD938X_CLASSH_CTRL_CCL_5,                            0x00},
373         {WCD938X_CLASSH_BUCK_TMUX_A_D,                         0x00},
374         {WCD938X_CLASSH_BUCK_SW_DRV_CNTL,                      0x77},
375         {WCD938X_CLASSH_SPARE,                                 0x00},
376         {WCD938X_FLYBACK_EN,                                   0x4E},
377         {WCD938X_FLYBACK_VNEG_CTRL_1,                          0x0B},
378         {WCD938X_FLYBACK_VNEG_CTRL_2,                          0x45},
379         {WCD938X_FLYBACK_VNEG_CTRL_3,                          0x74},
380         {WCD938X_FLYBACK_VNEG_CTRL_4,                          0x7F},
381         {WCD938X_FLYBACK_VNEG_CTRL_5,                          0x83},
382         {WCD938X_FLYBACK_VNEG_CTRL_6,                          0x98},
383         {WCD938X_FLYBACK_VNEG_CTRL_7,                          0xA9},
384         {WCD938X_FLYBACK_VNEG_CTRL_8,                          0x68},
385         {WCD938X_FLYBACK_VNEG_CTRL_9,                          0x64},
386         {WCD938X_FLYBACK_VNEGDAC_CTRL_1,                       0xED},
387         {WCD938X_FLYBACK_VNEGDAC_CTRL_2,                       0xF0},
388         {WCD938X_FLYBACK_VNEGDAC_CTRL_3,                       0xA6},
389         {WCD938X_FLYBACK_CTRL_1,                               0x65},
390         {WCD938X_FLYBACK_TEST_CTL,                             0x00},
391         {WCD938X_RX_AUX_SW_CTL,                                0x00},
392         {WCD938X_RX_PA_AUX_IN_CONN,                            0x01},
393         {WCD938X_RX_TIMER_DIV,                                 0x32},
394         {WCD938X_RX_OCP_CTL,                                   0x1F},
395         {WCD938X_RX_OCP_COUNT,                                 0x77},
396         {WCD938X_RX_BIAS_EAR_DAC,                              0xA0},
397         {WCD938X_RX_BIAS_EAR_AMP,                              0xAA},
398         {WCD938X_RX_BIAS_HPH_LDO,                              0xA9},
399         {WCD938X_RX_BIAS_HPH_PA,                               0xAA},
400         {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2,                    0x8A},
401         {WCD938X_RX_BIAS_HPH_RDAC_LDO,                         0x88},
402         {WCD938X_RX_BIAS_HPH_CNP1,                             0x82},
403         {WCD938X_RX_BIAS_HPH_LOWPOWER,                         0x82},
404         {WCD938X_RX_BIAS_AUX_DAC,                              0xA0},
405         {WCD938X_RX_BIAS_AUX_AMP,                              0xAA},
406         {WCD938X_RX_BIAS_VNEGDAC_BLEEDER,                      0x50},
407         {WCD938X_RX_BIAS_MISC,                                 0x00},
408         {WCD938X_RX_BIAS_BUCK_RST,                             0x08},
409         {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP,                     0x44},
410         {WCD938X_RX_BIAS_FLYB_ERRAMP,                          0x40},
411         {WCD938X_RX_BIAS_FLYB_BUFF,                            0xAA},
412         {WCD938X_RX_BIAS_FLYB_MID_RST,                         0x14},
413         {WCD938X_HPH_L_STATUS,                                 0x04},
414         {WCD938X_HPH_R_STATUS,                                 0x04},
415         {WCD938X_HPH_CNP_EN,                                   0x80},
416         {WCD938X_HPH_CNP_WG_CTL,                               0x9A},
417         {WCD938X_HPH_CNP_WG_TIME,                              0x14},
418         {WCD938X_HPH_OCP_CTL,                                  0x28},
419         {WCD938X_HPH_AUTO_CHOP,                                0x16},
420         {WCD938X_HPH_CHOP_CTL,                                 0x83},
421         {WCD938X_HPH_PA_CTL1,                                  0x46},
422         {WCD938X_HPH_PA_CTL2,                                  0x50},
423         {WCD938X_HPH_L_EN,                                     0x80},
424         {WCD938X_HPH_L_TEST,                                   0xE0},
425         {WCD938X_HPH_L_ATEST,                                  0x50},
426         {WCD938X_HPH_R_EN,                                     0x80},
427         {WCD938X_HPH_R_TEST,                                   0xE0},
428         {WCD938X_HPH_R_ATEST,                                  0x54},
429         {WCD938X_HPH_RDAC_CLK_CTL1,                            0x99},
430         {WCD938X_HPH_RDAC_CLK_CTL2,                            0x9B},
431         {WCD938X_HPH_RDAC_LDO_CTL,                             0x33},
432         {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL,                     0x00},
433         {WCD938X_HPH_REFBUFF_UHQA_CTL,                         0x68},
434         {WCD938X_HPH_REFBUFF_LP_CTL,                           0x0E},
435         {WCD938X_HPH_L_DAC_CTL,                                0x20},
436         {WCD938X_HPH_R_DAC_CTL,                                0x20},
437         {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL,               0x55},
438         {WCD938X_HPH_SURGE_HPHLR_SURGE_EN,                     0x19},
439         {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1,                  0xA0},
440         {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS,                 0x00},
441         {WCD938X_EAR_EAR_EN_REG,                               0x22},
442         {WCD938X_EAR_EAR_PA_CON,                               0x44},
443         {WCD938X_EAR_EAR_SP_CON,                               0xDB},
444         {WCD938X_EAR_EAR_DAC_CON,                              0x80},
445         {WCD938X_EAR_EAR_CNP_FSM_CON,                          0xB2},
446         {WCD938X_EAR_TEST_CTL,                                 0x00},
447         {WCD938X_EAR_STATUS_REG_1,                             0x00},
448         {WCD938X_EAR_STATUS_REG_2,                             0x08},
449         {WCD938X_ANA_NEW_PAGE_REGISTER,                        0x00},
450         {WCD938X_HPH_NEW_ANA_HPH2,                             0x00},
451         {WCD938X_HPH_NEW_ANA_HPH3,                             0x00},
452         {WCD938X_SLEEP_CTL,                                    0x16},
453         {WCD938X_SLEEP_WATCHDOG_CTL,                           0x00},
454         {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL,                 0x00},
455         {WCD938X_MBHC_NEW_CTL_1,                               0x02},
456         {WCD938X_MBHC_NEW_CTL_2,                               0x05},
457         {WCD938X_MBHC_NEW_PLUG_DETECT_CTL,                     0xE9},
458         {WCD938X_MBHC_NEW_ZDET_ANA_CTL,                        0x0F},
459         {WCD938X_MBHC_NEW_ZDET_RAMP_CTL,                       0x00},
460         {WCD938X_MBHC_NEW_FSM_STATUS,                          0x00},
461         {WCD938X_MBHC_NEW_ADC_RESULT,                          0x00},
462         {WCD938X_TX_NEW_AMIC_MUX_CFG,                          0x00},
463         {WCD938X_AUX_AUXPA,                                    0x00},
464         {WCD938X_LDORXTX_MODE,                                 0x0C},
465         {WCD938X_LDORXTX_CONFIG,                               0x10},
466         {WCD938X_DIE_CRACK_DIE_CRK_DET_EN,                     0x00},
467         {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT,                    0x00},
468         {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,                    0x40},
469         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,                   0x81},
470         {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL,                    0x10},
471         {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL,                0x00},
472         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,                   0x81},
473         {WCD938X_HPH_NEW_INT_PA_MISC1,                         0x22},
474         {WCD938X_HPH_NEW_INT_PA_MISC2,                         0x00},
475         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC,                     0x00},
476         {WCD938X_HPH_NEW_INT_HPH_TIMER1,                       0xFE},
477         {WCD938X_HPH_NEW_INT_HPH_TIMER2,                       0x02},
478         {WCD938X_HPH_NEW_INT_HPH_TIMER3,                       0x4E},
479         {WCD938X_HPH_NEW_INT_HPH_TIMER4,                       0x54},
480         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2,                    0x00},
481         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3,                    0x00},
482         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,               0x90},
483         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,               0x90},
484         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI,              0x62},
485         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,                 0x01},
486         {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP,                   0x11},
487         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL,            0x57},
488         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,       0x01},
489         {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,                0x00},
490         {WCD938X_MBHC_NEW_INT_SPARE_2,                         0x00},
491         {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON,                  0xA8},
492         {WCD938X_EAR_INT_NEW_CNP_VCM_CON1,                     0x42},
493         {WCD938X_EAR_INT_NEW_CNP_VCM_CON2,                     0x22},
494         {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS,                 0x00},
495         {WCD938X_AUX_INT_EN_REG,                               0x00},
496         {WCD938X_AUX_INT_PA_CTRL,                              0x06},
497         {WCD938X_AUX_INT_SP_CTRL,                              0xD2},
498         {WCD938X_AUX_INT_DAC_CTRL,                             0x80},
499         {WCD938X_AUX_INT_CLK_CTRL,                             0x50},
500         {WCD938X_AUX_INT_TEST_CTRL,                            0x00},
501         {WCD938X_AUX_INT_STATUS_REG,                           0x00},
502         {WCD938X_AUX_INT_MISC,                                 0x00},
503         {WCD938X_LDORXTX_INT_BIAS,                             0x6E},
504         {WCD938X_LDORXTX_INT_STB_LOADS_DTEST,                  0x50},
505         {WCD938X_LDORXTX_INT_TEST0,                            0x1C},
506         {WCD938X_LDORXTX_INT_STARTUP_TIMER,                    0xFF},
507         {WCD938X_LDORXTX_INT_TEST1,                            0x1F},
508         {WCD938X_LDORXTX_INT_STATUS,                           0x00},
509         {WCD938X_SLEEP_INT_WATCHDOG_CTL_1,                     0x0A},
510         {WCD938X_SLEEP_INT_WATCHDOG_CTL_2,                     0x0A},
511         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1,               0x02},
512         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2,               0x60},
513         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2,               0xFF},
514         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1,               0x7F},
515         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0,               0x3F},
516         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M,          0x1F},
517         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M,          0x0F},
518         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1,          0xD7},
519         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0,            0xC8},
520         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP,           0xC6},
521         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1,      0xD5},
522         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0,        0xCA},
523         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,       0x05},
524         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0,    0xA5},
525         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,       0x13},
526         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1,             0x88},
527         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP,            0x42},
528         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2,                  0xFF},
529         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1,                  0x64},
530         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0,                  0x64},
531         {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP,                 0x77},
532         {WCD938X_DIGITAL_PAGE_REGISTER,                        0x00},
533         {WCD938X_DIGITAL_CHIP_ID0,                             0x00},
534         {WCD938X_DIGITAL_CHIP_ID1,                             0x00},
535         {WCD938X_DIGITAL_CHIP_ID2,                             0x0D},
536         {WCD938X_DIGITAL_CHIP_ID3,                             0x01},
537         {WCD938X_DIGITAL_SWR_TX_CLK_RATE,                      0x00},
538         {WCD938X_DIGITAL_CDC_RST_CTL,                          0x03},
539         {WCD938X_DIGITAL_TOP_CLK_CFG,                          0x00},
540         {WCD938X_DIGITAL_CDC_ANA_CLK_CTL,                      0x00},
541         {WCD938X_DIGITAL_CDC_DIG_CLK_CTL,                      0xF0},
542         {WCD938X_DIGITAL_SWR_RST_EN,                           0x00},
543         {WCD938X_DIGITAL_CDC_PATH_MODE,                        0x55},
544         {WCD938X_DIGITAL_CDC_RX_RST,                           0x00},
545         {WCD938X_DIGITAL_CDC_RX0_CTL,                          0xFC},
546         {WCD938X_DIGITAL_CDC_RX1_CTL,                          0xFC},
547         {WCD938X_DIGITAL_CDC_RX2_CTL,                          0xFC},
548         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,                  0x00},
549         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,                  0x00},
550         {WCD938X_DIGITAL_CDC_COMP_CTL_0,                       0x00},
551         {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,                   0x1E},
552         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0,                     0x00},
553         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1,                     0x01},
554         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0,                     0x63},
555         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1,                     0x04},
556         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0,                     0xAC},
557         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1,                     0x04},
558         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0,                     0x1A},
559         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1,                     0x03},
560         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0,                     0xBC},
561         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1,                     0x02},
562         {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0,                     0xC7},
563         {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0,                     0xF8},
564         {WCD938X_DIGITAL_CDC_HPH_DSM_C_0,                      0x47},
565         {WCD938X_DIGITAL_CDC_HPH_DSM_C_1,                      0x43},
566         {WCD938X_DIGITAL_CDC_HPH_DSM_C_2,                      0xB1},
567         {WCD938X_DIGITAL_CDC_HPH_DSM_C_3,                      0x17},
568         {WCD938X_DIGITAL_CDC_HPH_DSM_R1,                       0x4D},
569         {WCD938X_DIGITAL_CDC_HPH_DSM_R2,                       0x29},
570         {WCD938X_DIGITAL_CDC_HPH_DSM_R3,                       0x34},
571         {WCD938X_DIGITAL_CDC_HPH_DSM_R4,                       0x59},
572         {WCD938X_DIGITAL_CDC_HPH_DSM_R5,                       0x66},
573         {WCD938X_DIGITAL_CDC_HPH_DSM_R6,                       0x87},
574         {WCD938X_DIGITAL_CDC_HPH_DSM_R7,                       0x64},
575         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0,                     0x00},
576         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1,                     0x01},
577         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0,                     0x96},
578         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1,                     0x09},
579         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0,                     0xAB},
580         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1,                     0x05},
581         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0,                     0x1C},
582         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1,                     0x02},
583         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0,                     0x17},
584         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1,                     0x02},
585         {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0,                     0xAA},
586         {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0,                     0xE3},
587         {WCD938X_DIGITAL_CDC_AUX_DSM_C_0,                      0x69},
588         {WCD938X_DIGITAL_CDC_AUX_DSM_C_1,                      0x54},
589         {WCD938X_DIGITAL_CDC_AUX_DSM_C_2,                      0x02},
590         {WCD938X_DIGITAL_CDC_AUX_DSM_C_3,                      0x15},
591         {WCD938X_DIGITAL_CDC_AUX_DSM_R1,                       0xA4},
592         {WCD938X_DIGITAL_CDC_AUX_DSM_R2,                       0xB5},
593         {WCD938X_DIGITAL_CDC_AUX_DSM_R3,                       0x86},
594         {WCD938X_DIGITAL_CDC_AUX_DSM_R4,                       0x85},
595         {WCD938X_DIGITAL_CDC_AUX_DSM_R5,                       0xAA},
596         {WCD938X_DIGITAL_CDC_AUX_DSM_R6,                       0xE2},
597         {WCD938X_DIGITAL_CDC_AUX_DSM_R7,                       0x62},
598         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0,                    0x55},
599         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1,                    0xA9},
600         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0,                   0x3D},
601         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1,                   0x2E},
602         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2,                   0x01},
603         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0,                   0x00},
604         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1,                   0xFC},
605         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2,                   0x01},
606         {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,                     0x00},
607         {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,                     0x00},
608         {WCD938X_DIGITAL_CDC_EAR_PATH_CTL,                     0x00},
609         {WCD938X_DIGITAL_CDC_SWR_CLH,                          0x00},
610         {WCD938X_DIGITAL_SWR_CLH_BYP,                          0x00},
611         {WCD938X_DIGITAL_CDC_TX0_CTL,                          0x68},
612         {WCD938X_DIGITAL_CDC_TX1_CTL,                          0x68},
613         {WCD938X_DIGITAL_CDC_TX2_CTL,                          0x68},
614         {WCD938X_DIGITAL_CDC_TX_RST,                           0x00},
615         {WCD938X_DIGITAL_CDC_REQ_CTL,                          0x01},
616         {WCD938X_DIGITAL_CDC_RST,                              0x00},
617         {WCD938X_DIGITAL_CDC_AMIC_CTL,                         0x0F},
618         {WCD938X_DIGITAL_CDC_DMIC_CTL,                         0x04},
619         {WCD938X_DIGITAL_CDC_DMIC1_CTL,                        0x01},
620         {WCD938X_DIGITAL_CDC_DMIC2_CTL,                        0x01},
621         {WCD938X_DIGITAL_CDC_DMIC3_CTL,                        0x01},
622         {WCD938X_DIGITAL_CDC_DMIC4_CTL,                        0x01},
623         {WCD938X_DIGITAL_EFUSE_PRG_CTL,                        0x00},
624         {WCD938X_DIGITAL_EFUSE_CTL,                            0x2B},
625         {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2,                    0x11},
626         {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4,                    0x11},
627         {WCD938X_DIGITAL_PDM_WD_CTL0,                          0x00},
628         {WCD938X_DIGITAL_PDM_WD_CTL1,                          0x00},
629         {WCD938X_DIGITAL_PDM_WD_CTL2,                          0x00},
630         {WCD938X_DIGITAL_INTR_MODE,                            0x00},
631         {WCD938X_DIGITAL_INTR_MASK_0,                          0xFF},
632         {WCD938X_DIGITAL_INTR_MASK_1,                          0xFF},
633         {WCD938X_DIGITAL_INTR_MASK_2,                          0x3F},
634         {WCD938X_DIGITAL_INTR_STATUS_0,                        0x00},
635         {WCD938X_DIGITAL_INTR_STATUS_1,                        0x00},
636         {WCD938X_DIGITAL_INTR_STATUS_2,                        0x00},
637         {WCD938X_DIGITAL_INTR_CLEAR_0,                         0x00},
638         {WCD938X_DIGITAL_INTR_CLEAR_1,                         0x00},
639         {WCD938X_DIGITAL_INTR_CLEAR_2,                         0x00},
640         {WCD938X_DIGITAL_INTR_LEVEL_0,                         0x00},
641         {WCD938X_DIGITAL_INTR_LEVEL_1,                         0x00},
642         {WCD938X_DIGITAL_INTR_LEVEL_2,                         0x00},
643         {WCD938X_DIGITAL_INTR_SET_0,                           0x00},
644         {WCD938X_DIGITAL_INTR_SET_1,                           0x00},
645         {WCD938X_DIGITAL_INTR_SET_2,                           0x00},
646         {WCD938X_DIGITAL_INTR_TEST_0,                          0x00},
647         {WCD938X_DIGITAL_INTR_TEST_1,                          0x00},
648         {WCD938X_DIGITAL_INTR_TEST_2,                          0x00},
649         {WCD938X_DIGITAL_TX_MODE_DBG_EN,                       0x00},
650         {WCD938X_DIGITAL_TX_MODE_DBG_0_1,                      0x00},
651         {WCD938X_DIGITAL_TX_MODE_DBG_2_3,                      0x00},
652         {WCD938X_DIGITAL_LB_IN_SEL_CTL,                        0x00},
653         {WCD938X_DIGITAL_LOOP_BACK_MODE,                       0x00},
654         {WCD938X_DIGITAL_SWR_DAC_TEST,                         0x00},
655         {WCD938X_DIGITAL_SWR_HM_TEST_RX_0,                     0x40},
656         {WCD938X_DIGITAL_SWR_HM_TEST_TX_0,                     0x40},
657         {WCD938X_DIGITAL_SWR_HM_TEST_RX_1,                     0x00},
658         {WCD938X_DIGITAL_SWR_HM_TEST_TX_1,                     0x00},
659         {WCD938X_DIGITAL_SWR_HM_TEST_TX_2,                     0x00},
660         {WCD938X_DIGITAL_SWR_HM_TEST_0,                        0x00},
661         {WCD938X_DIGITAL_SWR_HM_TEST_1,                        0x00},
662         {WCD938X_DIGITAL_PAD_CTL_SWR_0,                        0x8F},
663         {WCD938X_DIGITAL_PAD_CTL_SWR_1,                        0x06},
664         {WCD938X_DIGITAL_I2C_CTL,                              0x00},
665         {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE,                0x00},
666         {WCD938X_DIGITAL_EFUSE_TEST_CTL_0,                     0x00},
667         {WCD938X_DIGITAL_EFUSE_TEST_CTL_1,                     0x00},
668         {WCD938X_DIGITAL_EFUSE_T_DATA_0,                       0x00},
669         {WCD938X_DIGITAL_EFUSE_T_DATA_1,                       0x00},
670         {WCD938X_DIGITAL_PAD_CTL_PDM_RX0,                      0xF1},
671         {WCD938X_DIGITAL_PAD_CTL_PDM_RX1,                      0xF1},
672         {WCD938X_DIGITAL_PAD_CTL_PDM_TX0,                      0xF1},
673         {WCD938X_DIGITAL_PAD_CTL_PDM_TX1,                      0xF1},
674         {WCD938X_DIGITAL_PAD_CTL_PDM_TX2,                      0xF1},
675         {WCD938X_DIGITAL_PAD_INP_DIS_0,                        0x00},
676         {WCD938X_DIGITAL_PAD_INP_DIS_1,                        0x00},
677         {WCD938X_DIGITAL_DRIVE_STRENGTH_0,                     0x00},
678         {WCD938X_DIGITAL_DRIVE_STRENGTH_1,                     0x00},
679         {WCD938X_DIGITAL_DRIVE_STRENGTH_2,                     0x00},
680         {WCD938X_DIGITAL_RX_DATA_EDGE_CTL,                     0x1F},
681         {WCD938X_DIGITAL_TX_DATA_EDGE_CTL,                     0x80},
682         {WCD938X_DIGITAL_GPIO_MODE,                            0x00},
683         {WCD938X_DIGITAL_PIN_CTL_OE,                           0x00},
684         {WCD938X_DIGITAL_PIN_CTL_DATA_0,                       0x00},
685         {WCD938X_DIGITAL_PIN_CTL_DATA_1,                       0x00},
686         {WCD938X_DIGITAL_PIN_STATUS_0,                         0x00},
687         {WCD938X_DIGITAL_PIN_STATUS_1,                         0x00},
688         {WCD938X_DIGITAL_DIG_DEBUG_CTL,                        0x00},
689         {WCD938X_DIGITAL_DIG_DEBUG_EN,                         0x00},
690         {WCD938X_DIGITAL_ANA_CSR_DBG_ADD,                      0x00},
691         {WCD938X_DIGITAL_ANA_CSR_DBG_CTL,                      0x48},
692         {WCD938X_DIGITAL_SSP_DBG,                              0x00},
693         {WCD938X_DIGITAL_MODE_STATUS_0,                        0x00},
694         {WCD938X_DIGITAL_MODE_STATUS_1,                        0x00},
695         {WCD938X_DIGITAL_SPARE_0,                              0x00},
696         {WCD938X_DIGITAL_SPARE_1,                              0x00},
697         {WCD938X_DIGITAL_SPARE_2,                              0x00},
698         {WCD938X_DIGITAL_EFUSE_REG_0,                          0x00},
699         {WCD938X_DIGITAL_EFUSE_REG_1,                          0xFF},
700         {WCD938X_DIGITAL_EFUSE_REG_2,                          0xFF},
701         {WCD938X_DIGITAL_EFUSE_REG_3,                          0xFF},
702         {WCD938X_DIGITAL_EFUSE_REG_4,                          0xFF},
703         {WCD938X_DIGITAL_EFUSE_REG_5,                          0xFF},
704         {WCD938X_DIGITAL_EFUSE_REG_6,                          0xFF},
705         {WCD938X_DIGITAL_EFUSE_REG_7,                          0xFF},
706         {WCD938X_DIGITAL_EFUSE_REG_8,                          0xFF},
707         {WCD938X_DIGITAL_EFUSE_REG_9,                          0xFF},
708         {WCD938X_DIGITAL_EFUSE_REG_10,                         0xFF},
709         {WCD938X_DIGITAL_EFUSE_REG_11,                         0xFF},
710         {WCD938X_DIGITAL_EFUSE_REG_12,                         0xFF},
711         {WCD938X_DIGITAL_EFUSE_REG_13,                         0xFF},
712         {WCD938X_DIGITAL_EFUSE_REG_14,                         0xFF},
713         {WCD938X_DIGITAL_EFUSE_REG_15,                         0xFF},
714         {WCD938X_DIGITAL_EFUSE_REG_16,                         0xFF},
715         {WCD938X_DIGITAL_EFUSE_REG_17,                         0xFF},
716         {WCD938X_DIGITAL_EFUSE_REG_18,                         0xFF},
717         {WCD938X_DIGITAL_EFUSE_REG_19,                         0xFF},
718         {WCD938X_DIGITAL_EFUSE_REG_20,                         0x0E},
719         {WCD938X_DIGITAL_EFUSE_REG_21,                         0x00},
720         {WCD938X_DIGITAL_EFUSE_REG_22,                         0x00},
721         {WCD938X_DIGITAL_EFUSE_REG_23,                         0xF8},
722         {WCD938X_DIGITAL_EFUSE_REG_24,                         0x16},
723         {WCD938X_DIGITAL_EFUSE_REG_25,                         0x00},
724         {WCD938X_DIGITAL_EFUSE_REG_26,                         0x00},
725         {WCD938X_DIGITAL_EFUSE_REG_27,                         0x00},
726         {WCD938X_DIGITAL_EFUSE_REG_28,                         0x00},
727         {WCD938X_DIGITAL_EFUSE_REG_29,                         0x00},
728         {WCD938X_DIGITAL_EFUSE_REG_30,                         0x00},
729         {WCD938X_DIGITAL_EFUSE_REG_31,                         0x00},
730         {WCD938X_DIGITAL_TX_REQ_FB_CTL_0,                      0x88},
731         {WCD938X_DIGITAL_TX_REQ_FB_CTL_1,                      0x88},
732         {WCD938X_DIGITAL_TX_REQ_FB_CTL_2,                      0x88},
733         {WCD938X_DIGITAL_TX_REQ_FB_CTL_3,                      0x88},
734         {WCD938X_DIGITAL_TX_REQ_FB_CTL_4,                      0x88},
735         {WCD938X_DIGITAL_DEM_BYPASS_DATA0,                     0x55},
736         {WCD938X_DIGITAL_DEM_BYPASS_DATA1,                     0x55},
737         {WCD938X_DIGITAL_DEM_BYPASS_DATA2,                     0x55},
738         {WCD938X_DIGITAL_DEM_BYPASS_DATA3,                     0x01},
739 };
740 
741 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
742 {
743         switch (reg) {
744         case WCD938X_ANA_PAGE_REGISTER:
745         case WCD938X_ANA_BIAS:
746         case WCD938X_ANA_RX_SUPPLIES:
747         case WCD938X_ANA_HPH:
748         case WCD938X_ANA_EAR:
749         case WCD938X_ANA_EAR_COMPANDER_CTL:
750         case WCD938X_ANA_TX_CH1:
751         case WCD938X_ANA_TX_CH2:
752         case WCD938X_ANA_TX_CH3:
753         case WCD938X_ANA_TX_CH4:
754         case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
755         case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
756         case WCD938X_ANA_MBHC_MECH:
757         case WCD938X_ANA_MBHC_ELECT:
758         case WCD938X_ANA_MBHC_ZDET:
759         case WCD938X_ANA_MBHC_BTN0:
760         case WCD938X_ANA_MBHC_BTN1:
761         case WCD938X_ANA_MBHC_BTN2:
762         case WCD938X_ANA_MBHC_BTN3:
763         case WCD938X_ANA_MBHC_BTN4:
764         case WCD938X_ANA_MBHC_BTN5:
765         case WCD938X_ANA_MBHC_BTN6:
766         case WCD938X_ANA_MBHC_BTN7:
767         case WCD938X_ANA_MICB1:
768         case WCD938X_ANA_MICB2:
769         case WCD938X_ANA_MICB2_RAMP:
770         case WCD938X_ANA_MICB3:
771         case WCD938X_ANA_MICB4:
772         case WCD938X_BIAS_CTL:
773         case WCD938X_BIAS_VBG_FINE_ADJ:
774         case WCD938X_LDOL_VDDCX_ADJUST:
775         case WCD938X_LDOL_DISABLE_LDOL:
776         case WCD938X_MBHC_CTL_CLK:
777         case WCD938X_MBHC_CTL_ANA:
778         case WCD938X_MBHC_CTL_SPARE_1:
779         case WCD938X_MBHC_CTL_SPARE_2:
780         case WCD938X_MBHC_CTL_BCS:
781         case WCD938X_MBHC_TEST_CTL:
782         case WCD938X_LDOH_MODE:
783         case WCD938X_LDOH_BIAS:
784         case WCD938X_LDOH_STB_LOADS:
785         case WCD938X_LDOH_SLOWRAMP:
786         case WCD938X_MICB1_TEST_CTL_1:
787         case WCD938X_MICB1_TEST_CTL_2:
788         case WCD938X_MICB1_TEST_CTL_3:
789         case WCD938X_MICB2_TEST_CTL_1:
790         case WCD938X_MICB2_TEST_CTL_2:
791         case WCD938X_MICB2_TEST_CTL_3:
792         case WCD938X_MICB3_TEST_CTL_1:
793         case WCD938X_MICB3_TEST_CTL_2:
794         case WCD938X_MICB3_TEST_CTL_3:
795         case WCD938X_MICB4_TEST_CTL_1:
796         case WCD938X_MICB4_TEST_CTL_2:
797         case WCD938X_MICB4_TEST_CTL_3:
798         case WCD938X_TX_COM_ADC_VCM:
799         case WCD938X_TX_COM_BIAS_ATEST:
800         case WCD938X_TX_COM_SPARE1:
801         case WCD938X_TX_COM_SPARE2:
802         case WCD938X_TX_COM_TXFE_DIV_CTL:
803         case WCD938X_TX_COM_TXFE_DIV_START:
804         case WCD938X_TX_COM_SPARE3:
805         case WCD938X_TX_COM_SPARE4:
806         case WCD938X_TX_1_2_TEST_EN:
807         case WCD938X_TX_1_2_ADC_IB:
808         case WCD938X_TX_1_2_ATEST_REFCTL:
809         case WCD938X_TX_1_2_TEST_CTL:
810         case WCD938X_TX_1_2_TEST_BLK_EN1:
811         case WCD938X_TX_1_2_TXFE1_CLKDIV:
812         case WCD938X_TX_3_4_TEST_EN:
813         case WCD938X_TX_3_4_ADC_IB:
814         case WCD938X_TX_3_4_ATEST_REFCTL:
815         case WCD938X_TX_3_4_TEST_CTL:
816         case WCD938X_TX_3_4_TEST_BLK_EN3:
817         case WCD938X_TX_3_4_TXFE3_CLKDIV:
818         case WCD938X_TX_3_4_TEST_BLK_EN2:
819         case WCD938X_TX_3_4_TXFE2_CLKDIV:
820         case WCD938X_TX_3_4_SPARE1:
821         case WCD938X_TX_3_4_TEST_BLK_EN4:
822         case WCD938X_TX_3_4_TXFE4_CLKDIV:
823         case WCD938X_TX_3_4_SPARE2:
824         case WCD938X_CLASSH_MODE_1:
825         case WCD938X_CLASSH_MODE_2:
826         case WCD938X_CLASSH_MODE_3:
827         case WCD938X_CLASSH_CTRL_VCL_1:
828         case WCD938X_CLASSH_CTRL_VCL_2:
829         case WCD938X_CLASSH_CTRL_CCL_1:
830         case WCD938X_CLASSH_CTRL_CCL_2:
831         case WCD938X_CLASSH_CTRL_CCL_3:
832         case WCD938X_CLASSH_CTRL_CCL_4:
833         case WCD938X_CLASSH_CTRL_CCL_5:
834         case WCD938X_CLASSH_BUCK_TMUX_A_D:
835         case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
836         case WCD938X_CLASSH_SPARE:
837         case WCD938X_FLYBACK_EN:
838         case WCD938X_FLYBACK_VNEG_CTRL_1:
839         case WCD938X_FLYBACK_VNEG_CTRL_2:
840         case WCD938X_FLYBACK_VNEG_CTRL_3:
841         case WCD938X_FLYBACK_VNEG_CTRL_4:
842         case WCD938X_FLYBACK_VNEG_CTRL_5:
843         case WCD938X_FLYBACK_VNEG_CTRL_6:
844         case WCD938X_FLYBACK_VNEG_CTRL_7:
845         case WCD938X_FLYBACK_VNEG_CTRL_8:
846         case WCD938X_FLYBACK_VNEG_CTRL_9:
847         case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
848         case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
849         case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
850         case WCD938X_FLYBACK_CTRL_1:
851         case WCD938X_FLYBACK_TEST_CTL:
852         case WCD938X_RX_AUX_SW_CTL:
853         case WCD938X_RX_PA_AUX_IN_CONN:
854         case WCD938X_RX_TIMER_DIV:
855         case WCD938X_RX_OCP_CTL:
856         case WCD938X_RX_OCP_COUNT:
857         case WCD938X_RX_BIAS_EAR_DAC:
858         case WCD938X_RX_BIAS_EAR_AMP:
859         case WCD938X_RX_BIAS_HPH_LDO:
860         case WCD938X_RX_BIAS_HPH_PA:
861         case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
862         case WCD938X_RX_BIAS_HPH_RDAC_LDO:
863         case WCD938X_RX_BIAS_HPH_CNP1:
864         case WCD938X_RX_BIAS_HPH_LOWPOWER:
865         case WCD938X_RX_BIAS_AUX_DAC:
866         case WCD938X_RX_BIAS_AUX_AMP:
867         case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
868         case WCD938X_RX_BIAS_MISC:
869         case WCD938X_RX_BIAS_BUCK_RST:
870         case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
871         case WCD938X_RX_BIAS_FLYB_ERRAMP:
872         case WCD938X_RX_BIAS_FLYB_BUFF:
873         case WCD938X_RX_BIAS_FLYB_MID_RST:
874         case WCD938X_HPH_CNP_EN:
875         case WCD938X_HPH_CNP_WG_CTL:
876         case WCD938X_HPH_CNP_WG_TIME:
877         case WCD938X_HPH_OCP_CTL:
878         case WCD938X_HPH_AUTO_CHOP:
879         case WCD938X_HPH_CHOP_CTL:
880         case WCD938X_HPH_PA_CTL1:
881         case WCD938X_HPH_PA_CTL2:
882         case WCD938X_HPH_L_EN:
883         case WCD938X_HPH_L_TEST:
884         case WCD938X_HPH_L_ATEST:
885         case WCD938X_HPH_R_EN:
886         case WCD938X_HPH_R_TEST:
887         case WCD938X_HPH_R_ATEST:
888         case WCD938X_HPH_RDAC_CLK_CTL1:
889         case WCD938X_HPH_RDAC_CLK_CTL2:
890         case WCD938X_HPH_RDAC_LDO_CTL:
891         case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
892         case WCD938X_HPH_REFBUFF_UHQA_CTL:
893         case WCD938X_HPH_REFBUFF_LP_CTL:
894         case WCD938X_HPH_L_DAC_CTL:
895         case WCD938X_HPH_R_DAC_CTL:
896         case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
897         case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
898         case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
899         case WCD938X_EAR_EAR_EN_REG:
900         case WCD938X_EAR_EAR_PA_CON:
901         case WCD938X_EAR_EAR_SP_CON:
902         case WCD938X_EAR_EAR_DAC_CON:
903         case WCD938X_EAR_EAR_CNP_FSM_CON:
904         case WCD938X_EAR_TEST_CTL:
905         case WCD938X_ANA_NEW_PAGE_REGISTER:
906         case WCD938X_HPH_NEW_ANA_HPH2:
907         case WCD938X_HPH_NEW_ANA_HPH3:
908         case WCD938X_SLEEP_CTL:
909         case WCD938X_SLEEP_WATCHDOG_CTL:
910         case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
911         case WCD938X_MBHC_NEW_CTL_1:
912         case WCD938X_MBHC_NEW_CTL_2:
913         case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
914         case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
915         case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
916         case WCD938X_TX_NEW_AMIC_MUX_CFG:
917         case WCD938X_AUX_AUXPA:
918         case WCD938X_LDORXTX_MODE:
919         case WCD938X_LDORXTX_CONFIG:
920         case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
921         case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
922         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
923         case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
924         case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
925         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
926         case WCD938X_HPH_NEW_INT_PA_MISC1:
927         case WCD938X_HPH_NEW_INT_PA_MISC2:
928         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
929         case WCD938X_HPH_NEW_INT_HPH_TIMER1:
930         case WCD938X_HPH_NEW_INT_HPH_TIMER2:
931         case WCD938X_HPH_NEW_INT_HPH_TIMER3:
932         case WCD938X_HPH_NEW_INT_HPH_TIMER4:
933         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
934         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
935         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
936         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
937         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
938         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
939         case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
940         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
941         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
942         case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
943         case WCD938X_MBHC_NEW_INT_SPARE_2:
944         case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
945         case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
946         case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
947         case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
948         case WCD938X_AUX_INT_EN_REG:
949         case WCD938X_AUX_INT_PA_CTRL:
950         case WCD938X_AUX_INT_SP_CTRL:
951         case WCD938X_AUX_INT_DAC_CTRL:
952         case WCD938X_AUX_INT_CLK_CTRL:
953         case WCD938X_AUX_INT_TEST_CTRL:
954         case WCD938X_AUX_INT_MISC:
955         case WCD938X_LDORXTX_INT_BIAS:
956         case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
957         case WCD938X_LDORXTX_INT_TEST0:
958         case WCD938X_LDORXTX_INT_STARTUP_TIMER:
959         case WCD938X_LDORXTX_INT_TEST1:
960         case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
961         case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
962         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
963         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
964         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
965         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
966         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
967         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
968         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
969         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
970         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
971         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
972         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
973         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
974         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
975         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
976         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
977         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
978         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
979         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
980         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
981         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
982         case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
983         case WCD938X_DIGITAL_PAGE_REGISTER:
984         case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
985         case WCD938X_DIGITAL_CDC_RST_CTL:
986         case WCD938X_DIGITAL_TOP_CLK_CFG:
987         case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
988         case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
989         case WCD938X_DIGITAL_SWR_RST_EN:
990         case WCD938X_DIGITAL_CDC_PATH_MODE:
991         case WCD938X_DIGITAL_CDC_RX_RST:
992         case WCD938X_DIGITAL_CDC_RX0_CTL:
993         case WCD938X_DIGITAL_CDC_RX1_CTL:
994         case WCD938X_DIGITAL_CDC_RX2_CTL:
995         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
996         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
997         case WCD938X_DIGITAL_CDC_COMP_CTL_0:
998         case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
999         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
1000         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
1001         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
1002         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
1003         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
1004         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
1005         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
1006         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
1007         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
1008         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
1009         case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
1010         case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
1011         case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
1012         case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
1013         case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
1014         case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
1015         case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
1016         case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
1017         case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
1018         case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
1019         case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
1020         case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
1021         case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
1022         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
1023         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
1024         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
1025         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
1026         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
1027         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
1028         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
1029         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
1030         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
1031         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
1032         case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
1033         case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
1034         case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
1035         case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
1036         case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
1037         case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
1038         case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
1039         case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
1040         case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
1041         case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
1042         case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
1043         case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
1044         case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
1045         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
1046         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
1047         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
1048         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
1049         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
1050         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
1051         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
1052         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
1053         case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
1054         case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
1055         case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
1056         case WCD938X_DIGITAL_CDC_SWR_CLH:
1057         case WCD938X_DIGITAL_SWR_CLH_BYP:
1058         case WCD938X_DIGITAL_CDC_TX0_CTL:
1059         case WCD938X_DIGITAL_CDC_TX1_CTL:
1060         case WCD938X_DIGITAL_CDC_TX2_CTL:
1061         case WCD938X_DIGITAL_CDC_TX_RST:
1062         case WCD938X_DIGITAL_CDC_REQ_CTL:
1063         case WCD938X_DIGITAL_CDC_RST:
1064         case WCD938X_DIGITAL_CDC_AMIC_CTL:
1065         case WCD938X_DIGITAL_CDC_DMIC_CTL:
1066         case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1067         case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1068         case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1069         case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1070         case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1071         case WCD938X_DIGITAL_EFUSE_CTL:
1072         case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1073         case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1074         case WCD938X_DIGITAL_PDM_WD_CTL0:
1075         case WCD938X_DIGITAL_PDM_WD_CTL1:
1076         case WCD938X_DIGITAL_PDM_WD_CTL2:
1077         case WCD938X_DIGITAL_INTR_MODE:
1078         case WCD938X_DIGITAL_INTR_MASK_0:
1079         case WCD938X_DIGITAL_INTR_MASK_1:
1080         case WCD938X_DIGITAL_INTR_MASK_2:
1081         case WCD938X_DIGITAL_INTR_CLEAR_0:
1082         case WCD938X_DIGITAL_INTR_CLEAR_1:
1083         case WCD938X_DIGITAL_INTR_CLEAR_2:
1084         case WCD938X_DIGITAL_INTR_LEVEL_0:
1085         case WCD938X_DIGITAL_INTR_LEVEL_1:
1086         case WCD938X_DIGITAL_INTR_LEVEL_2:
1087         case WCD938X_DIGITAL_INTR_SET_0:
1088         case WCD938X_DIGITAL_INTR_SET_1:
1089         case WCD938X_DIGITAL_INTR_SET_2:
1090         case WCD938X_DIGITAL_INTR_TEST_0:
1091         case WCD938X_DIGITAL_INTR_TEST_1:
1092         case WCD938X_DIGITAL_INTR_TEST_2:
1093         case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1094         case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1095         case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1096         case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1097         case WCD938X_DIGITAL_LOOP_BACK_MODE:
1098         case WCD938X_DIGITAL_SWR_DAC_TEST:
1099         case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1100         case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1101         case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1102         case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1103         case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1104         case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1105         case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1106         case WCD938X_DIGITAL_I2C_CTL:
1107         case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1108         case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1109         case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1110         case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1111         case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1112         case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1113         case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1114         case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1115         case WCD938X_DIGITAL_PAD_INP_DIS_0:
1116         case WCD938X_DIGITAL_PAD_INP_DIS_1:
1117         case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1118         case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1119         case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1120         case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1121         case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1122         case WCD938X_DIGITAL_GPIO_MODE:
1123         case WCD938X_DIGITAL_PIN_CTL_OE:
1124         case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1125         case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1126         case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1127         case WCD938X_DIGITAL_DIG_DEBUG_EN:
1128         case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1129         case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1130         case WCD938X_DIGITAL_SSP_DBG:
1131         case WCD938X_DIGITAL_SPARE_0:
1132         case WCD938X_DIGITAL_SPARE_1:
1133         case WCD938X_DIGITAL_SPARE_2:
1134         case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1135         case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1136         case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1137         case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1138         case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1139         case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1140         case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1141         case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1142         case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1143                 return true;
1144         }
1145 
1146         return false;
1147 }
1148 
1149 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1150 {
1151         switch (reg) {
1152         case WCD938X_ANA_MBHC_RESULT_1:
1153         case WCD938X_ANA_MBHC_RESULT_2:
1154         case WCD938X_ANA_MBHC_RESULT_3:
1155         case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1156         case WCD938X_TX_1_2_SAR2_ERR:
1157         case WCD938X_TX_1_2_SAR1_ERR:
1158         case WCD938X_TX_3_4_SAR4_ERR:
1159         case WCD938X_TX_3_4_SAR3_ERR:
1160         case WCD938X_HPH_L_STATUS:
1161         case WCD938X_HPH_R_STATUS:
1162         case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1163         case WCD938X_EAR_STATUS_REG_1:
1164         case WCD938X_EAR_STATUS_REG_2:
1165         case WCD938X_MBHC_NEW_FSM_STATUS:
1166         case WCD938X_MBHC_NEW_ADC_RESULT:
1167         case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1168         case WCD938X_AUX_INT_STATUS_REG:
1169         case WCD938X_LDORXTX_INT_STATUS:
1170         case WCD938X_DIGITAL_CHIP_ID0:
1171         case WCD938X_DIGITAL_CHIP_ID1:
1172         case WCD938X_DIGITAL_CHIP_ID2:
1173         case WCD938X_DIGITAL_CHIP_ID3:
1174         case WCD938X_DIGITAL_INTR_STATUS_0:
1175         case WCD938X_DIGITAL_INTR_STATUS_1:
1176         case WCD938X_DIGITAL_INTR_STATUS_2:
1177         case WCD938X_DIGITAL_INTR_CLEAR_0:
1178         case WCD938X_DIGITAL_INTR_CLEAR_1:
1179         case WCD938X_DIGITAL_INTR_CLEAR_2:
1180         case WCD938X_DIGITAL_SWR_HM_TEST_0:
1181         case WCD938X_DIGITAL_SWR_HM_TEST_1:
1182         case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1183         case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1184         case WCD938X_DIGITAL_PIN_STATUS_0:
1185         case WCD938X_DIGITAL_PIN_STATUS_1:
1186         case WCD938X_DIGITAL_MODE_STATUS_0:
1187         case WCD938X_DIGITAL_MODE_STATUS_1:
1188         case WCD938X_DIGITAL_EFUSE_REG_0:
1189         case WCD938X_DIGITAL_EFUSE_REG_1:
1190         case WCD938X_DIGITAL_EFUSE_REG_2:
1191         case WCD938X_DIGITAL_EFUSE_REG_3:
1192         case WCD938X_DIGITAL_EFUSE_REG_4:
1193         case WCD938X_DIGITAL_EFUSE_REG_5:
1194         case WCD938X_DIGITAL_EFUSE_REG_6:
1195         case WCD938X_DIGITAL_EFUSE_REG_7:
1196         case WCD938X_DIGITAL_EFUSE_REG_8:
1197         case WCD938X_DIGITAL_EFUSE_REG_9:
1198         case WCD938X_DIGITAL_EFUSE_REG_10:
1199         case WCD938X_DIGITAL_EFUSE_REG_11:
1200         case WCD938X_DIGITAL_EFUSE_REG_12:
1201         case WCD938X_DIGITAL_EFUSE_REG_13:
1202         case WCD938X_DIGITAL_EFUSE_REG_14:
1203         case WCD938X_DIGITAL_EFUSE_REG_15:
1204         case WCD938X_DIGITAL_EFUSE_REG_16:
1205         case WCD938X_DIGITAL_EFUSE_REG_17:
1206         case WCD938X_DIGITAL_EFUSE_REG_18:
1207         case WCD938X_DIGITAL_EFUSE_REG_19:
1208         case WCD938X_DIGITAL_EFUSE_REG_20:
1209         case WCD938X_DIGITAL_EFUSE_REG_21:
1210         case WCD938X_DIGITAL_EFUSE_REG_22:
1211         case WCD938X_DIGITAL_EFUSE_REG_23:
1212         case WCD938X_DIGITAL_EFUSE_REG_24:
1213         case WCD938X_DIGITAL_EFUSE_REG_25:
1214         case WCD938X_DIGITAL_EFUSE_REG_26:
1215         case WCD938X_DIGITAL_EFUSE_REG_27:
1216         case WCD938X_DIGITAL_EFUSE_REG_28:
1217         case WCD938X_DIGITAL_EFUSE_REG_29:
1218         case WCD938X_DIGITAL_EFUSE_REG_30:
1219         case WCD938X_DIGITAL_EFUSE_REG_31:
1220                 return true;
1221         }
1222         return false;
1223 }
1224 
1225 static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1226 {
1227         bool ret;
1228 
1229         ret = wcd938x_readonly_register(dev, reg);
1230         if (!ret)
1231                 return wcd938x_rdwr_register(dev, reg);
1232 
1233         return ret;
1234 }
1235 
1236 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1237 {
1238         return wcd938x_rdwr_register(dev, reg);
1239 }
1240 
1241 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1242 {
1243         if (reg <= WCD938X_BASE_ADDRESS)
1244                 return false;
1245 
1246         if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1247                 return true;
1248 
1249         if (wcd938x_readonly_register(dev, reg))
1250                 return true;
1251 
1252         return false;
1253 }
1254 
1255 static struct regmap_config wcd938x_regmap_config = {
1256         .name = "wcd938x_csr",
1257         .reg_bits = 32,
1258         .val_bits = 8,
1259         .cache_type = REGCACHE_RBTREE,
1260         .reg_defaults = wcd938x_defaults,
1261         .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1262         .max_register = WCD938X_MAX_REGISTER,
1263         .readable_reg = wcd938x_readable_register,
1264         .writeable_reg = wcd938x_writeable_register,
1265         .volatile_reg = wcd938x_volatile_register,
1266         .can_multi_write = true,
1267 };
1268 
1269 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1270         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1271         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1272         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1273         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1274         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1275         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1276         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1277         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1278         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1279         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1280         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1281         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1282         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1283         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1284         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1285         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1286         REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1287         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1288         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1289         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1290 };
1291 
1292 static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1293         .name = "wcd938x",
1294         .irqs = wcd938x_irqs,
1295         .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1296         .num_regs = 3,
1297         .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1298         .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1299         .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1300         .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1301         .use_ack = 1,
1302         .runtime_pm = true,
1303         .irq_drv_data = NULL,
1304 };
1305 
1306 static int wcd938x_get_clk_rate(int mode)
1307 {
1308         int rate;
1309 
1310         switch (mode) {
1311         case ADC_MODE_ULP2:
1312                 rate = SWR_CLK_RATE_0P6MHZ;
1313                 break;
1314         case ADC_MODE_ULP1:
1315                 rate = SWR_CLK_RATE_1P2MHZ;
1316                 break;
1317         case ADC_MODE_LP:
1318                 rate = SWR_CLK_RATE_4P8MHZ;
1319                 break;
1320         case ADC_MODE_NORMAL:
1321         case ADC_MODE_LO_HIF:
1322         case ADC_MODE_HIFI:
1323         case ADC_MODE_INVALID:
1324         default:
1325                 rate = SWR_CLK_RATE_9P6MHZ;
1326                 break;
1327         }
1328 
1329         return rate;
1330 }
1331 
1332 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
1333 {
1334         u8 mask = (bank ? 0xF0 : 0x0F);
1335         u8 val = 0;
1336 
1337         switch (rate) {
1338         case SWR_CLK_RATE_0P6MHZ:
1339                 val = (bank ? 0x60 : 0x06);
1340                 break;
1341         case SWR_CLK_RATE_1P2MHZ:
1342                 val = (bank ? 0x50 : 0x05);
1343                 break;
1344         case SWR_CLK_RATE_2P4MHZ:
1345                 val = (bank ? 0x30 : 0x03);
1346                 break;
1347         case SWR_CLK_RATE_4P8MHZ:
1348                 val = (bank ? 0x10 : 0x01);
1349                 break;
1350         case SWR_CLK_RATE_9P6MHZ:
1351         default:
1352                 val = 0x00;
1353                 break;
1354         }
1355         snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
1356                                       mask, val);
1357 
1358         return 0;
1359 }
1360 
1361 static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1362 {
1363         struct regmap *rm = wcd938x->regmap;
1364 
1365         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1366         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1367         /* 1 msec delay as per HW requirement */
1368         usleep_range(1000, 1010);
1369         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1370         /* 1 msec delay as per HW requirement */
1371         usleep_range(1000, 1010);
1372         regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1373         regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1374                                                                 0xF0, 0x80);
1375         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1376         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1377         /* 10 msec delay as per HW requirement */
1378         usleep_range(10000, 10010);
1379 
1380         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1381         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1382                                       0xF0, 0x00);
1383         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1384                                       0x1F, 0x15);
1385         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1386                                       0x1F, 0x15);
1387         regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1388                                       0xC0, 0x80);
1389         regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1390                                       0x02, 0x02);
1391 
1392         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1393                            0xFF, 0x14);
1394         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1395                            0x1F, 0x08);
1396 
1397         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1398         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1399         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1400         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1401         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1402 
1403         /* Set Noise Filter Resistor value */
1404         regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1405         regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1406         regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1407         regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1408 
1409         regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1410         regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1411 
1412         return 0;
1413 
1414 }
1415 
1416 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1417                                     struct sdw_port_config *port_config,
1418                                     u8 enable)
1419 {
1420         u8 ch_mask, port_num;
1421 
1422         port_num = ch_info->port_num;
1423         ch_mask = ch_info->ch_mask;
1424 
1425         port_config->num = port_num;
1426 
1427         if (enable)
1428                 port_config->ch_mask |= ch_mask;
1429         else
1430                 port_config->ch_mask &= ~ch_mask;
1431 
1432         return 0;
1433 }
1434 
1435 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
1436 {
1437         return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1438                                         &wcd->port_config[port_num - 1],
1439                                         enable);
1440 }
1441 
1442 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1443                                       struct snd_kcontrol *kcontrol,
1444                                       int event)
1445 {
1446         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1447 
1448         switch (event) {
1449         case SND_SOC_DAPM_PRE_PMU:
1450                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1451                                 WCD938X_ANA_RX_CLK_EN_MASK, 1);
1452                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1453                                 WCD938X_RX_BIAS_EN_MASK, 1);
1454                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1455                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1456                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1457                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1458                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1459                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1460                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1461                                 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1462                 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1463                                               WCD938X_AUXPA_CLK_EN_MASK, 1);
1464                 break;
1465         case SND_SOC_DAPM_POST_PMD:
1466                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1467                                 WCD938X_VNEG_EN_MASK, 0);
1468                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1469                                 WCD938X_VPOS_EN_MASK, 0);
1470                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1471                                 WCD938X_RX_BIAS_EN_MASK, 0);
1472                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1473                                 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1474                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1475                                 WCD938X_ANA_RX_CLK_EN_MASK, 0);
1476                 break;
1477         }
1478         return 0;
1479 }
1480 
1481 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1482                                         struct snd_kcontrol *kcontrol,
1483                                         int event)
1484 {
1485         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1486         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1487 
1488         switch (event) {
1489         case SND_SOC_DAPM_PRE_PMU:
1490                 snd_soc_component_write_field(component,
1491                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1492                                 WCD938X_RXD0_CLK_EN_MASK, 0x01);
1493                 snd_soc_component_write_field(component,
1494                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1495                                 WCD938X_HPHL_RX_EN_MASK, 1);
1496                 snd_soc_component_write_field(component,
1497                                 WCD938X_HPH_RDAC_CLK_CTL1,
1498                                 WCD938X_CHOP_CLK_EN_MASK, 0);
1499                 break;
1500         case SND_SOC_DAPM_POST_PMU:
1501                 snd_soc_component_write_field(component,
1502                                 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1503                                 WCD938X_HPH_RES_DIV_MASK, 0x02);
1504                 if (wcd938x->comp1_enable) {
1505                         snd_soc_component_write_field(component,
1506                                 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1507                                 WCD938X_HPHL_COMP_EN_MASK, 1);
1508                         /* 5msec compander delay as per HW requirement */
1509                         if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1510                                                          WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1511                                 usleep_range(5000, 5010);
1512                         snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1513                                               WCD938X_AUTOCHOP_TIMER_EN, 0);
1514                 } else {
1515                         snd_soc_component_write_field(component,
1516                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1517                                         WCD938X_HPHL_COMP_EN_MASK, 0);
1518                         snd_soc_component_write_field(component,
1519                                         WCD938X_HPH_L_EN,
1520                                         WCD938X_GAIN_SRC_SEL_MASK,
1521                                         WCD938X_GAIN_SRC_SEL_REGISTER);
1522 
1523                 }
1524                 break;
1525         case SND_SOC_DAPM_POST_PMD:
1526                 snd_soc_component_write_field(component,
1527                         WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1528                         WCD938X_HPH_RES_DIV_MASK, 0x1);
1529                 break;
1530         }
1531 
1532         return 0;
1533 }
1534 
1535 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1536                                         struct snd_kcontrol *kcontrol,
1537                                         int event)
1538 {
1539         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1540         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1541 
1542         switch (event) {
1543         case SND_SOC_DAPM_PRE_PMU:
1544                 snd_soc_component_write_field(component,
1545                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1546                                 WCD938X_RXD1_CLK_EN_MASK, 1);
1547                 snd_soc_component_write_field(component,
1548                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1549                                 WCD938X_HPHR_RX_EN_MASK, 1);
1550                 snd_soc_component_write_field(component,
1551                                 WCD938X_HPH_RDAC_CLK_CTL1,
1552                                 WCD938X_CHOP_CLK_EN_MASK, 0);
1553                 break;
1554         case SND_SOC_DAPM_POST_PMU:
1555                 snd_soc_component_write_field(component,
1556                                 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1557                                 WCD938X_HPH_RES_DIV_MASK, 0x02);
1558                 if (wcd938x->comp2_enable) {
1559                         snd_soc_component_write_field(component,
1560                                 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1561                                 WCD938X_HPHR_COMP_EN_MASK, 1);
1562                         /* 5msec compander delay as per HW requirement */
1563                         if (!wcd938x->comp1_enable ||
1564                                 (snd_soc_component_read(component,
1565                                         WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1566                                 usleep_range(5000, 5010);
1567                         snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1568                                               WCD938X_AUTOCHOP_TIMER_EN, 0);
1569                 } else {
1570                         snd_soc_component_write_field(component,
1571                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1572                                         WCD938X_HPHR_COMP_EN_MASK, 0);
1573                         snd_soc_component_write_field(component,
1574                                         WCD938X_HPH_R_EN,
1575                                         WCD938X_GAIN_SRC_SEL_MASK,
1576                                         WCD938X_GAIN_SRC_SEL_REGISTER);
1577                 }
1578                 break;
1579         case SND_SOC_DAPM_POST_PMD:
1580                 snd_soc_component_write_field(component,
1581                         WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1582                         WCD938X_HPH_RES_DIV_MASK, 0x01);
1583                 break;
1584         }
1585 
1586         return 0;
1587 }
1588 
1589 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1590                                        struct snd_kcontrol *kcontrol,
1591                                        int event)
1592 {
1593         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1594         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1595 
1596         switch (event) {
1597         case SND_SOC_DAPM_PRE_PMU:
1598                 wcd938x->ear_rx_path =
1599                         snd_soc_component_read(
1600                                 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1601                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1602                         snd_soc_component_write_field(component,
1603                                 WCD938X_EAR_EAR_DAC_CON,
1604                                 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1605                         snd_soc_component_write_field(component,
1606                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1607                                 WCD938X_AUX_EN_MASK, 1);
1608                         snd_soc_component_write_field(component,
1609                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1610                                 WCD938X_RXD2_CLK_EN_MASK, 1);
1611                         snd_soc_component_write_field(component,
1612                                 WCD938X_ANA_EAR_COMPANDER_CTL,
1613                                 WCD938X_GAIN_OVRD_REG_MASK, 1);
1614                 } else {
1615                         snd_soc_component_write_field(component,
1616                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1617                                 WCD938X_HPHL_RX_EN_MASK, 1);
1618                         snd_soc_component_write_field(component,
1619                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1620                                 WCD938X_RXD0_CLK_EN_MASK, 1);
1621                         if (wcd938x->comp1_enable)
1622                                 snd_soc_component_write_field(component,
1623                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1624                                         WCD938X_HPHL_COMP_EN_MASK, 1);
1625                 }
1626                 /* 5 msec delay as per HW requirement */
1627                 usleep_range(5000, 5010);
1628                 if (wcd938x->flyback_cur_det_disable == 0)
1629                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1630                                                       WCD938X_EN_CUR_DET_MASK, 0);
1631                 wcd938x->flyback_cur_det_disable++;
1632                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1633                              WCD_CLSH_EVENT_PRE_DAC,
1634                              WCD_CLSH_STATE_EAR,
1635                              wcd938x->hph_mode);
1636                 break;
1637         case SND_SOC_DAPM_POST_PMD:
1638                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1639                         snd_soc_component_write_field(component,
1640                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1641                                 WCD938X_AUX_EN_MASK, 0);
1642                         snd_soc_component_write_field(component,
1643                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1644                                 WCD938X_RXD2_CLK_EN_MASK, 0);
1645                 } else {
1646                         snd_soc_component_write_field(component,
1647                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1648                                 WCD938X_HPHL_RX_EN_MASK, 0);
1649                         snd_soc_component_write_field(component,
1650                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1651                                 WCD938X_RXD0_CLK_EN_MASK, 0);
1652                         if (wcd938x->comp1_enable)
1653                                 snd_soc_component_write_field(component,
1654                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1655                                         WCD938X_HPHL_COMP_EN_MASK, 0);
1656                 }
1657                 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1658                                               WCD938X_GAIN_OVRD_REG_MASK, 0);
1659                 snd_soc_component_write_field(component,
1660                                 WCD938X_EAR_EAR_DAC_CON,
1661                                 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1662                 break;
1663         }
1664         return 0;
1665 
1666 }
1667 
1668 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1669                                        struct snd_kcontrol *kcontrol,
1670                                        int event)
1671 {
1672         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1673         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1674 
1675         switch (event) {
1676         case SND_SOC_DAPM_PRE_PMU:
1677                 snd_soc_component_write_field(component,
1678                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1679                                 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1680                 snd_soc_component_write_field(component,
1681                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1682                                 WCD938X_RXD2_CLK_EN_MASK, 1);
1683                 snd_soc_component_write_field(component,
1684                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1685                                 WCD938X_AUX_EN_MASK, 1);
1686                 if (wcd938x->flyback_cur_det_disable == 0)
1687                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1688                                                       WCD938X_EN_CUR_DET_MASK, 0);
1689                 wcd938x->flyback_cur_det_disable++;
1690                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1691                              WCD_CLSH_EVENT_PRE_DAC,
1692                              WCD_CLSH_STATE_AUX,
1693                              wcd938x->hph_mode);
1694                 break;
1695         case SND_SOC_DAPM_POST_PMD:
1696                 snd_soc_component_write_field(component,
1697                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1698                                 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1699                 break;
1700         }
1701         return 0;
1702 
1703 }
1704 
1705 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1706                                         struct snd_kcontrol *kcontrol, int event)
1707 {
1708         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1709         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1710         int hph_mode = wcd938x->hph_mode;
1711 
1712         switch (event) {
1713         case SND_SOC_DAPM_PRE_PMU:
1714                 if (wcd938x->ldoh)
1715                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1716                                                       WCD938X_LDOH_EN_MASK, 1);
1717                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1718                                         WCD_CLSH_STATE_HPHR, hph_mode);
1719                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1720 
1721                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1722                     hph_mode == CLS_H_ULP) {
1723                         snd_soc_component_write_field(component,
1724                                 WCD938X_HPH_REFBUFF_LP_CTL,
1725                                 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1726                 }
1727                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1728                                               WCD938X_HPHR_REF_EN_MASK, 1);
1729                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1730                 /* 100 usec delay as per HW requirement */
1731                 usleep_range(100, 110);
1732                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1733                 snd_soc_component_write_field(component,
1734                                               WCD938X_DIGITAL_PDM_WD_CTL1,
1735                                               WCD938X_PDM_WD_EN_MASK, 0x3);
1736                 break;
1737         case SND_SOC_DAPM_POST_PMU:
1738                 /*
1739                  * 7ms sleep is required if compander is enabled as per
1740                  * HW requirement. If compander is disabled, then
1741                  * 20ms delay is required.
1742                  */
1743                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1744                         if (!wcd938x->comp2_enable)
1745                                 usleep_range(20000, 20100);
1746                         else
1747                                 usleep_range(7000, 7100);
1748 
1749                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1750                             hph_mode == CLS_H_ULP)
1751                                 snd_soc_component_write_field(component,
1752                                                 WCD938X_HPH_REFBUFF_LP_CTL,
1753                                                 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1754                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1755                 }
1756                 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1757                                               WCD938X_AUTOCHOP_TIMER_EN, 1);
1758                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1759                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1760                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1761                                         WCD938X_REGULATOR_MODE_MASK,
1762                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1763                 enable_irq(wcd938x->hphr_pdm_wd_int);
1764                 break;
1765         case SND_SOC_DAPM_PRE_PMD:
1766                 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1767                 /*
1768                  * 7ms sleep is required if compander is enabled as per
1769                  * HW requirement. If compander is disabled, then
1770                  * 20ms delay is required.
1771                  */
1772                 if (!wcd938x->comp2_enable)
1773                         usleep_range(20000, 20100);
1774                 else
1775                         usleep_range(7000, 7100);
1776                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1777                                               WCD938X_HPHR_EN_MASK, 0);
1778                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1779                                              WCD_EVENT_PRE_HPHR_PA_OFF);
1780                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1781                 break;
1782         case SND_SOC_DAPM_POST_PMD:
1783                 /*
1784                  * 7ms sleep is required if compander is enabled as per
1785                  * HW requirement. If compander is disabled, then
1786                  * 20ms delay is required.
1787                  */
1788                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1789                         if (!wcd938x->comp2_enable)
1790                                 usleep_range(20000, 20100);
1791                         else
1792                                 usleep_range(7000, 7100);
1793                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1794                 }
1795                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1796                                              WCD_EVENT_POST_HPHR_PA_OFF);
1797                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1798                                               WCD938X_HPHR_REF_EN_MASK, 0);
1799                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1800                                               WCD938X_PDM_WD_EN_MASK, 0);
1801                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1802                                         WCD_CLSH_STATE_HPHR, hph_mode);
1803                 if (wcd938x->ldoh)
1804                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1805                                                       WCD938X_LDOH_EN_MASK, 0);
1806                 break;
1807         }
1808 
1809         return 0;
1810 }
1811 
1812 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1813                                         struct snd_kcontrol *kcontrol, int event)
1814 {
1815         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1816         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1817         int hph_mode = wcd938x->hph_mode;
1818 
1819         switch (event) {
1820         case SND_SOC_DAPM_PRE_PMU:
1821                 if (wcd938x->ldoh)
1822                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1823                                                       WCD938X_LDOH_EN_MASK, 1);
1824                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1825                                         WCD_CLSH_STATE_HPHL, hph_mode);
1826                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1827                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1828                     hph_mode == CLS_H_ULP) {
1829                         snd_soc_component_write_field(component,
1830                                         WCD938X_HPH_REFBUFF_LP_CTL,
1831                                         WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1832                 }
1833                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1834                                               WCD938X_HPHL_REF_EN_MASK, 1);
1835                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1836                 /* 100 usec delay as per HW requirement */
1837                 usleep_range(100, 110);
1838                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1839                 snd_soc_component_write_field(component,
1840                                         WCD938X_DIGITAL_PDM_WD_CTL0,
1841                                         WCD938X_PDM_WD_EN_MASK, 0x3);
1842                 break;
1843         case SND_SOC_DAPM_POST_PMU:
1844                 /*
1845                  * 7ms sleep is required if compander is enabled as per
1846                  * HW requirement. If compander is disabled, then
1847                  * 20ms delay is required.
1848                  */
1849                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1850                         if (!wcd938x->comp1_enable)
1851                                 usleep_range(20000, 20100);
1852                         else
1853                                 usleep_range(7000, 7100);
1854                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1855                             hph_mode == CLS_H_ULP)
1856                                 snd_soc_component_write_field(component,
1857                                         WCD938X_HPH_REFBUFF_LP_CTL,
1858                                         WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1859                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1860                 }
1861 
1862                 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1863                                               WCD938X_AUTOCHOP_TIMER_EN, 1);
1864                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1865                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1866                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1867                                         WCD938X_REGULATOR_MODE_MASK,
1868                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1869                 enable_irq(wcd938x->hphl_pdm_wd_int);
1870                 break;
1871         case SND_SOC_DAPM_PRE_PMD:
1872                 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1873                 /*
1874                  * 7ms sleep is required if compander is enabled as per
1875                  * HW requirement. If compander is disabled, then
1876                  * 20ms delay is required.
1877                  */
1878                 if (!wcd938x->comp1_enable)
1879                         usleep_range(20000, 20100);
1880                 else
1881                         usleep_range(7000, 7100);
1882                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1883                                               WCD938X_HPHL_EN_MASK, 0);
1884                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
1885                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1886                 break;
1887         case SND_SOC_DAPM_POST_PMD:
1888                 /*
1889                  * 7ms sleep is required if compander is enabled as per
1890                  * HW requirement. If compander is disabled, then
1891                  * 20ms delay is required.
1892                  */
1893                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1894                         if (!wcd938x->comp1_enable)
1895                                 usleep_range(21000, 21100);
1896                         else
1897                                 usleep_range(7000, 7100);
1898                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1899                 }
1900                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1901                                              WCD_EVENT_POST_HPHL_PA_OFF);
1902                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1903                                               WCD938X_HPHL_REF_EN_MASK, 0);
1904                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1905                                               WCD938X_PDM_WD_EN_MASK, 0);
1906                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1907                                         WCD_CLSH_STATE_HPHL, hph_mode);
1908                 if (wcd938x->ldoh)
1909                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1910                                                       WCD938X_LDOH_EN_MASK, 0);
1911                 break;
1912         }
1913 
1914         return 0;
1915 }
1916 
1917 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1918                                        struct snd_kcontrol *kcontrol, int event)
1919 {
1920         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1921         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1922         int hph_mode = wcd938x->hph_mode;
1923 
1924         switch (event) {
1925         case SND_SOC_DAPM_PRE_PMU:
1926                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1927                                               WCD938X_AUX_PDM_WD_EN_MASK, 1);
1928                 break;
1929         case SND_SOC_DAPM_POST_PMU:
1930                 /* 1 msec delay as per HW requirement */
1931                 usleep_range(1000, 1010);
1932                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1933                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1934                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1935                                         WCD938X_REGULATOR_MODE_MASK,
1936                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1937                 enable_irq(wcd938x->aux_pdm_wd_int);
1938                 break;
1939         case SND_SOC_DAPM_PRE_PMD:
1940                 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1941                 break;
1942         case SND_SOC_DAPM_POST_PMD:
1943                 /* 1 msec delay as per HW requirement */
1944                 usleep_range(1000, 1010);
1945                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1946                                               WCD938X_AUX_PDM_WD_EN_MASK, 0);
1947                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1948                              WCD_CLSH_EVENT_POST_PA,
1949                              WCD_CLSH_STATE_AUX,
1950                              hph_mode);
1951 
1952                 wcd938x->flyback_cur_det_disable--;
1953                 if (wcd938x->flyback_cur_det_disable == 0)
1954                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1955                                                       WCD938X_EN_CUR_DET_MASK, 1);
1956                 break;
1957         }
1958         return 0;
1959 }
1960 
1961 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1962                                        struct snd_kcontrol *kcontrol, int event)
1963 {
1964         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1965         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1966         int hph_mode = wcd938x->hph_mode;
1967 
1968         switch (event) {
1969         case SND_SOC_DAPM_PRE_PMU:
1970                 /*
1971                  * Enable watchdog interrupt for HPHL or AUX
1972                  * depending on mux value
1973                  */
1974                 wcd938x->ear_rx_path = snd_soc_component_read(component,
1975                                                               WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1976                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1977                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1978                                               WCD938X_AUX_PDM_WD_EN_MASK, 1);
1979                 else
1980                         snd_soc_component_write_field(component,
1981                                                       WCD938X_DIGITAL_PDM_WD_CTL0,
1982                                                       WCD938X_PDM_WD_EN_MASK, 0x3);
1983                 if (!wcd938x->comp1_enable)
1984                         snd_soc_component_write_field(component,
1985                                                       WCD938X_ANA_EAR_COMPANDER_CTL,
1986                                                       WCD938X_GAIN_OVRD_REG_MASK, 1);
1987 
1988                 break;
1989         case SND_SOC_DAPM_POST_PMU:
1990                 /* 6 msec delay as per HW requirement */
1991                 usleep_range(6000, 6010);
1992                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1993                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1994                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1995                                         WCD938X_REGULATOR_MODE_MASK,
1996                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1997                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1998                         enable_irq(wcd938x->aux_pdm_wd_int);
1999                 else
2000                         enable_irq(wcd938x->hphl_pdm_wd_int);
2001                 break;
2002         case SND_SOC_DAPM_PRE_PMD:
2003                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2004                         disable_irq_nosync(wcd938x->aux_pdm_wd_int);
2005                 else
2006                         disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
2007                 break;
2008         case SND_SOC_DAPM_POST_PMD:
2009                 if (!wcd938x->comp1_enable)
2010                         snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2011                                                       WCD938X_GAIN_OVRD_REG_MASK, 0);
2012                 /* 7 msec delay as per HW requirement */
2013                 usleep_range(7000, 7010);
2014                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2015                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
2016                                               WCD938X_AUX_PDM_WD_EN_MASK, 0);
2017                 else
2018                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
2019                                         WCD938X_PDM_WD_EN_MASK, 0);
2020 
2021                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
2022                                         WCD_CLSH_STATE_EAR, hph_mode);
2023 
2024                 wcd938x->flyback_cur_det_disable--;
2025                 if (wcd938x->flyback_cur_det_disable == 0)
2026                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
2027                                                       WCD938X_EN_CUR_DET_MASK, 1);
2028                 break;
2029         }
2030 
2031         return 0;
2032 }
2033 
2034 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2035                                      struct snd_kcontrol *kcontrol,
2036                                      int event)
2037 {
2038         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2039         u16 dmic_clk_reg, dmic_clk_en_reg;
2040         u8 dmic_sel_mask, dmic_clk_mask;
2041 
2042         switch (w->shift) {
2043         case 0:
2044         case 1:
2045                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2046                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
2047                 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
2048                 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
2049                 break;
2050         case 2:
2051         case 3:
2052                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2053                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
2054                 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
2055                 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
2056                 break;
2057         case 4:
2058         case 5:
2059                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2060                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
2061                 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
2062                 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
2063                 break;
2064         case 6:
2065         case 7:
2066                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2067                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
2068                 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
2069                 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
2070                 break;
2071         default:
2072                 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
2073                         __func__);
2074                 return -EINVAL;
2075         }
2076 
2077         switch (event) {
2078         case SND_SOC_DAPM_PRE_PMU:
2079                 snd_soc_component_write_field(component,
2080                                 WCD938X_DIGITAL_CDC_AMIC_CTL,
2081                                 dmic_sel_mask,
2082                                 WCD938X_AMIC1_IN_SEL_DMIC);
2083                 /* 250us sleep as per HW requirement */
2084                 usleep_range(250, 260);
2085                 /* Setting DMIC clock rate to 2.4MHz */
2086                 snd_soc_component_write_field(component, dmic_clk_reg,
2087                                               dmic_clk_mask,
2088                                               WCD938X_DMIC4_RATE_2P4MHZ);
2089                 snd_soc_component_write_field(component, dmic_clk_en_reg,
2090                                               WCD938X_DMIC_CLK_EN_MASK, 1);
2091                 /* enable clock scaling */
2092                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
2093                                               WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
2094                 break;
2095         case SND_SOC_DAPM_POST_PMD:
2096                 snd_soc_component_write_field(component,
2097                                 WCD938X_DIGITAL_CDC_AMIC_CTL,
2098                                 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
2099                 snd_soc_component_write_field(component, dmic_clk_en_reg,
2100                                               WCD938X_DMIC_CLK_EN_MASK, 0);
2101                 break;
2102         }
2103         return 0;
2104 }
2105 
2106 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
2107                                struct snd_kcontrol *kcontrol, int event)
2108 {
2109         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2110         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2111         int bank;
2112         int rate;
2113 
2114         bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
2115         bank = bank ? 0 : 1;
2116 
2117         switch (event) {
2118         case SND_SOC_DAPM_PRE_PMU:
2119                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2120                         int i = 0, mode = 0;
2121 
2122                         if (test_bit(WCD_ADC1, &wcd938x->status_mask))
2123                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
2124                         if (test_bit(WCD_ADC2, &wcd938x->status_mask))
2125                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
2126                         if (test_bit(WCD_ADC3, &wcd938x->status_mask))
2127                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
2128                         if (test_bit(WCD_ADC4, &wcd938x->status_mask))
2129                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
2130 
2131                         if (mode != 0) {
2132                                 for (i = 0; i < ADC_MODE_ULP2; i++) {
2133                                         if (mode & (1 << i)) {
2134                                                 i++;
2135                                                 break;
2136                                         }
2137                                 }
2138                         }
2139                         rate = wcd938x_get_clk_rate(i);
2140                         wcd938x_set_swr_clk_rate(component, rate, bank);
2141                         /* Copy clk settings to active bank */
2142                         wcd938x_set_swr_clk_rate(component, rate, !bank);
2143                 }
2144                 break;
2145         case SND_SOC_DAPM_POST_PMD:
2146                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2147                         rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
2148                         wcd938x_set_swr_clk_rate(component, rate, !bank);
2149                         wcd938x_set_swr_clk_rate(component, rate, bank);
2150                 }
2151                 break;
2152         }
2153 
2154         return 0;
2155 }
2156 
2157 static int wcd938x_get_adc_mode(int val)
2158 {
2159         int ret = 0;
2160 
2161         switch (val) {
2162         case ADC_MODE_INVALID:
2163                 ret = ADC_MODE_VAL_NORMAL;
2164                 break;
2165         case ADC_MODE_HIFI:
2166                 ret = ADC_MODE_VAL_HIFI;
2167                 break;
2168         case ADC_MODE_LO_HIF:
2169                 ret = ADC_MODE_VAL_LO_HIF;
2170                 break;
2171         case ADC_MODE_NORMAL:
2172                 ret = ADC_MODE_VAL_NORMAL;
2173                 break;
2174         case ADC_MODE_LP:
2175                 ret = ADC_MODE_VAL_LP;
2176                 break;
2177         case ADC_MODE_ULP1:
2178                 ret = ADC_MODE_VAL_ULP1;
2179                 break;
2180         case ADC_MODE_ULP2:
2181                 ret = ADC_MODE_VAL_ULP2;
2182                 break;
2183         default:
2184                 ret = -EINVAL;
2185                 break;
2186         }
2187         return ret;
2188 }
2189 
2190 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
2191                                     struct snd_kcontrol *kcontrol, int event)
2192 {
2193         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2194         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2195 
2196         switch (event) {
2197         case SND_SOC_DAPM_PRE_PMU:
2198                 snd_soc_component_write_field(component,
2199                                               WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2200                                               WCD938X_ANA_TX_CLK_EN_MASK, 1);
2201                 snd_soc_component_write_field(component,
2202                                               WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2203                                               WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2204                 set_bit(w->shift, &wcd938x->status_mask);
2205                 break;
2206         case SND_SOC_DAPM_POST_PMD:
2207                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2208                                               WCD938X_ANA_TX_CLK_EN_MASK, 0);
2209                 clear_bit(w->shift, &wcd938x->status_mask);
2210                 break;
2211         }
2212 
2213         return 0;
2214 }
2215 
2216 static void wcd938x_tx_channel_config(struct snd_soc_component *component,
2217                                      int channel, int mode)
2218 {
2219         int reg, mask;
2220 
2221         switch (channel) {
2222         case 0:
2223                 reg = WCD938X_ANA_TX_CH2;
2224                 mask = WCD938X_HPF1_INIT_MASK;
2225                 break;
2226         case 1:
2227                 reg = WCD938X_ANA_TX_CH2;
2228                 mask = WCD938X_HPF2_INIT_MASK;
2229                 break;
2230         case 2:
2231                 reg = WCD938X_ANA_TX_CH4;
2232                 mask = WCD938X_HPF3_INIT_MASK;
2233                 break;
2234         case 3:
2235                 reg = WCD938X_ANA_TX_CH4;
2236                 mask = WCD938X_HPF4_INIT_MASK;
2237                 break;
2238         default:
2239                 return;
2240         }
2241 
2242         snd_soc_component_write_field(component, reg, mask, mode);
2243 }
2244 
2245 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
2246                                   struct snd_kcontrol *kcontrol, int event)
2247 {
2248         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2249         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2250         int mode;
2251 
2252         switch (event) {
2253         case SND_SOC_DAPM_PRE_PMU:
2254                 snd_soc_component_write_field(component,
2255                                 WCD938X_DIGITAL_CDC_REQ_CTL,
2256                                 WCD938X_FS_RATE_4P8_MASK, 1);
2257                 snd_soc_component_write_field(component,
2258                                 WCD938X_DIGITAL_CDC_REQ_CTL,
2259                                 WCD938X_NO_NOTCH_MASK, 0);
2260                 wcd938x_tx_channel_config(component, w->shift, 1);
2261                 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
2262                 if (mode < 0) {
2263                         dev_info(component->dev, "Invalid ADC mode\n");
2264                         return -EINVAL;
2265                 }
2266                 switch (w->shift) {
2267                 case 0:
2268                         snd_soc_component_write_field(component,
2269                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2270                                 WCD938X_TXD0_MODE_MASK, mode);
2271                         snd_soc_component_write_field(component,
2272                                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2273                                                 WCD938X_TXD0_CLK_EN_MASK, 1);
2274                         break;
2275                 case 1:
2276                         snd_soc_component_write_field(component,
2277                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2278                                 WCD938X_TXD1_MODE_MASK, mode);
2279                         snd_soc_component_write_field(component,
2280                                               WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2281                                               WCD938X_TXD1_CLK_EN_MASK, 1);
2282                         break;
2283                 case 2:
2284                         snd_soc_component_write_field(component,
2285                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2286                                 WCD938X_TXD2_MODE_MASK, mode);
2287                         snd_soc_component_write_field(component,
2288                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2289                                 WCD938X_TXD2_CLK_EN_MASK, 1);
2290                         break;
2291                 case 3:
2292                         snd_soc_component_write_field(component,
2293                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2294                                 WCD938X_TXD3_MODE_MASK, mode);
2295                         snd_soc_component_write_field(component,
2296                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2297                                 WCD938X_TXD3_CLK_EN_MASK, 1);
2298                         break;
2299                 default:
2300                         break;
2301                 }
2302 
2303                 wcd938x_tx_channel_config(component, w->shift, 0);
2304                 break;
2305         case SND_SOC_DAPM_POST_PMD:
2306                 switch (w->shift) {
2307                 case 0:
2308                         snd_soc_component_write_field(component,
2309                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2310                                 WCD938X_TXD0_MODE_MASK, 0);
2311                         snd_soc_component_write_field(component,
2312                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2313                                 WCD938X_TXD0_CLK_EN_MASK, 0);
2314                         break;
2315                 case 1:
2316                         snd_soc_component_write_field(component,
2317                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2318                                 WCD938X_TXD1_MODE_MASK, 0);
2319                         snd_soc_component_write_field(component,
2320                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2321                                 WCD938X_TXD1_CLK_EN_MASK, 0);
2322                         break;
2323                 case 2:
2324                         snd_soc_component_write_field(component,
2325                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2326                                 WCD938X_TXD2_MODE_MASK, 0);
2327                         snd_soc_component_write_field(component,
2328                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2329                                 WCD938X_TXD2_CLK_EN_MASK, 0);
2330                         break;
2331                 case 3:
2332                         snd_soc_component_write_field(component,
2333                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2334                                 WCD938X_TXD3_MODE_MASK, 0);
2335                         snd_soc_component_write_field(component,
2336                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2337                                 WCD938X_TXD3_CLK_EN_MASK, 0);
2338                         break;
2339                 default:
2340                         break;
2341                 }
2342                 snd_soc_component_write_field(component,
2343                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2344                                 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
2345                 break;
2346         }
2347 
2348         return 0;
2349 }
2350 
2351 static int wcd938x_micbias_control(struct snd_soc_component *component,
2352                                    int micb_num, int req, bool is_dapm)
2353 {
2354         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2355         int micb_index = micb_num - 1;
2356         u16 micb_reg;
2357 
2358         switch (micb_num) {
2359         case MIC_BIAS_1:
2360                 micb_reg = WCD938X_ANA_MICB1;
2361                 break;
2362         case MIC_BIAS_2:
2363                 micb_reg = WCD938X_ANA_MICB2;
2364                 break;
2365         case MIC_BIAS_3:
2366                 micb_reg = WCD938X_ANA_MICB3;
2367                 break;
2368         case MIC_BIAS_4:
2369                 micb_reg = WCD938X_ANA_MICB4;
2370                 break;
2371         default:
2372                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2373                         __func__, micb_num);
2374                 return -EINVAL;
2375         }
2376 
2377         switch (req) {
2378         case MICB_PULLUP_ENABLE:
2379                 wcd938x->pullup_ref[micb_index]++;
2380                 if ((wcd938x->pullup_ref[micb_index] == 1) &&
2381                     (wcd938x->micb_ref[micb_index] == 0))
2382                         snd_soc_component_write_field(component, micb_reg,
2383                                                       WCD938X_MICB_EN_MASK,
2384                                                       WCD938X_MICB_PULL_UP);
2385                 break;
2386         case MICB_PULLUP_DISABLE:
2387                 if (wcd938x->pullup_ref[micb_index] > 0)
2388                         wcd938x->pullup_ref[micb_index]--;
2389 
2390                 if ((wcd938x->pullup_ref[micb_index] == 0) &&
2391                     (wcd938x->micb_ref[micb_index] == 0))
2392                         snd_soc_component_write_field(component, micb_reg,
2393                                                       WCD938X_MICB_EN_MASK, 0);
2394                 break;
2395         case MICB_ENABLE:
2396                 wcd938x->micb_ref[micb_index]++;
2397                 if (wcd938x->micb_ref[micb_index] == 1) {
2398                         snd_soc_component_write_field(component,
2399                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2400                                 WCD938X_TX_CLK_EN_MASK, 0xF);
2401                         snd_soc_component_write_field(component,
2402                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2403                                 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2404                         snd_soc_component_write_field(component,
2405                                WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
2406                                WCD938X_TX_SC_CLK_EN_MASK, 1);
2407 
2408                         snd_soc_component_write_field(component, micb_reg,
2409                                                       WCD938X_MICB_EN_MASK,
2410                                                       WCD938X_MICB_ENABLE);
2411                         if (micb_num  == MIC_BIAS_2)
2412                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2413                                                       WCD_EVENT_POST_MICBIAS_2_ON);
2414                 }
2415                 if (micb_num  == MIC_BIAS_2 && is_dapm)
2416                         wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2417                                               WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2418 
2419 
2420                 break;
2421         case MICB_DISABLE:
2422                 if (wcd938x->micb_ref[micb_index] > 0)
2423                         wcd938x->micb_ref[micb_index]--;
2424 
2425                 if ((wcd938x->micb_ref[micb_index] == 0) &&
2426                     (wcd938x->pullup_ref[micb_index] > 0))
2427                         snd_soc_component_write_field(component, micb_reg,
2428                                                       WCD938X_MICB_EN_MASK,
2429                                                       WCD938X_MICB_PULL_UP);
2430                 else if ((wcd938x->micb_ref[micb_index] == 0) &&
2431                          (wcd938x->pullup_ref[micb_index] == 0)) {
2432                         if (micb_num  == MIC_BIAS_2)
2433                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2434                                                       WCD_EVENT_PRE_MICBIAS_2_OFF);
2435 
2436                         snd_soc_component_write_field(component, micb_reg,
2437                                                       WCD938X_MICB_EN_MASK, 0);
2438                         if (micb_num  == MIC_BIAS_2)
2439                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2440                                                       WCD_EVENT_POST_MICBIAS_2_OFF);
2441                 }
2442                 if (is_dapm && micb_num  == MIC_BIAS_2)
2443                         wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2444                                               WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2445                 break;
2446         }
2447 
2448         return 0;
2449 }
2450 
2451 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2452                                         struct snd_kcontrol *kcontrol,
2453                                         int event)
2454 {
2455         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2456         int micb_num = w->shift;
2457 
2458         switch (event) {
2459         case SND_SOC_DAPM_PRE_PMU:
2460                 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
2461                 break;
2462         case SND_SOC_DAPM_POST_PMU:
2463                 /* 1 msec delay as per HW requirement */
2464                 usleep_range(1000, 1100);
2465                 break;
2466         case SND_SOC_DAPM_POST_PMD:
2467                 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
2468                 break;
2469         }
2470 
2471         return 0;
2472 }
2473 
2474 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
2475                                                struct snd_kcontrol *kcontrol,
2476                                                int event)
2477 {
2478         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2479         int micb_num = w->shift;
2480 
2481         switch (event) {
2482         case SND_SOC_DAPM_PRE_PMU:
2483                 wcd938x_micbias_control(component, micb_num,
2484                                         MICB_PULLUP_ENABLE, true);
2485                 break;
2486         case SND_SOC_DAPM_POST_PMU:
2487                 /* 1 msec delay as per HW requirement */
2488                 usleep_range(1000, 1100);
2489                 break;
2490         case SND_SOC_DAPM_POST_PMD:
2491                 wcd938x_micbias_control(component, micb_num,
2492                                         MICB_PULLUP_DISABLE, true);
2493                 break;
2494         }
2495 
2496         return 0;
2497 }
2498 
2499 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
2500                                struct snd_ctl_elem_value *ucontrol)
2501 {
2502         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2503         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2504         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2505         int path = e->shift_l;
2506 
2507         ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path];
2508 
2509         return 0;
2510 }
2511 
2512 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
2513                                struct snd_ctl_elem_value *ucontrol)
2514 {
2515         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2516         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2517         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2518         int path = e->shift_l;
2519 
2520         wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
2521 
2522         return 1;
2523 }
2524 
2525 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
2526                                  struct snd_ctl_elem_value *ucontrol)
2527 {
2528         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2529         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2530 
2531         ucontrol->value.enumerated.item[0] = wcd938x->hph_mode;
2532 
2533         return 0;
2534 }
2535 
2536 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
2537                                    struct snd_ctl_elem_value *ucontrol)
2538 {
2539         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2540         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2541 
2542         wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
2543 
2544         return 1;
2545 }
2546 
2547 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
2548                                    struct snd_ctl_elem_value *ucontrol)
2549 {
2550         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2551         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2552 
2553         if (wcd938x->comp1_enable) {
2554                 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
2555                 return -EINVAL;
2556         }
2557 
2558         snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2559                                       WCD938X_EAR_GAIN_MASK,
2560                                       ucontrol->value.integer.value[0]);
2561 
2562         return 1;
2563 }
2564 
2565 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
2566                                  struct snd_ctl_elem_value *ucontrol)
2567 {
2568 
2569         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2570         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2571         struct soc_mixer_control *mc;
2572         bool hphr;
2573 
2574         mc = (struct soc_mixer_control *)(kcontrol->private_value);
2575         hphr = mc->shift;
2576 
2577         if (hphr)
2578                 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
2579         else
2580                 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2581 
2582         return 0;
2583 }
2584 
2585 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2586                                  struct snd_ctl_elem_value *ucontrol)
2587 {
2588         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2589         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2590         struct wcd938x_sdw_priv *wcd;
2591         int value = ucontrol->value.integer.value[0];
2592         int portidx;
2593         struct soc_mixer_control *mc;
2594         bool hphr;
2595 
2596         mc = (struct soc_mixer_control *)(kcontrol->private_value);
2597         hphr = mc->shift;
2598 
2599         wcd = wcd938x->sdw_priv[AIF1_PB];
2600 
2601         if (hphr)
2602                 wcd938x->comp2_enable = value;
2603         else
2604                 wcd938x->comp1_enable = value;
2605 
2606         portidx = wcd->ch_info[mc->reg].port_num;
2607 
2608         if (value)
2609                 wcd938x_connect_port(wcd, portidx, mc->reg, true);
2610         else
2611                 wcd938x_connect_port(wcd, portidx, mc->reg, false);
2612 
2613         return 1;
2614 }
2615 
2616 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2617                             struct snd_ctl_elem_value *ucontrol)
2618 {
2619         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2620         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2621 
2622         ucontrol->value.integer.value[0] = wcd938x->ldoh;
2623 
2624         return 0;
2625 }
2626 
2627 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2628                             struct snd_ctl_elem_value *ucontrol)
2629 {
2630         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2631         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2632 
2633         wcd938x->ldoh = ucontrol->value.integer.value[0];
2634 
2635         return 1;
2636 }
2637 
2638 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2639                            struct snd_ctl_elem_value *ucontrol)
2640 {
2641         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2642         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2643 
2644         ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2645 
2646         return 0;
2647 }
2648 
2649 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2650                            struct snd_ctl_elem_value *ucontrol)
2651 {
2652         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2653         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2654 
2655         wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2656 
2657         return 1;
2658 }
2659 
2660 static const char * const tx_mode_mux_text_wcd9380[] = {
2661         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2662 };
2663 
2664 static const char * const tx_mode_mux_text[] = {
2665         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2666         "ADC_ULP1", "ADC_ULP2",
2667 };
2668 
2669 static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2670         "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2671         "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2672         "CLS_AB_LOHIFI",
2673 };
2674 
2675 static const char * const rx_hph_mode_mux_text[] = {
2676         "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2677         "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2678 };
2679 
2680 static const char * const adc2_mux_text[] = {
2681         "INP2", "INP3"
2682 };
2683 
2684 static const char * const adc3_mux_text[] = {
2685         "INP4", "INP6"
2686 };
2687 
2688 static const char * const adc4_mux_text[] = {
2689         "INP5", "INP7"
2690 };
2691 
2692 static const char * const rdac3_mux_text[] = {
2693         "RX1", "RX3"
2694 };
2695 
2696 static const char * const hdr12_mux_text[] = {
2697         "NO_HDR12", "HDR12"
2698 };
2699 
2700 static const char * const hdr34_mux_text[] = {
2701         "NO_HDR34", "HDR34"
2702 };
2703 
2704 static const struct soc_enum tx0_mode_enum_wcd9380 =
2705         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2706                         tx_mode_mux_text_wcd9380);
2707 
2708 static const struct soc_enum tx1_mode_enum_wcd9380 =
2709         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2710                         tx_mode_mux_text_wcd9380);
2711 
2712 static const struct soc_enum tx2_mode_enum_wcd9380 =
2713         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2714                         tx_mode_mux_text_wcd9380);
2715 
2716 static const struct soc_enum tx3_mode_enum_wcd9380 =
2717         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2718                         tx_mode_mux_text_wcd9380);
2719 
2720 static const struct soc_enum tx0_mode_enum_wcd9385 =
2721         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2722                         tx_mode_mux_text);
2723 
2724 static const struct soc_enum tx1_mode_enum_wcd9385 =
2725         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2726                         tx_mode_mux_text);
2727 
2728 static const struct soc_enum tx2_mode_enum_wcd9385 =
2729         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2730                         tx_mode_mux_text);
2731 
2732 static const struct soc_enum tx3_mode_enum_wcd9385 =
2733         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2734                         tx_mode_mux_text);
2735 
2736 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2737                 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2738                                     rx_hph_mode_mux_text_wcd9380);
2739 
2740 static const struct soc_enum rx_hph_mode_mux_enum =
2741                 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2742                                     rx_hph_mode_mux_text);
2743 
2744 static const struct soc_enum adc2_enum =
2745                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
2746                                 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2747 
2748 static const struct soc_enum adc3_enum =
2749                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
2750                                 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
2751 
2752 static const struct soc_enum adc4_enum =
2753                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
2754                                 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
2755 
2756 static const struct soc_enum hdr12_enum =
2757                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
2758                                 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
2759 
2760 static const struct soc_enum hdr34_enum =
2761                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
2762                                 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
2763 
2764 static const struct soc_enum rdac3_enum =
2765                 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2766                                 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2767 
2768 static const struct snd_kcontrol_new adc1_switch[] = {
2769         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2770 };
2771 
2772 static const struct snd_kcontrol_new adc2_switch[] = {
2773         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2774 };
2775 
2776 static const struct snd_kcontrol_new adc3_switch[] = {
2777         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2778 };
2779 
2780 static const struct snd_kcontrol_new adc4_switch[] = {
2781         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2782 };
2783 
2784 static const struct snd_kcontrol_new dmic1_switch[] = {
2785         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2786 };
2787 
2788 static const struct snd_kcontrol_new dmic2_switch[] = {
2789         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2790 };
2791 
2792 static const struct snd_kcontrol_new dmic3_switch[] = {
2793         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2794 };
2795 
2796 static const struct snd_kcontrol_new dmic4_switch[] = {
2797         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2798 };
2799 
2800 static const struct snd_kcontrol_new dmic5_switch[] = {
2801         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2802 };
2803 
2804 static const struct snd_kcontrol_new dmic6_switch[] = {
2805         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2806 };
2807 
2808 static const struct snd_kcontrol_new dmic7_switch[] = {
2809         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2810 };
2811 
2812 static const struct snd_kcontrol_new dmic8_switch[] = {
2813         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2814 };
2815 
2816 static const struct snd_kcontrol_new ear_rdac_switch[] = {
2817         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2818 };
2819 
2820 static const struct snd_kcontrol_new aux_rdac_switch[] = {
2821         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2822 };
2823 
2824 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2825         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2826 };
2827 
2828 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2829         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2830 };
2831 
2832 static const struct snd_kcontrol_new tx_adc2_mux =
2833         SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2834 
2835 static const struct snd_kcontrol_new tx_adc3_mux =
2836         SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
2837 
2838 static const struct snd_kcontrol_new tx_adc4_mux =
2839         SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
2840 
2841 static const struct snd_kcontrol_new tx_hdr12_mux =
2842         SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
2843 
2844 static const struct snd_kcontrol_new tx_hdr34_mux =
2845         SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
2846 
2847 static const struct snd_kcontrol_new rx_rdac3_mux =
2848         SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2849 
2850 static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2851         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2852                      wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2853         SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2854                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2855         SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2856                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2857         SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2858                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2859         SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2860                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2861 };
2862 
2863 static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2864         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2865                      wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2866         SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2867                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2868         SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2869                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2870         SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2871                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2872         SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2873                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2874 };
2875 
2876 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2877                             struct snd_ctl_elem_value *ucontrol)
2878 {
2879         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2880         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2881         struct wcd938x_sdw_priv *wcd;
2882         struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2883         int dai_id = mixer->shift;
2884         int portidx, ch_idx = mixer->reg;
2885 
2886 
2887         wcd = wcd938x->sdw_priv[dai_id];
2888         portidx = wcd->ch_info[ch_idx].port_num;
2889 
2890         ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2891 
2892         return 0;
2893 }
2894 
2895 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2896                             struct snd_ctl_elem_value *ucontrol)
2897 {
2898         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2899         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2900         struct wcd938x_sdw_priv *wcd;
2901         struct soc_mixer_control *mixer =
2902                 (struct soc_mixer_control *)kcontrol->private_value;
2903         int ch_idx = mixer->reg;
2904         int portidx;
2905         int dai_id = mixer->shift;
2906         bool enable;
2907 
2908         wcd = wcd938x->sdw_priv[dai_id];
2909 
2910         portidx = wcd->ch_info[ch_idx].port_num;
2911         if (ucontrol->value.integer.value[0])
2912                 enable = true;
2913         else
2914                 enable = false;
2915 
2916         wcd->port_enable[portidx] = enable;
2917 
2918         wcd938x_connect_port(wcd, portidx, ch_idx, enable);
2919 
2920         return 1;
2921 
2922 }
2923 
2924 /* MBHC related */
2925 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
2926                                    bool enable)
2927 {
2928         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
2929                                       WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
2930 }
2931 
2932 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2933                                            bool enable)
2934 {
2935         snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
2936                                       WCD938X_ANA_MBHC_BIAS_EN, enable);
2937 }
2938 
2939 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
2940                                          int *btn_low, int *btn_high,
2941                                          int num_btn, bool is_micbias)
2942 {
2943         int i, vth;
2944 
2945         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2946                 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2947                         __func__, num_btn);
2948                 return;
2949         }
2950 
2951         for (i = 0; i < num_btn; i++) {
2952                 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2953                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
2954                                            WCD938X_MBHC_BTN_VTH_MASK, vth);
2955                 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
2956                         __func__, i, btn_high[i], vth);
2957         }
2958 }
2959 
2960 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2961 {
2962         u8 val;
2963 
2964         if (micb_num == MIC_BIAS_2) {
2965                 val = snd_soc_component_read_field(component,
2966                                                    WCD938X_ANA_MICB2,
2967                                                    WCD938X_ANA_MICB2_ENABLE_MASK);
2968                 if (val == WCD938X_MICB_ENABLE)
2969                         return true;
2970         }
2971         return false;
2972 }
2973 
2974 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2975                                                         int pull_up_cur)
2976 {
2977         /* Default pull up current to 2uA */
2978         if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
2979                 pull_up_cur = HS_PULLUP_I_2P0_UA;
2980 
2981         snd_soc_component_write_field(component,
2982                                       WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
2983                                       WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
2984 }
2985 
2986 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
2987                                         int micb_num, int req)
2988 {
2989         return wcd938x_micbias_control(component, micb_num, req, false);
2990 }
2991 
2992 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2993                                            bool enable)
2994 {
2995         if (enable) {
2996                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
2997                                     WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
2998                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
2999                                     WCD938X_RAMP_EN_MASK, 1);
3000         } else {
3001                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3002                                     WCD938X_RAMP_EN_MASK, 0);
3003                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3004                                     WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
3005         }
3006 }
3007 
3008 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3009 {
3010         /* min micbias voltage is 1V and maximum is 2.85V */
3011         if (micb_mv < 1000 || micb_mv > 2850)
3012                 return -EINVAL;
3013 
3014         return (micb_mv - 1000) / 50;
3015 }
3016 
3017 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
3018                                             int req_volt, int micb_num)
3019 {
3020         struct wcd938x_priv *wcd938x =  snd_soc_component_get_drvdata(component);
3021         int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
3022 
3023         switch (micb_num) {
3024         case MIC_BIAS_1:
3025                 micb_reg = WCD938X_ANA_MICB1;
3026                 break;
3027         case MIC_BIAS_2:
3028                 micb_reg = WCD938X_ANA_MICB2;
3029                 break;
3030         case MIC_BIAS_3:
3031                 micb_reg = WCD938X_ANA_MICB3;
3032                 break;
3033         case MIC_BIAS_4:
3034                 micb_reg = WCD938X_ANA_MICB4;
3035                 break;
3036         default:
3037                 return -EINVAL;
3038         }
3039         mutex_lock(&wcd938x->micb_lock);
3040         /*
3041          * If requested micbias voltage is same as current micbias
3042          * voltage, then just return. Otherwise, adjust voltage as
3043          * per requested value. If micbias is already enabled, then
3044          * to avoid slow micbias ramp-up or down enable pull-up
3045          * momentarily, change the micbias value and then re-enable
3046          * micbias.
3047          */
3048         micb_en = snd_soc_component_read_field(component, micb_reg,
3049                                                 WCD938X_MICB_EN_MASK);
3050         cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
3051                                                     WCD938X_MICB_VOUT_MASK);
3052 
3053         req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
3054         if (req_vout_ctl < 0) {
3055                 ret = -EINVAL;
3056                 goto exit;
3057         }
3058 
3059         if (cur_vout_ctl == req_vout_ctl) {
3060                 ret = 0;
3061                 goto exit;
3062         }
3063 
3064         if (micb_en == WCD938X_MICB_ENABLE)
3065                 snd_soc_component_write_field(component, micb_reg,
3066                                               WCD938X_MICB_EN_MASK,
3067                                               WCD938X_MICB_PULL_UP);
3068 
3069         snd_soc_component_write_field(component, micb_reg,
3070                                       WCD938X_MICB_VOUT_MASK,
3071                                       req_vout_ctl);
3072 
3073         if (micb_en == WCD938X_MICB_ENABLE) {
3074                 snd_soc_component_write_field(component, micb_reg,
3075                                               WCD938X_MICB_EN_MASK,
3076                                               WCD938X_MICB_ENABLE);
3077                 /*
3078                  * Add 2ms delay as per HW requirement after enabling
3079                  * micbias
3080                  */
3081                 usleep_range(2000, 2100);
3082         }
3083 exit:
3084         mutex_unlock(&wcd938x->micb_lock);
3085         return ret;
3086 }
3087 
3088 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
3089                                                 int micb_num, bool req_en)
3090 {
3091         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3092         int rc, micb_mv;
3093 
3094         if (micb_num != MIC_BIAS_2)
3095                 return -EINVAL;
3096         /*
3097          * If device tree micbias level is already above the minimum
3098          * voltage needed to detect threshold microphone, then do
3099          * not change the micbias, just return.
3100          */
3101         if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
3102                 return 0;
3103 
3104         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
3105 
3106         rc = wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
3107 
3108         return rc;
3109 }
3110 
3111 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x,
3112                                                 s16 *d1_a, u16 noff,
3113                                                 int32_t *zdet)
3114 {
3115         int i;
3116         int val, val1;
3117         s16 c1;
3118         s32 x1, d1;
3119         int32_t denom;
3120         int minCode_param[] = {
3121                         3277, 1639, 820, 410, 205, 103, 52, 26
3122         };
3123 
3124         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
3125         for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
3126                 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
3127                 if (val & 0x80)
3128                         break;
3129         }
3130         val = val << 0x8;
3131         regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
3132         val |= val1;
3133         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
3134         x1 = WCD938X_MBHC_GET_X1(val);
3135         c1 = WCD938X_MBHC_GET_C1(val);
3136         /* If ramp is not complete, give additional 5ms */
3137         if ((c1 < 2) && x1)
3138                 usleep_range(5000, 5050);
3139 
3140         if (!c1 || !x1) {
3141                 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
3142                         __func__, c1, x1);
3143                 goto ramp_down;
3144         }
3145         d1 = d1_a[c1];
3146         denom = (x1 * d1) - (1 << (14 - noff));
3147         if (denom > 0)
3148                 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom;
3149         else if (x1 < minCode_param[noff])
3150                 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
3151 
3152         pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
3153                 __func__, d1, c1, x1, *zdet);
3154 ramp_down:
3155         i = 0;
3156         while (x1) {
3157                 regmap_read(wcd938x->regmap,
3158                                  WCD938X_ANA_MBHC_RESULT_1, &val);
3159                 regmap_read(wcd938x->regmap,
3160                                  WCD938X_ANA_MBHC_RESULT_2, &val1);
3161                 val = val << 0x08;
3162                 val |= val1;
3163                 x1 = WCD938X_MBHC_GET_X1(val);
3164                 i++;
3165                 if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
3166                         break;
3167         }
3168 }
3169 
3170 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
3171                                  struct wcd938x_mbhc_zdet_param *zdet_param,
3172                                  int32_t *zl, int32_t *zr, s16 *d1_a)
3173 {
3174         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3175         int32_t zdet = 0;
3176 
3177         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3178                                 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
3179         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
3180                                     WCD938X_VTH_MASK, zdet_param->btn5);
3181         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
3182                                       WCD938X_VTH_MASK, zdet_param->btn6);
3183         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
3184                                      WCD938X_VTH_MASK, zdet_param->btn7);
3185         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3186                                 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
3187         snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
3188                                 0x0F, zdet_param->nshift);
3189 
3190         if (!zl)
3191                 goto z_right;
3192         /* Start impedance measurement for HPH_L */
3193         regmap_update_bits(wcd938x->regmap,
3194                            WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
3195         dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
3196                 __func__, zdet_param->noff);
3197         wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3198         regmap_update_bits(wcd938x->regmap,
3199                            WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
3200 
3201         *zl = zdet;
3202 
3203 z_right:
3204         if (!zr)
3205                 return;
3206         /* Start impedance measurement for HPH_R */
3207         regmap_update_bits(wcd938x->regmap,
3208                            WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
3209         dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
3210                 __func__, zdet_param->noff);
3211         wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3212         regmap_update_bits(wcd938x->regmap,
3213                            WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
3214 
3215         *zr = zdet;
3216 }
3217 
3218 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
3219                                               int32_t *z_val, int flag_l_r)
3220 {
3221         s16 q1;
3222         int q1_cal;
3223 
3224         if (*z_val < (WCD938X_ZDET_VAL_400/1000))
3225                 q1 = snd_soc_component_read(component,
3226                         WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
3227         else
3228                 q1 = snd_soc_component_read(component,
3229                         WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
3230         if (q1 & 0x80)
3231                 q1_cal = (10000 - ((q1 & 0x7F) * 25));
3232         else
3233                 q1_cal = (10000 + (q1 * 25));
3234         if (q1_cal > 0)
3235                 *z_val = ((*z_val) * 10000) / q1_cal;
3236 }
3237 
3238 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
3239                                             uint32_t *zl, uint32_t *zr)
3240 {
3241         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3242         s16 reg0, reg1, reg2, reg3, reg4;
3243         int32_t z1L, z1R, z1Ls;
3244         int zMono, z_diff1, z_diff2;
3245         bool is_fsm_disable = false;
3246         struct wcd938x_mbhc_zdet_param zdet_param[] = {
3247                 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
3248                 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
3249                 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
3250                 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
3251         };
3252         struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
3253         s16 d1_a[][4] = {
3254                 {0, 30, 90, 30},
3255                 {0, 30, 30, 5},
3256                 {0, 30, 30, 5},
3257                 {0, 30, 30, 5},
3258         };
3259         s16 *d1 = NULL;
3260 
3261         reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
3262         reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
3263         reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
3264         reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
3265         reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
3266 
3267         if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
3268                 is_fsm_disable = true;
3269                 regmap_update_bits(wcd938x->regmap,
3270                                    WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
3271         }
3272 
3273         /* For NO-jack, disable L_DET_EN before Z-det measurements */
3274         if (wcd938x->mbhc_cfg.hphl_swh)
3275                 regmap_update_bits(wcd938x->regmap,
3276                                    WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
3277 
3278         /* Turn off 100k pull down on HPHL */
3279         regmap_update_bits(wcd938x->regmap,
3280                            WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
3281 
3282         /* Disable surge protection before impedance detection.
3283          * This is done to give correct value for high impedance.
3284          */
3285         regmap_update_bits(wcd938x->regmap,
3286                            WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
3287         /* 1ms delay needed after disable surge protection */
3288         usleep_range(1000, 1010);
3289 
3290         /* First get impedance on Left */
3291         d1 = d1_a[1];
3292         zdet_param_ptr = &zdet_param[1];
3293         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3294 
3295         if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
3296                 goto left_ch_impedance;
3297 
3298         /* Second ramp for left ch */
3299         if (z1L < WCD938X_ZDET_VAL_32) {
3300                 zdet_param_ptr = &zdet_param[0];
3301                 d1 = d1_a[0];
3302         } else if ((z1L > WCD938X_ZDET_VAL_400) &&
3303                   (z1L <= WCD938X_ZDET_VAL_1200)) {
3304                 zdet_param_ptr = &zdet_param[2];
3305                 d1 = d1_a[2];
3306         } else if (z1L > WCD938X_ZDET_VAL_1200) {
3307                 zdet_param_ptr = &zdet_param[3];
3308                 d1 = d1_a[3];
3309         }
3310         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3311 
3312 left_ch_impedance:
3313         if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3314                 (z1L > WCD938X_ZDET_VAL_100K)) {
3315                 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
3316                 zdet_param_ptr = &zdet_param[1];
3317                 d1 = d1_a[1];
3318         } else {
3319                 *zl = z1L/1000;
3320                 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
3321         }
3322         dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
3323                 __func__, *zl);
3324 
3325         /* Start of right impedance ramp and calculation */
3326         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3327         if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
3328                 if (((z1R > WCD938X_ZDET_VAL_1200) &&
3329                         (zdet_param_ptr->noff == 0x6)) ||
3330                         ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
3331                         goto right_ch_impedance;
3332                 /* Second ramp for right ch */
3333                 if (z1R < WCD938X_ZDET_VAL_32) {
3334                         zdet_param_ptr = &zdet_param[0];
3335                         d1 = d1_a[0];
3336                 } else if ((z1R > WCD938X_ZDET_VAL_400) &&
3337                         (z1R <= WCD938X_ZDET_VAL_1200)) {
3338                         zdet_param_ptr = &zdet_param[2];
3339                         d1 = d1_a[2];
3340                 } else if (z1R > WCD938X_ZDET_VAL_1200) {
3341                         zdet_param_ptr = &zdet_param[3];
3342                         d1 = d1_a[3];
3343                 }
3344                 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3345         }
3346 right_ch_impedance:
3347         if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3348                 (z1R > WCD938X_ZDET_VAL_100K)) {
3349                 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
3350         } else {
3351                 *zr = z1R/1000;
3352                 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
3353         }
3354         dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
3355                 __func__, *zr);
3356 
3357         /* Mono/stereo detection */
3358         if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
3359                 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
3360                 dev_dbg(component->dev,
3361                         "%s: plug type is invalid or extension cable\n",
3362                         __func__);
3363                 goto zdet_complete;
3364         }
3365         if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3366             (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3367             ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
3368             ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
3369                 dev_dbg(component->dev,
3370                         "%s: Mono plug type with one ch floating or shorted to GND\n",
3371                         __func__);
3372                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3373                 goto zdet_complete;
3374         }
3375         snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3376                                       WCD938X_HPHPA_GND_OVR_MASK, 1);
3377         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3378                                       WCD938X_HPHPA_GND_R_MASK, 1);
3379         if (*zl < (WCD938X_ZDET_VAL_32/1000))
3380                 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
3381         else
3382                 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
3383         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3384                                       WCD938X_HPHPA_GND_R_MASK, 0);
3385         snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3386                                       WCD938X_HPHPA_GND_OVR_MASK, 0);
3387         z1Ls /= 1000;
3388         wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
3389         /* Parallel of left Z and 9 ohm pull down resistor */
3390         zMono = ((*zl) * 9) / ((*zl) + 9);
3391         z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
3392         z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
3393         if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
3394                 dev_dbg(component->dev, "%s: stereo plug type detected\n",
3395                         __func__);
3396                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
3397         } else {
3398                 dev_dbg(component->dev, "%s: MONO plug type detected\n",
3399                         __func__);
3400                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3401         }
3402 
3403         /* Enable surge protection again after impedance detection */
3404         regmap_update_bits(wcd938x->regmap,
3405                            WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
3406 zdet_complete:
3407         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
3408         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
3409         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
3410         /* Turn on 100k pull down on HPHL */
3411         regmap_update_bits(wcd938x->regmap,
3412                            WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
3413 
3414         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
3415         if (wcd938x->mbhc_cfg.hphl_swh)
3416                 regmap_update_bits(wcd938x->regmap,
3417                                    WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
3418 
3419         snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
3420         snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
3421         if (is_fsm_disable)
3422                 regmap_update_bits(wcd938x->regmap,
3423                                    WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
3424 }
3425 
3426 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
3427                         bool enable)
3428 {
3429         if (enable) {
3430                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3431                                               WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
3432                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3433                                               WCD938X_MBHC_GND_DET_EN_MASK, 1);
3434         } else {
3435                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3436                                               WCD938X_MBHC_GND_DET_EN_MASK, 0);
3437                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3438                                               WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
3439         }
3440 }
3441 
3442 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
3443                                           bool enable)
3444 {
3445         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3446                                       WCD938X_HPHPA_GND_R_MASK, enable);
3447         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3448                                       WCD938X_HPHPA_GND_L_MASK, enable);
3449 }
3450 
3451 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
3452 {
3453         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3454 
3455         if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3456                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3457                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3458                 return;
3459         }
3460 
3461         /* Do not enable moisture detection if jack type is NC */
3462         if (!wcd938x->mbhc_cfg.hphl_swh) {
3463                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3464                         __func__);
3465                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3466                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3467                 return;
3468         }
3469 
3470         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3471                             WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3472 }
3473 
3474 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
3475 {
3476         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3477 
3478         if (enable)
3479                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3480                                         WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3481         else
3482                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3483                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3484 }
3485 
3486 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
3487 {
3488         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3489         bool ret = false;
3490 
3491         if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3492                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3493                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3494                 goto done;
3495         }
3496 
3497         /* Do not enable moisture detection if jack type is NC */
3498         if (!wcd938x->mbhc_cfg.hphl_swh) {
3499                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3500                         __func__);
3501                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3502                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3503                 goto done;
3504         }
3505 
3506         /*
3507          * If moisture_en is already enabled, then skip to plug type
3508          * detection.
3509          */
3510         if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
3511                 goto done;
3512 
3513         wcd938x_mbhc_moisture_detect_en(component, true);
3514         /* Read moisture comparator status */
3515         ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
3516                                 & 0x20) ? 0 : 1);
3517 
3518 done:
3519         return ret;
3520 
3521 }
3522 
3523 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
3524                                                 bool enable)
3525 {
3526         snd_soc_component_write_field(component,
3527                               WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
3528                               WCD938X_MOISTURE_EN_POLLING_MASK, enable);
3529 }
3530 
3531 static const struct wcd_mbhc_cb mbhc_cb = {
3532         .clk_setup = wcd938x_mbhc_clk_setup,
3533         .mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
3534         .set_btn_thr = wcd938x_mbhc_program_btn_thr,
3535         .micbias_enable_status = wcd938x_mbhc_micb_en_status,
3536         .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
3537         .mbhc_micbias_control = wcd938x_mbhc_request_micbias,
3538         .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
3539         .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
3540         .compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
3541         .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
3542         .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
3543         .mbhc_moisture_config = wcd938x_mbhc_moisture_config,
3544         .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
3545         .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
3546         .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
3547 };
3548 
3549 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
3550                               struct snd_ctl_elem_value *ucontrol)
3551 {
3552         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3553         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3554 
3555         ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
3556 
3557         return 0;
3558 }
3559 
3560 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
3561                                    struct snd_ctl_elem_value *ucontrol)
3562 {
3563         uint32_t zl, zr;
3564         bool hphr;
3565         struct soc_mixer_control *mc;
3566         struct snd_soc_component *component =
3567                                         snd_soc_kcontrol_component(kcontrol);
3568         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3569 
3570         mc = (struct soc_mixer_control *)(kcontrol->private_value);
3571         hphr = mc->shift;
3572         wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
3573         dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
3574         ucontrol->value.integer.value[0] = hphr ? zr : zl;
3575 
3576         return 0;
3577 }
3578 
3579 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3580         SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3581                        wcd938x_get_hph_type, NULL),
3582 };
3583 
3584 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3585         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3586                        wcd938x_hph_impedance_get, NULL),
3587         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3588                        wcd938x_hph_impedance_get, NULL),
3589 };
3590 
3591 static int wcd938x_mbhc_init(struct snd_soc_component *component)
3592 {
3593         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3594         struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
3595 
3596         intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3597                                                     WCD938X_IRQ_MBHC_SW_DET);
3598         intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3599                                                            WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
3600         intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3601                                                              WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
3602         intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3603                                                         WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3604         intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3605                                                         WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
3606         intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3607                                                     WCD938X_IRQ_HPHL_OCP_INT);
3608         intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3609                                                      WCD938X_IRQ_HPHR_OCP_INT);
3610 
3611         wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3612 
3613         snd_soc_add_component_controls(component, impedance_detect_controls,
3614                                        ARRAY_SIZE(impedance_detect_controls));
3615         snd_soc_add_component_controls(component, hph_type_detect_controls,
3616                                        ARRAY_SIZE(hph_type_detect_controls));
3617 
3618         return 0;
3619 }
3620 /* END MBHC */
3621 
3622 static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
3623         SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
3624                        wcd938x_get_compander, wcd938x_set_compander),
3625         SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
3626                        wcd938x_get_compander, wcd938x_set_compander),
3627         SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
3628                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3629         SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
3630                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3631         SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
3632                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3633         SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
3634                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3635         SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
3636                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3637         SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
3638                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3639         SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
3640         SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
3641         WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
3642                                 2, 0x10, 0, ear_pa_gain),
3643         SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
3644                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3645         SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
3646                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3647         SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
3648                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3649         SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
3650                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3651         SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
3652                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3653         SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
3654                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3655         SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
3656                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3657         SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
3658                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3659         SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
3660                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3661         SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
3662                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3663         SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
3664                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3665         SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
3666                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3667         SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
3668                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3669         SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
3670                        wcd938x_ldoh_get, wcd938x_ldoh_put),
3671         SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
3672                        wcd938x_bcs_get, wcd938x_bcs_put),
3673 
3674         SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
3675         SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
3676         SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
3677         SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
3678 };
3679 
3680 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
3681 
3682         /*input widgets*/
3683         SND_SOC_DAPM_INPUT("AMIC1"),
3684         SND_SOC_DAPM_INPUT("AMIC2"),
3685         SND_SOC_DAPM_INPUT("AMIC3"),
3686         SND_SOC_DAPM_INPUT("AMIC4"),
3687         SND_SOC_DAPM_INPUT("AMIC5"),
3688         SND_SOC_DAPM_INPUT("AMIC6"),
3689         SND_SOC_DAPM_INPUT("AMIC7"),
3690         SND_SOC_DAPM_MIC("Analog Mic1", NULL),
3691         SND_SOC_DAPM_MIC("Analog Mic2", NULL),
3692         SND_SOC_DAPM_MIC("Analog Mic3", NULL),
3693         SND_SOC_DAPM_MIC("Analog Mic4", NULL),
3694         SND_SOC_DAPM_MIC("Analog Mic5", NULL),
3695 
3696         /*tx widgets*/
3697         SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
3698                            wcd938x_codec_enable_adc,
3699                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3700         SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
3701                            wcd938x_codec_enable_adc,
3702                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3703         SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
3704                            wcd938x_codec_enable_adc,
3705                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3706         SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
3707                            wcd938x_codec_enable_adc,
3708                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3709         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
3710                            wcd938x_codec_enable_dmic,
3711                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3712         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
3713                            wcd938x_codec_enable_dmic,
3714                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3715         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
3716                            wcd938x_codec_enable_dmic,
3717                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3718         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
3719                            wcd938x_codec_enable_dmic,
3720                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3721         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
3722                            wcd938x_codec_enable_dmic,
3723                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3724         SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
3725                            wcd938x_codec_enable_dmic,
3726                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3727         SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
3728                            wcd938x_codec_enable_dmic,
3729                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3730         SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
3731                            wcd938x_codec_enable_dmic,
3732                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3733 
3734         SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
3735                              NULL, 0, wcd938x_adc_enable_req,
3736                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3737         SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
3738                              NULL, 0, wcd938x_adc_enable_req,
3739                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3740         SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
3741                              NULL, 0, wcd938x_adc_enable_req,
3742                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3743         SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
3744                              wcd938x_adc_enable_req,
3745                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3746 
3747         SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
3748         SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
3749         SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
3750         SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
3751         SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
3752 
3753         /*tx mixers*/
3754         SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
3755                              ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
3756                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3757         SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
3758                              ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
3759                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3760         SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
3761                              ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
3762                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3763         SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
3764                              ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
3765                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3766         SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
3767                              ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
3768                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3769         SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
3770                              ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
3771                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3772         SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
3773                              ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
3774                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3775         SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
3776                              ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
3777                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3778         SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
3779                              ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
3780                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3781         SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
3782                              ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
3783                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3784         SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
3785                              ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
3786                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3787         SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
3788                              ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
3789                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3790         /* micbias widgets*/
3791         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3792                             wcd938x_codec_enable_micbias,
3793                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3794                             SND_SOC_DAPM_POST_PMD),
3795         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3796                             wcd938x_codec_enable_micbias,
3797                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3798                             SND_SOC_DAPM_POST_PMD),
3799         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3800                             wcd938x_codec_enable_micbias,
3801                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3802                             SND_SOC_DAPM_POST_PMD),
3803         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3804                             wcd938x_codec_enable_micbias,
3805                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3806                             SND_SOC_DAPM_POST_PMD),
3807 
3808         /* micbias pull up widgets*/
3809         SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3810                                 wcd938x_codec_enable_micbias_pullup,
3811                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3812                                 SND_SOC_DAPM_POST_PMD),
3813         SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3814                                 wcd938x_codec_enable_micbias_pullup,
3815                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3816                                 SND_SOC_DAPM_POST_PMD),
3817         SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3818                                 wcd938x_codec_enable_micbias_pullup,
3819                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3820                                 SND_SOC_DAPM_POST_PMD),
3821         SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3822                                 wcd938x_codec_enable_micbias_pullup,
3823                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3824                                 SND_SOC_DAPM_POST_PMD),
3825 
3826         /*output widgets tx*/
3827         SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
3828         SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
3829         SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
3830         SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
3831         SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
3832         SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
3833         SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
3834         SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
3835         SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
3836         SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
3837         SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
3838         SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
3839 
3840         SND_SOC_DAPM_INPUT("IN1_HPHL"),
3841         SND_SOC_DAPM_INPUT("IN2_HPHR"),
3842         SND_SOC_DAPM_INPUT("IN3_AUX"),
3843 
3844         /*rx widgets*/
3845         SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
3846                            wcd938x_codec_enable_ear_pa,
3847                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3848                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3849         SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
3850                            wcd938x_codec_enable_aux_pa,
3851                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3852                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3853         SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
3854                            wcd938x_codec_enable_hphl_pa,
3855                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3856                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3857         SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
3858                            wcd938x_codec_enable_hphr_pa,
3859                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3860                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3861 
3862         SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
3863                            wcd938x_codec_hphl_dac_event,
3864                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3865                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3866         SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
3867                            wcd938x_codec_hphr_dac_event,
3868                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3869                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3870         SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
3871                            wcd938x_codec_ear_dac_event,
3872                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3873                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3874         SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
3875                            wcd938x_codec_aux_dac_event,
3876                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3877                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3878 
3879         SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
3880 
3881         SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
3882         SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
3883                             wcd938x_codec_enable_rxclk,
3884                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3885                             SND_SOC_DAPM_POST_PMD),
3886 
3887         SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
3888 
3889         SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3890         SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3891         SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3892 
3893         /* rx mixer widgets*/
3894         SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
3895                            ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
3896         SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
3897                            aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
3898         SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
3899                            hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
3900         SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
3901                            hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
3902 
3903         /*output widgets rx*/
3904         SND_SOC_DAPM_OUTPUT("EAR"),
3905         SND_SOC_DAPM_OUTPUT("AUX"),
3906         SND_SOC_DAPM_OUTPUT("HPHL"),
3907         SND_SOC_DAPM_OUTPUT("HPHR"),
3908 
3909 };
3910 
3911 static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
3912         {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
3913         {"ADC1_MIXER", "Switch", "ADC1 REQ"},
3914         {"ADC1 REQ", NULL, "ADC1"},
3915         {"ADC1", NULL, "AMIC1"},
3916 
3917         {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
3918         {"ADC2_MIXER", "Switch", "ADC2 REQ"},
3919         {"ADC2 REQ", NULL, "ADC2"},
3920         {"ADC2", NULL, "HDR12 MUX"},
3921         {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
3922         {"HDR12 MUX", "HDR12", "AMIC1"},
3923         {"ADC2 MUX", "INP3", "AMIC3"},
3924         {"ADC2 MUX", "INP2", "AMIC2"},
3925 
3926         {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
3927         {"ADC3_MIXER", "Switch", "ADC3 REQ"},
3928         {"ADC3 REQ", NULL, "ADC3"},
3929         {"ADC3", NULL, "HDR34 MUX"},
3930         {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
3931         {"HDR34 MUX", "HDR34", "AMIC5"},
3932         {"ADC3 MUX", "INP4", "AMIC4"},
3933         {"ADC3 MUX", "INP6", "AMIC6"},
3934 
3935         {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
3936         {"ADC4_MIXER", "Switch", "ADC4 REQ"},
3937         {"ADC4 REQ", NULL, "ADC4"},
3938         {"ADC4", NULL, "ADC4 MUX"},
3939         {"ADC4 MUX", "INP5", "AMIC5"},
3940         {"ADC4 MUX", "INP7", "AMIC7"},
3941 
3942         {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
3943         {"DMIC1_MIXER", "Switch", "DMIC1"},
3944 
3945         {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
3946         {"DMIC2_MIXER", "Switch", "DMIC2"},
3947 
3948         {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
3949         {"DMIC3_MIXER", "Switch", "DMIC3"},
3950 
3951         {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
3952         {"DMIC4_MIXER", "Switch", "DMIC4"},
3953 
3954         {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
3955         {"DMIC5_MIXER", "Switch", "DMIC5"},
3956 
3957         {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
3958         {"DMIC6_MIXER", "Switch", "DMIC6"},
3959 
3960         {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
3961         {"DMIC7_MIXER", "Switch", "DMIC7"},
3962 
3963         {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
3964         {"DMIC8_MIXER", "Switch", "DMIC8"},
3965 
3966         {"IN1_HPHL", NULL, "VDD_BUCK"},
3967         {"IN1_HPHL", NULL, "CLS_H_PORT"},
3968 
3969         {"RX1", NULL, "IN1_HPHL"},
3970         {"RX1", NULL, "RXCLK"},
3971         {"RDAC1", NULL, "RX1"},
3972         {"HPHL_RDAC", "Switch", "RDAC1"},
3973         {"HPHL PGA", NULL, "HPHL_RDAC"},
3974         {"HPHL", NULL, "HPHL PGA"},
3975 
3976         {"IN2_HPHR", NULL, "VDD_BUCK"},
3977         {"IN2_HPHR", NULL, "CLS_H_PORT"},
3978         {"RX2", NULL, "IN2_HPHR"},
3979         {"RDAC2", NULL, "RX2"},
3980         {"RX2", NULL, "RXCLK"},
3981         {"HPHR_RDAC", "Switch", "RDAC2"},
3982         {"HPHR PGA", NULL, "HPHR_RDAC"},
3983         {"HPHR", NULL, "HPHR PGA"},
3984 
3985         {"IN3_AUX", NULL, "VDD_BUCK"},
3986         {"IN3_AUX", NULL, "CLS_H_PORT"},
3987         {"RX3", NULL, "IN3_AUX"},
3988         {"RDAC4", NULL, "RX3"},
3989         {"RX3", NULL, "RXCLK"},
3990         {"AUX_RDAC", "Switch", "RDAC4"},
3991         {"AUX PGA", NULL, "AUX_RDAC"},
3992         {"AUX", NULL, "AUX PGA"},
3993 
3994         {"RDAC3_MUX", "RX3", "RX3"},
3995         {"RDAC3_MUX", "RX1", "RX1"},
3996         {"RDAC3", NULL, "RDAC3_MUX"},
3997         {"EAR_RDAC", "Switch", "RDAC3"},
3998         {"EAR PGA", NULL, "EAR_RDAC"},
3999         {"EAR", NULL, "EAR PGA"},
4000 };
4001 
4002 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
4003 {
4004         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
4005 
4006         /* set micbias voltage */
4007         vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
4008         vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
4009         vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
4010         vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
4011         if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
4012                 return -EINVAL;
4013 
4014         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
4015                            WCD938X_MICB_VOUT_MASK, vout_ctl_1);
4016         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
4017                            WCD938X_MICB_VOUT_MASK, vout_ctl_2);
4018         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
4019                            WCD938X_MICB_VOUT_MASK, vout_ctl_3);
4020         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
4021                            WCD938X_MICB_VOUT_MASK, vout_ctl_4);
4022 
4023         return 0;
4024 }
4025 
4026 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
4027 {
4028         return IRQ_HANDLED;
4029 }
4030 
4031 static struct irq_chip wcd_irq_chip = {
4032         .name = "WCD938x",
4033 };
4034 
4035 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
4036                         irq_hw_number_t hw)
4037 {
4038         irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
4039         irq_set_nested_thread(virq, 1);
4040         irq_set_noprobe(virq);
4041 
4042         return 0;
4043 }
4044 
4045 static const struct irq_domain_ops wcd_domain_ops = {
4046         .map = wcd_irq_chip_map,
4047 };
4048 
4049 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
4050 {
4051 
4052         wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
4053         if (!(wcd->virq)) {
4054                 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
4055                 return -EINVAL;
4056         }
4057 
4058         return devm_regmap_add_irq_chip(dev, wcd->regmap,
4059                                         irq_create_mapping(wcd->virq, 0),
4060                                         IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
4061                                         &wcd->irq_chip);
4062 }
4063 
4064 static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
4065 {
4066         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
4067         struct device *dev = component->dev;
4068         int ret, i;
4069 
4070         snd_soc_component_init_regmap(component, wcd938x->regmap);
4071 
4072         wcd938x->variant = snd_soc_component_read_field(component,
4073                                                  WCD938X_DIGITAL_EFUSE_REG_0,
4074                                                  WCD938X_ID_MASK);
4075 
4076         wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
4077 
4078         wcd938x_io_init(wcd938x);
4079         /* Set all interrupts as edge triggered */
4080         for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
4081                 regmap_write(wcd938x->regmap,
4082                              (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
4083         }
4084 
4085         wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4086                                                        WCD938X_IRQ_HPHR_PDM_WD_INT);
4087         wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4088                                                        WCD938X_IRQ_HPHL_PDM_WD_INT);
4089         wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4090                                                        WCD938X_IRQ_AUX_PDM_WD_INT);
4091 
4092         /* Request for watchdog interrupt */
4093         ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4094                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4095                                    "HPHR PDM WD INT", wcd938x);
4096         if (ret)
4097                 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
4098 
4099         ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4100                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4101                                    "HPHL PDM WD INT", wcd938x);
4102         if (ret)
4103                 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
4104 
4105         ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4106                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4107                                    "AUX PDM WD INT", wcd938x);
4108         if (ret)
4109                 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
4110 
4111         /* Disable watchdog interrupt for HPH and AUX */
4112         disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
4113         disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
4114         disable_irq_nosync(wcd938x->aux_pdm_wd_int);
4115 
4116         switch (wcd938x->variant) {
4117         case WCD9380:
4118                 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
4119                                         ARRAY_SIZE(wcd9380_snd_controls));
4120                 if (ret < 0) {
4121                         dev_err(component->dev,
4122                                 "%s: Failed to add snd ctrls for variant: %d\n",
4123                                 __func__, wcd938x->variant);
4124                         goto err;
4125                 }
4126                 break;
4127         case WCD9385:
4128                 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
4129                                         ARRAY_SIZE(wcd9385_snd_controls));
4130                 if (ret < 0) {
4131                         dev_err(component->dev,
4132                                 "%s: Failed to add snd ctrls for variant: %d\n",
4133                                 __func__, wcd938x->variant);
4134                         goto err;
4135                 }
4136                 break;
4137         default:
4138                 break;
4139         }
4140 
4141         ret = wcd938x_mbhc_init(component);
4142         if (ret)
4143                 dev_err(component->dev,  "mbhc initialization failed\n");
4144 err:
4145         return ret;
4146 }
4147 
4148 static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
4149                                   struct snd_soc_jack *jack, void *data)
4150 {
4151         struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
4152 
4153         if (jack)
4154                 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
4155         else
4156                 wcd_mbhc_stop(wcd->wcd_mbhc);
4157 
4158         return 0;
4159 }
4160 
4161 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
4162         .name = "wcd938x_codec",
4163         .probe = wcd938x_soc_codec_probe,
4164         .controls = wcd938x_snd_controls,
4165         .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
4166         .dapm_widgets = wcd938x_dapm_widgets,
4167         .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
4168         .dapm_routes = wcd938x_audio_map,
4169         .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
4170         .set_jack = wcd938x_codec_set_jack,
4171 };
4172 
4173 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
4174 {
4175         struct device_node *np = dev->of_node;
4176         u32 prop_val = 0;
4177         int rc = 0;
4178 
4179         rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
4180         if (!rc)
4181                 wcd->micb1_mv = prop_val/1000;
4182         else
4183                 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
4184 
4185         rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
4186         if (!rc)
4187                 wcd->micb2_mv = prop_val/1000;
4188         else
4189                 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
4190 
4191         rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
4192         if (!rc)
4193                 wcd->micb3_mv = prop_val/1000;
4194         else
4195                 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
4196 
4197         rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
4198         if (!rc)
4199                 wcd->micb4_mv = prop_val/1000;
4200         else
4201                 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
4202 }
4203 
4204 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
4205 {
4206         struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
4207         int ret;
4208 
4209         wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
4210         if (wcd938x->reset_gpio < 0) {
4211                 dev_err(dev, "Failed to get reset gpio: err = %d\n",
4212                         wcd938x->reset_gpio);
4213                 return wcd938x->reset_gpio;
4214         }
4215 
4216         wcd938x->supplies[0].supply = "vdd-rxtx";
4217         wcd938x->supplies[1].supply = "vdd-io";
4218         wcd938x->supplies[2].supply = "vdd-buck";
4219         wcd938x->supplies[3].supply = "vdd-mic-bias";
4220 
4221         ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
4222         if (ret) {
4223                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
4224                 return ret;
4225         }
4226 
4227         ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
4228         if (ret) {
4229                 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
4230                 return ret;
4231         }
4232 
4233         wcd938x_dt_parse_micbias_info(dev, wcd938x);
4234 
4235         cfg->mbhc_micbias = MIC_BIAS_2;
4236         cfg->anc_micbias = MIC_BIAS_2;
4237         cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
4238         cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
4239         cfg->micb_mv = wcd938x->micb2_mv;
4240         cfg->linein_th = 5000;
4241         cfg->hs_thr = 1700;
4242         cfg->hph_thr = 50;
4243 
4244         wcd_dt_parse_mbhc_data(dev, cfg);
4245 
4246         return 0;
4247 }
4248 
4249 static int wcd938x_reset(struct wcd938x_priv *wcd938x)
4250 {
4251         gpio_direction_output(wcd938x->reset_gpio, 0);
4252         /* 20us sleep required after pulling the reset gpio to LOW */
4253         usleep_range(20, 30);
4254         gpio_set_value(wcd938x->reset_gpio, 1);
4255         /* 20us sleep required after pulling the reset gpio to HIGH */
4256         usleep_range(20, 30);
4257 
4258         return 0;
4259 }
4260 
4261 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
4262                                 struct snd_pcm_hw_params *params,
4263                                 struct snd_soc_dai *dai)
4264 {
4265         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4266         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4267 
4268         return wcd938x_sdw_hw_params(wcd, substream, params, dai);
4269 }
4270 
4271 static int wcd938x_codec_free(struct snd_pcm_substream *substream,
4272                               struct snd_soc_dai *dai)
4273 {
4274         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4275         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4276 
4277         return wcd938x_sdw_free(wcd, substream, dai);
4278 }
4279 
4280 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
4281                                   void *stream, int direction)
4282 {
4283         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4284         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4285 
4286         return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
4287 
4288 }
4289 
4290 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
4291         .hw_params = wcd938x_codec_hw_params,
4292         .hw_free = wcd938x_codec_free,
4293         .set_sdw_stream = wcd938x_codec_set_sdw_stream,
4294 };
4295 
4296 static struct snd_soc_dai_driver wcd938x_dais[] = {
4297         [0] = {
4298                 .name = "wcd938x-sdw-rx",
4299                 .playback = {
4300                         .stream_name = "WCD AIF1 Playback",
4301                         .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
4302                         .formats = WCD938X_FORMATS_S16_S24_LE,
4303                         .rate_max = 192000,
4304                         .rate_min = 8000,
4305                         .channels_min = 1,
4306                         .channels_max = 2,
4307                 },
4308                 .ops = &wcd938x_sdw_dai_ops,
4309         },
4310         [1] = {
4311                 .name = "wcd938x-sdw-tx",
4312                 .capture = {
4313                         .stream_name = "WCD AIF1 Capture",
4314                         .rates = WCD938X_RATES_MASK,
4315                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
4316                         .rate_min = 8000,
4317                         .rate_max = 192000,
4318                         .channels_min = 1,
4319                         .channels_max = 4,
4320                 },
4321                 .ops = &wcd938x_sdw_dai_ops,
4322         },
4323 };
4324 
4325 static int wcd938x_bind(struct device *dev)
4326 {
4327         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4328         int ret;
4329 
4330         ret = component_bind_all(dev, wcd938x);
4331         if (ret) {
4332                 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
4333                         __func__, ret);
4334                 return ret;
4335         }
4336 
4337         wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
4338         if (!wcd938x->rxdev) {
4339                 dev_err(dev, "could not find slave with matching of node\n");
4340                 return -EINVAL;
4341         }
4342         wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
4343         wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
4344 
4345         wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
4346         if (!wcd938x->txdev) {
4347                 dev_err(dev, "could not find txslave with matching of node\n");
4348                 return -EINVAL;
4349         }
4350         wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
4351         wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
4352         wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
4353         if (!wcd938x->tx_sdw_dev) {
4354                 dev_err(dev, "could not get txslave with matching of dev\n");
4355                 return -EINVAL;
4356         }
4357 
4358         /* As TX is main CSR reg interface, which should not be suspended first.
4359          * expicilty add the dependency link */
4360         if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
4361                             DL_FLAG_PM_RUNTIME)) {
4362                 dev_err(dev, "could not devlink tx and rx\n");
4363                 return -EINVAL;
4364         }
4365 
4366         if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
4367                                         DL_FLAG_PM_RUNTIME)) {
4368                 dev_err(dev, "could not devlink wcd and tx\n");
4369                 return -EINVAL;
4370         }
4371 
4372         if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
4373                                         DL_FLAG_PM_RUNTIME)) {
4374                 dev_err(dev, "could not devlink wcd and rx\n");
4375                 return -EINVAL;
4376         }
4377 
4378         wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
4379         if (IS_ERR(wcd938x->regmap)) {
4380                 dev_err(dev, "%s: tx csr regmap not found\n", __func__);
4381                 return PTR_ERR(wcd938x->regmap);
4382         }
4383 
4384         ret = wcd938x_irq_init(wcd938x, dev);
4385         if (ret) {
4386                 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
4387                 return ret;
4388         }
4389 
4390         wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
4391         wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
4392 
4393         ret = wcd938x_set_micbias_data(wcd938x);
4394         if (ret < 0) {
4395                 dev_err(dev, "%s: bad micbias pdata\n", __func__);
4396                 return ret;
4397         }
4398 
4399         ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
4400                                          wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
4401         if (ret)
4402                 dev_err(dev, "%s: Codec registration failed\n",
4403                                 __func__);
4404 
4405         return ret;
4406 
4407 }
4408 
4409 static void wcd938x_unbind(struct device *dev)
4410 {
4411         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4412 
4413         device_link_remove(dev, wcd938x->txdev);
4414         device_link_remove(dev, wcd938x->rxdev);
4415         device_link_remove(wcd938x->rxdev, wcd938x->txdev);
4416         snd_soc_unregister_component(dev);
4417         component_unbind_all(dev, wcd938x);
4418 }
4419 
4420 static const struct component_master_ops wcd938x_comp_ops = {
4421         .bind   = wcd938x_bind,
4422         .unbind = wcd938x_unbind,
4423 };
4424 
4425 static int wcd938x_compare_of(struct device *dev, void *data)
4426 {
4427         return dev->of_node == data;
4428 }
4429 
4430 static void wcd938x_release_of(struct device *dev, void *data)
4431 {
4432         of_node_put(data);
4433 }
4434 
4435 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
4436                                         struct device *dev,
4437                                         struct component_match **matchptr)
4438 {
4439         struct device_node *np;
4440 
4441         np = dev->of_node;
4442 
4443         wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
4444         if (!wcd938x->rxnode) {
4445                 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
4446                 return -ENODEV;
4447         }
4448 
4449         of_node_get(wcd938x->rxnode);
4450         component_match_add_release(dev, matchptr, wcd938x_release_of,
4451                                     wcd938x_compare_of, wcd938x->rxnode);
4452 
4453         wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
4454         if (!wcd938x->txnode) {
4455                 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
4456                 return -ENODEV;
4457         }
4458         of_node_get(wcd938x->txnode);
4459         component_match_add_release(dev, matchptr, wcd938x_release_of,
4460                                     wcd938x_compare_of, wcd938x->txnode);
4461         return 0;
4462 }
4463 
4464 static int wcd938x_probe(struct platform_device *pdev)
4465 {
4466         struct component_match *match = NULL;
4467         struct wcd938x_priv *wcd938x = NULL;
4468         struct device *dev = &pdev->dev;
4469         int ret;
4470 
4471         wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
4472                                 GFP_KERNEL);
4473         if (!wcd938x)
4474                 return -ENOMEM;
4475 
4476         dev_set_drvdata(dev, wcd938x);
4477         mutex_init(&wcd938x->micb_lock);
4478 
4479         ret = wcd938x_populate_dt_data(wcd938x, dev);
4480         if (ret) {
4481                 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
4482                 return -EINVAL;
4483         }
4484 
4485         ret = wcd938x_add_slave_components(wcd938x, dev, &match);
4486         if (ret)
4487                 return ret;
4488 
4489         wcd938x_reset(wcd938x);
4490 
4491         ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
4492         if (ret)
4493                 return ret;
4494 
4495         pm_runtime_set_autosuspend_delay(dev, 1000);
4496         pm_runtime_use_autosuspend(dev);
4497         pm_runtime_mark_last_busy(dev);
4498         pm_runtime_set_active(dev);
4499         pm_runtime_enable(dev);
4500         pm_runtime_idle(dev);
4501 
4502         return 0;
4503 }
4504 
4505 static int wcd938x_remove(struct platform_device *pdev)
4506 {
4507         component_master_del(&pdev->dev, &wcd938x_comp_ops);
4508 
4509         return 0;
4510 }
4511 
4512 #if defined(CONFIG_OF)
4513 static const struct of_device_id wcd938x_dt_match[] = {
4514         { .compatible = "qcom,wcd9380-codec" },
4515         { .compatible = "qcom,wcd9385-codec" },
4516         {}
4517 };
4518 MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
4519 #endif
4520 
4521 static struct platform_driver wcd938x_codec_driver = {
4522         .probe = wcd938x_probe,
4523         .remove = wcd938x_remove,
4524         .driver = {
4525                 .name = "wcd938x_codec",
4526                 .of_match_table = of_match_ptr(wcd938x_dt_match),
4527                 .suppress_bind_attrs = true,
4528         },
4529 };
4530 
4531 module_platform_driver(wcd938x_codec_driver);
4532 MODULE_DESCRIPTION("WCD938X Codec driver");
4533 MODULE_LICENSE("GPL");
4534 

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