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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm5100.c

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  1 /*
  2  * wm5100.c  --  WM5100 ALSA SoC Audio driver
  3  *
  4  * Copyright 2011-2 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/init.h>
 16 #include <linux/delay.h>
 17 #include <linux/export.h>
 18 #include <linux/pm.h>
 19 #include <linux/gcd.h>
 20 #include <linux/gpio.h>
 21 #include <linux/i2c.h>
 22 #include <linux/pm_runtime.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/regulator/fixed.h>
 25 #include <linux/slab.h>
 26 #include <sound/core.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/jack.h>
 31 #include <sound/initval.h>
 32 #include <sound/tlv.h>
 33 #include <sound/wm5100.h>
 34 
 35 #include "wm5100.h"
 36 
 37 #define WM5100_NUM_CORE_SUPPLIES 2
 38 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
 39         "DBVDD1",
 40         "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
 41 };
 42 
 43 #define WM5100_AIFS     3
 44 #define WM5100_SYNC_SRS 3
 45 
 46 struct wm5100_fll {
 47         int fref;
 48         int fout;
 49         int src;
 50         struct completion lock;
 51 };
 52 
 53 /* codec private data */
 54 struct wm5100_priv {
 55         struct device *dev;
 56         struct regmap *regmap;
 57         struct snd_soc_codec *codec;
 58 
 59         struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
 60 
 61         int rev;
 62 
 63         int sysclk;
 64         int asyncclk;
 65 
 66         bool aif_async[WM5100_AIFS];
 67         bool aif_symmetric[WM5100_AIFS];
 68         int sr_ref[WM5100_SYNC_SRS];
 69 
 70         bool out_ena[2];
 71 
 72         struct snd_soc_jack *jack;
 73         bool jack_detecting;
 74         bool jack_mic;
 75         int jack_mode;
 76         int jack_flips;
 77 
 78         struct wm5100_fll fll[2];
 79 
 80         struct wm5100_pdata pdata;
 81 
 82 #ifdef CONFIG_GPIOLIB
 83         struct gpio_chip gpio_chip;
 84 #endif
 85 };
 86 
 87 static int wm5100_sr_code[] = {
 88         0,
 89         12000,
 90         24000,
 91         48000,
 92         96000,
 93         192000,
 94         384000,
 95         768000,
 96         0,
 97         11025,
 98         22050,
 99         44100,
100         88200,
101         176400,
102         352800,
103         705600,
104         4000,
105         8000,
106         16000,
107         32000,
108         64000,
109         128000,
110         256000,
111         512000,
112 };
113 
114 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
115         WM5100_CLOCKING_4,
116         WM5100_CLOCKING_5,
117         WM5100_CLOCKING_6,
118 };
119 
120 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
121 {
122         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
123         int sr_code, sr_free, i;
124 
125         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
126                 if (wm5100_sr_code[i] == rate)
127                         break;
128         if (i == ARRAY_SIZE(wm5100_sr_code)) {
129                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
130                 return -EINVAL;
131         }
132         sr_code = i;
133 
134         if ((wm5100->sysclk % rate) == 0) {
135                 /* Is this rate already in use? */
136                 sr_free = -1;
137                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
138                         if (!wm5100->sr_ref[i] && sr_free == -1) {
139                                 sr_free = i;
140                                 continue;
141                         }
142                         if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
143                              WM5100_SAMPLE_RATE_1_MASK) == sr_code)
144                                 break;
145                 }
146 
147                 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
148                         wm5100->sr_ref[i]++;
149                         dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
150                                 rate, i, wm5100->sr_ref[i]);
151                         return i;
152                 }
153 
154                 if (sr_free == -1) {
155                         dev_err(codec->dev, "All SR slots already in use\n");
156                         return -EBUSY;
157                 }
158 
159                 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
160                         sr_free, rate);
161                 wm5100->sr_ref[sr_free]++;
162                 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
163                                     WM5100_SAMPLE_RATE_1_MASK,
164                                     sr_code);
165 
166                 return sr_free;
167 
168         } else {
169                 dev_err(codec->dev,
170                         "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171                         rate, wm5100->sysclk, wm5100->asyncclk);
172                 return -EINVAL;
173         }
174 }
175 
176 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
177 {
178         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
179         int i, sr_code;
180 
181         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
182                 if (wm5100_sr_code[i] == rate)
183                         break;
184         if (i == ARRAY_SIZE(wm5100_sr_code)) {
185                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
186                 return;
187         }
188         sr_code = wm5100_sr_code[i];
189 
190         for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
191                 if (!wm5100->sr_ref[i])
192                         continue;
193 
194                 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
195                      WM5100_SAMPLE_RATE_1_MASK) == sr_code)
196                         break;
197         }
198         if (i < ARRAY_SIZE(wm5100_sr_regs)) {
199                 wm5100->sr_ref[i]--;
200                 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
201                         rate, wm5100->sr_ref[i]);
202         } else {
203                 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
204                          rate);
205         }
206 }
207 
208 static int wm5100_reset(struct wm5100_priv *wm5100)
209 {
210         if (wm5100->pdata.reset) {
211                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
212                 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
213 
214                 return 0;
215         } else {
216                 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
217         }
218 }
219 
220 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
221 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
222 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
223 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
224 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
225 
226 static const char *wm5100_mixer_texts[] = {
227         "None",
228         "Tone Generator 1",
229         "Tone Generator 2",
230         "AEC loopback",
231         "IN1L",
232         "IN1R",
233         "IN2L",
234         "IN2R",
235         "IN3L",
236         "IN3R",
237         "IN4L",
238         "IN4R",
239         "AIF1RX1",
240         "AIF1RX2",
241         "AIF1RX3",
242         "AIF1RX4",
243         "AIF1RX5",
244         "AIF1RX6",
245         "AIF1RX7",
246         "AIF1RX8",
247         "AIF2RX1",
248         "AIF2RX2",
249         "AIF3RX1",
250         "AIF3RX2",
251         "EQ1",
252         "EQ2",
253         "EQ3",
254         "EQ4",
255         "DRC1L",
256         "DRC1R",
257         "LHPF1",
258         "LHPF2",
259         "LHPF3",
260         "LHPF4",
261         "DSP1.1",
262         "DSP1.2",
263         "DSP1.3",
264         "DSP1.4",
265         "DSP1.5",
266         "DSP1.6",
267         "DSP2.1",
268         "DSP2.2",
269         "DSP2.3",
270         "DSP2.4",
271         "DSP2.5",
272         "DSP2.6",
273         "DSP3.1",
274         "DSP3.2",
275         "DSP3.3",
276         "DSP3.4",
277         "DSP3.5",
278         "DSP3.6",
279         "ASRC1L",
280         "ASRC1R",
281         "ASRC2L",
282         "ASRC2R",
283         "ISRC1INT1",
284         "ISRC1INT2",
285         "ISRC1INT3",
286         "ISRC1INT4",
287         "ISRC2INT1",
288         "ISRC2INT2",
289         "ISRC2INT3",
290         "ISRC2INT4",
291         "ISRC1DEC1",
292         "ISRC1DEC2",
293         "ISRC1DEC3",
294         "ISRC1DEC4",
295         "ISRC2DEC1",
296         "ISRC2DEC2",
297         "ISRC2DEC3",
298         "ISRC2DEC4",
299 };
300 
301 static int wm5100_mixer_values[] = {
302         0x00,
303         0x04,   /* Tone */
304         0x05,
305         0x08,   /* AEC */
306         0x10,   /* Input */
307         0x11,
308         0x12,
309         0x13,
310         0x14,
311         0x15,
312         0x16,
313         0x17,
314         0x20,   /* AIF */
315         0x21,
316         0x22,
317         0x23,
318         0x24,
319         0x25,
320         0x26,
321         0x27,
322         0x28,
323         0x29,
324         0x30,   /* AIF3 - check */
325         0x31,
326         0x50,   /* EQ */
327         0x51,
328         0x52,
329         0x53,
330         0x54,
331         0x58,   /* DRC */
332         0x59,
333         0x60,   /* LHPF1 */
334         0x61,   /* LHPF2 */
335         0x62,   /* LHPF3 */
336         0x63,   /* LHPF4 */
337         0x68,   /* DSP1 */
338         0x69,
339         0x6a,
340         0x6b,
341         0x6c,
342         0x6d,
343         0x70,   /* DSP2 */
344         0x71,
345         0x72,
346         0x73,
347         0x74,
348         0x75,
349         0x78,   /* DSP3 */
350         0x79,
351         0x7a,
352         0x7b,
353         0x7c,
354         0x7d,
355         0x90,   /* ASRC1 */
356         0x91,
357         0x92,   /* ASRC2 */
358         0x93,
359         0xa0,   /* ISRC1DEC1 */
360         0xa1,
361         0xa2,
362         0xa3,
363         0xa4,   /* ISRC1INT1 */
364         0xa5,
365         0xa6,
366         0xa7,
367         0xa8,   /* ISRC2DEC1 */
368         0xa9,
369         0xaa,
370         0xab,
371         0xac,   /* ISRC2INT1 */
372         0xad,
373         0xae,
374         0xaf,
375 };
376 
377 #define WM5100_MIXER_CONTROLS(name, base) \
378         SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380         SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382         SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384         SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
386 
387 #define WM5100_MUX_ENUM_DECL(name, reg) \
388         SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff,                  \
389                                    wm5100_mixer_texts, wm5100_mixer_values)
390 
391 #define WM5100_MUX_CTL_DECL(name) \
392         const struct snd_kcontrol_new name##_mux =      \
393                 SOC_DAPM_ENUM("Route", name##_enum)
394 
395 #define WM5100_MIXER_ENUMS(name, base_reg) \
396         static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg);      \
397         static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2);  \
398         static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4);  \
399         static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6);  \
400         static WM5100_MUX_CTL_DECL(name##_in1); \
401         static WM5100_MUX_CTL_DECL(name##_in2); \
402         static WM5100_MUX_CTL_DECL(name##_in3); \
403         static WM5100_MUX_CTL_DECL(name##_in4) 
404 
405 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
406 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
407 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
408 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
409 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
410 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
411 
412 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
413 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
414 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
415 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
416 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
417 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
418 
419 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
420 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
421 
422 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
423 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
424 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
425 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
426 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
427 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
428 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
429 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
430 
431 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
432 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
433 
434 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
435 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
436 
437 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
438 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
439 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
440 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
441 
442 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
443 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
444 
445 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
446 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
447 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
448 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449 
450 #define WM5100_MUX(name, ctrl) \
451         SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
452 
453 #define WM5100_MIXER_WIDGETS(name, name_str)    \
454         WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455         WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456         WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457         WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458         SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
459 
460 #define WM5100_MIXER_INPUT_ROUTES(name) \
461         { name, "Tone Generator 1", "Tone Generator 1" }, \
462         { name, "Tone Generator 2", "Tone Generator 2" }, \
463         { name, "IN1L", "IN1L PGA" }, \
464         { name, "IN1R", "IN1R PGA" }, \
465         { name, "IN2L", "IN2L PGA" }, \
466         { name, "IN2R", "IN2R PGA" }, \
467         { name, "IN3L", "IN3L PGA" }, \
468         { name, "IN3R", "IN3R PGA" }, \
469         { name, "IN4L", "IN4L PGA" }, \
470         { name, "IN4R", "IN4R PGA" }, \
471         { name, "AIF1RX1", "AIF1RX1" }, \
472         { name, "AIF1RX2", "AIF1RX2" }, \
473         { name, "AIF1RX3", "AIF1RX3" }, \
474         { name, "AIF1RX4", "AIF1RX4" }, \
475         { name, "AIF1RX5", "AIF1RX5" }, \
476         { name, "AIF1RX6", "AIF1RX6" }, \
477         { name, "AIF1RX7", "AIF1RX7" }, \
478         { name, "AIF1RX8", "AIF1RX8" }, \
479         { name, "AIF2RX1", "AIF2RX1" }, \
480         { name, "AIF2RX2", "AIF2RX2" }, \
481         { name, "AIF3RX1", "AIF3RX1" }, \
482         { name, "AIF3RX2", "AIF3RX2" }, \
483         { name, "EQ1", "EQ1" }, \
484         { name, "EQ2", "EQ2" }, \
485         { name, "EQ3", "EQ3" }, \
486         { name, "EQ4", "EQ4" }, \
487         { name, "DRC1L", "DRC1L" }, \
488         { name, "DRC1R", "DRC1R" }, \
489         { name, "LHPF1", "LHPF1" }, \
490         { name, "LHPF2", "LHPF2" }, \
491         { name, "LHPF3", "LHPF3" }, \
492         { name, "LHPF4", "LHPF4" }
493 
494 #define WM5100_MIXER_ROUTES(widget, name) \
495         { widget, NULL, name " Mixer" },         \
496         { name " Mixer", NULL, name " Input 1" }, \
497         { name " Mixer", NULL, name " Input 2" }, \
498         { name " Mixer", NULL, name " Input 3" }, \
499         { name " Mixer", NULL, name " Input 4" }, \
500         WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501         WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502         WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503         WM5100_MIXER_INPUT_ROUTES(name " Input 4")
504 
505 static const char *wm5100_lhpf_mode_text[] = {
506         "Low-pass", "High-pass"
507 };
508 
509 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
510                             WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
511                             wm5100_lhpf_mode_text);
512 
513 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
514                             WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
515                             wm5100_lhpf_mode_text);
516 
517 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
518                             WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
519                             wm5100_lhpf_mode_text);
520 
521 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
522                             WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
523                             wm5100_lhpf_mode_text);
524 
525 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
526 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
527            WM5100_IN1_OSR_SHIFT, 1, 0),
528 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
529            WM5100_IN2_OSR_SHIFT, 1, 0),
530 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
531            WM5100_IN3_OSR_SHIFT, 1, 0),
532 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
533            WM5100_IN4_OSR_SHIFT, 1, 0),
534 
535 /* Only applicable for analogue inputs */
536 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
537                  WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
538 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
539                  WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
540 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
541                  WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
542 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
543                  WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
544 
545 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
546                  WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
547                  0, digital_tlv),
548 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
549                  WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
550                  0, digital_tlv),
551 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
552                  WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
553                  0, digital_tlv),
554 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
555                  WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
556                  0, digital_tlv),
557 
558 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
559              WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
560 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
561              WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
562 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
563              WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
564 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
565              WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
566 
567 SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
568 SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
569 SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
570 SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
571 
572 SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
573                    WM5100_DRCL_ENA | WM5100_DRCR_ENA),
574 
575 SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1),
576 SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1),
577 SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1),
578 SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1),
579 
580 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
581            WM5100_OUT1_OSR_SHIFT, 1, 0),
582 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
583            WM5100_OUT2_OSR_SHIFT, 1, 0),
584 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
585            WM5100_OUT3_OSR_SHIFT, 1, 0),
586 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
587            WM5100_OUT4_OSR_SHIFT, 1, 0),
588 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
589            WM5100_OUT5_OSR_SHIFT, 1, 0),
590 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
591            WM5100_OUT6_OSR_SHIFT, 1, 0),
592 
593 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
594                  WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
595                  digital_tlv),
596 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
597                  WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
598                  digital_tlv),
599 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
600                  WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
601                  digital_tlv),
602 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
603                  WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
604                  digital_tlv),
605 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
606                  WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
607                  digital_tlv),
608 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
609                  WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
610                  digital_tlv),
611 
612 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
613              WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
614 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
615              WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
616 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
617              WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
618 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
619              WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
620 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
621              WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
622 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
623              WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
624 
625 /* FIXME: Only valid from -12dB to 0dB (52-64) */
626 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
627                  WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
628 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
629                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
630 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
631                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
632 
633 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
634            WM5100_SPK1R_MUTE_SHIFT, 1, 1),
635 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
636            WM5100_SPK2R_MUTE_SHIFT, 1, 1),
637 
638 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
639                24, 0, eq_tlv),
640 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
641                24, 0, eq_tlv),
642 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
643                24, 0, eq_tlv),
644 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
645                24, 0, eq_tlv),
646 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
647                24, 0, eq_tlv),
648 
649 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
650                24, 0, eq_tlv),
651 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
652                24, 0, eq_tlv),
653 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
654                24, 0, eq_tlv),
655 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
656                24, 0, eq_tlv),
657 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
658                24, 0, eq_tlv),
659 
660 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
661                24, 0, eq_tlv),
662 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
663                24, 0, eq_tlv),
664 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
665                24, 0, eq_tlv),
666 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
667                24, 0, eq_tlv),
668 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
669                24, 0, eq_tlv),
670 
671 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
672                24, 0, eq_tlv),
673 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
674                24, 0, eq_tlv),
675 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
676                24, 0, eq_tlv),
677 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
678                24, 0, eq_tlv),
679 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
680                24, 0, eq_tlv),
681 
682 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
683 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
684 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
685 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
686 
687 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
688 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
689 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
690 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
691 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
692 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
693 
694 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
695 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
696 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
697 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
698 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
699 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
700 
701 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
702 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
703 
704 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
705 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
706 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
707 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
708 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
709 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
710 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
711 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
712 
713 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
714 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
715 
716 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
717 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
718 
719 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
720 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
721 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
722 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
723 
724 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
725 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
726 SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
727                    WM5100_DRCL_ENA | WM5100_DRCR_ENA),
728 
729 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
730 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
731 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
732 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
733 };
734 
735 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
736                                 enum snd_soc_dapm_type event, int subseq)
737 {
738         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
739         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
740         u16 val, expect, i;
741 
742         /* Wait for the outputs to flag themselves as enabled */
743         if (wm5100->out_ena[0]) {
744                 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
745                 for (i = 0; i < 200; i++) {
746                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
747                         if (val == expect) {
748                                 wm5100->out_ena[0] = false;
749                                 break;
750                         }
751                 }
752                 if (i == 200) {
753                         dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
754                                 expect);
755                 }
756         }
757 
758         if (wm5100->out_ena[1]) {
759                 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
760                 for (i = 0; i < 200; i++) {
761                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
762                         if (val == expect) {
763                                 wm5100->out_ena[1] = false;
764                                 break;
765                         }
766                 }
767                 if (i == 200) {
768                         dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
769                                 expect);
770                 }
771         }
772 }
773 
774 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
775                          struct snd_kcontrol *kcontrol,
776                          int event)
777 {
778         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
779         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
780 
781         switch (w->reg) {
782         case WM5100_CHANNEL_ENABLES_1:
783                 wm5100->out_ena[0] = true;
784                 break;
785         case WM5100_OUTPUT_ENABLES_2:
786                 wm5100->out_ena[0] = true;
787                 break;
788         default:
789                 break;
790         }
791 
792         return 0;
793 }
794 
795 static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
796 {
797         if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
798                 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
799         if (val & WM5100_SPK_SHUTDOWN_EINT)
800                 dev_crit(wm5100->dev, "Speaker shutdown\n");
801         if (val & WM5100_CLKGEN_ERR_EINT)
802                 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
803         if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
804                 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
805 }
806 
807 static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
808 {
809         if (val & WM5100_AIF3_ERR_EINT)
810                 dev_err(wm5100->dev, "AIF3 configuration error\n");
811         if (val & WM5100_AIF2_ERR_EINT)
812                 dev_err(wm5100->dev, "AIF2 configuration error\n");
813         if (val & WM5100_AIF1_ERR_EINT)
814                 dev_err(wm5100->dev, "AIF1 configuration error\n");
815         if (val & WM5100_CTRLIF_ERR_EINT)
816                 dev_err(wm5100->dev, "Control interface error\n");
817         if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
818                 dev_err(wm5100->dev, "ISRC2 underclocked\n");
819         if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
820                 dev_err(wm5100->dev, "ISRC1 underclocked\n");
821         if (val & WM5100_FX_UNDERCLOCKED_EINT)
822                 dev_err(wm5100->dev, "FX underclocked\n");
823         if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
824                 dev_err(wm5100->dev, "AIF3 underclocked\n");
825         if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
826                 dev_err(wm5100->dev, "AIF2 underclocked\n");
827         if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
828                 dev_err(wm5100->dev, "AIF1 underclocked\n");
829         if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
830                 dev_err(wm5100->dev, "ASRC underclocked\n");
831         if (val & WM5100_DAC_UNDERCLOCKED_EINT)
832                 dev_err(wm5100->dev, "DAC underclocked\n");
833         if (val & WM5100_ADC_UNDERCLOCKED_EINT)
834                 dev_err(wm5100->dev, "ADC underclocked\n");
835         if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
836                 dev_err(wm5100->dev, "Mixer underclocked\n");
837 }
838 
839 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
840                           struct snd_kcontrol *kcontrol,
841                           int event)
842 {
843         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
844         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
845         int ret;
846 
847         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
848         ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
849                 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
850                 WM5100_CLKGEN_ERR_ASYNC_STS;
851         wm5100_log_status3(wm5100, ret);
852 
853         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
854         wm5100_log_status4(wm5100, ret);
855 
856         return 0;
857 }
858 
859 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
860 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
861                     NULL, 0),
862 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
863                     0, NULL, 0),
864 
865 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
866 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
867 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
868 
869 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
870                     NULL, 0),
871 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
872                     NULL, 0),
873 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
874                     WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
875 
876 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
877                     0, NULL, 0),
878 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
879                     0, NULL, 0),
880 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
881                     0, NULL, 0),
882 
883 SND_SOC_DAPM_INPUT("IN1L"),
884 SND_SOC_DAPM_INPUT("IN1R"),
885 SND_SOC_DAPM_INPUT("IN2L"),
886 SND_SOC_DAPM_INPUT("IN2R"),
887 SND_SOC_DAPM_INPUT("IN3L"),
888 SND_SOC_DAPM_INPUT("IN3R"),
889 SND_SOC_DAPM_INPUT("IN4L"),
890 SND_SOC_DAPM_INPUT("IN4R"),
891 SND_SOC_DAPM_SIGGEN("TONE"),
892 
893 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
894                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
895 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
896                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
897 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
898                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
899 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
900                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
901 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
902                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
903 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
904                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
905 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
906                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
907 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
908                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
909 
910 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
911                  WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
912 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
913                  WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
914 
915 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
916                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
917 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
918                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
919 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
920                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
921 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
922                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
923 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
924                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
925 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
926                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
927 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
928                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
929 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
930                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
931 
932 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
933                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
934 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
935                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
936 
937 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
938                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
939 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
940                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
941 
942 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
943                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
944 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
945                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
946 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
947                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
948 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
949                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
950 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
951                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
952 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
953                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
954 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
955                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
956 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
957                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
958 
959 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
960                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
961 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
962                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
963 
964 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
965                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
966 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
967                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
968 
969 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
970                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
972                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
974                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
976                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
977 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
978                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
979 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
980                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
981 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
982                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
983 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
984                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
985 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
986                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
987 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
988                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
989 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
990                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
991 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
992                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
993 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
994                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
995 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
996                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
997 
998 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
999 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1002 
1003 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1004                  NULL, 0),
1005 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1006                  NULL, 0),
1007 
1008 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1009                  NULL, 0),
1010 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1011                  NULL, 0),
1012 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1013                  NULL, 0),
1014 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1015                  NULL, 0),
1016 
1017 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1018 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1019 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1020 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1021 
1022 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1023 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1024 
1025 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1026 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1027 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1028 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1029 
1030 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1031 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1032 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1033 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1034 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1035 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1036 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1037 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1038 
1039 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1040 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1041 
1042 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1043 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1044 
1045 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1046 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1047 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1048 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1049 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1050 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1051 
1052 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1053 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1054 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1055 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1056 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1057 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1058 
1059 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1060 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1061 
1062 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1063 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1067 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1068 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1069 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1070 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1071 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1072 SND_SOC_DAPM_OUTPUT("PWM1"),
1073 SND_SOC_DAPM_OUTPUT("PWM2"),
1074 };
1075 
1076 /* We register a _POST event if we don't have IRQ support so we can
1077  * look at the error status from the CODEC - if we've got the IRQ
1078  * hooked up then we will get prompted to look by an interrupt.
1079  */
1080 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1081 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1082 };
1083 
1084 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1085         { "CP1", NULL, "CPVDD" },
1086         { "CP2 Active", NULL, "CPVDD" },
1087 
1088         { "IN1L", NULL, "SYSCLK" },
1089         { "IN1R", NULL, "SYSCLK" },
1090         { "IN2L", NULL, "SYSCLK" },
1091         { "IN2R", NULL, "SYSCLK" },
1092         { "IN3L", NULL, "SYSCLK" },
1093         { "IN3R", NULL, "SYSCLK" },
1094         { "IN4L", NULL, "SYSCLK" },
1095         { "IN4R", NULL, "SYSCLK" },
1096 
1097         { "OUT1L", NULL, "SYSCLK" },
1098         { "OUT1R", NULL, "SYSCLK" },
1099         { "OUT2L", NULL, "SYSCLK" },
1100         { "OUT2R", NULL, "SYSCLK" },
1101         { "OUT3L", NULL, "SYSCLK" },
1102         { "OUT3R", NULL, "SYSCLK" },
1103         { "OUT4L", NULL, "SYSCLK" },
1104         { "OUT4R", NULL, "SYSCLK" },
1105         { "OUT5L", NULL, "SYSCLK" },
1106         { "OUT5R", NULL, "SYSCLK" },
1107         { "OUT6L", NULL, "SYSCLK" },
1108         { "OUT6R", NULL, "SYSCLK" },
1109 
1110         { "AIF1RX1", NULL, "SYSCLK" },
1111         { "AIF1RX2", NULL, "SYSCLK" },
1112         { "AIF1RX3", NULL, "SYSCLK" },
1113         { "AIF1RX4", NULL, "SYSCLK" },
1114         { "AIF1RX5", NULL, "SYSCLK" },
1115         { "AIF1RX6", NULL, "SYSCLK" },
1116         { "AIF1RX7", NULL, "SYSCLK" },
1117         { "AIF1RX8", NULL, "SYSCLK" },
1118 
1119         { "AIF2RX1", NULL, "SYSCLK" },
1120         { "AIF2RX1", NULL, "DBVDD2" },
1121         { "AIF2RX2", NULL, "SYSCLK" },
1122         { "AIF2RX2", NULL, "DBVDD2" },
1123 
1124         { "AIF3RX1", NULL, "SYSCLK" },
1125         { "AIF3RX1", NULL, "DBVDD3" },
1126         { "AIF3RX2", NULL, "SYSCLK" },
1127         { "AIF3RX2", NULL, "DBVDD3" },
1128 
1129         { "AIF1TX1", NULL, "SYSCLK" },
1130         { "AIF1TX2", NULL, "SYSCLK" },
1131         { "AIF1TX3", NULL, "SYSCLK" },
1132         { "AIF1TX4", NULL, "SYSCLK" },
1133         { "AIF1TX5", NULL, "SYSCLK" },
1134         { "AIF1TX6", NULL, "SYSCLK" },
1135         { "AIF1TX7", NULL, "SYSCLK" },
1136         { "AIF1TX8", NULL, "SYSCLK" },
1137 
1138         { "AIF2TX1", NULL, "SYSCLK" },
1139         { "AIF2TX1", NULL, "DBVDD2" },
1140         { "AIF2TX2", NULL, "SYSCLK" },
1141         { "AIF2TX2", NULL, "DBVDD2" },
1142 
1143         { "AIF3TX1", NULL, "SYSCLK" },
1144         { "AIF3TX1", NULL, "DBVDD3" },
1145         { "AIF3TX2", NULL, "SYSCLK" },
1146         { "AIF3TX2", NULL, "DBVDD3" },
1147 
1148         { "MICBIAS1", NULL, "CP2" },
1149         { "MICBIAS2", NULL, "CP2" },
1150         { "MICBIAS3", NULL, "CP2" },
1151 
1152         { "IN1L PGA", NULL, "CP2" },
1153         { "IN1R PGA", NULL, "CP2" },
1154         { "IN2L PGA", NULL, "CP2" },
1155         { "IN2R PGA", NULL, "CP2" },
1156         { "IN3L PGA", NULL, "CP2" },
1157         { "IN3R PGA", NULL, "CP2" },
1158         { "IN4L PGA", NULL, "CP2" },
1159         { "IN4R PGA", NULL, "CP2" },
1160 
1161         { "IN1L PGA", NULL, "CP2 Active" },
1162         { "IN1R PGA", NULL, "CP2 Active" },
1163         { "IN2L PGA", NULL, "CP2 Active" },
1164         { "IN2R PGA", NULL, "CP2 Active" },
1165         { "IN3L PGA", NULL, "CP2 Active" },
1166         { "IN3R PGA", NULL, "CP2 Active" },
1167         { "IN4L PGA", NULL, "CP2 Active" },
1168         { "IN4R PGA", NULL, "CP2 Active" },
1169 
1170         { "OUT1L", NULL, "CP1" },
1171         { "OUT1R", NULL, "CP1" },
1172         { "OUT2L", NULL, "CP1" },
1173         { "OUT2R", NULL, "CP1" },
1174         { "OUT3L", NULL, "CP1" },
1175         { "OUT3R", NULL, "CP1" },
1176 
1177         { "Tone Generator 1", NULL, "TONE" },
1178         { "Tone Generator 2", NULL, "TONE" },
1179 
1180         { "IN1L PGA", NULL, "IN1L" },
1181         { "IN1R PGA", NULL, "IN1R" },
1182         { "IN2L PGA", NULL, "IN2L" },
1183         { "IN2R PGA", NULL, "IN2R" },
1184         { "IN3L PGA", NULL, "IN3L" },
1185         { "IN3R PGA", NULL, "IN3R" },
1186         { "IN4L PGA", NULL, "IN4L" },
1187         { "IN4R PGA", NULL, "IN4R" },
1188 
1189         WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1190         WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1191         WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1192         WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1193         WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1194         WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1195 
1196         WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1197         WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1198         WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1199         WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1200         WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1201         WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1202 
1203         WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1204         WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1205 
1206         WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1207         WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1208         WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1209         WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1210         WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1211         WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1212         WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1213         WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1214 
1215         WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1216         WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1217 
1218         WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1219         WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1220 
1221         WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1222         WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1223         WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1224         WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1225 
1226         WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1227         WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1228 
1229         WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1230         WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1231         WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1232         WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1233 
1234         { "HPOUT1L", NULL, "OUT1L" },
1235         { "HPOUT1R", NULL, "OUT1R" },
1236         { "HPOUT2L", NULL, "OUT2L" },
1237         { "HPOUT2R", NULL, "OUT2R" },
1238         { "HPOUT3L", NULL, "OUT3L" },
1239         { "HPOUT3R", NULL, "OUT3R" },
1240         { "SPKOUTL", NULL, "OUT4L" },
1241         { "SPKOUTR", NULL, "OUT4R" },
1242         { "SPKDAT1", NULL, "OUT5L" },
1243         { "SPKDAT1", NULL, "OUT5R" },
1244         { "SPKDAT2", NULL, "OUT6L" },
1245         { "SPKDAT2", NULL, "OUT6R" },
1246         { "PWM1", NULL, "PWM1 Driver" },
1247         { "PWM2", NULL, "PWM2 Driver" },
1248 };
1249 
1250 static const struct reg_default wm5100_reva_patches[] = {
1251         { WM5100_AUDIO_IF_1_10, 0 },
1252         { WM5100_AUDIO_IF_1_11, 1 },
1253         { WM5100_AUDIO_IF_1_12, 2 },
1254         { WM5100_AUDIO_IF_1_13, 3 },
1255         { WM5100_AUDIO_IF_1_14, 4 },
1256         { WM5100_AUDIO_IF_1_15, 5 },
1257         { WM5100_AUDIO_IF_1_16, 6 },
1258         { WM5100_AUDIO_IF_1_17, 7 },
1259 
1260         { WM5100_AUDIO_IF_1_18, 0 },
1261         { WM5100_AUDIO_IF_1_19, 1 },
1262         { WM5100_AUDIO_IF_1_20, 2 },
1263         { WM5100_AUDIO_IF_1_21, 3 },
1264         { WM5100_AUDIO_IF_1_22, 4 },
1265         { WM5100_AUDIO_IF_1_23, 5 },
1266         { WM5100_AUDIO_IF_1_24, 6 },
1267         { WM5100_AUDIO_IF_1_25, 7 },
1268 
1269         { WM5100_AUDIO_IF_2_10, 0 },
1270         { WM5100_AUDIO_IF_2_11, 1 },
1271 
1272         { WM5100_AUDIO_IF_2_18, 0 },
1273         { WM5100_AUDIO_IF_2_19, 1 },
1274 
1275         { WM5100_AUDIO_IF_3_10, 0 },
1276         { WM5100_AUDIO_IF_3_11, 1 },
1277 
1278         { WM5100_AUDIO_IF_3_18, 0 },
1279         { WM5100_AUDIO_IF_3_19, 1 },
1280 };
1281 
1282 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1283 {
1284         struct snd_soc_codec *codec = dai->codec;
1285         int lrclk, bclk, mask, base;
1286 
1287         base = dai->driver->base;
1288 
1289         lrclk = 0;
1290         bclk = 0;
1291 
1292         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1293         case SND_SOC_DAIFMT_DSP_A:
1294                 mask = 0;
1295                 break;
1296         case SND_SOC_DAIFMT_I2S:
1297                 mask = 2;
1298                 break;
1299         default:
1300                 dev_err(codec->dev, "Unsupported DAI format %d\n",
1301                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1302                 return -EINVAL;
1303         }
1304 
1305         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1306         case SND_SOC_DAIFMT_CBS_CFS:
1307                 break;
1308         case SND_SOC_DAIFMT_CBS_CFM:
1309                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1310                 break;
1311         case SND_SOC_DAIFMT_CBM_CFS:
1312                 bclk |= WM5100_AIF1_BCLK_MSTR;
1313                 break;
1314         case SND_SOC_DAIFMT_CBM_CFM:
1315                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1316                 bclk |= WM5100_AIF1_BCLK_MSTR;
1317                 break;
1318         default:
1319                 dev_err(codec->dev, "Unsupported master mode %d\n",
1320                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
1321                 return -EINVAL;
1322         }
1323 
1324         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1325         case SND_SOC_DAIFMT_NB_NF:
1326                 break;
1327         case SND_SOC_DAIFMT_IB_IF:
1328                 bclk |= WM5100_AIF1_BCLK_INV;
1329                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1330                 break;
1331         case SND_SOC_DAIFMT_IB_NF:
1332                 bclk |= WM5100_AIF1_BCLK_INV;
1333                 break;
1334         case SND_SOC_DAIFMT_NB_IF:
1335                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1336                 break;
1337         default:
1338                 return -EINVAL;
1339         }
1340 
1341         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1342                             WM5100_AIF1_BCLK_INV, bclk);
1343         snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1344                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1345         snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1346                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1347         snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1348 
1349         return 0;
1350 }
1351 
1352 #define WM5100_NUM_BCLK_RATES 19
1353 
1354 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1355         32000,
1356         48000,
1357         64000,
1358         96000,
1359         128000,
1360         192000,
1361         256000,
1362         384000,
1363         512000,
1364         768000,
1365         1024000,
1366         1536000,
1367         2048000,
1368         3072000,
1369         4096000,
1370         6144000,
1371         8192000,
1372         12288000,
1373         24576000,
1374 };
1375 
1376 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1377         29400,
1378         44100,
1379         58800,
1380         88200,
1381         117600,
1382         176400,
1383         235200,
1384         352800,
1385         470400,
1386         705600,
1387         940800,
1388         1411200,
1389         1881600,
1390         2882400,
1391         3763200,
1392         5644800,
1393         7526400,
1394         11289600,
1395         22579600,
1396 };
1397 
1398 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1399                             struct snd_pcm_hw_params *params,
1400                             struct snd_soc_dai *dai)
1401 {
1402         struct snd_soc_codec *codec = dai->codec;
1403         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1404         bool async = wm5100->aif_async[dai->id];
1405         int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1406         int *bclk_rates;
1407 
1408         base = dai->driver->base;
1409 
1410         /* Data sizes if not using TDM */
1411         wl = snd_pcm_format_width(params_format(params));
1412         if (wl < 0)
1413                 return wl;
1414         fl = snd_soc_params_to_frame_size(params);
1415         if (fl < 0)
1416                 return fl;
1417 
1418         dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1419                 wl, fl);
1420 
1421         /* Target BCLK rate */
1422         bclk = snd_soc_params_to_bclk(params);
1423         if (bclk < 0)
1424                 return bclk;
1425 
1426         /* Root for BCLK depends on SYS/ASYNCCLK */
1427         if (!async) {
1428                 aif_rate = wm5100->sysclk;
1429                 sr = wm5100_alloc_sr(codec, params_rate(params));
1430                 if (sr < 0)
1431                         return sr;
1432         } else {
1433                 /* If we're in ASYNCCLK set the ASYNC sample rate */
1434                 aif_rate = wm5100->asyncclk;
1435                 sr = 3;
1436 
1437                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1438                         if (params_rate(params) == wm5100_sr_code[i])
1439                                 break;
1440                 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1441                         dev_err(codec->dev, "Invalid rate %dHzn",
1442                                 params_rate(params));
1443                         return -EINVAL;
1444                 }
1445 
1446                 /* TODO: We should really check for symmetry */
1447                 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1448                                     WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1449         }
1450 
1451         if (!aif_rate) {
1452                 dev_err(codec->dev, "%s has no rate set\n",
1453                         async ? "ASYNCCLK" : "SYSCLK");
1454                 return -EINVAL;
1455         }
1456 
1457         dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1458                 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1459 
1460         if (aif_rate % 4000)
1461                 bclk_rates = wm5100_bclk_rates_cd;
1462         else
1463                 bclk_rates = wm5100_bclk_rates_dat;
1464 
1465         for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1466                 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1467                         break;
1468         if (i == WM5100_NUM_BCLK_RATES) {
1469                 dev_err(codec->dev,
1470                         "No valid BCLK for %dHz found from %dHz %s\n",
1471                         bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1472                 return -EINVAL;
1473         }
1474 
1475         bclk = i;
1476         dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1477         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1478 
1479         lrclk = bclk_rates[bclk] / params_rate(params);
1480         dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1481         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1482             wm5100->aif_symmetric[dai->id])
1483                 snd_soc_update_bits(codec, base + 7,
1484                                     WM5100_AIF1RX_BCPF_MASK, lrclk);
1485         else
1486                 snd_soc_update_bits(codec, base + 6,
1487                                     WM5100_AIF1TX_BCPF_MASK, lrclk);
1488 
1489         i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1490         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1491                 snd_soc_update_bits(codec, base + 9,
1492                                     WM5100_AIF1RX_WL_MASK |
1493                                     WM5100_AIF1RX_SLOT_LEN_MASK, i);
1494         else
1495                 snd_soc_update_bits(codec, base + 8,
1496                                     WM5100_AIF1TX_WL_MASK |
1497                                     WM5100_AIF1TX_SLOT_LEN_MASK, i);
1498 
1499         snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1500 
1501         return 0;
1502 }
1503 
1504 static const struct snd_soc_dai_ops wm5100_dai_ops = {
1505         .set_fmt = wm5100_set_fmt,
1506         .hw_params = wm5100_hw_params,
1507 };
1508 
1509 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1510                              int source, unsigned int freq, int dir)
1511 {
1512         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1513         int *rate_store;
1514         int fval, audio_rate, ret, reg;
1515 
1516         switch (clk_id) {
1517         case WM5100_CLK_SYSCLK:
1518                 reg = WM5100_CLOCKING_3;
1519                 rate_store = &wm5100->sysclk;
1520                 break;
1521         case WM5100_CLK_ASYNCCLK:
1522                 reg = WM5100_CLOCKING_7;
1523                 rate_store = &wm5100->asyncclk;
1524                 break;
1525         case WM5100_CLK_32KHZ:
1526                 /* The 32kHz clock is slightly different to the others */
1527                 switch (source) {
1528                 case WM5100_CLKSRC_MCLK1:
1529                 case WM5100_CLKSRC_MCLK2:
1530                 case WM5100_CLKSRC_SYSCLK:
1531                         snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1532                                             WM5100_CLK_32K_SRC_MASK,
1533                                             source);
1534                         break;
1535                 default:
1536                         return -EINVAL;
1537                 }
1538                 return 0;
1539 
1540         case WM5100_CLK_AIF1:
1541         case WM5100_CLK_AIF2:
1542         case WM5100_CLK_AIF3:
1543                 /* Not real clocks, record which clock domain they're in */
1544                 switch (source) {
1545                 case WM5100_CLKSRC_SYSCLK:
1546                         wm5100->aif_async[clk_id - 1] = false;
1547                         break;
1548                 case WM5100_CLKSRC_ASYNCCLK:
1549                         wm5100->aif_async[clk_id - 1] = true;
1550                         break;
1551                 default:
1552                         dev_err(codec->dev, "Invalid source %d\n", source);
1553                         return -EINVAL;
1554                 }       
1555                 return 0;
1556 
1557         case WM5100_CLK_OPCLK:
1558                 switch (freq) {
1559                 case 5644800:
1560                 case 6144000:
1561                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1562                                             WM5100_OPCLK_SEL_MASK, 0);
1563                         break;
1564                 case 11289600:
1565                 case 12288000:
1566                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1567                                             WM5100_OPCLK_SEL_MASK, 0);
1568                         break;
1569                 case 22579200:
1570                 case 24576000:
1571                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1572                                             WM5100_OPCLK_SEL_MASK, 0);
1573                         break;
1574                 default:
1575                         dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1576                                 freq);
1577                         return -EINVAL;
1578                 }
1579                 return 0;
1580 
1581         default:
1582                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1583                 return -EINVAL;
1584         }
1585 
1586         switch (source) {
1587         case WM5100_CLKSRC_SYSCLK:
1588         case WM5100_CLKSRC_ASYNCCLK:
1589                 dev_err(codec->dev, "Invalid source %d\n", source);
1590                 return -EINVAL;
1591         }
1592 
1593         switch (freq) {
1594         case 5644800:
1595         case 6144000:
1596                 fval = 0;
1597                 break;
1598         case 11289600:
1599         case 12288000:
1600                 fval = 1;
1601                 break;
1602         case 22579200:
1603         case 24576000:
1604                 fval = 2;
1605                 break;
1606         default:
1607                 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1608                 return -EINVAL;
1609         }
1610 
1611         switch (freq) {
1612         case 5644800:
1613         case 11289600:
1614         case 22579200:
1615                 audio_rate = 44100;
1616                 break;
1617 
1618         case 6144000:
1619         case 12288000:
1620         case 24576000:
1621                 audio_rate = 48000;
1622                 break;
1623 
1624         default:
1625                 BUG();
1626                 audio_rate = 0;
1627                 break;
1628         }
1629 
1630         /* TODO: Check if MCLKs are in use and enable/disable pulls to
1631          * match.
1632          */
1633 
1634         snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1635                             WM5100_SYSCLK_SRC_MASK,
1636                             fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1637 
1638         /* If this is SYSCLK then configure the clock rate for the
1639          * internal audio functions to the natural sample rate for
1640          * this clock rate.
1641          */
1642         if (clk_id == WM5100_CLK_SYSCLK) {
1643                 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1644                         audio_rate);
1645                 if (0 && *rate_store)
1646                         wm5100_free_sr(codec, audio_rate);
1647                 ret = wm5100_alloc_sr(codec, audio_rate);
1648                 if (ret != 0)
1649                         dev_warn(codec->dev, "Primary audio slot is %d\n",
1650                                  ret);
1651         }
1652 
1653         *rate_store = freq;
1654 
1655         return 0;
1656 }
1657 
1658 struct _fll_div {
1659         u16 fll_fratio;
1660         u16 fll_outdiv;
1661         u16 fll_refclk_div;
1662         u16 n;
1663         u16 theta;
1664         u16 lambda;
1665 };
1666 
1667 static struct {
1668         unsigned int min;
1669         unsigned int max;
1670         u16 fll_fratio;
1671         int ratio;
1672 } fll_fratios[] = {
1673         {       0,    64000, 4, 16 },
1674         {   64000,   128000, 3,  8 },
1675         {  128000,   256000, 2,  4 },
1676         {  256000,  1000000, 1,  2 },
1677         { 1000000, 13500000, 0,  1 },
1678 };
1679 
1680 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1681                        unsigned int Fout)
1682 {
1683         unsigned int target;
1684         unsigned int div;
1685         unsigned int fratio, gcd_fll;
1686         int i;
1687 
1688         /* Fref must be <=13.5MHz */
1689         div = 1;
1690         fll_div->fll_refclk_div = 0;
1691         while ((Fref / div) > 13500000) {
1692                 div *= 2;
1693                 fll_div->fll_refclk_div++;
1694 
1695                 if (div > 8) {
1696                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1697                                Fref);
1698                         return -EINVAL;
1699                 }
1700         }
1701 
1702         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1703 
1704         /* Apply the division for our remaining calculations */
1705         Fref /= div;
1706 
1707         /* Fvco should be 90-100MHz; don't check the upper bound */
1708         div = 2;
1709         while (Fout * div < 90000000) {
1710                 div++;
1711                 if (div > 64) {
1712                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1713                                Fout);
1714                         return -EINVAL;
1715                 }
1716         }
1717         target = Fout * div;
1718         fll_div->fll_outdiv = div - 1;
1719 
1720         pr_debug("FLL Fvco=%dHz\n", target);
1721 
1722         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1723         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1724                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1725                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1726                         fratio = fll_fratios[i].ratio;
1727                         break;
1728                 }
1729         }
1730         if (i == ARRAY_SIZE(fll_fratios)) {
1731                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1732                 return -EINVAL;
1733         }
1734 
1735         fll_div->n = target / (fratio * Fref);
1736 
1737         if (target % Fref == 0) {
1738                 fll_div->theta = 0;
1739                 fll_div->lambda = 0;
1740         } else {
1741                 gcd_fll = gcd(target, fratio * Fref);
1742 
1743                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1744                         / gcd_fll;
1745                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1746         }
1747 
1748         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1749                  fll_div->n, fll_div->theta, fll_div->lambda);
1750         pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1751                  fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1752                  fll_div->fll_refclk_div);
1753 
1754         return 0;
1755 }
1756 
1757 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1758                           unsigned int Fref, unsigned int Fout)
1759 {
1760         struct i2c_client *i2c = to_i2c_client(codec->dev);
1761         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1762         struct _fll_div factors;
1763         struct wm5100_fll *fll;
1764         int ret, base, lock, i, timeout;
1765 
1766         switch (fll_id) {
1767         case WM5100_FLL1:
1768                 fll = &wm5100->fll[0];
1769                 base = WM5100_FLL1_CONTROL_1 - 1;
1770                 lock = WM5100_FLL1_LOCK_STS;
1771                 break;
1772         case WM5100_FLL2:
1773                 fll = &wm5100->fll[1];
1774                 base = WM5100_FLL2_CONTROL_2 - 1;
1775                 lock = WM5100_FLL2_LOCK_STS;
1776                 break;
1777         default:
1778                 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1779                 return -EINVAL;
1780         }
1781 
1782         if (!Fout) {
1783                 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1784                 if (fll->fout)
1785                         pm_runtime_put(codec->dev);
1786                 fll->fout = 0;
1787                 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1788                 return 0;
1789         }
1790 
1791         switch (source) {
1792         case WM5100_FLL_SRC_MCLK1:
1793         case WM5100_FLL_SRC_MCLK2:
1794         case WM5100_FLL_SRC_FLL1:
1795         case WM5100_FLL_SRC_FLL2:
1796         case WM5100_FLL_SRC_AIF1BCLK:
1797         case WM5100_FLL_SRC_AIF2BCLK:
1798         case WM5100_FLL_SRC_AIF3BCLK:
1799                 break;
1800         default:
1801                 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1802                 return -EINVAL;
1803         }
1804 
1805         ret = fll_factors(&factors, Fref, Fout);
1806         if (ret < 0)
1807                 return ret;
1808 
1809         /* Disable the FLL while we reconfigure */
1810         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1811 
1812         snd_soc_update_bits(codec, base + 2,
1813                             WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1814                             (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1815                             factors.fll_fratio);
1816         snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1817                             factors.theta);
1818         snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1819         snd_soc_update_bits(codec, base + 6,
1820                             WM5100_FLL1_REFCLK_DIV_MASK |
1821                             WM5100_FLL1_REFCLK_SRC_MASK,
1822                             (factors.fll_refclk_div
1823                              << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1824         snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1825                             factors.lambda);
1826 
1827         /* Clear any pending completions */
1828         try_wait_for_completion(&fll->lock);
1829 
1830         pm_runtime_get_sync(codec->dev);
1831 
1832         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1833 
1834         if (i2c->irq)
1835                 timeout = 2;
1836         else
1837                 timeout = 50;
1838 
1839         snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1840                             WM5100_SYSCLK_ENA);
1841 
1842         /* Poll for the lock; will use interrupt when we can test */
1843         for (i = 0; i < timeout; i++) {
1844                 if (i2c->irq) {
1845                         ret = wait_for_completion_timeout(&fll->lock,
1846                                                           msecs_to_jiffies(25));
1847                         if (ret > 0)
1848                                 break;
1849                 } else {
1850                         msleep(1);
1851                 }
1852 
1853                 ret = snd_soc_read(codec,
1854                                    WM5100_INTERRUPT_RAW_STATUS_3);
1855                 if (ret < 0) {
1856                         dev_err(codec->dev,
1857                                 "Failed to read FLL status: %d\n",
1858                                 ret);
1859                         continue;
1860                 }
1861                 if (ret & lock)
1862                         break;
1863         }
1864         if (i == timeout) {
1865                 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1866                 pm_runtime_put(codec->dev);
1867                 return -ETIMEDOUT;
1868         }
1869 
1870         fll->src = source;
1871         fll->fref = Fref;
1872         fll->fout = Fout;
1873 
1874         dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1875                 Fref, Fout);
1876 
1877         return 0;
1878 }
1879 
1880 /* Actually go much higher */
1881 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1882 
1883 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1884                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1885 
1886 static struct snd_soc_dai_driver wm5100_dai[] = {
1887         {
1888                 .name = "wm5100-aif1",
1889                 .base = WM5100_AUDIO_IF_1_1 - 1,
1890                 .playback = {
1891                         .stream_name = "AIF1 Playback",
1892                         .channels_min = 2,
1893                         .channels_max = 2,
1894                         .rates = WM5100_RATES,
1895                         .formats = WM5100_FORMATS,
1896                 },
1897                 .capture = {
1898                          .stream_name = "AIF1 Capture",
1899                          .channels_min = 2,
1900                          .channels_max = 2,
1901                          .rates = WM5100_RATES,
1902                          .formats = WM5100_FORMATS,
1903                  },
1904                 .ops = &wm5100_dai_ops,
1905         },
1906         {
1907                 .name = "wm5100-aif2",
1908                 .id = 1,
1909                 .base = WM5100_AUDIO_IF_2_1 - 1,
1910                 .playback = {
1911                         .stream_name = "AIF2 Playback",
1912                         .channels_min = 2,
1913                         .channels_max = 2,
1914                         .rates = WM5100_RATES,
1915                         .formats = WM5100_FORMATS,
1916                 },
1917                 .capture = {
1918                          .stream_name = "AIF2 Capture",
1919                          .channels_min = 2,
1920                          .channels_max = 2,
1921                          .rates = WM5100_RATES,
1922                          .formats = WM5100_FORMATS,
1923                  },
1924                 .ops = &wm5100_dai_ops,
1925         },
1926         {
1927                 .name = "wm5100-aif3",
1928                 .id = 2,
1929                 .base = WM5100_AUDIO_IF_3_1 - 1,
1930                 .playback = {
1931                         .stream_name = "AIF3 Playback",
1932                         .channels_min = 2,
1933                         .channels_max = 2,
1934                         .rates = WM5100_RATES,
1935                         .formats = WM5100_FORMATS,
1936                 },
1937                 .capture = {
1938                          .stream_name = "AIF3 Capture",
1939                          .channels_min = 2,
1940                          .channels_max = 2,
1941                          .rates = WM5100_RATES,
1942                          .formats = WM5100_FORMATS,
1943                  },
1944                 .ops = &wm5100_dai_ops,
1945         },
1946 };
1947 
1948 static int wm5100_dig_vu[] = {
1949         WM5100_ADC_DIGITAL_VOLUME_1L,
1950         WM5100_ADC_DIGITAL_VOLUME_1R,
1951         WM5100_ADC_DIGITAL_VOLUME_2L,
1952         WM5100_ADC_DIGITAL_VOLUME_2R,
1953         WM5100_ADC_DIGITAL_VOLUME_3L,
1954         WM5100_ADC_DIGITAL_VOLUME_3R,
1955         WM5100_ADC_DIGITAL_VOLUME_4L,
1956         WM5100_ADC_DIGITAL_VOLUME_4R,
1957 
1958         WM5100_DAC_DIGITAL_VOLUME_1L,
1959         WM5100_DAC_DIGITAL_VOLUME_1R,
1960         WM5100_DAC_DIGITAL_VOLUME_2L,
1961         WM5100_DAC_DIGITAL_VOLUME_2R,
1962         WM5100_DAC_DIGITAL_VOLUME_3L,
1963         WM5100_DAC_DIGITAL_VOLUME_3R,
1964         WM5100_DAC_DIGITAL_VOLUME_4L,
1965         WM5100_DAC_DIGITAL_VOLUME_4R,
1966         WM5100_DAC_DIGITAL_VOLUME_5L,
1967         WM5100_DAC_DIGITAL_VOLUME_5R,
1968         WM5100_DAC_DIGITAL_VOLUME_6L,
1969         WM5100_DAC_DIGITAL_VOLUME_6R,
1970 };
1971 
1972 static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
1973 {
1974         struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1975 
1976         if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
1977                 return;
1978 
1979         gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
1980         regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1981                            WM5100_ACCDET_BIAS_SRC_MASK |
1982                            WM5100_ACCDET_SRC,
1983                            (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1984                            mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1985         regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1986                            WM5100_HPCOM_SRC,
1987                            mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
1988 
1989         wm5100->jack_mode = the_mode;
1990 
1991         dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
1992                 wm5100->jack_mode);
1993 }
1994 
1995 static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1996 {
1997         dev_dbg(wm5100->dev, "Headphone detected\n");
1998         wm5100->jack_detecting = false;
1999         snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2000                             SND_JACK_HEADPHONE);
2001 
2002         /* Increase the detection rate a bit for responsiveness. */
2003         regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2004                            WM5100_ACCDET_RATE_MASK,
2005                            7 << WM5100_ACCDET_RATE_SHIFT);
2006 }
2007 
2008 static void wm5100_micd_irq(struct wm5100_priv *wm5100)
2009 {
2010         unsigned int val;
2011         int ret;
2012 
2013         ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2014         if (ret != 0) {
2015                 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2016                         ret);
2017                 return;
2018         }
2019 
2020         dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
2021 
2022         if (!(val & WM5100_ACCDET_VALID)) {
2023                 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
2024                 return;
2025         }
2026 
2027         /* No accessory, reset everything and report removal */
2028         if (!(val & WM5100_ACCDET_STS)) {
2029                 dev_dbg(wm5100->dev, "Jack removal detected\n");
2030                 wm5100->jack_mic = false;
2031                 wm5100->jack_detecting = true;
2032                 wm5100->jack_flips = 0;
2033                 snd_soc_jack_report(wm5100->jack, 0,
2034                                     SND_JACK_LINEOUT | SND_JACK_HEADSET |
2035                                     SND_JACK_BTN_0);
2036 
2037                 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2038                                    WM5100_ACCDET_RATE_MASK,
2039                                    WM5100_ACCDET_RATE_MASK);
2040                 return;
2041         }
2042 
2043         /* If the measurement is very high we've got a microphone,
2044          * either we just detected one or if we already reported then
2045          * we've got a button release event.
2046          */
2047         if (val & 0x400) {
2048                 if (wm5100->jack_detecting) {
2049                         dev_dbg(wm5100->dev, "Microphone detected\n");
2050                         wm5100->jack_mic = true;
2051                         wm5100->jack_detecting = false;
2052                         snd_soc_jack_report(wm5100->jack,
2053                                             SND_JACK_HEADSET,
2054                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2055 
2056                         /* Increase poll rate to give better responsiveness
2057                          * for buttons */
2058                         regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2059                                            WM5100_ACCDET_RATE_MASK,
2060                                            5 << WM5100_ACCDET_RATE_SHIFT);
2061                 } else {
2062                         dev_dbg(wm5100->dev, "Mic button up\n");
2063                         snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2064                 }
2065 
2066                 return;
2067         }
2068 
2069         /* If we detected a lower impedence during initial startup
2070          * then we probably have the wrong polarity, flip it.  Don't
2071          * do this for the lowest impedences to speed up detection of
2072          * plain headphones and give up if neither polarity looks
2073          * sensible.
2074          */
2075         if (wm5100->jack_detecting && (val & 0x3f8)) {
2076                 wm5100->jack_flips++;
2077 
2078                 if (wm5100->jack_flips > 1)
2079                         wm5100_report_headphone(wm5100);
2080                 else
2081                         wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
2082 
2083                 return;
2084         }
2085 
2086         /* Don't distinguish between buttons, just report any low
2087          * impedence as BTN_0.
2088          */
2089         if (val & 0x3fc) {
2090                 if (wm5100->jack_mic) {
2091                         dev_dbg(wm5100->dev, "Mic button detected\n");
2092                         snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2093                                             SND_JACK_BTN_0);
2094                 } else if (wm5100->jack_detecting) {
2095                         wm5100_report_headphone(wm5100);
2096                 }
2097         }
2098 }
2099 
2100 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2101 {
2102         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2103         struct snd_soc_dapm_context *dapm = &codec->dapm;
2104 
2105         if (jack) {
2106                 wm5100->jack = jack;
2107                 wm5100->jack_detecting = true;
2108                 wm5100->jack_flips = 0;
2109 
2110                 wm5100_set_detect_mode(wm5100, 0);
2111 
2112                 /* Slowest detection rate, gives debounce for initial
2113                  * detection */
2114                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2115                                     WM5100_ACCDET_BIAS_STARTTIME_MASK |
2116                                     WM5100_ACCDET_RATE_MASK,
2117                                     (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2118                                     WM5100_ACCDET_RATE_MASK);
2119 
2120                 /* We need the charge pump to power MICBIAS */
2121                 snd_soc_dapm_mutex_lock(dapm);
2122 
2123                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
2124                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2125 
2126                 snd_soc_dapm_sync_unlocked(dapm);
2127 
2128                 snd_soc_dapm_mutex_unlock(dapm);
2129 
2130                 /* We start off just enabling microphone detection - even a
2131                  * plain headphone will trigger detection.
2132                  */
2133                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2134                                     WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2135 
2136                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2137                                     WM5100_IM_ACCDET_EINT, 0);
2138         } else {
2139                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2140                                     WM5100_IM_HPDET_EINT |
2141                                     WM5100_IM_ACCDET_EINT,
2142                                     WM5100_IM_HPDET_EINT |
2143                                     WM5100_IM_ACCDET_EINT);
2144                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2145                                     WM5100_ACCDET_ENA, 0);
2146                 wm5100->jack = NULL;
2147         }
2148 
2149         return 0;
2150 }
2151 EXPORT_SYMBOL_GPL(wm5100_detect);
2152 
2153 static irqreturn_t wm5100_irq(int irq, void *data)
2154 {
2155         struct wm5100_priv *wm5100 = data;
2156         irqreturn_t status = IRQ_NONE;
2157         unsigned int irq_val, mask_val;
2158         int ret;
2159 
2160         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2161         if (ret < 0) {
2162                 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2163                         ret);
2164                 irq_val = 0;
2165         }
2166 
2167         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2168                           &mask_val);
2169         if (ret < 0) {
2170                 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2171                         ret);
2172                 mask_val = 0xffff;
2173         }
2174 
2175         irq_val &= ~mask_val;
2176 
2177         regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
2178 
2179         if (irq_val)
2180                 status = IRQ_HANDLED;
2181 
2182         wm5100_log_status3(wm5100, irq_val);
2183 
2184         if (irq_val & WM5100_FLL1_LOCK_EINT) {
2185                 dev_dbg(wm5100->dev, "FLL1 locked\n");
2186                 complete(&wm5100->fll[0].lock);
2187         }
2188         if (irq_val & WM5100_FLL2_LOCK_EINT) {
2189                 dev_dbg(wm5100->dev, "FLL2 locked\n");
2190                 complete(&wm5100->fll[1].lock);
2191         }
2192 
2193         if (irq_val & WM5100_ACCDET_EINT)
2194                 wm5100_micd_irq(wm5100);
2195 
2196         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2197         if (ret < 0) {
2198                 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2199                         ret);
2200                 irq_val = 0;
2201         }
2202 
2203         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2204                           &mask_val);
2205         if (ret < 0) {
2206                 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2207                         ret);
2208                 mask_val = 0xffff;
2209         }
2210 
2211         irq_val &= ~mask_val;
2212 
2213         if (irq_val)
2214                 status = IRQ_HANDLED;
2215 
2216         regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
2217 
2218         wm5100_log_status4(wm5100, irq_val);
2219 
2220         return status;
2221 }
2222 
2223 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2224 {
2225         irqreturn_t ret = IRQ_NONE;
2226         irqreturn_t val;
2227 
2228         do {
2229                 val = wm5100_irq(irq, data);
2230                 if (val != IRQ_NONE)
2231                         ret = val;
2232         } while (val != IRQ_NONE);
2233 
2234         return ret;
2235 }
2236 
2237 #ifdef CONFIG_GPIOLIB
2238 static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2239 {
2240         return container_of(chip, struct wm5100_priv, gpio_chip);
2241 }
2242 
2243 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2244 {
2245         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2246 
2247         regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2248                            WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2249 }
2250 
2251 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2252                                      unsigned offset, int value)
2253 {
2254         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2255         int val, ret;
2256 
2257         val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2258 
2259         ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2260                                  WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2261                                  WM5100_GP1_LVL, val);
2262         if (ret < 0)
2263                 return ret;
2264         else
2265                 return 0;
2266 }
2267 
2268 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2269 {
2270         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2271         unsigned int reg;
2272         int ret;
2273 
2274         ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
2275         if (ret < 0)
2276                 return ret;
2277 
2278         return (reg & WM5100_GP1_LVL) != 0;
2279 }
2280 
2281 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2282 {
2283         struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2284 
2285         return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2286                                   WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2287                                   (1 << WM5100_GP1_FN_SHIFT) |
2288                                   (1 << WM5100_GP1_DIR_SHIFT));
2289 }
2290 
2291 static struct gpio_chip wm5100_template_chip = {
2292         .label                  = "wm5100",
2293         .owner                  = THIS_MODULE,
2294         .direction_output       = wm5100_gpio_direction_out,
2295         .set                    = wm5100_gpio_set,
2296         .direction_input        = wm5100_gpio_direction_in,
2297         .get                    = wm5100_gpio_get,
2298         .can_sleep              = 1,
2299 };
2300 
2301 static void wm5100_init_gpio(struct i2c_client *i2c)
2302 {
2303         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2304         int ret;
2305 
2306         wm5100->gpio_chip = wm5100_template_chip;
2307         wm5100->gpio_chip.ngpio = 6;
2308         wm5100->gpio_chip.dev = &i2c->dev;
2309 
2310         if (wm5100->pdata.gpio_base)
2311                 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2312         else
2313                 wm5100->gpio_chip.base = -1;
2314 
2315         ret = gpiochip_add(&wm5100->gpio_chip);
2316         if (ret != 0)
2317                 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
2318 }
2319 
2320 static void wm5100_free_gpio(struct i2c_client *i2c)
2321 {
2322         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2323 
2324         gpiochip_remove(&wm5100->gpio_chip);
2325 }
2326 #else
2327 static void wm5100_init_gpio(struct i2c_client *i2c)
2328 {
2329 }
2330 
2331 static void wm5100_free_gpio(struct i2c_client *i2c)
2332 {
2333 }
2334 #endif
2335 
2336 static int wm5100_probe(struct snd_soc_codec *codec)
2337 {
2338         struct i2c_client *i2c = to_i2c_client(codec->dev);
2339         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2340         int ret, i;
2341 
2342         wm5100->codec = codec;
2343 
2344         for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2345                 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2346                                     WM5100_OUT_VU);
2347 
2348         /* Don't debounce interrupts to support use of SYSCLK only */
2349         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2350         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2351 
2352         /* TODO: check if we're symmetric */
2353 
2354         if (i2c->irq)
2355                 snd_soc_dapm_new_controls(&codec->dapm,
2356                                           wm5100_dapm_widgets_noirq,
2357                                           ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2358 
2359         if (wm5100->pdata.hp_pol) {
2360                 ret = gpio_request_one(wm5100->pdata.hp_pol,
2361                                        GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2362                 if (ret < 0) {
2363                         dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2364                                 wm5100->pdata.hp_pol, ret);
2365                         goto err_gpio;
2366                 }
2367         }
2368 
2369         return 0;
2370 
2371 err_gpio:
2372 
2373         return ret;
2374 }
2375 
2376 static int wm5100_remove(struct snd_soc_codec *codec)
2377 {
2378         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2379 
2380         if (wm5100->pdata.hp_pol) {
2381                 gpio_free(wm5100->pdata.hp_pol);
2382         }
2383 
2384         return 0;
2385 }
2386 
2387 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2388         .probe =        wm5100_probe,
2389         .remove =       wm5100_remove,
2390 
2391         .set_sysclk = wm5100_set_sysclk,
2392         .set_pll = wm5100_set_fll,
2393         .idle_bias_off = 1,
2394 
2395         .seq_notifier = wm5100_seq_notifier,
2396         .controls = wm5100_snd_controls,
2397         .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2398         .dapm_widgets = wm5100_dapm_widgets,
2399         .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2400         .dapm_routes = wm5100_dapm_routes,
2401         .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2402 };
2403 
2404 static const struct regmap_config wm5100_regmap = {
2405         .reg_bits = 16,
2406         .val_bits = 16,
2407 
2408         .max_register = WM5100_MAX_REGISTER,
2409         .reg_defaults = wm5100_reg_defaults,
2410         .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2411         .volatile_reg = wm5100_volatile_register,
2412         .readable_reg = wm5100_readable_register,
2413         .cache_type = REGCACHE_RBTREE,
2414 };
2415 
2416 static const unsigned int wm5100_mic_ctrl_reg[] = {
2417         WM5100_IN1L_CONTROL,
2418         WM5100_IN2L_CONTROL,
2419         WM5100_IN3L_CONTROL,
2420         WM5100_IN4L_CONTROL,
2421 };
2422 
2423 static int wm5100_i2c_probe(struct i2c_client *i2c,
2424                             const struct i2c_device_id *id)
2425 {
2426         struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2427         struct wm5100_priv *wm5100;
2428         unsigned int reg;
2429         int ret, i, irq_flags;
2430 
2431         wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2432                               GFP_KERNEL);
2433         if (wm5100 == NULL)
2434                 return -ENOMEM;
2435 
2436         wm5100->dev = &i2c->dev;
2437 
2438         wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
2439         if (IS_ERR(wm5100->regmap)) {
2440                 ret = PTR_ERR(wm5100->regmap);
2441                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2442                         ret);
2443                 goto err;
2444         }
2445 
2446         for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2447                 init_completion(&wm5100->fll[i].lock);
2448 
2449         if (pdata)
2450                 wm5100->pdata = *pdata;
2451 
2452         i2c_set_clientdata(i2c, wm5100);
2453 
2454         for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2455                 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2456 
2457         ret = devm_regulator_bulk_get(&i2c->dev,
2458                                       ARRAY_SIZE(wm5100->core_supplies),
2459                                       wm5100->core_supplies);
2460         if (ret != 0) {
2461                 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2462                         ret);
2463                 goto err;
2464         }
2465 
2466         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2467                                     wm5100->core_supplies);
2468         if (ret != 0) {
2469                 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2470                         ret);
2471                 goto err;
2472         }
2473 
2474         if (wm5100->pdata.ldo_ena) {
2475                 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2476                                        GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2477                 if (ret < 0) {
2478                         dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2479                                 wm5100->pdata.ldo_ena, ret);
2480                         goto err_enable;
2481                 }
2482                 msleep(2);
2483         }
2484 
2485         if (wm5100->pdata.reset) {
2486                 ret = gpio_request_one(wm5100->pdata.reset,
2487                                        GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2488                 if (ret < 0) {
2489                         dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2490                                 wm5100->pdata.reset, ret);
2491                         goto err_ldo;
2492                 }
2493         }
2494 
2495         ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2496         if (ret < 0) {
2497                 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2498                 goto err_reset;
2499         }
2500         switch (reg) {
2501         case 0x8997:
2502         case 0x5100:
2503                 break;
2504 
2505         default:
2506                 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2507                 ret = -EINVAL;
2508                 goto err_reset;
2509         }
2510 
2511         ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2512         if (ret < 0) {
2513                 dev_err(&i2c->dev, "Failed to read revision register\n");
2514                 goto err_reset;
2515         }
2516         wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2517 
2518         dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2519 
2520         ret = wm5100_reset(wm5100);
2521         if (ret < 0) {
2522                 dev_err(&i2c->dev, "Failed to issue reset\n");
2523                 goto err_reset;
2524         }
2525 
2526         switch (wm5100->rev) {
2527         case 0:
2528                 ret = regmap_register_patch(wm5100->regmap,
2529                                             wm5100_reva_patches,
2530                                             ARRAY_SIZE(wm5100_reva_patches));
2531                 if (ret != 0) {
2532                         dev_err(&i2c->dev, "Failed to register patches: %d\n",
2533                                 ret);
2534                         goto err_reset;
2535                 }
2536                 break;
2537         default:
2538                 break;
2539         }
2540 
2541 
2542         wm5100_init_gpio(i2c);
2543 
2544         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2545                 if (!wm5100->pdata.gpio_defaults[i])
2546                         continue;
2547 
2548                 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2549                              wm5100->pdata.gpio_defaults[i]);
2550         }
2551 
2552         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2553                 regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
2554                                    WM5100_IN1_MODE_MASK |
2555                                    WM5100_IN1_DMIC_SUP_MASK,
2556                                    (wm5100->pdata.in_mode[i] <<
2557                                     WM5100_IN1_MODE_SHIFT) |
2558                                    (wm5100->pdata.dmic_sup[i] <<
2559                                     WM5100_IN1_DMIC_SUP_SHIFT));
2560         }
2561 
2562         if (i2c->irq) {
2563                 if (wm5100->pdata.irq_flags)
2564                         irq_flags = wm5100->pdata.irq_flags;
2565                 else
2566                         irq_flags = IRQF_TRIGGER_LOW;
2567 
2568                 irq_flags |= IRQF_ONESHOT;
2569 
2570                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2571                         ret = request_threaded_irq(i2c->irq, NULL,
2572                                                    wm5100_edge_irq, irq_flags,
2573                                                    "wm5100", wm5100);
2574                 else
2575                         ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2576                                                    irq_flags, "wm5100",
2577                                                    wm5100);
2578 
2579                 if (ret != 0) {
2580                         dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2581                                 i2c->irq, ret);
2582                 } else {
2583                         /* Enable default interrupts */
2584                         regmap_update_bits(wm5100->regmap,
2585                                            WM5100_INTERRUPT_STATUS_3_MASK,
2586                                            WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2587                                            WM5100_IM_SPK_SHUTDOWN_EINT |
2588                                            WM5100_IM_ASRC2_LOCK_EINT |
2589                                            WM5100_IM_ASRC1_LOCK_EINT |
2590                                            WM5100_IM_FLL2_LOCK_EINT |
2591                                            WM5100_IM_FLL1_LOCK_EINT |
2592                                            WM5100_CLKGEN_ERR_EINT |
2593                                            WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2594 
2595                         regmap_update_bits(wm5100->regmap,
2596                                            WM5100_INTERRUPT_STATUS_4_MASK,
2597                                            WM5100_AIF3_ERR_EINT |
2598                                            WM5100_AIF2_ERR_EINT |
2599                                            WM5100_AIF1_ERR_EINT |
2600                                            WM5100_CTRLIF_ERR_EINT |
2601                                            WM5100_ISRC2_UNDERCLOCKED_EINT |
2602                                            WM5100_ISRC1_UNDERCLOCKED_EINT |
2603                                            WM5100_FX_UNDERCLOCKED_EINT |
2604                                            WM5100_AIF3_UNDERCLOCKED_EINT |
2605                                            WM5100_AIF2_UNDERCLOCKED_EINT |
2606                                            WM5100_AIF1_UNDERCLOCKED_EINT |
2607                                            WM5100_ASRC_UNDERCLOCKED_EINT |
2608                                            WM5100_DAC_UNDERCLOCKED_EINT |
2609                                            WM5100_ADC_UNDERCLOCKED_EINT |
2610                                            WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2611                 }
2612         }
2613 
2614         pm_runtime_set_active(&i2c->dev);
2615         pm_runtime_enable(&i2c->dev);
2616         pm_request_idle(&i2c->dev);
2617 
2618         ret = snd_soc_register_codec(&i2c->dev,
2619                                      &soc_codec_dev_wm5100, wm5100_dai,
2620                                      ARRAY_SIZE(wm5100_dai));
2621         if (ret < 0) {
2622                 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2623                 goto err_reset;
2624         }
2625 
2626         return ret;
2627 
2628 err_reset:
2629         if (i2c->irq)
2630                 free_irq(i2c->irq, wm5100);
2631         wm5100_free_gpio(i2c);
2632         if (wm5100->pdata.reset) {
2633                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2634                 gpio_free(wm5100->pdata.reset);
2635         }
2636 err_ldo:
2637         if (wm5100->pdata.ldo_ena) {
2638                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2639                 gpio_free(wm5100->pdata.ldo_ena);
2640         }
2641 err_enable:
2642         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2643                                wm5100->core_supplies);
2644 err:
2645         return ret;
2646 }
2647 
2648 static int wm5100_i2c_remove(struct i2c_client *i2c)
2649 {
2650         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2651 
2652         snd_soc_unregister_codec(&i2c->dev);
2653         if (i2c->irq)
2654                 free_irq(i2c->irq, wm5100);
2655         wm5100_free_gpio(i2c);
2656         if (wm5100->pdata.reset) {
2657                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2658                 gpio_free(wm5100->pdata.reset);
2659         }
2660         if (wm5100->pdata.ldo_ena) {
2661                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2662                 gpio_free(wm5100->pdata.ldo_ena);
2663         }
2664 
2665         return 0;
2666 }
2667 
2668 #ifdef CONFIG_PM
2669 static int wm5100_runtime_suspend(struct device *dev)
2670 {
2671         struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2672 
2673         regcache_cache_only(wm5100->regmap, true);
2674         regcache_mark_dirty(wm5100->regmap);
2675         if (wm5100->pdata.ldo_ena)
2676                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2677         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2678                                wm5100->core_supplies);
2679 
2680         return 0;
2681 }
2682 
2683 static int wm5100_runtime_resume(struct device *dev)
2684 {
2685         struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2686         int ret;
2687 
2688         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2689                                     wm5100->core_supplies);
2690         if (ret != 0) {
2691                 dev_err(dev, "Failed to enable supplies: %d\n",
2692                         ret);
2693                 return ret;
2694         }
2695 
2696         if (wm5100->pdata.ldo_ena) {
2697                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2698                 msleep(2);
2699         }
2700 
2701         regcache_cache_only(wm5100->regmap, false);
2702         regcache_sync(wm5100->regmap);
2703 
2704         return 0;
2705 }
2706 #endif
2707 
2708 static struct dev_pm_ops wm5100_pm = {
2709         SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2710                            NULL)
2711 };
2712 
2713 static const struct i2c_device_id wm5100_i2c_id[] = {
2714         { "wm5100", 0 },
2715         { }
2716 };
2717 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2718 
2719 static struct i2c_driver wm5100_i2c_driver = {
2720         .driver = {
2721                 .name = "wm5100",
2722                 .owner = THIS_MODULE,
2723                 .pm = &wm5100_pm,
2724         },
2725         .probe =    wm5100_i2c_probe,
2726         .remove =   wm5100_i2c_remove,
2727         .id_table = wm5100_i2c_id,
2728 };
2729 
2730 module_i2c_driver(wm5100_i2c_driver);
2731 
2732 MODULE_DESCRIPTION("ASoC WM5100 driver");
2733 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2734 MODULE_LICENSE("GPL");
2735 

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