~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm5100.c

Version: ~ [ linux-5.19-rc3 ] ~ [ linux-5.18.5 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.48 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.123 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.199 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.248 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.284 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.319 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * wm5100.c  --  WM5100 ALSA SoC Audio driver
  3  *
  4  * Copyright 2011-2 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/init.h>
 16 #include <linux/delay.h>
 17 #include <linux/export.h>
 18 #include <linux/pm.h>
 19 #include <linux/gcd.h>
 20 #include <linux/gpio/driver.h>
 21 #include <linux/gpio.h>
 22 #include <linux/i2c.h>
 23 #include <linux/pm_runtime.h>
 24 #include <linux/regulator/consumer.h>
 25 #include <linux/regulator/fixed.h>
 26 #include <linux/slab.h>
 27 #include <sound/core.h>
 28 #include <sound/pcm.h>
 29 #include <sound/pcm_params.h>
 30 #include <sound/soc.h>
 31 #include <sound/jack.h>
 32 #include <sound/initval.h>
 33 #include <sound/tlv.h>
 34 #include <sound/wm5100.h>
 35 
 36 #include "wm5100.h"
 37 
 38 #define WM5100_NUM_CORE_SUPPLIES 2
 39 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
 40         "DBVDD1",
 41         "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
 42 };
 43 
 44 #define WM5100_AIFS     3
 45 #define WM5100_SYNC_SRS 3
 46 
 47 struct wm5100_fll {
 48         int fref;
 49         int fout;
 50         int src;
 51         struct completion lock;
 52 };
 53 
 54 /* codec private data */
 55 struct wm5100_priv {
 56         struct device *dev;
 57         struct regmap *regmap;
 58         struct snd_soc_codec *codec;
 59 
 60         struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
 61 
 62         int rev;
 63 
 64         int sysclk;
 65         int asyncclk;
 66 
 67         bool aif_async[WM5100_AIFS];
 68         bool aif_symmetric[WM5100_AIFS];
 69         int sr_ref[WM5100_SYNC_SRS];
 70 
 71         bool out_ena[2];
 72 
 73         struct snd_soc_jack *jack;
 74         bool jack_detecting;
 75         bool jack_mic;
 76         int jack_mode;
 77         int jack_flips;
 78 
 79         struct wm5100_fll fll[2];
 80 
 81         struct wm5100_pdata pdata;
 82 
 83 #ifdef CONFIG_GPIOLIB
 84         struct gpio_chip gpio_chip;
 85 #endif
 86 };
 87 
 88 static int wm5100_sr_code[] = {
 89         0,
 90         12000,
 91         24000,
 92         48000,
 93         96000,
 94         192000,
 95         384000,
 96         768000,
 97         0,
 98         11025,
 99         22050,
100         44100,
101         88200,
102         176400,
103         352800,
104         705600,
105         4000,
106         8000,
107         16000,
108         32000,
109         64000,
110         128000,
111         256000,
112         512000,
113 };
114 
115 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
116         WM5100_CLOCKING_4,
117         WM5100_CLOCKING_5,
118         WM5100_CLOCKING_6,
119 };
120 
121 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
122 {
123         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
124         int sr_code, sr_free, i;
125 
126         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
127                 if (wm5100_sr_code[i] == rate)
128                         break;
129         if (i == ARRAY_SIZE(wm5100_sr_code)) {
130                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
131                 return -EINVAL;
132         }
133         sr_code = i;
134 
135         if ((wm5100->sysclk % rate) == 0) {
136                 /* Is this rate already in use? */
137                 sr_free = -1;
138                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
139                         if (!wm5100->sr_ref[i] && sr_free == -1) {
140                                 sr_free = i;
141                                 continue;
142                         }
143                         if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
144                              WM5100_SAMPLE_RATE_1_MASK) == sr_code)
145                                 break;
146                 }
147 
148                 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
149                         wm5100->sr_ref[i]++;
150                         dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
151                                 rate, i, wm5100->sr_ref[i]);
152                         return i;
153                 }
154 
155                 if (sr_free == -1) {
156                         dev_err(codec->dev, "All SR slots already in use\n");
157                         return -EBUSY;
158                 }
159 
160                 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
161                         sr_free, rate);
162                 wm5100->sr_ref[sr_free]++;
163                 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
164                                     WM5100_SAMPLE_RATE_1_MASK,
165                                     sr_code);
166 
167                 return sr_free;
168 
169         } else {
170                 dev_err(codec->dev,
171                         "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
172                         rate, wm5100->sysclk, wm5100->asyncclk);
173                 return -EINVAL;
174         }
175 }
176 
177 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
178 {
179         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
180         int i, sr_code;
181 
182         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
183                 if (wm5100_sr_code[i] == rate)
184                         break;
185         if (i == ARRAY_SIZE(wm5100_sr_code)) {
186                 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
187                 return;
188         }
189         sr_code = wm5100_sr_code[i];
190 
191         for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
192                 if (!wm5100->sr_ref[i])
193                         continue;
194 
195                 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
196                      WM5100_SAMPLE_RATE_1_MASK) == sr_code)
197                         break;
198         }
199         if (i < ARRAY_SIZE(wm5100_sr_regs)) {
200                 wm5100->sr_ref[i]--;
201                 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
202                         rate, wm5100->sr_ref[i]);
203         } else {
204                 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
205                          rate);
206         }
207 }
208 
209 static int wm5100_reset(struct wm5100_priv *wm5100)
210 {
211         if (wm5100->pdata.reset) {
212                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
213                 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
214 
215                 return 0;
216         } else {
217                 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
218         }
219 }
220 
221 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
222 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
223 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
224 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
225 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
226 
227 static const char *wm5100_mixer_texts[] = {
228         "None",
229         "Tone Generator 1",
230         "Tone Generator 2",
231         "AEC loopback",
232         "IN1L",
233         "IN1R",
234         "IN2L",
235         "IN2R",
236         "IN3L",
237         "IN3R",
238         "IN4L",
239         "IN4R",
240         "AIF1RX1",
241         "AIF1RX2",
242         "AIF1RX3",
243         "AIF1RX4",
244         "AIF1RX5",
245         "AIF1RX6",
246         "AIF1RX7",
247         "AIF1RX8",
248         "AIF2RX1",
249         "AIF2RX2",
250         "AIF3RX1",
251         "AIF3RX2",
252         "EQ1",
253         "EQ2",
254         "EQ3",
255         "EQ4",
256         "DRC1L",
257         "DRC1R",
258         "LHPF1",
259         "LHPF2",
260         "LHPF3",
261         "LHPF4",
262         "DSP1.1",
263         "DSP1.2",
264         "DSP1.3",
265         "DSP1.4",
266         "DSP1.5",
267         "DSP1.6",
268         "DSP2.1",
269         "DSP2.2",
270         "DSP2.3",
271         "DSP2.4",
272         "DSP2.5",
273         "DSP2.6",
274         "DSP3.1",
275         "DSP3.2",
276         "DSP3.3",
277         "DSP3.4",
278         "DSP3.5",
279         "DSP3.6",
280         "ASRC1L",
281         "ASRC1R",
282         "ASRC2L",
283         "ASRC2R",
284         "ISRC1INT1",
285         "ISRC1INT2",
286         "ISRC1INT3",
287         "ISRC1INT4",
288         "ISRC2INT1",
289         "ISRC2INT2",
290         "ISRC2INT3",
291         "ISRC2INT4",
292         "ISRC1DEC1",
293         "ISRC1DEC2",
294         "ISRC1DEC3",
295         "ISRC1DEC4",
296         "ISRC2DEC1",
297         "ISRC2DEC2",
298         "ISRC2DEC3",
299         "ISRC2DEC4",
300 };
301 
302 static int wm5100_mixer_values[] = {
303         0x00,
304         0x04,   /* Tone */
305         0x05,
306         0x08,   /* AEC */
307         0x10,   /* Input */
308         0x11,
309         0x12,
310         0x13,
311         0x14,
312         0x15,
313         0x16,
314         0x17,
315         0x20,   /* AIF */
316         0x21,
317         0x22,
318         0x23,
319         0x24,
320         0x25,
321         0x26,
322         0x27,
323         0x28,
324         0x29,
325         0x30,   /* AIF3 - check */
326         0x31,
327         0x50,   /* EQ */
328         0x51,
329         0x52,
330         0x53,
331         0x54,
332         0x58,   /* DRC */
333         0x59,
334         0x60,   /* LHPF1 */
335         0x61,   /* LHPF2 */
336         0x62,   /* LHPF3 */
337         0x63,   /* LHPF4 */
338         0x68,   /* DSP1 */
339         0x69,
340         0x6a,
341         0x6b,
342         0x6c,
343         0x6d,
344         0x70,   /* DSP2 */
345         0x71,
346         0x72,
347         0x73,
348         0x74,
349         0x75,
350         0x78,   /* DSP3 */
351         0x79,
352         0x7a,
353         0x7b,
354         0x7c,
355         0x7d,
356         0x90,   /* ASRC1 */
357         0x91,
358         0x92,   /* ASRC2 */
359         0x93,
360         0xa0,   /* ISRC1DEC1 */
361         0xa1,
362         0xa2,
363         0xa3,
364         0xa4,   /* ISRC1INT1 */
365         0xa5,
366         0xa6,
367         0xa7,
368         0xa8,   /* ISRC2DEC1 */
369         0xa9,
370         0xaa,
371         0xab,
372         0xac,   /* ISRC2INT1 */
373         0xad,
374         0xae,
375         0xaf,
376 };
377 
378 #define WM5100_MIXER_CONTROLS(name, base) \
379         SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
380                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381         SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
382                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383         SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
384                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
385         SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
386                        WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
387 
388 #define WM5100_MUX_ENUM_DECL(name, reg) \
389         SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff,                  \
390                                    wm5100_mixer_texts, wm5100_mixer_values)
391 
392 #define WM5100_MUX_CTL_DECL(name) \
393         const struct snd_kcontrol_new name##_mux =      \
394                 SOC_DAPM_ENUM("Route", name##_enum)
395 
396 #define WM5100_MIXER_ENUMS(name, base_reg) \
397         static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg);      \
398         static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2);  \
399         static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4);  \
400         static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6);  \
401         static WM5100_MUX_CTL_DECL(name##_in1); \
402         static WM5100_MUX_CTL_DECL(name##_in2); \
403         static WM5100_MUX_CTL_DECL(name##_in3); \
404         static WM5100_MUX_CTL_DECL(name##_in4) 
405 
406 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
407 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
408 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
409 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
410 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
411 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
412 
413 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
414 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
415 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
416 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
417 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
418 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
419 
420 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
421 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
422 
423 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
424 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
425 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
426 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
427 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
428 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
429 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
430 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
431 
432 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
433 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
434 
435 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
436 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
437 
438 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
439 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
440 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
441 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
442 
443 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
444 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
445 
446 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
447 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
448 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
449 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
450 
451 #define WM5100_MUX(name, ctrl) \
452         SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
453 
454 #define WM5100_MIXER_WIDGETS(name, name_str)    \
455         WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
456         WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
457         WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
458         WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
459         SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
460 
461 #define WM5100_MIXER_INPUT_ROUTES(name) \
462         { name, "Tone Generator 1", "Tone Generator 1" }, \
463         { name, "Tone Generator 2", "Tone Generator 2" }, \
464         { name, "IN1L", "IN1L PGA" }, \
465         { name, "IN1R", "IN1R PGA" }, \
466         { name, "IN2L", "IN2L PGA" }, \
467         { name, "IN2R", "IN2R PGA" }, \
468         { name, "IN3L", "IN3L PGA" }, \
469         { name, "IN3R", "IN3R PGA" }, \
470         { name, "IN4L", "IN4L PGA" }, \
471         { name, "IN4R", "IN4R PGA" }, \
472         { name, "AIF1RX1", "AIF1RX1" }, \
473         { name, "AIF1RX2", "AIF1RX2" }, \
474         { name, "AIF1RX3", "AIF1RX3" }, \
475         { name, "AIF1RX4", "AIF1RX4" }, \
476         { name, "AIF1RX5", "AIF1RX5" }, \
477         { name, "AIF1RX6", "AIF1RX6" }, \
478         { name, "AIF1RX7", "AIF1RX7" }, \
479         { name, "AIF1RX8", "AIF1RX8" }, \
480         { name, "AIF2RX1", "AIF2RX1" }, \
481         { name, "AIF2RX2", "AIF2RX2" }, \
482         { name, "AIF3RX1", "AIF3RX1" }, \
483         { name, "AIF3RX2", "AIF3RX2" }, \
484         { name, "EQ1", "EQ1" }, \
485         { name, "EQ2", "EQ2" }, \
486         { name, "EQ3", "EQ3" }, \
487         { name, "EQ4", "EQ4" }, \
488         { name, "DRC1L", "DRC1L" }, \
489         { name, "DRC1R", "DRC1R" }, \
490         { name, "LHPF1", "LHPF1" }, \
491         { name, "LHPF2", "LHPF2" }, \
492         { name, "LHPF3", "LHPF3" }, \
493         { name, "LHPF4", "LHPF4" }
494 
495 #define WM5100_MIXER_ROUTES(widget, name) \
496         { widget, NULL, name " Mixer" },         \
497         { name " Mixer", NULL, name " Input 1" }, \
498         { name " Mixer", NULL, name " Input 2" }, \
499         { name " Mixer", NULL, name " Input 3" }, \
500         { name " Mixer", NULL, name " Input 4" }, \
501         WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
502         WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
503         WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
504         WM5100_MIXER_INPUT_ROUTES(name " Input 4")
505 
506 static const char *wm5100_lhpf_mode_text[] = {
507         "Low-pass", "High-pass"
508 };
509 
510 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
511                             WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
512                             wm5100_lhpf_mode_text);
513 
514 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
515                             WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
516                             wm5100_lhpf_mode_text);
517 
518 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
519                             WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
520                             wm5100_lhpf_mode_text);
521 
522 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
523                             WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
524                             wm5100_lhpf_mode_text);
525 
526 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
527 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
528            WM5100_IN1_OSR_SHIFT, 1, 0),
529 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
530            WM5100_IN2_OSR_SHIFT, 1, 0),
531 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
532            WM5100_IN3_OSR_SHIFT, 1, 0),
533 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
534            WM5100_IN4_OSR_SHIFT, 1, 0),
535 
536 /* Only applicable for analogue inputs */
537 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
538                  WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
540                  WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
542                  WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
543 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
544                  WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
545 
546 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
547                  WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
548                  0, digital_tlv),
549 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
550                  WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
551                  0, digital_tlv),
552 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
553                  WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
554                  0, digital_tlv),
555 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
556                  WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
557                  0, digital_tlv),
558 
559 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
560              WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
561 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
562              WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
563 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
564              WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
565 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
566              WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
567 
568 SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
569 SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
570 SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
571 SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
572 
573 SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
574                    WM5100_DRCL_ENA | WM5100_DRCR_ENA),
575 
576 SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1),
577 SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1),
578 SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1),
579 SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1),
580 
581 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
582            WM5100_OUT1_OSR_SHIFT, 1, 0),
583 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
584            WM5100_OUT2_OSR_SHIFT, 1, 0),
585 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
586            WM5100_OUT3_OSR_SHIFT, 1, 0),
587 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
588            WM5100_OUT4_OSR_SHIFT, 1, 0),
589 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
590            WM5100_OUT5_OSR_SHIFT, 1, 0),
591 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
592            WM5100_OUT6_OSR_SHIFT, 1, 0),
593 
594 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
595                  WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
596                  digital_tlv),
597 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
598                  WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
599                  digital_tlv),
600 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
601                  WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
602                  digital_tlv),
603 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
604                  WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
605                  digital_tlv),
606 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
607                  WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
608                  digital_tlv),
609 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
610                  WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
611                  digital_tlv),
612 
613 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
614              WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
615 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
616              WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
617 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
618              WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
619 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
620              WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
621 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
622              WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
623 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
624              WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
625 
626 /* FIXME: Only valid from -12dB to 0dB (52-64) */
627 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
628                  WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
629 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
630                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
631 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
632                  WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
633 
634 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
635            WM5100_SPK1R_MUTE_SHIFT, 1, 1),
636 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
637            WM5100_SPK2R_MUTE_SHIFT, 1, 1),
638 
639 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
640                24, 0, eq_tlv),
641 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
642                24, 0, eq_tlv),
643 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
644                24, 0, eq_tlv),
645 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
646                24, 0, eq_tlv),
647 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
648                24, 0, eq_tlv),
649 
650 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
651                24, 0, eq_tlv),
652 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
653                24, 0, eq_tlv),
654 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
655                24, 0, eq_tlv),
656 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
657                24, 0, eq_tlv),
658 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
659                24, 0, eq_tlv),
660 
661 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
662                24, 0, eq_tlv),
663 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
664                24, 0, eq_tlv),
665 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
666                24, 0, eq_tlv),
667 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
668                24, 0, eq_tlv),
669 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
670                24, 0, eq_tlv),
671 
672 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
673                24, 0, eq_tlv),
674 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
675                24, 0, eq_tlv),
676 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
677                24, 0, eq_tlv),
678 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
679                24, 0, eq_tlv),
680 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
681                24, 0, eq_tlv),
682 
683 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
684 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
685 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
686 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
687 
688 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
689 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
690 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
691 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
692 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
693 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
694 
695 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
696 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
697 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
698 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
699 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
700 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
701 
702 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
703 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
704 
705 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
706 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
707 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
708 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
709 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
710 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
711 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
712 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
713 
714 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
715 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
716 
717 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
718 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
719 
720 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
721 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
722 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
723 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
724 
725 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
726 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
727 SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
728                    WM5100_DRCL_ENA | WM5100_DRCR_ENA),
729 
730 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
731 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
732 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
733 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
734 };
735 
736 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
737                                 enum snd_soc_dapm_type event, int subseq)
738 {
739         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
740         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
741         u16 val, expect, i;
742 
743         /* Wait for the outputs to flag themselves as enabled */
744         if (wm5100->out_ena[0]) {
745                 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
746                 for (i = 0; i < 200; i++) {
747                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
748                         if (val == expect) {
749                                 wm5100->out_ena[0] = false;
750                                 break;
751                         }
752                 }
753                 if (i == 200) {
754                         dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
755                                 expect);
756                 }
757         }
758 
759         if (wm5100->out_ena[1]) {
760                 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
761                 for (i = 0; i < 200; i++) {
762                         val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
763                         if (val == expect) {
764                                 wm5100->out_ena[1] = false;
765                                 break;
766                         }
767                 }
768                 if (i == 200) {
769                         dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
770                                 expect);
771                 }
772         }
773 }
774 
775 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
776                          struct snd_kcontrol *kcontrol,
777                          int event)
778 {
779         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
780         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
781 
782         switch (w->reg) {
783         case WM5100_CHANNEL_ENABLES_1:
784                 wm5100->out_ena[0] = true;
785                 break;
786         case WM5100_OUTPUT_ENABLES_2:
787                 wm5100->out_ena[0] = true;
788                 break;
789         default:
790                 break;
791         }
792 
793         return 0;
794 }
795 
796 static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
797 {
798         if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
799                 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
800         if (val & WM5100_SPK_SHUTDOWN_EINT)
801                 dev_crit(wm5100->dev, "Speaker shutdown\n");
802         if (val & WM5100_CLKGEN_ERR_EINT)
803                 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
804         if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
805                 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
806 }
807 
808 static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
809 {
810         if (val & WM5100_AIF3_ERR_EINT)
811                 dev_err(wm5100->dev, "AIF3 configuration error\n");
812         if (val & WM5100_AIF2_ERR_EINT)
813                 dev_err(wm5100->dev, "AIF2 configuration error\n");
814         if (val & WM5100_AIF1_ERR_EINT)
815                 dev_err(wm5100->dev, "AIF1 configuration error\n");
816         if (val & WM5100_CTRLIF_ERR_EINT)
817                 dev_err(wm5100->dev, "Control interface error\n");
818         if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
819                 dev_err(wm5100->dev, "ISRC2 underclocked\n");
820         if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
821                 dev_err(wm5100->dev, "ISRC1 underclocked\n");
822         if (val & WM5100_FX_UNDERCLOCKED_EINT)
823                 dev_err(wm5100->dev, "FX underclocked\n");
824         if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
825                 dev_err(wm5100->dev, "AIF3 underclocked\n");
826         if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
827                 dev_err(wm5100->dev, "AIF2 underclocked\n");
828         if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
829                 dev_err(wm5100->dev, "AIF1 underclocked\n");
830         if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
831                 dev_err(wm5100->dev, "ASRC underclocked\n");
832         if (val & WM5100_DAC_UNDERCLOCKED_EINT)
833                 dev_err(wm5100->dev, "DAC underclocked\n");
834         if (val & WM5100_ADC_UNDERCLOCKED_EINT)
835                 dev_err(wm5100->dev, "ADC underclocked\n");
836         if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
837                 dev_err(wm5100->dev, "Mixer underclocked\n");
838 }
839 
840 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
841                           struct snd_kcontrol *kcontrol,
842                           int event)
843 {
844         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
845         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
846         int ret;
847 
848         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
849         ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
850                 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
851                 WM5100_CLKGEN_ERR_ASYNC_STS;
852         wm5100_log_status3(wm5100, ret);
853 
854         ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
855         wm5100_log_status4(wm5100, ret);
856 
857         return 0;
858 }
859 
860 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
861 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
862                     NULL, 0),
863 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
864                     0, NULL, 0),
865 
866 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
867 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
868 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
869 
870 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
871                     NULL, 0),
872 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
873                     NULL, 0),
874 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
875                     WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
876 
877 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
878                     0, NULL, 0),
879 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
880                     0, NULL, 0),
881 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
882                     0, NULL, 0),
883 
884 SND_SOC_DAPM_INPUT("IN1L"),
885 SND_SOC_DAPM_INPUT("IN1R"),
886 SND_SOC_DAPM_INPUT("IN2L"),
887 SND_SOC_DAPM_INPUT("IN2R"),
888 SND_SOC_DAPM_INPUT("IN3L"),
889 SND_SOC_DAPM_INPUT("IN3R"),
890 SND_SOC_DAPM_INPUT("IN4L"),
891 SND_SOC_DAPM_INPUT("IN4R"),
892 SND_SOC_DAPM_SIGGEN("TONE"),
893 
894 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
895                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
896 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
897                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
898 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
899                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
900 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
901                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
902 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
903                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
904 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
905                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
906 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
907                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
908 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
909                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
910 
911 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
912                  WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
913 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
914                  WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
915 
916 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
917                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
918 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
919                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
920 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
921                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
922 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
923                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
924 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
925                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
926 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
927                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
928 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
929                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
930 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
931                     WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
932 
933 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
934                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
935 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
936                     WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
937 
938 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
939                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
940 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
941                     WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
942 
943 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
944                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
945 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
946                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
947 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
948                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
949 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
950                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
951 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
952                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
953 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
954                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
955 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
956                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
957 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
958                     WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
959 
960 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
961                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
962 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
963                     WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
964 
965 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
966                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
967 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
968                     WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
969 
970 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
971                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
972 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
973                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
974 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
975                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
976 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
977                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
978 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
979                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
980 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
981                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
982 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
983                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
984 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
985                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
986 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
987                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
988 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
989                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
990 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
991                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
992 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
993                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
994 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
995                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
996 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
997                    NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
998 
999 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1002 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1003 
1004 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1005                  NULL, 0),
1006 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1007                  NULL, 0),
1008 
1009 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1010                  NULL, 0),
1011 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1012                  NULL, 0),
1013 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1014                  NULL, 0),
1015 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1016                  NULL, 0),
1017 
1018 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1019 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1020 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1021 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1022 
1023 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1024 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1025 
1026 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1027 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1028 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1029 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1030 
1031 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1032 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1033 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1034 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1035 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1036 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1037 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1038 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1039 
1040 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1041 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1042 
1043 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1044 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1045 
1046 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1047 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1048 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1049 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1050 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1051 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1052 
1053 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1054 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1055 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1056 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1057 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1058 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1059 
1060 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1061 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1062 
1063 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1067 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1068 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1069 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1070 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1071 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1072 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1073 SND_SOC_DAPM_OUTPUT("PWM1"),
1074 SND_SOC_DAPM_OUTPUT("PWM2"),
1075 };
1076 
1077 /* We register a _POST event if we don't have IRQ support so we can
1078  * look at the error status from the CODEC - if we've got the IRQ
1079  * hooked up then we will get prompted to look by an interrupt.
1080  */
1081 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1082 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1083 };
1084 
1085 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1086         { "CP1", NULL, "CPVDD" },
1087         { "CP2 Active", NULL, "CPVDD" },
1088 
1089         { "IN1L", NULL, "SYSCLK" },
1090         { "IN1R", NULL, "SYSCLK" },
1091         { "IN2L", NULL, "SYSCLK" },
1092         { "IN2R", NULL, "SYSCLK" },
1093         { "IN3L", NULL, "SYSCLK" },
1094         { "IN3R", NULL, "SYSCLK" },
1095         { "IN4L", NULL, "SYSCLK" },
1096         { "IN4R", NULL, "SYSCLK" },
1097 
1098         { "OUT1L", NULL, "SYSCLK" },
1099         { "OUT1R", NULL, "SYSCLK" },
1100         { "OUT2L", NULL, "SYSCLK" },
1101         { "OUT2R", NULL, "SYSCLK" },
1102         { "OUT3L", NULL, "SYSCLK" },
1103         { "OUT3R", NULL, "SYSCLK" },
1104         { "OUT4L", NULL, "SYSCLK" },
1105         { "OUT4R", NULL, "SYSCLK" },
1106         { "OUT5L", NULL, "SYSCLK" },
1107         { "OUT5R", NULL, "SYSCLK" },
1108         { "OUT6L", NULL, "SYSCLK" },
1109         { "OUT6R", NULL, "SYSCLK" },
1110 
1111         { "AIF1RX1", NULL, "SYSCLK" },
1112         { "AIF1RX2", NULL, "SYSCLK" },
1113         { "AIF1RX3", NULL, "SYSCLK" },
1114         { "AIF1RX4", NULL, "SYSCLK" },
1115         { "AIF1RX5", NULL, "SYSCLK" },
1116         { "AIF1RX6", NULL, "SYSCLK" },
1117         { "AIF1RX7", NULL, "SYSCLK" },
1118         { "AIF1RX8", NULL, "SYSCLK" },
1119 
1120         { "AIF2RX1", NULL, "SYSCLK" },
1121         { "AIF2RX1", NULL, "DBVDD2" },
1122         { "AIF2RX2", NULL, "SYSCLK" },
1123         { "AIF2RX2", NULL, "DBVDD2" },
1124 
1125         { "AIF3RX1", NULL, "SYSCLK" },
1126         { "AIF3RX1", NULL, "DBVDD3" },
1127         { "AIF3RX2", NULL, "SYSCLK" },
1128         { "AIF3RX2", NULL, "DBVDD3" },
1129 
1130         { "AIF1TX1", NULL, "SYSCLK" },
1131         { "AIF1TX2", NULL, "SYSCLK" },
1132         { "AIF1TX3", NULL, "SYSCLK" },
1133         { "AIF1TX4", NULL, "SYSCLK" },
1134         { "AIF1TX5", NULL, "SYSCLK" },
1135         { "AIF1TX6", NULL, "SYSCLK" },
1136         { "AIF1TX7", NULL, "SYSCLK" },
1137         { "AIF1TX8", NULL, "SYSCLK" },
1138 
1139         { "AIF2TX1", NULL, "SYSCLK" },
1140         { "AIF2TX1", NULL, "DBVDD2" },
1141         { "AIF2TX2", NULL, "SYSCLK" },
1142         { "AIF2TX2", NULL, "DBVDD2" },
1143 
1144         { "AIF3TX1", NULL, "SYSCLK" },
1145         { "AIF3TX1", NULL, "DBVDD3" },
1146         { "AIF3TX2", NULL, "SYSCLK" },
1147         { "AIF3TX2", NULL, "DBVDD3" },
1148 
1149         { "MICBIAS1", NULL, "CP2" },
1150         { "MICBIAS2", NULL, "CP2" },
1151         { "MICBIAS3", NULL, "CP2" },
1152 
1153         { "IN1L PGA", NULL, "CP2" },
1154         { "IN1R PGA", NULL, "CP2" },
1155         { "IN2L PGA", NULL, "CP2" },
1156         { "IN2R PGA", NULL, "CP2" },
1157         { "IN3L PGA", NULL, "CP2" },
1158         { "IN3R PGA", NULL, "CP2" },
1159         { "IN4L PGA", NULL, "CP2" },
1160         { "IN4R PGA", NULL, "CP2" },
1161 
1162         { "IN1L PGA", NULL, "CP2 Active" },
1163         { "IN1R PGA", NULL, "CP2 Active" },
1164         { "IN2L PGA", NULL, "CP2 Active" },
1165         { "IN2R PGA", NULL, "CP2 Active" },
1166         { "IN3L PGA", NULL, "CP2 Active" },
1167         { "IN3R PGA", NULL, "CP2 Active" },
1168         { "IN4L PGA", NULL, "CP2 Active" },
1169         { "IN4R PGA", NULL, "CP2 Active" },
1170 
1171         { "OUT1L", NULL, "CP1" },
1172         { "OUT1R", NULL, "CP1" },
1173         { "OUT2L", NULL, "CP1" },
1174         { "OUT2R", NULL, "CP1" },
1175         { "OUT3L", NULL, "CP1" },
1176         { "OUT3R", NULL, "CP1" },
1177 
1178         { "Tone Generator 1", NULL, "TONE" },
1179         { "Tone Generator 2", NULL, "TONE" },
1180 
1181         { "IN1L PGA", NULL, "IN1L" },
1182         { "IN1R PGA", NULL, "IN1R" },
1183         { "IN2L PGA", NULL, "IN2L" },
1184         { "IN2R PGA", NULL, "IN2R" },
1185         { "IN3L PGA", NULL, "IN3L" },
1186         { "IN3R PGA", NULL, "IN3R" },
1187         { "IN4L PGA", NULL, "IN4L" },
1188         { "IN4R PGA", NULL, "IN4R" },
1189 
1190         WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1191         WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1192         WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1193         WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1194         WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1195         WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1196 
1197         WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1198         WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1199         WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1200         WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1201         WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1202         WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1203 
1204         WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1205         WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1206 
1207         WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1208         WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1209         WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1210         WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1211         WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1212         WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1213         WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1214         WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1215 
1216         WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1217         WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1218 
1219         WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1220         WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1221 
1222         WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1223         WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1224         WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1225         WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1226 
1227         WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1228         WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1229 
1230         WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1231         WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1232         WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1233         WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1234 
1235         { "HPOUT1L", NULL, "OUT1L" },
1236         { "HPOUT1R", NULL, "OUT1R" },
1237         { "HPOUT2L", NULL, "OUT2L" },
1238         { "HPOUT2R", NULL, "OUT2R" },
1239         { "HPOUT3L", NULL, "OUT3L" },
1240         { "HPOUT3R", NULL, "OUT3R" },
1241         { "SPKOUTL", NULL, "OUT4L" },
1242         { "SPKOUTR", NULL, "OUT4R" },
1243         { "SPKDAT1", NULL, "OUT5L" },
1244         { "SPKDAT1", NULL, "OUT5R" },
1245         { "SPKDAT2", NULL, "OUT6L" },
1246         { "SPKDAT2", NULL, "OUT6R" },
1247         { "PWM1", NULL, "PWM1 Driver" },
1248         { "PWM2", NULL, "PWM2 Driver" },
1249 };
1250 
1251 static const struct reg_sequence wm5100_reva_patches[] = {
1252         { WM5100_AUDIO_IF_1_10, 0 },
1253         { WM5100_AUDIO_IF_1_11, 1 },
1254         { WM5100_AUDIO_IF_1_12, 2 },
1255         { WM5100_AUDIO_IF_1_13, 3 },
1256         { WM5100_AUDIO_IF_1_14, 4 },
1257         { WM5100_AUDIO_IF_1_15, 5 },
1258         { WM5100_AUDIO_IF_1_16, 6 },
1259         { WM5100_AUDIO_IF_1_17, 7 },
1260 
1261         { WM5100_AUDIO_IF_1_18, 0 },
1262         { WM5100_AUDIO_IF_1_19, 1 },
1263         { WM5100_AUDIO_IF_1_20, 2 },
1264         { WM5100_AUDIO_IF_1_21, 3 },
1265         { WM5100_AUDIO_IF_1_22, 4 },
1266         { WM5100_AUDIO_IF_1_23, 5 },
1267         { WM5100_AUDIO_IF_1_24, 6 },
1268         { WM5100_AUDIO_IF_1_25, 7 },
1269 
1270         { WM5100_AUDIO_IF_2_10, 0 },
1271         { WM5100_AUDIO_IF_2_11, 1 },
1272 
1273         { WM5100_AUDIO_IF_2_18, 0 },
1274         { WM5100_AUDIO_IF_2_19, 1 },
1275 
1276         { WM5100_AUDIO_IF_3_10, 0 },
1277         { WM5100_AUDIO_IF_3_11, 1 },
1278 
1279         { WM5100_AUDIO_IF_3_18, 0 },
1280         { WM5100_AUDIO_IF_3_19, 1 },
1281 };
1282 
1283 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1284 {
1285         struct snd_soc_codec *codec = dai->codec;
1286         int lrclk, bclk, mask, base;
1287 
1288         base = dai->driver->base;
1289 
1290         lrclk = 0;
1291         bclk = 0;
1292 
1293         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1294         case SND_SOC_DAIFMT_DSP_A:
1295                 mask = 0;
1296                 break;
1297         case SND_SOC_DAIFMT_I2S:
1298                 mask = 2;
1299                 break;
1300         default:
1301                 dev_err(codec->dev, "Unsupported DAI format %d\n",
1302                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1303                 return -EINVAL;
1304         }
1305 
1306         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1307         case SND_SOC_DAIFMT_CBS_CFS:
1308                 break;
1309         case SND_SOC_DAIFMT_CBS_CFM:
1310                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1311                 break;
1312         case SND_SOC_DAIFMT_CBM_CFS:
1313                 bclk |= WM5100_AIF1_BCLK_MSTR;
1314                 break;
1315         case SND_SOC_DAIFMT_CBM_CFM:
1316                 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1317                 bclk |= WM5100_AIF1_BCLK_MSTR;
1318                 break;
1319         default:
1320                 dev_err(codec->dev, "Unsupported master mode %d\n",
1321                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
1322                 return -EINVAL;
1323         }
1324 
1325         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1326         case SND_SOC_DAIFMT_NB_NF:
1327                 break;
1328         case SND_SOC_DAIFMT_IB_IF:
1329                 bclk |= WM5100_AIF1_BCLK_INV;
1330                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1331                 break;
1332         case SND_SOC_DAIFMT_IB_NF:
1333                 bclk |= WM5100_AIF1_BCLK_INV;
1334                 break;
1335         case SND_SOC_DAIFMT_NB_IF:
1336                 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1337                 break;
1338         default:
1339                 return -EINVAL;
1340         }
1341 
1342         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1343                             WM5100_AIF1_BCLK_INV, bclk);
1344         snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1345                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1346         snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1347                             WM5100_AIF1TX_LRCLK_INV, lrclk);
1348         snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1349 
1350         return 0;
1351 }
1352 
1353 #define WM5100_NUM_BCLK_RATES 19
1354 
1355 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1356         32000,
1357         48000,
1358         64000,
1359         96000,
1360         128000,
1361         192000,
1362         256000,
1363         384000,
1364         512000,
1365         768000,
1366         1024000,
1367         1536000,
1368         2048000,
1369         3072000,
1370         4096000,
1371         6144000,
1372         8192000,
1373         12288000,
1374         24576000,
1375 };
1376 
1377 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1378         29400,
1379         44100,
1380         58800,
1381         88200,
1382         117600,
1383         176400,
1384         235200,
1385         352800,
1386         470400,
1387         705600,
1388         940800,
1389         1411200,
1390         1881600,
1391         2882400,
1392         3763200,
1393         5644800,
1394         7526400,
1395         11289600,
1396         22579600,
1397 };
1398 
1399 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1400                             struct snd_pcm_hw_params *params,
1401                             struct snd_soc_dai *dai)
1402 {
1403         struct snd_soc_codec *codec = dai->codec;
1404         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1405         bool async = wm5100->aif_async[dai->id];
1406         int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1407         int *bclk_rates;
1408 
1409         base = dai->driver->base;
1410 
1411         /* Data sizes if not using TDM */
1412         wl = params_width(params);
1413         if (wl < 0)
1414                 return wl;
1415         fl = snd_soc_params_to_frame_size(params);
1416         if (fl < 0)
1417                 return fl;
1418 
1419         dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1420                 wl, fl);
1421 
1422         /* Target BCLK rate */
1423         bclk = snd_soc_params_to_bclk(params);
1424         if (bclk < 0)
1425                 return bclk;
1426 
1427         /* Root for BCLK depends on SYS/ASYNCCLK */
1428         if (!async) {
1429                 aif_rate = wm5100->sysclk;
1430                 sr = wm5100_alloc_sr(codec, params_rate(params));
1431                 if (sr < 0)
1432                         return sr;
1433         } else {
1434                 /* If we're in ASYNCCLK set the ASYNC sample rate */
1435                 aif_rate = wm5100->asyncclk;
1436                 sr = 3;
1437 
1438                 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1439                         if (params_rate(params) == wm5100_sr_code[i])
1440                                 break;
1441                 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1442                         dev_err(codec->dev, "Invalid rate %dHzn",
1443                                 params_rate(params));
1444                         return -EINVAL;
1445                 }
1446 
1447                 /* TODO: We should really check for symmetry */
1448                 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1449                                     WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1450         }
1451 
1452         if (!aif_rate) {
1453                 dev_err(codec->dev, "%s has no rate set\n",
1454                         async ? "ASYNCCLK" : "SYSCLK");
1455                 return -EINVAL;
1456         }
1457 
1458         dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1459                 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1460 
1461         if (aif_rate % 4000)
1462                 bclk_rates = wm5100_bclk_rates_cd;
1463         else
1464                 bclk_rates = wm5100_bclk_rates_dat;
1465 
1466         for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1467                 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1468                         break;
1469         if (i == WM5100_NUM_BCLK_RATES) {
1470                 dev_err(codec->dev,
1471                         "No valid BCLK for %dHz found from %dHz %s\n",
1472                         bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1473                 return -EINVAL;
1474         }
1475 
1476         bclk = i;
1477         dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1478         snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1479 
1480         lrclk = bclk_rates[bclk] / params_rate(params);
1481         dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1482         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1483             wm5100->aif_symmetric[dai->id])
1484                 snd_soc_update_bits(codec, base + 7,
1485                                     WM5100_AIF1RX_BCPF_MASK, lrclk);
1486         else
1487                 snd_soc_update_bits(codec, base + 6,
1488                                     WM5100_AIF1TX_BCPF_MASK, lrclk);
1489 
1490         i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1491         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1492                 snd_soc_update_bits(codec, base + 9,
1493                                     WM5100_AIF1RX_WL_MASK |
1494                                     WM5100_AIF1RX_SLOT_LEN_MASK, i);
1495         else
1496                 snd_soc_update_bits(codec, base + 8,
1497                                     WM5100_AIF1TX_WL_MASK |
1498                                     WM5100_AIF1TX_SLOT_LEN_MASK, i);
1499 
1500         snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1501 
1502         return 0;
1503 }
1504 
1505 static const struct snd_soc_dai_ops wm5100_dai_ops = {
1506         .set_fmt = wm5100_set_fmt,
1507         .hw_params = wm5100_hw_params,
1508 };
1509 
1510 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1511                              int source, unsigned int freq, int dir)
1512 {
1513         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1514         int *rate_store;
1515         int fval, audio_rate, ret, reg;
1516 
1517         switch (clk_id) {
1518         case WM5100_CLK_SYSCLK:
1519                 reg = WM5100_CLOCKING_3;
1520                 rate_store = &wm5100->sysclk;
1521                 break;
1522         case WM5100_CLK_ASYNCCLK:
1523                 reg = WM5100_CLOCKING_7;
1524                 rate_store = &wm5100->asyncclk;
1525                 break;
1526         case WM5100_CLK_32KHZ:
1527                 /* The 32kHz clock is slightly different to the others */
1528                 switch (source) {
1529                 case WM5100_CLKSRC_MCLK1:
1530                 case WM5100_CLKSRC_MCLK2:
1531                 case WM5100_CLKSRC_SYSCLK:
1532                         snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1533                                             WM5100_CLK_32K_SRC_MASK,
1534                                             source);
1535                         break;
1536                 default:
1537                         return -EINVAL;
1538                 }
1539                 return 0;
1540 
1541         case WM5100_CLK_AIF1:
1542         case WM5100_CLK_AIF2:
1543         case WM5100_CLK_AIF3:
1544                 /* Not real clocks, record which clock domain they're in */
1545                 switch (source) {
1546                 case WM5100_CLKSRC_SYSCLK:
1547                         wm5100->aif_async[clk_id - 1] = false;
1548                         break;
1549                 case WM5100_CLKSRC_ASYNCCLK:
1550                         wm5100->aif_async[clk_id - 1] = true;
1551                         break;
1552                 default:
1553                         dev_err(codec->dev, "Invalid source %d\n", source);
1554                         return -EINVAL;
1555                 }       
1556                 return 0;
1557 
1558         case WM5100_CLK_OPCLK:
1559                 switch (freq) {
1560                 case 5644800:
1561                 case 6144000:
1562                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1563                                             WM5100_OPCLK_SEL_MASK, 0);
1564                         break;
1565                 case 11289600:
1566                 case 12288000:
1567                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1568                                             WM5100_OPCLK_SEL_MASK, 0);
1569                         break;
1570                 case 22579200:
1571                 case 24576000:
1572                         snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1573                                             WM5100_OPCLK_SEL_MASK, 0);
1574                         break;
1575                 default:
1576                         dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1577                                 freq);
1578                         return -EINVAL;
1579                 }
1580                 return 0;
1581 
1582         default:
1583                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1584                 return -EINVAL;
1585         }
1586 
1587         switch (source) {
1588         case WM5100_CLKSRC_SYSCLK:
1589         case WM5100_CLKSRC_ASYNCCLK:
1590                 dev_err(codec->dev, "Invalid source %d\n", source);
1591                 return -EINVAL;
1592         }
1593 
1594         switch (freq) {
1595         case 5644800:
1596         case 6144000:
1597                 fval = 0;
1598                 break;
1599         case 11289600:
1600         case 12288000:
1601                 fval = 1;
1602                 break;
1603         case 22579200:
1604         case 24576000:
1605                 fval = 2;
1606                 break;
1607         default:
1608                 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1609                 return -EINVAL;
1610         }
1611 
1612         switch (freq) {
1613         case 5644800:
1614         case 11289600:
1615         case 22579200:
1616                 audio_rate = 44100;
1617                 break;
1618 
1619         case 6144000:
1620         case 12288000:
1621         case 24576000:
1622                 audio_rate = 48000;
1623                 break;
1624 
1625         default:
1626                 BUG();
1627                 audio_rate = 0;
1628                 break;
1629         }
1630 
1631         /* TODO: Check if MCLKs are in use and enable/disable pulls to
1632          * match.
1633          */
1634 
1635         snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1636                             WM5100_SYSCLK_SRC_MASK,
1637                             fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1638 
1639         /* If this is SYSCLK then configure the clock rate for the
1640          * internal audio functions to the natural sample rate for
1641          * this clock rate.
1642          */
1643         if (clk_id == WM5100_CLK_SYSCLK) {
1644                 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1645                         audio_rate);
1646                 if (0 && *rate_store)
1647                         wm5100_free_sr(codec, audio_rate);
1648                 ret = wm5100_alloc_sr(codec, audio_rate);
1649                 if (ret != 0)
1650                         dev_warn(codec->dev, "Primary audio slot is %d\n",
1651                                  ret);
1652         }
1653 
1654         *rate_store = freq;
1655 
1656         return 0;
1657 }
1658 
1659 struct _fll_div {
1660         u16 fll_fratio;
1661         u16 fll_outdiv;
1662         u16 fll_refclk_div;
1663         u16 n;
1664         u16 theta;
1665         u16 lambda;
1666 };
1667 
1668 static struct {
1669         unsigned int min;
1670         unsigned int max;
1671         u16 fll_fratio;
1672         int ratio;
1673 } fll_fratios[] = {
1674         {       0,    64000, 4, 16 },
1675         {   64000,   128000, 3,  8 },
1676         {  128000,   256000, 2,  4 },
1677         {  256000,  1000000, 1,  2 },
1678         { 1000000, 13500000, 0,  1 },
1679 };
1680 
1681 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1682                        unsigned int Fout)
1683 {
1684         unsigned int target;
1685         unsigned int div;
1686         unsigned int fratio, gcd_fll;
1687         int i;
1688 
1689         /* Fref must be <=13.5MHz */
1690         div = 1;
1691         fll_div->fll_refclk_div = 0;
1692         while ((Fref / div) > 13500000) {
1693                 div *= 2;
1694                 fll_div->fll_refclk_div++;
1695 
1696                 if (div > 8) {
1697                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1698                                Fref);
1699                         return -EINVAL;
1700                 }
1701         }
1702 
1703         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1704 
1705         /* Apply the division for our remaining calculations */
1706         Fref /= div;
1707 
1708         /* Fvco should be 90-100MHz; don't check the upper bound */
1709         div = 2;
1710         while (Fout * div < 90000000) {
1711                 div++;
1712                 if (div > 64) {
1713                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1714                                Fout);
1715                         return -EINVAL;
1716                 }
1717         }
1718         target = Fout * div;
1719         fll_div->fll_outdiv = div - 1;
1720 
1721         pr_debug("FLL Fvco=%dHz\n", target);
1722 
1723         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1724         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1725                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1726                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1727                         fratio = fll_fratios[i].ratio;
1728                         break;
1729                 }
1730         }
1731         if (i == ARRAY_SIZE(fll_fratios)) {
1732                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1733                 return -EINVAL;
1734         }
1735 
1736         fll_div->n = target / (fratio * Fref);
1737 
1738         if (target % Fref == 0) {
1739                 fll_div->theta = 0;
1740                 fll_div->lambda = 0;
1741         } else {
1742                 gcd_fll = gcd(target, fratio * Fref);
1743 
1744                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1745                         / gcd_fll;
1746                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1747         }
1748 
1749         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1750                  fll_div->n, fll_div->theta, fll_div->lambda);
1751         pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1752                  fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1753                  fll_div->fll_refclk_div);
1754 
1755         return 0;
1756 }
1757 
1758 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1759                           unsigned int Fref, unsigned int Fout)
1760 {
1761         struct i2c_client *i2c = to_i2c_client(codec->dev);
1762         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1763         struct _fll_div factors;
1764         struct wm5100_fll *fll;
1765         int ret, base, lock, i, timeout;
1766         unsigned long time_left;
1767 
1768         switch (fll_id) {
1769         case WM5100_FLL1:
1770                 fll = &wm5100->fll[0];
1771                 base = WM5100_FLL1_CONTROL_1 - 1;
1772                 lock = WM5100_FLL1_LOCK_STS;
1773                 break;
1774         case WM5100_FLL2:
1775                 fll = &wm5100->fll[1];
1776                 base = WM5100_FLL2_CONTROL_2 - 1;
1777                 lock = WM5100_FLL2_LOCK_STS;
1778                 break;
1779         default:
1780                 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1781                 return -EINVAL;
1782         }
1783 
1784         if (!Fout) {
1785                 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1786                 if (fll->fout)
1787                         pm_runtime_put(codec->dev);
1788                 fll->fout = 0;
1789                 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1790                 return 0;
1791         }
1792 
1793         switch (source) {
1794         case WM5100_FLL_SRC_MCLK1:
1795         case WM5100_FLL_SRC_MCLK2:
1796         case WM5100_FLL_SRC_FLL1:
1797         case WM5100_FLL_SRC_FLL2:
1798         case WM5100_FLL_SRC_AIF1BCLK:
1799         case WM5100_FLL_SRC_AIF2BCLK:
1800         case WM5100_FLL_SRC_AIF3BCLK:
1801                 break;
1802         default:
1803                 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1804                 return -EINVAL;
1805         }
1806 
1807         ret = fll_factors(&factors, Fref, Fout);
1808         if (ret < 0)
1809                 return ret;
1810 
1811         /* Disable the FLL while we reconfigure */
1812         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1813 
1814         snd_soc_update_bits(codec, base + 2,
1815                             WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1816                             (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1817                             factors.fll_fratio);
1818         snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1819                             factors.theta);
1820         snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1821         snd_soc_update_bits(codec, base + 6,
1822                             WM5100_FLL1_REFCLK_DIV_MASK |
1823                             WM5100_FLL1_REFCLK_SRC_MASK,
1824                             (factors.fll_refclk_div
1825                              << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1826         snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1827                             factors.lambda);
1828 
1829         /* Clear any pending completions */
1830         try_wait_for_completion(&fll->lock);
1831 
1832         pm_runtime_get_sync(codec->dev);
1833 
1834         snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1835 
1836         if (i2c->irq)
1837                 timeout = 2;
1838         else
1839                 timeout = 50;
1840 
1841         snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1842                             WM5100_SYSCLK_ENA);
1843 
1844         /* Poll for the lock; will use interrupt when we can test */
1845         for (i = 0; i < timeout; i++) {
1846                 if (i2c->irq) {
1847                         time_left = wait_for_completion_timeout(&fll->lock,
1848                                                         msecs_to_jiffies(25));
1849                         if (time_left > 0)
1850                                 break;
1851                 } else {
1852                         msleep(1);
1853                 }
1854 
1855                 ret = snd_soc_read(codec,
1856                                    WM5100_INTERRUPT_RAW_STATUS_3);
1857                 if (ret < 0) {
1858                         dev_err(codec->dev,
1859                                 "Failed to read FLL status: %d\n",
1860                                 ret);
1861                         continue;
1862                 }
1863                 if (ret & lock)
1864                         break;
1865         }
1866         if (i == timeout) {
1867                 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1868                 pm_runtime_put(codec->dev);
1869                 return -ETIMEDOUT;
1870         }
1871 
1872         fll->src = source;
1873         fll->fref = Fref;
1874         fll->fout = Fout;
1875 
1876         dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1877                 Fref, Fout);
1878 
1879         return 0;
1880 }
1881 
1882 /* Actually go much higher */
1883 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1884 
1885 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1886                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1887 
1888 static struct snd_soc_dai_driver wm5100_dai[] = {
1889         {
1890                 .name = "wm5100-aif1",
1891                 .base = WM5100_AUDIO_IF_1_1 - 1,
1892                 .playback = {
1893                         .stream_name = "AIF1 Playback",
1894                         .channels_min = 2,
1895                         .channels_max = 2,
1896                         .rates = WM5100_RATES,
1897                         .formats = WM5100_FORMATS,
1898                 },
1899                 .capture = {
1900                          .stream_name = "AIF1 Capture",
1901                          .channels_min = 2,
1902                          .channels_max = 2,
1903                          .rates = WM5100_RATES,
1904                          .formats = WM5100_FORMATS,
1905                  },
1906                 .ops = &wm5100_dai_ops,
1907         },
1908         {
1909                 .name = "wm5100-aif2",
1910                 .id = 1,
1911                 .base = WM5100_AUDIO_IF_2_1 - 1,
1912                 .playback = {
1913                         .stream_name = "AIF2 Playback",
1914                         .channels_min = 2,
1915                         .channels_max = 2,
1916                         .rates = WM5100_RATES,
1917                         .formats = WM5100_FORMATS,
1918                 },
1919                 .capture = {
1920                          .stream_name = "AIF2 Capture",
1921                          .channels_min = 2,
1922                          .channels_max = 2,
1923                          .rates = WM5100_RATES,
1924                          .formats = WM5100_FORMATS,
1925                  },
1926                 .ops = &wm5100_dai_ops,
1927         },
1928         {
1929                 .name = "wm5100-aif3",
1930                 .id = 2,
1931                 .base = WM5100_AUDIO_IF_3_1 - 1,
1932                 .playback = {
1933                         .stream_name = "AIF3 Playback",
1934                         .channels_min = 2,
1935                         .channels_max = 2,
1936                         .rates = WM5100_RATES,
1937                         .formats = WM5100_FORMATS,
1938                 },
1939                 .capture = {
1940                          .stream_name = "AIF3 Capture",
1941                          .channels_min = 2,
1942                          .channels_max = 2,
1943                          .rates = WM5100_RATES,
1944                          .formats = WM5100_FORMATS,
1945                  },
1946                 .ops = &wm5100_dai_ops,
1947         },
1948 };
1949 
1950 static int wm5100_dig_vu[] = {
1951         WM5100_ADC_DIGITAL_VOLUME_1L,
1952         WM5100_ADC_DIGITAL_VOLUME_1R,
1953         WM5100_ADC_DIGITAL_VOLUME_2L,
1954         WM5100_ADC_DIGITAL_VOLUME_2R,
1955         WM5100_ADC_DIGITAL_VOLUME_3L,
1956         WM5100_ADC_DIGITAL_VOLUME_3R,
1957         WM5100_ADC_DIGITAL_VOLUME_4L,
1958         WM5100_ADC_DIGITAL_VOLUME_4R,
1959 
1960         WM5100_DAC_DIGITAL_VOLUME_1L,
1961         WM5100_DAC_DIGITAL_VOLUME_1R,
1962         WM5100_DAC_DIGITAL_VOLUME_2L,
1963         WM5100_DAC_DIGITAL_VOLUME_2R,
1964         WM5100_DAC_DIGITAL_VOLUME_3L,
1965         WM5100_DAC_DIGITAL_VOLUME_3R,
1966         WM5100_DAC_DIGITAL_VOLUME_4L,
1967         WM5100_DAC_DIGITAL_VOLUME_4R,
1968         WM5100_DAC_DIGITAL_VOLUME_5L,
1969         WM5100_DAC_DIGITAL_VOLUME_5R,
1970         WM5100_DAC_DIGITAL_VOLUME_6L,
1971         WM5100_DAC_DIGITAL_VOLUME_6R,
1972 };
1973 
1974 static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
1975 {
1976         struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1977 
1978         if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
1979                 return;
1980 
1981         gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
1982         regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1983                            WM5100_ACCDET_BIAS_SRC_MASK |
1984                            WM5100_ACCDET_SRC,
1985                            (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1986                            mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1987         regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1988                            WM5100_HPCOM_SRC,
1989                            mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
1990 
1991         wm5100->jack_mode = the_mode;
1992 
1993         dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
1994                 wm5100->jack_mode);
1995 }
1996 
1997 static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1998 {
1999         dev_dbg(wm5100->dev, "Headphone detected\n");
2000         wm5100->jack_detecting = false;
2001         snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2002                             SND_JACK_HEADPHONE);
2003 
2004         /* Increase the detection rate a bit for responsiveness. */
2005         regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2006                            WM5100_ACCDET_RATE_MASK,
2007                            7 << WM5100_ACCDET_RATE_SHIFT);
2008 }
2009 
2010 static void wm5100_micd_irq(struct wm5100_priv *wm5100)
2011 {
2012         unsigned int val;
2013         int ret;
2014 
2015         ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2016         if (ret != 0) {
2017                 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2018                         ret);
2019                 return;
2020         }
2021 
2022         dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
2023 
2024         if (!(val & WM5100_ACCDET_VALID)) {
2025                 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
2026                 return;
2027         }
2028 
2029         /* No accessory, reset everything and report removal */
2030         if (!(val & WM5100_ACCDET_STS)) {
2031                 dev_dbg(wm5100->dev, "Jack removal detected\n");
2032                 wm5100->jack_mic = false;
2033                 wm5100->jack_detecting = true;
2034                 wm5100->jack_flips = 0;
2035                 snd_soc_jack_report(wm5100->jack, 0,
2036                                     SND_JACK_LINEOUT | SND_JACK_HEADSET |
2037                                     SND_JACK_BTN_0);
2038 
2039                 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2040                                    WM5100_ACCDET_RATE_MASK,
2041                                    WM5100_ACCDET_RATE_MASK);
2042                 return;
2043         }
2044 
2045         /* If the measurement is very high we've got a microphone,
2046          * either we just detected one or if we already reported then
2047          * we've got a button release event.
2048          */
2049         if (val & 0x400) {
2050                 if (wm5100->jack_detecting) {
2051                         dev_dbg(wm5100->dev, "Microphone detected\n");
2052                         wm5100->jack_mic = true;
2053                         wm5100->jack_detecting = false;
2054                         snd_soc_jack_report(wm5100->jack,
2055                                             SND_JACK_HEADSET,
2056                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2057 
2058                         /* Increase poll rate to give better responsiveness
2059                          * for buttons */
2060                         regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2061                                            WM5100_ACCDET_RATE_MASK,
2062                                            5 << WM5100_ACCDET_RATE_SHIFT);
2063                 } else {
2064                         dev_dbg(wm5100->dev, "Mic button up\n");
2065                         snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2066                 }
2067 
2068                 return;
2069         }
2070 
2071         /* If we detected a lower impedence during initial startup
2072          * then we probably have the wrong polarity, flip it.  Don't
2073          * do this for the lowest impedences to speed up detection of
2074          * plain headphones and give up if neither polarity looks
2075          * sensible.
2076          */
2077         if (wm5100->jack_detecting && (val & 0x3f8)) {
2078                 wm5100->jack_flips++;
2079 
2080                 if (wm5100->jack_flips > 1)
2081                         wm5100_report_headphone(wm5100);
2082                 else
2083                         wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
2084 
2085                 return;
2086         }
2087 
2088         /* Don't distinguish between buttons, just report any low
2089          * impedence as BTN_0.
2090          */
2091         if (val & 0x3fc) {
2092                 if (wm5100->jack_mic) {
2093                         dev_dbg(wm5100->dev, "Mic button detected\n");
2094                         snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2095                                             SND_JACK_BTN_0);
2096                 } else if (wm5100->jack_detecting) {
2097                         wm5100_report_headphone(wm5100);
2098                 }
2099         }
2100 }
2101 
2102 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2103 {
2104         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2105         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2106 
2107         if (jack) {
2108                 wm5100->jack = jack;
2109                 wm5100->jack_detecting = true;
2110                 wm5100->jack_flips = 0;
2111 
2112                 wm5100_set_detect_mode(wm5100, 0);
2113 
2114                 /* Slowest detection rate, gives debounce for initial
2115                  * detection */
2116                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2117                                     WM5100_ACCDET_BIAS_STARTTIME_MASK |
2118                                     WM5100_ACCDET_RATE_MASK,
2119                                     (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2120                                     WM5100_ACCDET_RATE_MASK);
2121 
2122                 /* We need the charge pump to power MICBIAS */
2123                 snd_soc_dapm_mutex_lock(dapm);
2124 
2125                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
2126                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2127 
2128                 snd_soc_dapm_sync_unlocked(dapm);
2129 
2130                 snd_soc_dapm_mutex_unlock(dapm);
2131 
2132                 /* We start off just enabling microphone detection - even a
2133                  * plain headphone will trigger detection.
2134                  */
2135                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2136                                     WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2137 
2138                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2139                                     WM5100_IM_ACCDET_EINT, 0);
2140         } else {
2141                 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2142                                     WM5100_IM_HPDET_EINT |
2143                                     WM5100_IM_ACCDET_EINT,
2144                                     WM5100_IM_HPDET_EINT |
2145                                     WM5100_IM_ACCDET_EINT);
2146                 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2147                                     WM5100_ACCDET_ENA, 0);
2148                 wm5100->jack = NULL;
2149         }
2150 
2151         return 0;
2152 }
2153 EXPORT_SYMBOL_GPL(wm5100_detect);
2154 
2155 static irqreturn_t wm5100_irq(int irq, void *data)
2156 {
2157         struct wm5100_priv *wm5100 = data;
2158         irqreturn_t status = IRQ_NONE;
2159         unsigned int irq_val, mask_val;
2160         int ret;
2161 
2162         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2163         if (ret < 0) {
2164                 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2165                         ret);
2166                 irq_val = 0;
2167         }
2168 
2169         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2170                           &mask_val);
2171         if (ret < 0) {
2172                 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2173                         ret);
2174                 mask_val = 0xffff;
2175         }
2176 
2177         irq_val &= ~mask_val;
2178 
2179         regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
2180 
2181         if (irq_val)
2182                 status = IRQ_HANDLED;
2183 
2184         wm5100_log_status3(wm5100, irq_val);
2185 
2186         if (irq_val & WM5100_FLL1_LOCK_EINT) {
2187                 dev_dbg(wm5100->dev, "FLL1 locked\n");
2188                 complete(&wm5100->fll[0].lock);
2189         }
2190         if (irq_val & WM5100_FLL2_LOCK_EINT) {
2191                 dev_dbg(wm5100->dev, "FLL2 locked\n");
2192                 complete(&wm5100->fll[1].lock);
2193         }
2194 
2195         if (irq_val & WM5100_ACCDET_EINT)
2196                 wm5100_micd_irq(wm5100);
2197 
2198         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2199         if (ret < 0) {
2200                 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2201                         ret);
2202                 irq_val = 0;
2203         }
2204 
2205         ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2206                           &mask_val);
2207         if (ret < 0) {
2208                 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2209                         ret);
2210                 mask_val = 0xffff;
2211         }
2212 
2213         irq_val &= ~mask_val;
2214 
2215         if (irq_val)
2216                 status = IRQ_HANDLED;
2217 
2218         regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
2219 
2220         wm5100_log_status4(wm5100, irq_val);
2221 
2222         return status;
2223 }
2224 
2225 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2226 {
2227         irqreturn_t ret = IRQ_NONE;
2228         irqreturn_t val;
2229 
2230         do {
2231                 val = wm5100_irq(irq, data);
2232                 if (val != IRQ_NONE)
2233                         ret = val;
2234         } while (val != IRQ_NONE);
2235 
2236         return ret;
2237 }
2238 
2239 #ifdef CONFIG_GPIOLIB
2240 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2241 {
2242         struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2243 
2244         regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2245                            WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2246 }
2247 
2248 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2249                                      unsigned offset, int value)
2250 {
2251         struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2252         int val, ret;
2253 
2254         val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2255 
2256         ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2257                                  WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2258                                  WM5100_GP1_LVL, val);
2259         if (ret < 0)
2260                 return ret;
2261         else
2262                 return 0;
2263 }
2264 
2265 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2266 {
2267         struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2268         unsigned int reg;
2269         int ret;
2270 
2271         ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
2272         if (ret < 0)
2273                 return ret;
2274 
2275         return (reg & WM5100_GP1_LVL) != 0;
2276 }
2277 
2278 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2279 {
2280         struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2281 
2282         return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2283                                   WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2284                                   (1 << WM5100_GP1_FN_SHIFT) |
2285                                   (1 << WM5100_GP1_DIR_SHIFT));
2286 }
2287 
2288 static struct gpio_chip wm5100_template_chip = {
2289         .label                  = "wm5100",
2290         .owner                  = THIS_MODULE,
2291         .direction_output       = wm5100_gpio_direction_out,
2292         .set                    = wm5100_gpio_set,
2293         .direction_input        = wm5100_gpio_direction_in,
2294         .get                    = wm5100_gpio_get,
2295         .can_sleep              = 1,
2296 };
2297 
2298 static void wm5100_init_gpio(struct i2c_client *i2c)
2299 {
2300         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2301         int ret;
2302 
2303         wm5100->gpio_chip = wm5100_template_chip;
2304         wm5100->gpio_chip.ngpio = 6;
2305         wm5100->gpio_chip.parent = &i2c->dev;
2306 
2307         if (wm5100->pdata.gpio_base)
2308                 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2309         else
2310                 wm5100->gpio_chip.base = -1;
2311 
2312         ret = gpiochip_add_data(&wm5100->gpio_chip, wm5100);
2313         if (ret != 0)
2314                 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
2315 }
2316 
2317 static void wm5100_free_gpio(struct i2c_client *i2c)
2318 {
2319         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2320 
2321         gpiochip_remove(&wm5100->gpio_chip);
2322 }
2323 #else
2324 static void wm5100_init_gpio(struct i2c_client *i2c)
2325 {
2326 }
2327 
2328 static void wm5100_free_gpio(struct i2c_client *i2c)
2329 {
2330 }
2331 #endif
2332 
2333 static int wm5100_probe(struct snd_soc_codec *codec)
2334 {
2335         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2336         struct i2c_client *i2c = to_i2c_client(codec->dev);
2337         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2338         int ret, i;
2339 
2340         wm5100->codec = codec;
2341 
2342         for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2343                 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2344                                     WM5100_OUT_VU);
2345 
2346         /* Don't debounce interrupts to support use of SYSCLK only */
2347         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2348         snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2349 
2350         /* TODO: check if we're symmetric */
2351 
2352         if (i2c->irq)
2353                 snd_soc_dapm_new_controls(dapm, wm5100_dapm_widgets_noirq,
2354                                           ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2355 
2356         if (wm5100->pdata.hp_pol) {
2357                 ret = gpio_request_one(wm5100->pdata.hp_pol,
2358                                        GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2359                 if (ret < 0) {
2360                         dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2361                                 wm5100->pdata.hp_pol, ret);
2362                         goto err_gpio;
2363                 }
2364         }
2365 
2366         return 0;
2367 
2368 err_gpio:
2369 
2370         return ret;
2371 }
2372 
2373 static int wm5100_remove(struct snd_soc_codec *codec)
2374 {
2375         struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2376 
2377         if (wm5100->pdata.hp_pol) {
2378                 gpio_free(wm5100->pdata.hp_pol);
2379         }
2380 
2381         return 0;
2382 }
2383 
2384 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2385         .probe =        wm5100_probe,
2386         .remove =       wm5100_remove,
2387 
2388         .set_sysclk = wm5100_set_sysclk,
2389         .set_pll = wm5100_set_fll,
2390         .idle_bias_off = 1,
2391 
2392         .seq_notifier = wm5100_seq_notifier,
2393         .controls = wm5100_snd_controls,
2394         .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2395         .dapm_widgets = wm5100_dapm_widgets,
2396         .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2397         .dapm_routes = wm5100_dapm_routes,
2398         .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2399 };
2400 
2401 static const struct regmap_config wm5100_regmap = {
2402         .reg_bits = 16,
2403         .val_bits = 16,
2404 
2405         .max_register = WM5100_MAX_REGISTER,
2406         .reg_defaults = wm5100_reg_defaults,
2407         .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2408         .volatile_reg = wm5100_volatile_register,
2409         .readable_reg = wm5100_readable_register,
2410         .cache_type = REGCACHE_RBTREE,
2411 };
2412 
2413 static const unsigned int wm5100_mic_ctrl_reg[] = {
2414         WM5100_IN1L_CONTROL,
2415         WM5100_IN2L_CONTROL,
2416         WM5100_IN3L_CONTROL,
2417         WM5100_IN4L_CONTROL,
2418 };
2419 
2420 static int wm5100_i2c_probe(struct i2c_client *i2c,
2421                             const struct i2c_device_id *id)
2422 {
2423         struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2424         struct wm5100_priv *wm5100;
2425         unsigned int reg;
2426         int ret, i, irq_flags;
2427 
2428         wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2429                               GFP_KERNEL);
2430         if (wm5100 == NULL)
2431                 return -ENOMEM;
2432 
2433         wm5100->dev = &i2c->dev;
2434 
2435         wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
2436         if (IS_ERR(wm5100->regmap)) {
2437                 ret = PTR_ERR(wm5100->regmap);
2438                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2439                         ret);
2440                 goto err;
2441         }
2442 
2443         for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2444                 init_completion(&wm5100->fll[i].lock);
2445 
2446         if (pdata)
2447                 wm5100->pdata = *pdata;
2448 
2449         i2c_set_clientdata(i2c, wm5100);
2450 
2451         for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2452                 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2453 
2454         ret = devm_regulator_bulk_get(&i2c->dev,
2455                                       ARRAY_SIZE(wm5100->core_supplies),
2456                                       wm5100->core_supplies);
2457         if (ret != 0) {
2458                 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2459                         ret);
2460                 goto err;
2461         }
2462 
2463         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2464                                     wm5100->core_supplies);
2465         if (ret != 0) {
2466                 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2467                         ret);
2468                 goto err;
2469         }
2470 
2471         if (wm5100->pdata.ldo_ena) {
2472                 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2473                                        GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2474                 if (ret < 0) {
2475                         dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2476                                 wm5100->pdata.ldo_ena, ret);
2477                         goto err_enable;
2478                 }
2479                 msleep(2);
2480         }
2481 
2482         if (wm5100->pdata.reset) {
2483                 ret = gpio_request_one(wm5100->pdata.reset,
2484                                        GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2485                 if (ret < 0) {
2486                         dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2487                                 wm5100->pdata.reset, ret);
2488                         goto err_ldo;
2489                 }
2490         }
2491 
2492         ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2493         if (ret < 0) {
2494                 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2495                 goto err_reset;
2496         }
2497         switch (reg) {
2498         case 0x8997:
2499         case 0x5100:
2500                 break;
2501 
2502         default:
2503                 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2504                 ret = -EINVAL;
2505                 goto err_reset;
2506         }
2507 
2508         ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2509         if (ret < 0) {
2510                 dev_err(&i2c->dev, "Failed to read revision register\n");
2511                 goto err_reset;
2512         }
2513         wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2514 
2515         dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2516 
2517         ret = wm5100_reset(wm5100);
2518         if (ret < 0) {
2519                 dev_err(&i2c->dev, "Failed to issue reset\n");
2520                 goto err_reset;
2521         }
2522 
2523         switch (wm5100->rev) {
2524         case 0:
2525                 ret = regmap_register_patch(wm5100->regmap,
2526                                             wm5100_reva_patches,
2527                                             ARRAY_SIZE(wm5100_reva_patches));
2528                 if (ret != 0) {
2529                         dev_err(&i2c->dev, "Failed to register patches: %d\n",
2530                                 ret);
2531                         goto err_reset;
2532                 }
2533                 break;
2534         default:
2535                 break;
2536         }
2537 
2538 
2539         wm5100_init_gpio(i2c);
2540 
2541         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2542                 if (!wm5100->pdata.gpio_defaults[i])
2543                         continue;
2544 
2545                 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2546                              wm5100->pdata.gpio_defaults[i]);
2547         }
2548 
2549         for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2550                 regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
2551                                    WM5100_IN1_MODE_MASK |
2552                                    WM5100_IN1_DMIC_SUP_MASK,
2553                                    (wm5100->pdata.in_mode[i] <<
2554                                     WM5100_IN1_MODE_SHIFT) |
2555                                    (wm5100->pdata.dmic_sup[i] <<
2556                                     WM5100_IN1_DMIC_SUP_SHIFT));
2557         }
2558 
2559         if (i2c->irq) {
2560                 if (wm5100->pdata.irq_flags)
2561                         irq_flags = wm5100->pdata.irq_flags;
2562                 else
2563                         irq_flags = IRQF_TRIGGER_LOW;
2564 
2565                 irq_flags |= IRQF_ONESHOT;
2566 
2567                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2568                         ret = request_threaded_irq(i2c->irq, NULL,
2569                                                    wm5100_edge_irq, irq_flags,
2570                                                    "wm5100", wm5100);
2571                 else
2572                         ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2573                                                    irq_flags, "wm5100",
2574                                                    wm5100);
2575 
2576                 if (ret != 0) {
2577                         dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2578                                 i2c->irq, ret);
2579                 } else {
2580                         /* Enable default interrupts */
2581                         regmap_update_bits(wm5100->regmap,
2582                                            WM5100_INTERRUPT_STATUS_3_MASK,
2583                                            WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2584                                            WM5100_IM_SPK_SHUTDOWN_EINT |
2585                                            WM5100_IM_ASRC2_LOCK_EINT |
2586                                            WM5100_IM_ASRC1_LOCK_EINT |
2587                                            WM5100_IM_FLL2_LOCK_EINT |
2588                                            WM5100_IM_FLL1_LOCK_EINT |
2589                                            WM5100_CLKGEN_ERR_EINT |
2590                                            WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2591 
2592                         regmap_update_bits(wm5100->regmap,
2593                                            WM5100_INTERRUPT_STATUS_4_MASK,
2594                                            WM5100_AIF3_ERR_EINT |
2595                                            WM5100_AIF2_ERR_EINT |
2596                                            WM5100_AIF1_ERR_EINT |
2597                                            WM5100_CTRLIF_ERR_EINT |
2598                                            WM5100_ISRC2_UNDERCLOCKED_EINT |
2599                                            WM5100_ISRC1_UNDERCLOCKED_EINT |
2600                                            WM5100_FX_UNDERCLOCKED_EINT |
2601                                            WM5100_AIF3_UNDERCLOCKED_EINT |
2602                                            WM5100_AIF2_UNDERCLOCKED_EINT |
2603                                            WM5100_AIF1_UNDERCLOCKED_EINT |
2604                                            WM5100_ASRC_UNDERCLOCKED_EINT |
2605                                            WM5100_DAC_UNDERCLOCKED_EINT |
2606                                            WM5100_ADC_UNDERCLOCKED_EINT |
2607                                            WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2608                 }
2609         }
2610 
2611         pm_runtime_set_active(&i2c->dev);
2612         pm_runtime_enable(&i2c->dev);
2613         pm_request_idle(&i2c->dev);
2614 
2615         ret = snd_soc_register_codec(&i2c->dev,
2616                                      &soc_codec_dev_wm5100, wm5100_dai,
2617                                      ARRAY_SIZE(wm5100_dai));
2618         if (ret < 0) {
2619                 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2620                 goto err_reset;
2621         }
2622 
2623         return ret;
2624 
2625 err_reset:
2626         if (i2c->irq)
2627                 free_irq(i2c->irq, wm5100);
2628         wm5100_free_gpio(i2c);
2629         if (wm5100->pdata.reset) {
2630                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2631                 gpio_free(wm5100->pdata.reset);
2632         }
2633 err_ldo:
2634         if (wm5100->pdata.ldo_ena) {
2635                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2636                 gpio_free(wm5100->pdata.ldo_ena);
2637         }
2638 err_enable:
2639         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2640                                wm5100->core_supplies);
2641 err:
2642         return ret;
2643 }
2644 
2645 static int wm5100_i2c_remove(struct i2c_client *i2c)
2646 {
2647         struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2648 
2649         snd_soc_unregister_codec(&i2c->dev);
2650         if (i2c->irq)
2651                 free_irq(i2c->irq, wm5100);
2652         wm5100_free_gpio(i2c);
2653         if (wm5100->pdata.reset) {
2654                 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2655                 gpio_free(wm5100->pdata.reset);
2656         }
2657         if (wm5100->pdata.ldo_ena) {
2658                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2659                 gpio_free(wm5100->pdata.ldo_ena);
2660         }
2661 
2662         return 0;
2663 }
2664 
2665 #ifdef CONFIG_PM
2666 static int wm5100_runtime_suspend(struct device *dev)
2667 {
2668         struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2669 
2670         regcache_cache_only(wm5100->regmap, true);
2671         regcache_mark_dirty(wm5100->regmap);
2672         if (wm5100->pdata.ldo_ena)
2673                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2674         regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2675                                wm5100->core_supplies);
2676 
2677         return 0;
2678 }
2679 
2680 static int wm5100_runtime_resume(struct device *dev)
2681 {
2682         struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2683         int ret;
2684 
2685         ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2686                                     wm5100->core_supplies);
2687         if (ret != 0) {
2688                 dev_err(dev, "Failed to enable supplies: %d\n",
2689                         ret);
2690                 return ret;
2691         }
2692 
2693         if (wm5100->pdata.ldo_ena) {
2694                 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2695                 msleep(2);
2696         }
2697 
2698         regcache_cache_only(wm5100->regmap, false);
2699         regcache_sync(wm5100->regmap);
2700 
2701         return 0;
2702 }
2703 #endif
2704 
2705 static const struct dev_pm_ops wm5100_pm = {
2706         SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2707                            NULL)
2708 };
2709 
2710 static const struct i2c_device_id wm5100_i2c_id[] = {
2711         { "wm5100", 0 },
2712         { }
2713 };
2714 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2715 
2716 static struct i2c_driver wm5100_i2c_driver = {
2717         .driver = {
2718                 .name = "wm5100",
2719                 .pm = &wm5100_pm,
2720         },
2721         .probe =    wm5100_i2c_probe,
2722         .remove =   wm5100_i2c_remove,
2723         .id_table = wm5100_i2c_id,
2724 };
2725 
2726 module_i2c_driver(wm5100_i2c_driver);
2727 
2728 MODULE_DESCRIPTION("ASoC WM5100 driver");
2729 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2730 MODULE_LICENSE("GPL");
2731 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp