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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm5100.h

Version: ~ [ linux-5.4-rc7 ] ~ [ linux-5.3.11 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.84 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.154 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.201 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.201 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.77 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * wm5100.h  --  WM5100 ALSA SoC Audio driver
  3  *
  4  * Copyright 2011 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #ifndef WM5100_ASOC_H
 15 #define WM5100_ASOC_H
 16 
 17 #include <sound/soc.h>
 18 #include <linux/regmap.h>
 19 
 20 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
 21 
 22 #define WM5100_CLK_AIF1     1
 23 #define WM5100_CLK_AIF2     2
 24 #define WM5100_CLK_AIF3     3
 25 #define WM5100_CLK_SYSCLK   4
 26 #define WM5100_CLK_ASYNCCLK 5
 27 #define WM5100_CLK_32KHZ    6
 28 #define WM5100_CLK_OPCLK    7
 29 
 30 #define WM5100_CLKSRC_MCLK1    0
 31 #define WM5100_CLKSRC_MCLK2    1
 32 #define WM5100_CLKSRC_SYSCLK   2
 33 #define WM5100_CLKSRC_FLL1     4
 34 #define WM5100_CLKSRC_FLL2     5
 35 #define WM5100_CLKSRC_AIF1BCLK 8
 36 #define WM5100_CLKSRC_AIF2BCLK 9
 37 #define WM5100_CLKSRC_AIF3BCLK 10
 38 #define WM5100_CLKSRC_ASYNCCLK 0x100
 39 
 40 #define WM5100_FLL1 1
 41 #define WM5100_FLL2 2
 42 
 43 #define WM5100_FLL_SRC_MCLK1    0x0
 44 #define WM5100_FLL_SRC_MCLK2    0x1
 45 #define WM5100_FLL_SRC_FLL1     0x4
 46 #define WM5100_FLL_SRC_FLL2     0x5
 47 #define WM5100_FLL_SRC_AIF1BCLK 0x8
 48 #define WM5100_FLL_SRC_AIF2BCLK 0x9
 49 #define WM5100_FLL_SRC_AIF3BCLK 0xa
 50 
 51 /*
 52  * Register values.
 53  */
 54 #define WM5100_SOFTWARE_RESET                   0x00
 55 #define WM5100_DEVICE_REVISION                  0x01
 56 #define WM5100_CTRL_IF_1                        0x10
 57 #define WM5100_TONE_GENERATOR_1                 0x20
 58 #define WM5100_PWM_DRIVE_1                      0x30
 59 #define WM5100_PWM_DRIVE_2                      0x31
 60 #define WM5100_PWM_DRIVE_3                      0x32
 61 #define WM5100_CLOCKING_1                       0x100
 62 #define WM5100_CLOCKING_3                       0x101
 63 #define WM5100_CLOCKING_4                       0x102
 64 #define WM5100_CLOCKING_5                       0x103
 65 #define WM5100_CLOCKING_6                       0x104
 66 #define WM5100_CLOCKING_7                       0x107
 67 #define WM5100_CLOCKING_8                       0x108
 68 #define WM5100_ASRC_ENABLE                      0x120
 69 #define WM5100_ASRC_STATUS                      0x121
 70 #define WM5100_ASRC_RATE1                       0x122
 71 #define WM5100_ISRC_1_CTRL_1                    0x141
 72 #define WM5100_ISRC_1_CTRL_2                    0x142
 73 #define WM5100_ISRC_2_CTRL1                     0x143
 74 #define WM5100_ISRC_2_CTRL_2                    0x144
 75 #define WM5100_FLL1_CONTROL_1                   0x182
 76 #define WM5100_FLL1_CONTROL_2                   0x183
 77 #define WM5100_FLL1_CONTROL_3                   0x184
 78 #define WM5100_FLL1_CONTROL_5                   0x186
 79 #define WM5100_FLL1_CONTROL_6                   0x187
 80 #define WM5100_FLL1_EFS_1                       0x188
 81 #define WM5100_FLL2_CONTROL_1                   0x1A2
 82 #define WM5100_FLL2_CONTROL_2                   0x1A3
 83 #define WM5100_FLL2_CONTROL_3                   0x1A4
 84 #define WM5100_FLL2_CONTROL_5                   0x1A6
 85 #define WM5100_FLL2_CONTROL_6                   0x1A7
 86 #define WM5100_FLL2_EFS_1                       0x1A8
 87 #define WM5100_MIC_CHARGE_PUMP_1                0x200
 88 #define WM5100_MIC_CHARGE_PUMP_2                0x201
 89 #define WM5100_HP_CHARGE_PUMP_1                 0x202
 90 #define WM5100_LDO1_CONTROL                     0x211
 91 #define WM5100_MIC_BIAS_CTRL_1                  0x215
 92 #define WM5100_MIC_BIAS_CTRL_2                  0x216
 93 #define WM5100_MIC_BIAS_CTRL_3                  0x217
 94 #define WM5100_ACCESSORY_DETECT_MODE_1          0x280
 95 #define WM5100_HEADPHONE_DETECT_1               0x288
 96 #define WM5100_HEADPHONE_DETECT_2               0x289
 97 #define WM5100_MIC_DETECT_1                     0x290
 98 #define WM5100_MIC_DETECT_2                     0x291
 99 #define WM5100_MIC_DETECT_3                     0x292
100 #define WM5100_MISC_CONTROL                     0x2BB
101 #define WM5100_INPUT_ENABLES                    0x301
102 #define WM5100_INPUT_ENABLES_STATUS             0x302
103 #define WM5100_IN1L_CONTROL                     0x310
104 #define WM5100_IN1R_CONTROL                     0x311
105 #define WM5100_IN2L_CONTROL                     0x312
106 #define WM5100_IN2R_CONTROL                     0x313
107 #define WM5100_IN3L_CONTROL                     0x314
108 #define WM5100_IN3R_CONTROL                     0x315
109 #define WM5100_IN4L_CONTROL                     0x316
110 #define WM5100_IN4R_CONTROL                     0x317
111 #define WM5100_RXANC_SRC                        0x318
112 #define WM5100_INPUT_VOLUME_RAMP                0x319
113 #define WM5100_ADC_DIGITAL_VOLUME_1L            0x320
114 #define WM5100_ADC_DIGITAL_VOLUME_1R            0x321
115 #define WM5100_ADC_DIGITAL_VOLUME_2L            0x322
116 #define WM5100_ADC_DIGITAL_VOLUME_2R            0x323
117 #define WM5100_ADC_DIGITAL_VOLUME_3L            0x324
118 #define WM5100_ADC_DIGITAL_VOLUME_3R            0x325
119 #define WM5100_ADC_DIGITAL_VOLUME_4L            0x326
120 #define WM5100_ADC_DIGITAL_VOLUME_4R            0x327
121 #define WM5100_OUTPUT_ENABLES_2                 0x401
122 #define WM5100_OUTPUT_STATUS_1                  0x402
123 #define WM5100_OUTPUT_STATUS_2                  0x403
124 #define WM5100_CHANNEL_ENABLES_1                0x408
125 #define WM5100_OUT_VOLUME_1L                    0x410
126 #define WM5100_OUT_VOLUME_1R                    0x411
127 #define WM5100_DAC_VOLUME_LIMIT_1L              0x412
128 #define WM5100_DAC_VOLUME_LIMIT_1R              0x413
129 #define WM5100_OUT_VOLUME_2L                    0x414
130 #define WM5100_OUT_VOLUME_2R                    0x415
131 #define WM5100_DAC_VOLUME_LIMIT_2L              0x416
132 #define WM5100_DAC_VOLUME_LIMIT_2R              0x417
133 #define WM5100_OUT_VOLUME_3L                    0x418
134 #define WM5100_OUT_VOLUME_3R                    0x419
135 #define WM5100_DAC_VOLUME_LIMIT_3L              0x41A
136 #define WM5100_DAC_VOLUME_LIMIT_3R              0x41B
137 #define WM5100_OUT_VOLUME_4L                    0x41C
138 #define WM5100_OUT_VOLUME_4R                    0x41D
139 #define WM5100_DAC_VOLUME_LIMIT_5L              0x41E
140 #define WM5100_DAC_VOLUME_LIMIT_5R              0x41F
141 #define WM5100_DAC_VOLUME_LIMIT_6L              0x420
142 #define WM5100_DAC_VOLUME_LIMIT_6R              0x421
143 #define WM5100_DAC_AEC_CONTROL_1                0x440
144 #define WM5100_OUTPUT_VOLUME_RAMP               0x441
145 #define WM5100_DAC_DIGITAL_VOLUME_1L            0x480
146 #define WM5100_DAC_DIGITAL_VOLUME_1R            0x481
147 #define WM5100_DAC_DIGITAL_VOLUME_2L            0x482
148 #define WM5100_DAC_DIGITAL_VOLUME_2R            0x483
149 #define WM5100_DAC_DIGITAL_VOLUME_3L            0x484
150 #define WM5100_DAC_DIGITAL_VOLUME_3R            0x485
151 #define WM5100_DAC_DIGITAL_VOLUME_4L            0x486
152 #define WM5100_DAC_DIGITAL_VOLUME_4R            0x487
153 #define WM5100_DAC_DIGITAL_VOLUME_5L            0x488
154 #define WM5100_DAC_DIGITAL_VOLUME_5R            0x489
155 #define WM5100_DAC_DIGITAL_VOLUME_6L            0x48A
156 #define WM5100_DAC_DIGITAL_VOLUME_6R            0x48B
157 #define WM5100_PDM_SPK1_CTRL_1                  0x4C0
158 #define WM5100_PDM_SPK1_CTRL_2                  0x4C1
159 #define WM5100_PDM_SPK2_CTRL_1                  0x4C2
160 #define WM5100_PDM_SPK2_CTRL_2                  0x4C3
161 #define WM5100_AUDIO_IF_1_1                     0x500
162 #define WM5100_AUDIO_IF_1_2                     0x501
163 #define WM5100_AUDIO_IF_1_3                     0x502
164 #define WM5100_AUDIO_IF_1_4                     0x503
165 #define WM5100_AUDIO_IF_1_5                     0x504
166 #define WM5100_AUDIO_IF_1_6                     0x505
167 #define WM5100_AUDIO_IF_1_7                     0x506
168 #define WM5100_AUDIO_IF_1_8                     0x507
169 #define WM5100_AUDIO_IF_1_9                     0x508
170 #define WM5100_AUDIO_IF_1_10                    0x509
171 #define WM5100_AUDIO_IF_1_11                    0x50A
172 #define WM5100_AUDIO_IF_1_12                    0x50B
173 #define WM5100_AUDIO_IF_1_13                    0x50C
174 #define WM5100_AUDIO_IF_1_14                    0x50D
175 #define WM5100_AUDIO_IF_1_15                    0x50E
176 #define WM5100_AUDIO_IF_1_16                    0x50F
177 #define WM5100_AUDIO_IF_1_17                    0x510
178 #define WM5100_AUDIO_IF_1_18                    0x511
179 #define WM5100_AUDIO_IF_1_19                    0x512
180 #define WM5100_AUDIO_IF_1_20                    0x513
181 #define WM5100_AUDIO_IF_1_21                    0x514
182 #define WM5100_AUDIO_IF_1_22                    0x515
183 #define WM5100_AUDIO_IF_1_23                    0x516
184 #define WM5100_AUDIO_IF_1_24                    0x517
185 #define WM5100_AUDIO_IF_1_25                    0x518
186 #define WM5100_AUDIO_IF_1_26                    0x519
187 #define WM5100_AUDIO_IF_1_27                    0x51A
188 #define WM5100_AUDIO_IF_2_1                     0x540
189 #define WM5100_AUDIO_IF_2_2                     0x541
190 #define WM5100_AUDIO_IF_2_3                     0x542
191 #define WM5100_AUDIO_IF_2_4                     0x543
192 #define WM5100_AUDIO_IF_2_5                     0x544
193 #define WM5100_AUDIO_IF_2_6                     0x545
194 #define WM5100_AUDIO_IF_2_7                     0x546
195 #define WM5100_AUDIO_IF_2_8                     0x547
196 #define WM5100_AUDIO_IF_2_9                     0x548
197 #define WM5100_AUDIO_IF_2_10                    0x549
198 #define WM5100_AUDIO_IF_2_11                    0x54A
199 #define WM5100_AUDIO_IF_2_18                    0x551
200 #define WM5100_AUDIO_IF_2_19                    0x552
201 #define WM5100_AUDIO_IF_2_26                    0x559
202 #define WM5100_AUDIO_IF_2_27                    0x55A
203 #define WM5100_AUDIO_IF_3_1                     0x580
204 #define WM5100_AUDIO_IF_3_2                     0x581
205 #define WM5100_AUDIO_IF_3_3                     0x582
206 #define WM5100_AUDIO_IF_3_4                     0x583
207 #define WM5100_AUDIO_IF_3_5                     0x584
208 #define WM5100_AUDIO_IF_3_6                     0x585
209 #define WM5100_AUDIO_IF_3_7                     0x586
210 #define WM5100_AUDIO_IF_3_8                     0x587
211 #define WM5100_AUDIO_IF_3_9                     0x588
212 #define WM5100_AUDIO_IF_3_10                    0x589
213 #define WM5100_AUDIO_IF_3_11                    0x58A
214 #define WM5100_AUDIO_IF_3_18                    0x591
215 #define WM5100_AUDIO_IF_3_19                    0x592
216 #define WM5100_AUDIO_IF_3_26                    0x599
217 #define WM5100_AUDIO_IF_3_27                    0x59A
218 #define WM5100_PWM1MIX_INPUT_1_SOURCE           0x640
219 #define WM5100_PWM1MIX_INPUT_1_VOLUME           0x641
220 #define WM5100_PWM1MIX_INPUT_2_SOURCE           0x642
221 #define WM5100_PWM1MIX_INPUT_2_VOLUME           0x643
222 #define WM5100_PWM1MIX_INPUT_3_SOURCE           0x644
223 #define WM5100_PWM1MIX_INPUT_3_VOLUME           0x645
224 #define WM5100_PWM1MIX_INPUT_4_SOURCE           0x646
225 #define WM5100_PWM1MIX_INPUT_4_VOLUME           0x647
226 #define WM5100_PWM2MIX_INPUT_1_SOURCE           0x648
227 #define WM5100_PWM2MIX_INPUT_1_VOLUME           0x649
228 #define WM5100_PWM2MIX_INPUT_2_SOURCE           0x64A
229 #define WM5100_PWM2MIX_INPUT_2_VOLUME           0x64B
230 #define WM5100_PWM2MIX_INPUT_3_SOURCE           0x64C
231 #define WM5100_PWM2MIX_INPUT_3_VOLUME           0x64D
232 #define WM5100_PWM2MIX_INPUT_4_SOURCE           0x64E
233 #define WM5100_PWM2MIX_INPUT_4_VOLUME           0x64F
234 #define WM5100_OUT1LMIX_INPUT_1_SOURCE          0x680
235 #define WM5100_OUT1LMIX_INPUT_1_VOLUME          0x681
236 #define WM5100_OUT1LMIX_INPUT_2_SOURCE          0x682
237 #define WM5100_OUT1LMIX_INPUT_2_VOLUME          0x683
238 #define WM5100_OUT1LMIX_INPUT_3_SOURCE          0x684
239 #define WM5100_OUT1LMIX_INPUT_3_VOLUME          0x685
240 #define WM5100_OUT1LMIX_INPUT_4_SOURCE          0x686
241 #define WM5100_OUT1LMIX_INPUT_4_VOLUME          0x687
242 #define WM5100_OUT1RMIX_INPUT_1_SOURCE          0x688
243 #define WM5100_OUT1RMIX_INPUT_1_VOLUME          0x689
244 #define WM5100_OUT1RMIX_INPUT_2_SOURCE          0x68A
245 #define WM5100_OUT1RMIX_INPUT_2_VOLUME          0x68B
246 #define WM5100_OUT1RMIX_INPUT_3_SOURCE          0x68C
247 #define WM5100_OUT1RMIX_INPUT_3_VOLUME          0x68D
248 #define WM5100_OUT1RMIX_INPUT_4_SOURCE          0x68E
249 #define WM5100_OUT1RMIX_INPUT_4_VOLUME          0x68F
250 #define WM5100_OUT2LMIX_INPUT_1_SOURCE          0x690
251 #define WM5100_OUT2LMIX_INPUT_1_VOLUME          0x691
252 #define WM5100_OUT2LMIX_INPUT_2_SOURCE          0x692
253 #define WM5100_OUT2LMIX_INPUT_2_VOLUME          0x693
254 #define WM5100_OUT2LMIX_INPUT_3_SOURCE          0x694
255 #define WM5100_OUT2LMIX_INPUT_3_VOLUME          0x695
256 #define WM5100_OUT2LMIX_INPUT_4_SOURCE          0x696
257 #define WM5100_OUT2LMIX_INPUT_4_VOLUME          0x697
258 #define WM5100_OUT2RMIX_INPUT_1_SOURCE          0x698
259 #define WM5100_OUT2RMIX_INPUT_1_VOLUME          0x699
260 #define WM5100_OUT2RMIX_INPUT_2_SOURCE          0x69A
261 #define WM5100_OUT2RMIX_INPUT_2_VOLUME          0x69B
262 #define WM5100_OUT2RMIX_INPUT_3_SOURCE          0x69C
263 #define WM5100_OUT2RMIX_INPUT_3_VOLUME          0x69D
264 #define WM5100_OUT2RMIX_INPUT_4_SOURCE          0x69E
265 #define WM5100_OUT2RMIX_INPUT_4_VOLUME          0x69F
266 #define WM5100_OUT3LMIX_INPUT_1_SOURCE          0x6A0
267 #define WM5100_OUT3LMIX_INPUT_1_VOLUME          0x6A1
268 #define WM5100_OUT3LMIX_INPUT_2_SOURCE          0x6A2
269 #define WM5100_OUT3LMIX_INPUT_2_VOLUME          0x6A3
270 #define WM5100_OUT3LMIX_INPUT_3_SOURCE          0x6A4
271 #define WM5100_OUT3LMIX_INPUT_3_VOLUME          0x6A5
272 #define WM5100_OUT3LMIX_INPUT_4_SOURCE          0x6A6
273 #define WM5100_OUT3LMIX_INPUT_4_VOLUME          0x6A7
274 #define WM5100_OUT3RMIX_INPUT_1_SOURCE          0x6A8
275 #define WM5100_OUT3RMIX_INPUT_1_VOLUME          0x6A9
276 #define WM5100_OUT3RMIX_INPUT_2_SOURCE          0x6AA
277 #define WM5100_OUT3RMIX_INPUT_2_VOLUME          0x6AB
278 #define WM5100_OUT3RMIX_INPUT_3_SOURCE          0x6AC
279 #define WM5100_OUT3RMIX_INPUT_3_VOLUME          0x6AD
280 #define WM5100_OUT3RMIX_INPUT_4_SOURCE          0x6AE
281 #define WM5100_OUT3RMIX_INPUT_4_VOLUME          0x6AF
282 #define WM5100_OUT4LMIX_INPUT_1_SOURCE          0x6B0
283 #define WM5100_OUT4LMIX_INPUT_1_VOLUME          0x6B1
284 #define WM5100_OUT4LMIX_INPUT_2_SOURCE          0x6B2
285 #define WM5100_OUT4LMIX_INPUT_2_VOLUME          0x6B3
286 #define WM5100_OUT4LMIX_INPUT_3_SOURCE          0x6B4
287 #define WM5100_OUT4LMIX_INPUT_3_VOLUME          0x6B5
288 #define WM5100_OUT4LMIX_INPUT_4_SOURCE          0x6B6
289 #define WM5100_OUT4LMIX_INPUT_4_VOLUME          0x6B7
290 #define WM5100_OUT4RMIX_INPUT_1_SOURCE          0x6B8
291 #define WM5100_OUT4RMIX_INPUT_1_VOLUME          0x6B9
292 #define WM5100_OUT4RMIX_INPUT_2_SOURCE          0x6BA
293 #define WM5100_OUT4RMIX_INPUT_2_VOLUME          0x6BB
294 #define WM5100_OUT4RMIX_INPUT_3_SOURCE          0x6BC
295 #define WM5100_OUT4RMIX_INPUT_3_VOLUME          0x6BD
296 #define WM5100_OUT4RMIX_INPUT_4_SOURCE          0x6BE
297 #define WM5100_OUT4RMIX_INPUT_4_VOLUME          0x6BF
298 #define WM5100_OUT5LMIX_INPUT_1_SOURCE          0x6C0
299 #define WM5100_OUT5LMIX_INPUT_1_VOLUME          0x6C1
300 #define WM5100_OUT5LMIX_INPUT_2_SOURCE          0x6C2
301 #define WM5100_OUT5LMIX_INPUT_2_VOLUME          0x6C3
302 #define WM5100_OUT5LMIX_INPUT_3_SOURCE          0x6C4
303 #define WM5100_OUT5LMIX_INPUT_3_VOLUME          0x6C5
304 #define WM5100_OUT5LMIX_INPUT_4_SOURCE          0x6C6
305 #define WM5100_OUT5LMIX_INPUT_4_VOLUME          0x6C7
306 #define WM5100_OUT5RMIX_INPUT_1_SOURCE          0x6C8
307 #define WM5100_OUT5RMIX_INPUT_1_VOLUME          0x6C9
308 #define WM5100_OUT5RMIX_INPUT_2_SOURCE          0x6CA
309 #define WM5100_OUT5RMIX_INPUT_2_VOLUME          0x6CB
310 #define WM5100_OUT5RMIX_INPUT_3_SOURCE          0x6CC
311 #define WM5100_OUT5RMIX_INPUT_3_VOLUME          0x6CD
312 #define WM5100_OUT5RMIX_INPUT_4_SOURCE          0x6CE
313 #define WM5100_OUT5RMIX_INPUT_4_VOLUME          0x6CF
314 #define WM5100_OUT6LMIX_INPUT_1_SOURCE          0x6D0
315 #define WM5100_OUT6LMIX_INPUT_1_VOLUME          0x6D1
316 #define WM5100_OUT6LMIX_INPUT_2_SOURCE          0x6D2
317 #define WM5100_OUT6LMIX_INPUT_2_VOLUME          0x6D3
318 #define WM5100_OUT6LMIX_INPUT_3_SOURCE          0x6D4
319 #define WM5100_OUT6LMIX_INPUT_3_VOLUME          0x6D5
320 #define WM5100_OUT6LMIX_INPUT_4_SOURCE          0x6D6
321 #define WM5100_OUT6LMIX_INPUT_4_VOLUME          0x6D7
322 #define WM5100_OUT6RMIX_INPUT_1_SOURCE          0x6D8
323 #define WM5100_OUT6RMIX_INPUT_1_VOLUME          0x6D9
324 #define WM5100_OUT6RMIX_INPUT_2_SOURCE          0x6DA
325 #define WM5100_OUT6RMIX_INPUT_2_VOLUME          0x6DB
326 #define WM5100_OUT6RMIX_INPUT_3_SOURCE          0x6DC
327 #define WM5100_OUT6RMIX_INPUT_3_VOLUME          0x6DD
328 #define WM5100_OUT6RMIX_INPUT_4_SOURCE          0x6DE
329 #define WM5100_OUT6RMIX_INPUT_4_VOLUME          0x6DF
330 #define WM5100_AIF1TX1MIX_INPUT_1_SOURCE        0x700
331 #define WM5100_AIF1TX1MIX_INPUT_1_VOLUME        0x701
332 #define WM5100_AIF1TX1MIX_INPUT_2_SOURCE        0x702
333 #define WM5100_AIF1TX1MIX_INPUT_2_VOLUME        0x703
334 #define WM5100_AIF1TX1MIX_INPUT_3_SOURCE        0x704
335 #define WM5100_AIF1TX1MIX_INPUT_3_VOLUME        0x705
336 #define WM5100_AIF1TX1MIX_INPUT_4_SOURCE        0x706
337 #define WM5100_AIF1TX1MIX_INPUT_4_VOLUME        0x707
338 #define WM5100_AIF1TX2MIX_INPUT_1_SOURCE        0x708
339 #define WM5100_AIF1TX2MIX_INPUT_1_VOLUME        0x709
340 #define WM5100_AIF1TX2MIX_INPUT_2_SOURCE        0x70A
341 #define WM5100_AIF1TX2MIX_INPUT_2_VOLUME        0x70B
342 #define WM5100_AIF1TX2MIX_INPUT_3_SOURCE        0x70C
343 #define WM5100_AIF1TX2MIX_INPUT_3_VOLUME        0x70D
344 #define WM5100_AIF1TX2MIX_INPUT_4_SOURCE        0x70E
345 #define WM5100_AIF1TX2MIX_INPUT_4_VOLUME        0x70F
346 #define WM5100_AIF1TX3MIX_INPUT_1_SOURCE        0x710
347 #define WM5100_AIF1TX3MIX_INPUT_1_VOLUME        0x711
348 #define WM5100_AIF1TX3MIX_INPUT_2_SOURCE        0x712
349 #define WM5100_AIF1TX3MIX_INPUT_2_VOLUME        0x713
350 #define WM5100_AIF1TX3MIX_INPUT_3_SOURCE        0x714
351 #define WM5100_AIF1TX3MIX_INPUT_3_VOLUME        0x715
352 #define WM5100_AIF1TX3MIX_INPUT_4_SOURCE        0x716
353 #define WM5100_AIF1TX3MIX_INPUT_4_VOLUME        0x717
354 #define WM5100_AIF1TX4MIX_INPUT_1_SOURCE        0x718
355 #define WM5100_AIF1TX4MIX_INPUT_1_VOLUME        0x719
356 #define WM5100_AIF1TX4MIX_INPUT_2_SOURCE        0x71A
357 #define WM5100_AIF1TX4MIX_INPUT_2_VOLUME        0x71B
358 #define WM5100_AIF1TX4MIX_INPUT_3_SOURCE        0x71C
359 #define WM5100_AIF1TX4MIX_INPUT_3_VOLUME        0x71D
360 #define WM5100_AIF1TX4MIX_INPUT_4_SOURCE        0x71E
361 #define WM5100_AIF1TX4MIX_INPUT_4_VOLUME        0x71F
362 #define WM5100_AIF1TX5MIX_INPUT_1_SOURCE        0x720
363 #define WM5100_AIF1TX5MIX_INPUT_1_VOLUME        0x721
364 #define WM5100_AIF1TX5MIX_INPUT_2_SOURCE        0x722
365 #define WM5100_AIF1TX5MIX_INPUT_2_VOLUME        0x723
366 #define WM5100_AIF1TX5MIX_INPUT_3_SOURCE        0x724
367 #define WM5100_AIF1TX5MIX_INPUT_3_VOLUME        0x725
368 #define WM5100_AIF1TX5MIX_INPUT_4_SOURCE        0x726
369 #define WM5100_AIF1TX5MIX_INPUT_4_VOLUME        0x727
370 #define WM5100_AIF1TX6MIX_INPUT_1_SOURCE        0x728
371 #define WM5100_AIF1TX6MIX_INPUT_1_VOLUME        0x729
372 #define WM5100_AIF1TX6MIX_INPUT_2_SOURCE        0x72A
373 #define WM5100_AIF1TX6MIX_INPUT_2_VOLUME        0x72B
374 #define WM5100_AIF1TX6MIX_INPUT_3_SOURCE        0x72C
375 #define WM5100_AIF1TX6MIX_INPUT_3_VOLUME        0x72D
376 #define WM5100_AIF1TX6MIX_INPUT_4_SOURCE        0x72E
377 #define WM5100_AIF1TX6MIX_INPUT_4_VOLUME        0x72F
378 #define WM5100_AIF1TX7MIX_INPUT_1_SOURCE        0x730
379 #define WM5100_AIF1TX7MIX_INPUT_1_VOLUME        0x731
380 #define WM5100_AIF1TX7MIX_INPUT_2_SOURCE        0x732
381 #define WM5100_AIF1TX7MIX_INPUT_2_VOLUME        0x733
382 #define WM5100_AIF1TX7MIX_INPUT_3_SOURCE        0x734
383 #define WM5100_AIF1TX7MIX_INPUT_3_VOLUME        0x735
384 #define WM5100_AIF1TX7MIX_INPUT_4_SOURCE        0x736
385 #define WM5100_AIF1TX7MIX_INPUT_4_VOLUME        0x737
386 #define WM5100_AIF1TX8MIX_INPUT_1_SOURCE        0x738
387 #define WM5100_AIF1TX8MIX_INPUT_1_VOLUME        0x739
388 #define WM5100_AIF1TX8MIX_INPUT_2_SOURCE        0x73A
389 #define WM5100_AIF1TX8MIX_INPUT_2_VOLUME        0x73B
390 #define WM5100_AIF1TX8MIX_INPUT_3_SOURCE        0x73C
391 #define WM5100_AIF1TX8MIX_INPUT_3_VOLUME        0x73D
392 #define WM5100_AIF1TX8MIX_INPUT_4_SOURCE        0x73E
393 #define WM5100_AIF1TX8MIX_INPUT_4_VOLUME        0x73F
394 #define WM5100_AIF2TX1MIX_INPUT_1_SOURCE        0x740
395 #define WM5100_AIF2TX1MIX_INPUT_1_VOLUME        0x741
396 #define WM5100_AIF2TX1MIX_INPUT_2_SOURCE        0x742
397 #define WM5100_AIF2TX1MIX_INPUT_2_VOLUME        0x743
398 #define WM5100_AIF2TX1MIX_INPUT_3_SOURCE        0x744
399 #define WM5100_AIF2TX1MIX_INPUT_3_VOLUME        0x745
400 #define WM5100_AIF2TX1MIX_INPUT_4_SOURCE        0x746
401 #define WM5100_AIF2TX1MIX_INPUT_4_VOLUME        0x747
402 #define WM5100_AIF2TX2MIX_INPUT_1_SOURCE        0x748
403 #define WM5100_AIF2TX2MIX_INPUT_1_VOLUME        0x749
404 #define WM5100_AIF2TX2MIX_INPUT_2_SOURCE        0x74A
405 #define WM5100_AIF2TX2MIX_INPUT_2_VOLUME        0x74B
406 #define WM5100_AIF2TX2MIX_INPUT_3_SOURCE        0x74C
407 #define WM5100_AIF2TX2MIX_INPUT_3_VOLUME        0x74D
408 #define WM5100_AIF2TX2MIX_INPUT_4_SOURCE        0x74E
409 #define WM5100_AIF2TX2MIX_INPUT_4_VOLUME        0x74F
410 #define WM5100_AIF3TX1MIX_INPUT_1_SOURCE        0x780
411 #define WM5100_AIF3TX1MIX_INPUT_1_VOLUME        0x781
412 #define WM5100_AIF3TX1MIX_INPUT_2_SOURCE        0x782
413 #define WM5100_AIF3TX1MIX_INPUT_2_VOLUME        0x783
414 #define WM5100_AIF3TX1MIX_INPUT_3_SOURCE        0x784
415 #define WM5100_AIF3TX1MIX_INPUT_3_VOLUME        0x785
416 #define WM5100_AIF3TX1MIX_INPUT_4_SOURCE        0x786
417 #define WM5100_AIF3TX1MIX_INPUT_4_VOLUME        0x787
418 #define WM5100_AIF3TX2MIX_INPUT_1_SOURCE        0x788
419 #define WM5100_AIF3TX2MIX_INPUT_1_VOLUME        0x789
420 #define WM5100_AIF3TX2MIX_INPUT_2_SOURCE        0x78A
421 #define WM5100_AIF3TX2MIX_INPUT_2_VOLUME        0x78B
422 #define WM5100_AIF3TX2MIX_INPUT_3_SOURCE        0x78C
423 #define WM5100_AIF3TX2MIX_INPUT_3_VOLUME        0x78D
424 #define WM5100_AIF3TX2MIX_INPUT_4_SOURCE        0x78E
425 #define WM5100_AIF3TX2MIX_INPUT_4_VOLUME        0x78F
426 #define WM5100_EQ1MIX_INPUT_1_SOURCE            0x880
427 #define WM5100_EQ1MIX_INPUT_1_VOLUME            0x881
428 #define WM5100_EQ1MIX_INPUT_2_SOURCE            0x882
429 #define WM5100_EQ1MIX_INPUT_2_VOLUME            0x883
430 #define WM5100_EQ1MIX_INPUT_3_SOURCE            0x884
431 #define WM5100_EQ1MIX_INPUT_3_VOLUME            0x885
432 #define WM5100_EQ1MIX_INPUT_4_SOURCE            0x886
433 #define WM5100_EQ1MIX_INPUT_4_VOLUME            0x887
434 #define WM5100_EQ2MIX_INPUT_1_SOURCE            0x888
435 #define WM5100_EQ2MIX_INPUT_1_VOLUME            0x889
436 #define WM5100_EQ2MIX_INPUT_2_SOURCE            0x88A
437 #define WM5100_EQ2MIX_INPUT_2_VOLUME            0x88B
438 #define WM5100_EQ2MIX_INPUT_3_SOURCE            0x88C
439 #define WM5100_EQ2MIX_INPUT_3_VOLUME            0x88D
440 #define WM5100_EQ2MIX_INPUT_4_SOURCE            0x88E
441 #define WM5100_EQ2MIX_INPUT_4_VOLUME            0x88F
442 #define WM5100_EQ3MIX_INPUT_1_SOURCE            0x890
443 #define WM5100_EQ3MIX_INPUT_1_VOLUME            0x891
444 #define WM5100_EQ3MIX_INPUT_2_SOURCE            0x892
445 #define WM5100_EQ3MIX_INPUT_2_VOLUME            0x893
446 #define WM5100_EQ3MIX_INPUT_3_SOURCE            0x894
447 #define WM5100_EQ3MIX_INPUT_3_VOLUME            0x895
448 #define WM5100_EQ3MIX_INPUT_4_SOURCE            0x896
449 #define WM5100_EQ3MIX_INPUT_4_VOLUME            0x897
450 #define WM5100_EQ4MIX_INPUT_1_SOURCE            0x898
451 #define WM5100_EQ4MIX_INPUT_1_VOLUME            0x899
452 #define WM5100_EQ4MIX_INPUT_2_SOURCE            0x89A
453 #define WM5100_EQ4MIX_INPUT_2_VOLUME            0x89B
454 #define WM5100_EQ4MIX_INPUT_3_SOURCE            0x89C
455 #define WM5100_EQ4MIX_INPUT_3_VOLUME            0x89D
456 #define WM5100_EQ4MIX_INPUT_4_SOURCE            0x89E
457 #define WM5100_EQ4MIX_INPUT_4_VOLUME            0x89F
458 #define WM5100_DRC1LMIX_INPUT_1_SOURCE          0x8C0
459 #define WM5100_DRC1LMIX_INPUT_1_VOLUME          0x8C1
460 #define WM5100_DRC1LMIX_INPUT_2_SOURCE          0x8C2
461 #define WM5100_DRC1LMIX_INPUT_2_VOLUME          0x8C3
462 #define WM5100_DRC1LMIX_INPUT_3_SOURCE          0x8C4
463 #define WM5100_DRC1LMIX_INPUT_3_VOLUME          0x8C5
464 #define WM5100_DRC1LMIX_INPUT_4_SOURCE          0x8C6
465 #define WM5100_DRC1LMIX_INPUT_4_VOLUME          0x8C7
466 #define WM5100_DRC1RMIX_INPUT_1_SOURCE          0x8C8
467 #define WM5100_DRC1RMIX_INPUT_1_VOLUME          0x8C9
468 #define WM5100_DRC1RMIX_INPUT_2_SOURCE          0x8CA
469 #define WM5100_DRC1RMIX_INPUT_2_VOLUME          0x8CB
470 #define WM5100_DRC1RMIX_INPUT_3_SOURCE          0x8CC
471 #define WM5100_DRC1RMIX_INPUT_3_VOLUME          0x8CD
472 #define WM5100_DRC1RMIX_INPUT_4_SOURCE          0x8CE
473 #define WM5100_DRC1RMIX_INPUT_4_VOLUME          0x8CF
474 #define WM5100_HPLP1MIX_INPUT_1_SOURCE          0x900
475 #define WM5100_HPLP1MIX_INPUT_1_VOLUME          0x901
476 #define WM5100_HPLP1MIX_INPUT_2_SOURCE          0x902
477 #define WM5100_HPLP1MIX_INPUT_2_VOLUME          0x903
478 #define WM5100_HPLP1MIX_INPUT_3_SOURCE          0x904
479 #define WM5100_HPLP1MIX_INPUT_3_VOLUME          0x905
480 #define WM5100_HPLP1MIX_INPUT_4_SOURCE          0x906
481 #define WM5100_HPLP1MIX_INPUT_4_VOLUME          0x907
482 #define WM5100_HPLP2MIX_INPUT_1_SOURCE          0x908
483 #define WM5100_HPLP2MIX_INPUT_1_VOLUME          0x909
484 #define WM5100_HPLP2MIX_INPUT_2_SOURCE          0x90A
485 #define WM5100_HPLP2MIX_INPUT_2_VOLUME          0x90B
486 #define WM5100_HPLP2MIX_INPUT_3_SOURCE          0x90C
487 #define WM5100_HPLP2MIX_INPUT_3_VOLUME          0x90D
488 #define WM5100_HPLP2MIX_INPUT_4_SOURCE          0x90E
489 #define WM5100_HPLP2MIX_INPUT_4_VOLUME          0x90F
490 #define WM5100_HPLP3MIX_INPUT_1_SOURCE          0x910
491 #define WM5100_HPLP3MIX_INPUT_1_VOLUME          0x911
492 #define WM5100_HPLP3MIX_INPUT_2_SOURCE          0x912
493 #define WM5100_HPLP3MIX_INPUT_2_VOLUME          0x913
494 #define WM5100_HPLP3MIX_INPUT_3_SOURCE          0x914
495 #define WM5100_HPLP3MIX_INPUT_3_VOLUME          0x915
496 #define WM5100_HPLP3MIX_INPUT_4_SOURCE          0x916
497 #define WM5100_HPLP3MIX_INPUT_4_VOLUME          0x917
498 #define WM5100_HPLP4MIX_INPUT_1_SOURCE          0x918
499 #define WM5100_HPLP4MIX_INPUT_1_VOLUME          0x919
500 #define WM5100_HPLP4MIX_INPUT_2_SOURCE          0x91A
501 #define WM5100_HPLP4MIX_INPUT_2_VOLUME          0x91B
502 #define WM5100_HPLP4MIX_INPUT_3_SOURCE          0x91C
503 #define WM5100_HPLP4MIX_INPUT_3_VOLUME          0x91D
504 #define WM5100_HPLP4MIX_INPUT_4_SOURCE          0x91E
505 #define WM5100_HPLP4MIX_INPUT_4_VOLUME          0x91F
506 #define WM5100_DSP1LMIX_INPUT_1_SOURCE          0x940
507 #define WM5100_DSP1LMIX_INPUT_1_VOLUME          0x941
508 #define WM5100_DSP1LMIX_INPUT_2_SOURCE          0x942
509 #define WM5100_DSP1LMIX_INPUT_2_VOLUME          0x943
510 #define WM5100_DSP1LMIX_INPUT_3_SOURCE          0x944
511 #define WM5100_DSP1LMIX_INPUT_3_VOLUME          0x945
512 #define WM5100_DSP1LMIX_INPUT_4_SOURCE          0x946
513 #define WM5100_DSP1LMIX_INPUT_4_VOLUME          0x947
514 #define WM5100_DSP1RMIX_INPUT_1_SOURCE          0x948
515 #define WM5100_DSP1RMIX_INPUT_1_VOLUME          0x949
516 #define WM5100_DSP1RMIX_INPUT_2_SOURCE          0x94A
517 #define WM5100_DSP1RMIX_INPUT_2_VOLUME          0x94B
518 #define WM5100_DSP1RMIX_INPUT_3_SOURCE          0x94C
519 #define WM5100_DSP1RMIX_INPUT_3_VOLUME          0x94D
520 #define WM5100_DSP1RMIX_INPUT_4_SOURCE          0x94E
521 #define WM5100_DSP1RMIX_INPUT_4_VOLUME          0x94F
522 #define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE       0x950
523 #define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE       0x958
524 #define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE       0x960
525 #define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE       0x968
526 #define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE       0x970
527 #define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE       0x978
528 #define WM5100_DSP2LMIX_INPUT_1_SOURCE          0x980
529 #define WM5100_DSP2LMIX_INPUT_1_VOLUME          0x981
530 #define WM5100_DSP2LMIX_INPUT_2_SOURCE          0x982
531 #define WM5100_DSP2LMIX_INPUT_2_VOLUME          0x983
532 #define WM5100_DSP2LMIX_INPUT_3_SOURCE          0x984
533 #define WM5100_DSP2LMIX_INPUT_3_VOLUME          0x985
534 #define WM5100_DSP2LMIX_INPUT_4_SOURCE          0x986
535 #define WM5100_DSP2LMIX_INPUT_4_VOLUME          0x987
536 #define WM5100_DSP2RMIX_INPUT_1_SOURCE          0x988
537 #define WM5100_DSP2RMIX_INPUT_1_VOLUME          0x989
538 #define WM5100_DSP2RMIX_INPUT_2_SOURCE          0x98A
539 #define WM5100_DSP2RMIX_INPUT_2_VOLUME          0x98B
540 #define WM5100_DSP2RMIX_INPUT_3_SOURCE          0x98C
541 #define WM5100_DSP2RMIX_INPUT_3_VOLUME          0x98D
542 #define WM5100_DSP2RMIX_INPUT_4_SOURCE          0x98E
543 #define WM5100_DSP2RMIX_INPUT_4_VOLUME          0x98F
544 #define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE       0x990
545 #define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE       0x998
546 #define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE       0x9A0
547 #define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE       0x9A8
548 #define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE       0x9B0
549 #define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE       0x9B8
550 #define WM5100_DSP3LMIX_INPUT_1_SOURCE          0x9C0
551 #define WM5100_DSP3LMIX_INPUT_1_VOLUME          0x9C1
552 #define WM5100_DSP3LMIX_INPUT_2_SOURCE          0x9C2
553 #define WM5100_DSP3LMIX_INPUT_2_VOLUME          0x9C3
554 #define WM5100_DSP3LMIX_INPUT_3_SOURCE          0x9C4
555 #define WM5100_DSP3LMIX_INPUT_3_VOLUME          0x9C5
556 #define WM5100_DSP3LMIX_INPUT_4_SOURCE          0x9C6
557 #define WM5100_DSP3LMIX_INPUT_4_VOLUME          0x9C7
558 #define WM5100_DSP3RMIX_INPUT_1_SOURCE          0x9C8
559 #define WM5100_DSP3RMIX_INPUT_1_VOLUME          0x9C9
560 #define WM5100_DSP3RMIX_INPUT_2_SOURCE          0x9CA
561 #define WM5100_DSP3RMIX_INPUT_2_VOLUME          0x9CB
562 #define WM5100_DSP3RMIX_INPUT_3_SOURCE          0x9CC
563 #define WM5100_DSP3RMIX_INPUT_3_VOLUME          0x9CD
564 #define WM5100_DSP3RMIX_INPUT_4_SOURCE          0x9CE
565 #define WM5100_DSP3RMIX_INPUT_4_VOLUME          0x9CF
566 #define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE       0x9D0
567 #define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE       0x9D8
568 #define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE       0x9E0
569 #define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE       0x9E8
570 #define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE       0x9F0
571 #define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE       0x9F8
572 #define WM5100_ASRC1LMIX_INPUT_1_SOURCE         0xA80
573 #define WM5100_ASRC1RMIX_INPUT_1_SOURCE         0xA88
574 #define WM5100_ASRC2LMIX_INPUT_1_SOURCE         0xA90
575 #define WM5100_ASRC2RMIX_INPUT_1_SOURCE         0xA98
576 #define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE      0xB00
577 #define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE      0xB08
578 #define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE      0xB10
579 #define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE      0xB18
580 #define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE      0xB20
581 #define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE      0xB28
582 #define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE      0xB30
583 #define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE      0xB38
584 #define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE      0xB40
585 #define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE      0xB48
586 #define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE      0xB50
587 #define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE      0xB58
588 #define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE      0xB60
589 #define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE      0xB68
590 #define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE      0xB70
591 #define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE      0xB78
592 #define WM5100_GPIO_CTRL_1                      0xC00
593 #define WM5100_GPIO_CTRL_2                      0xC01
594 #define WM5100_GPIO_CTRL_3                      0xC02
595 #define WM5100_GPIO_CTRL_4                      0xC03
596 #define WM5100_GPIO_CTRL_5                      0xC04
597 #define WM5100_GPIO_CTRL_6                      0xC05
598 #define WM5100_MISC_PAD_CTRL_1                  0xC23
599 #define WM5100_MISC_PAD_CTRL_2                  0xC24
600 #define WM5100_MISC_PAD_CTRL_3                  0xC25
601 #define WM5100_MISC_PAD_CTRL_4                  0xC26
602 #define WM5100_MISC_PAD_CTRL_5                  0xC27
603 #define WM5100_MISC_GPIO_1                      0xC28
604 #define WM5100_INTERRUPT_STATUS_1               0xD00
605 #define WM5100_INTERRUPT_STATUS_2               0xD01
606 #define WM5100_INTERRUPT_STATUS_3               0xD02
607 #define WM5100_INTERRUPT_STATUS_4               0xD03
608 #define WM5100_INTERRUPT_RAW_STATUS_2           0xD04
609 #define WM5100_INTERRUPT_RAW_STATUS_3           0xD05
610 #define WM5100_INTERRUPT_RAW_STATUS_4           0xD06
611 #define WM5100_INTERRUPT_STATUS_1_MASK          0xD07
612 #define WM5100_INTERRUPT_STATUS_2_MASK          0xD08
613 #define WM5100_INTERRUPT_STATUS_3_MASK          0xD09
614 #define WM5100_INTERRUPT_STATUS_4_MASK          0xD0A
615 #define WM5100_INTERRUPT_CONTROL                0xD1F
616 #define WM5100_IRQ_DEBOUNCE_1                   0xD20
617 #define WM5100_IRQ_DEBOUNCE_2                   0xD21
618 #define WM5100_FX_CTRL                          0xE00
619 #define WM5100_EQ1_1                            0xE10
620 #define WM5100_EQ1_2                            0xE11
621 #define WM5100_EQ1_3                            0xE12
622 #define WM5100_EQ1_4                            0xE13
623 #define WM5100_EQ1_5                            0xE14
624 #define WM5100_EQ1_6                            0xE15
625 #define WM5100_EQ1_7                            0xE16
626 #define WM5100_EQ1_8                            0xE17
627 #define WM5100_EQ1_9                            0xE18
628 #define WM5100_EQ1_10                           0xE19
629 #define WM5100_EQ1_11                           0xE1A
630 #define WM5100_EQ1_12                           0xE1B
631 #define WM5100_EQ1_13                           0xE1C
632 #define WM5100_EQ1_14                           0xE1D
633 #define WM5100_EQ1_15                           0xE1E
634 #define WM5100_EQ1_16                           0xE1F
635 #define WM5100_EQ1_17                           0xE20
636 #define WM5100_EQ1_18                           0xE21
637 #define WM5100_EQ1_19                           0xE22
638 #define WM5100_EQ1_20                           0xE23
639 #define WM5100_EQ2_1                            0xE26
640 #define WM5100_EQ2_2                            0xE27
641 #define WM5100_EQ2_3                            0xE28
642 #define WM5100_EQ2_4                            0xE29
643 #define WM5100_EQ2_5                            0xE2A
644 #define WM5100_EQ2_6                            0xE2B
645 #define WM5100_EQ2_7                            0xE2C
646 #define WM5100_EQ2_8                            0xE2D
647 #define WM5100_EQ2_9                            0xE2E
648 #define WM5100_EQ2_10                           0xE2F
649 #define WM5100_EQ2_11                           0xE30
650 #define WM5100_EQ2_12                           0xE31
651 #define WM5100_EQ2_13                           0xE32
652 #define WM5100_EQ2_14                           0xE33
653 #define WM5100_EQ2_15                           0xE34
654 #define WM5100_EQ2_16                           0xE35
655 #define WM5100_EQ2_17                           0xE36
656 #define WM5100_EQ2_18                           0xE37
657 #define WM5100_EQ2_19                           0xE38
658 #define WM5100_EQ2_20                           0xE39
659 #define WM5100_EQ3_1                            0xE3C
660 #define WM5100_EQ3_2                            0xE3D
661 #define WM5100_EQ3_3                            0xE3E
662 #define WM5100_EQ3_4                            0xE3F
663 #define WM5100_EQ3_5                            0xE40
664 #define WM5100_EQ3_6                            0xE41
665 #define WM5100_EQ3_7                            0xE42
666 #define WM5100_EQ3_8                            0xE43
667 #define WM5100_EQ3_9                            0xE44
668 #define WM5100_EQ3_10                           0xE45
669 #define WM5100_EQ3_11                           0xE46
670 #define WM5100_EQ3_12                           0xE47
671 #define WM5100_EQ3_13                           0xE48
672 #define WM5100_EQ3_14                           0xE49
673 #define WM5100_EQ3_15                           0xE4A
674 #define WM5100_EQ3_16                           0xE4B
675 #define WM5100_EQ3_17                           0xE4C
676 #define WM5100_EQ3_18                           0xE4D
677 #define WM5100_EQ3_19                           0xE4E
678 #define WM5100_EQ3_20                           0xE4F
679 #define WM5100_EQ4_1                            0xE52
680 #define WM5100_EQ4_2                            0xE53
681 #define WM5100_EQ4_3                            0xE54
682 #define WM5100_EQ4_4                            0xE55
683 #define WM5100_EQ4_5                            0xE56
684 #define WM5100_EQ4_6                            0xE57
685 #define WM5100_EQ4_7                            0xE58
686 #define WM5100_EQ4_8                            0xE59
687 #define WM5100_EQ4_9                            0xE5A
688 #define WM5100_EQ4_10                           0xE5B
689 #define WM5100_EQ4_11                           0xE5C
690 #define WM5100_EQ4_12                           0xE5D
691 #define WM5100_EQ4_13                           0xE5E
692 #define WM5100_EQ4_14                           0xE5F
693 #define WM5100_EQ4_15                           0xE60
694 #define WM5100_EQ4_16                           0xE61
695 #define WM5100_EQ4_17                           0xE62
696 #define WM5100_EQ4_18                           0xE63
697 #define WM5100_EQ4_19                           0xE64
698 #define WM5100_EQ4_20                           0xE65
699 #define WM5100_DRC1_CTRL1                       0xE80
700 #define WM5100_DRC1_CTRL2                       0xE81
701 #define WM5100_DRC1_CTRL3                       0xE82
702 #define WM5100_DRC1_CTRL4                       0xE83
703 #define WM5100_DRC1_CTRL5                       0xE84
704 #define WM5100_HPLPF1_1                         0xEC0
705 #define WM5100_HPLPF1_2                         0xEC1
706 #define WM5100_HPLPF2_1                         0xEC4
707 #define WM5100_HPLPF2_2                         0xEC5
708 #define WM5100_HPLPF3_1                         0xEC8
709 #define WM5100_HPLPF3_2                         0xEC9
710 #define WM5100_HPLPF4_1                         0xECC
711 #define WM5100_HPLPF4_2                         0xECD
712 #define WM5100_DSP1_CONTROL_1                   0xF00
713 #define WM5100_DSP1_CONTROL_2                   0xF02
714 #define WM5100_DSP1_CONTROL_3                   0xF03
715 #define WM5100_DSP1_CONTROL_4                   0xF04
716 #define WM5100_DSP1_CONTROL_5                   0xF06
717 #define WM5100_DSP1_CONTROL_6                   0xF07
718 #define WM5100_DSP1_CONTROL_7                   0xF08
719 #define WM5100_DSP1_CONTROL_8                   0xF09
720 #define WM5100_DSP1_CONTROL_9                   0xF0A
721 #define WM5100_DSP1_CONTROL_10                  0xF0B
722 #define WM5100_DSP1_CONTROL_11                  0xF0C
723 #define WM5100_DSP1_CONTROL_12                  0xF0D
724 #define WM5100_DSP1_CONTROL_13                  0xF0F
725 #define WM5100_DSP1_CONTROL_14                  0xF10
726 #define WM5100_DSP1_CONTROL_15                  0xF11
727 #define WM5100_DSP1_CONTROL_16                  0xF12
728 #define WM5100_DSP1_CONTROL_17                  0xF13
729 #define WM5100_DSP1_CONTROL_18                  0xF14
730 #define WM5100_DSP1_CONTROL_19                  0xF16
731 #define WM5100_DSP1_CONTROL_20                  0xF17
732 #define WM5100_DSP1_CONTROL_21                  0xF18
733 #define WM5100_DSP1_CONTROL_22                  0xF1A
734 #define WM5100_DSP1_CONTROL_23                  0xF1B
735 #define WM5100_DSP1_CONTROL_24                  0xF1C
736 #define WM5100_DSP1_CONTROL_25                  0xF1E
737 #define WM5100_DSP1_CONTROL_26                  0xF20
738 #define WM5100_DSP1_CONTROL_27                  0xF21
739 #define WM5100_DSP1_CONTROL_28                  0xF22
740 #define WM5100_DSP1_CONTROL_29                  0xF23
741 #define WM5100_DSP1_CONTROL_30                  0xF24
742 #define WM5100_DSP2_CONTROL_1                   0x1000
743 #define WM5100_DSP2_CONTROL_2                   0x1002
744 #define WM5100_DSP2_CONTROL_3                   0x1003
745 #define WM5100_DSP2_CONTROL_4                   0x1004
746 #define WM5100_DSP2_CONTROL_5                   0x1006
747 #define WM5100_DSP2_CONTROL_6                   0x1007
748 #define WM5100_DSP2_CONTROL_7                   0x1008
749 #define WM5100_DSP2_CONTROL_8                   0x1009
750 #define WM5100_DSP2_CONTROL_9                   0x100A
751 #define WM5100_DSP2_CONTROL_10                  0x100B
752 #define WM5100_DSP2_CONTROL_11                  0x100C
753 #define WM5100_DSP2_CONTROL_12                  0x100D
754 #define WM5100_DSP2_CONTROL_13                  0x100F
755 #define WM5100_DSP2_CONTROL_14                  0x1010
756 #define WM5100_DSP2_CONTROL_15                  0x1011
757 #define WM5100_DSP2_CONTROL_16                  0x1012
758 #define WM5100_DSP2_CONTROL_17                  0x1013
759 #define WM5100_DSP2_CONTROL_18                  0x1014
760 #define WM5100_DSP2_CONTROL_19                  0x1016
761 #define WM5100_DSP2_CONTROL_20                  0x1017
762 #define WM5100_DSP2_CONTROL_21                  0x1018
763 #define WM5100_DSP2_CONTROL_22                  0x101A
764 #define WM5100_DSP2_CONTROL_23                  0x101B
765 #define WM5100_DSP2_CONTROL_24                  0x101C
766 #define WM5100_DSP2_CONTROL_25                  0x101E
767 #define WM5100_DSP2_CONTROL_26                  0x1020
768 #define WM5100_DSP2_CONTROL_27                  0x1021
769 #define WM5100_DSP2_CONTROL_28                  0x1022
770 #define WM5100_DSP2_CONTROL_29                  0x1023
771 #define WM5100_DSP2_CONTROL_30                  0x1024
772 #define WM5100_DSP3_CONTROL_1                   0x1100
773 #define WM5100_DSP3_CONTROL_2                   0x1102
774 #define WM5100_DSP3_CONTROL_3                   0x1103
775 #define WM5100_DSP3_CONTROL_4                   0x1104
776 #define WM5100_DSP3_CONTROL_5                   0x1106
777 #define WM5100_DSP3_CONTROL_6                   0x1107
778 #define WM5100_DSP3_CONTROL_7                   0x1108
779 #define WM5100_DSP3_CONTROL_8                   0x1109
780 #define WM5100_DSP3_CONTROL_9                   0x110A
781 #define WM5100_DSP3_CONTROL_10                  0x110B
782 #define WM5100_DSP3_CONTROL_11                  0x110C
783 #define WM5100_DSP3_CONTROL_12                  0x110D
784 #define WM5100_DSP3_CONTROL_13                  0x110F
785 #define WM5100_DSP3_CONTROL_14                  0x1110
786 #define WM5100_DSP3_CONTROL_15                  0x1111
787 #define WM5100_DSP3_CONTROL_16                  0x1112
788 #define WM5100_DSP3_CONTROL_17                  0x1113
789 #define WM5100_DSP3_CONTROL_18                  0x1114
790 #define WM5100_DSP3_CONTROL_19                  0x1116
791 #define WM5100_DSP3_CONTROL_20                  0x1117
792 #define WM5100_DSP3_CONTROL_21                  0x1118
793 #define WM5100_DSP3_CONTROL_22                  0x111A
794 #define WM5100_DSP3_CONTROL_23                  0x111B
795 #define WM5100_DSP3_CONTROL_24                  0x111C
796 #define WM5100_DSP3_CONTROL_25                  0x111E
797 #define WM5100_DSP3_CONTROL_26                  0x1120
798 #define WM5100_DSP3_CONTROL_27                  0x1121
799 #define WM5100_DSP3_CONTROL_28                  0x1122
800 #define WM5100_DSP3_CONTROL_29                  0x1123
801 #define WM5100_DSP3_CONTROL_30                  0x1124
802 #define WM5100_DSP1_DM_0                        0x4000
803 #define WM5100_DSP1_DM_1                        0x4001
804 #define WM5100_DSP1_DM_2                        0x4002
805 #define WM5100_DSP1_DM_3                        0x4003
806 #define WM5100_DSP1_DM_508                      0x41FC
807 #define WM5100_DSP1_DM_509                      0x41FD
808 #define WM5100_DSP1_DM_510                      0x41FE
809 #define WM5100_DSP1_DM_511                      0x41FF
810 #define WM5100_DSP1_PM_0                        0x4800
811 #define WM5100_DSP1_PM_1                        0x4801
812 #define WM5100_DSP1_PM_2                        0x4802
813 #define WM5100_DSP1_PM_3                        0x4803
814 #define WM5100_DSP1_PM_4                        0x4804
815 #define WM5100_DSP1_PM_5                        0x4805
816 #define WM5100_DSP1_PM_1530                     0x4DFA
817 #define WM5100_DSP1_PM_1531                     0x4DFB
818 #define WM5100_DSP1_PM_1532                     0x4DFC
819 #define WM5100_DSP1_PM_1533                     0x4DFD
820 #define WM5100_DSP1_PM_1534                     0x4DFE
821 #define WM5100_DSP1_PM_1535                     0x4DFF
822 #define WM5100_DSP1_ZM_0                        0x5000
823 #define WM5100_DSP1_ZM_1                        0x5001
824 #define WM5100_DSP1_ZM_2                        0x5002
825 #define WM5100_DSP1_ZM_3                        0x5003
826 #define WM5100_DSP1_ZM_2044                     0x57FC
827 #define WM5100_DSP1_ZM_2045                     0x57FD
828 #define WM5100_DSP1_ZM_2046                     0x57FE
829 #define WM5100_DSP1_ZM_2047                     0x57FF
830 #define WM5100_DSP2_DM_0                        0x6000
831 #define WM5100_DSP2_DM_1                        0x6001
832 #define WM5100_DSP2_DM_2                        0x6002
833 #define WM5100_DSP2_DM_3                        0x6003
834 #define WM5100_DSP2_DM_508                      0x61FC
835 #define WM5100_DSP2_DM_509                      0x61FD
836 #define WM5100_DSP2_DM_510                      0x61FE
837 #define WM5100_DSP2_DM_511                      0x61FF
838 #define WM5100_DSP2_PM_0                        0x6800
839 #define WM5100_DSP2_PM_1                        0x6801
840 #define WM5100_DSP2_PM_2                        0x6802
841 #define WM5100_DSP2_PM_3                        0x6803
842 #define WM5100_DSP2_PM_4                        0x6804
843 #define WM5100_DSP2_PM_5                        0x6805
844 #define WM5100_DSP2_PM_1530                     0x6DFA
845 #define WM5100_DSP2_PM_1531                     0x6DFB
846 #define WM5100_DSP2_PM_1532                     0x6DFC
847 #define WM5100_DSP2_PM_1533                     0x6DFD
848 #define WM5100_DSP2_PM_1534                     0x6DFE
849 #define WM5100_DSP2_PM_1535                     0x6DFF
850 #define WM5100_DSP2_ZM_0                        0x7000
851 #define WM5100_DSP2_ZM_1                        0x7001
852 #define WM5100_DSP2_ZM_2                        0x7002
853 #define WM5100_DSP2_ZM_3                        0x7003
854 #define WM5100_DSP2_ZM_2044                     0x77FC
855 #define WM5100_DSP2_ZM_2045                     0x77FD
856 #define WM5100_DSP2_ZM_2046                     0x77FE
857 #define WM5100_DSP2_ZM_2047                     0x77FF
858 #define WM5100_DSP3_DM_0                        0x8000
859 #define WM5100_DSP3_DM_1                        0x8001
860 #define WM5100_DSP3_DM_2                        0x8002
861 #define WM5100_DSP3_DM_3                        0x8003
862 #define WM5100_DSP3_DM_508                      0x81FC
863 #define WM5100_DSP3_DM_509                      0x81FD
864 #define WM5100_DSP3_DM_510                      0x81FE
865 #define WM5100_DSP3_DM_511                      0x81FF
866 #define WM5100_DSP3_PM_0                        0x8800
867 #define WM5100_DSP3_PM_1                        0x8801
868 #define WM5100_DSP3_PM_2                        0x8802
869 #define WM5100_DSP3_PM_3                        0x8803
870 #define WM5100_DSP3_PM_4                        0x8804
871 #define WM5100_DSP3_PM_5                        0x8805
872 #define WM5100_DSP3_PM_1530                     0x8DFA
873 #define WM5100_DSP3_PM_1531                     0x8DFB
874 #define WM5100_DSP3_PM_1532                     0x8DFC
875 #define WM5100_DSP3_PM_1533                     0x8DFD
876 #define WM5100_DSP3_PM_1534                     0x8DFE
877 #define WM5100_DSP3_PM_1535                     0x8DFF
878 #define WM5100_DSP3_ZM_0                        0x9000
879 #define WM5100_DSP3_ZM_1                        0x9001
880 #define WM5100_DSP3_ZM_2                        0x9002
881 #define WM5100_DSP3_ZM_3                        0x9003
882 #define WM5100_DSP3_ZM_2044                     0x97FC
883 #define WM5100_DSP3_ZM_2045                     0x97FD
884 #define WM5100_DSP3_ZM_2046                     0x97FE
885 #define WM5100_DSP3_ZM_2047                     0x97FF
886 
887 #define WM5100_REGISTER_COUNT                   1435
888 #define WM5100_MAX_REGISTER                     0x97FF
889 
890 /*
891  * Field Definitions.
892  */
893 
894 /*
895  * R0 (0x00) - software reset
896  */
897 #define WM5100_SW_RST_DEV_ID1_MASK              0xFFFF  /* SW_RST_DEV_ID1 - [15:0] */
898 #define WM5100_SW_RST_DEV_ID1_SHIFT                  0  /* SW_RST_DEV_ID1 - [15:0] */
899 #define WM5100_SW_RST_DEV_ID1_WIDTH                 16  /* SW_RST_DEV_ID1 - [15:0] */
900 
901 /*
902  * R1 (0x01) - Device Revision
903  */
904 #define WM5100_DEVICE_REVISION_MASK             0x000F  /* DEVICE_REVISION - [3:0] */
905 #define WM5100_DEVICE_REVISION_SHIFT                 0  /* DEVICE_REVISION - [3:0] */
906 #define WM5100_DEVICE_REVISION_WIDTH                 4  /* DEVICE_REVISION - [3:0] */
907 
908 /*
909  * R16 (0x10) - Ctrl IF 1
910  */
911 #define WM5100_AUTO_INC                         0x0001  /* AUTO_INC */
912 #define WM5100_AUTO_INC_MASK                    0x0001  /* AUTO_INC */
913 #define WM5100_AUTO_INC_SHIFT                        0  /* AUTO_INC */
914 #define WM5100_AUTO_INC_WIDTH                        1  /* AUTO_INC */
915 
916 /*
917  * R32 (0x20) - Tone Generator 1
918  */
919 #define WM5100_TONE_RATE_MASK                   0x3000  /* TONE_RATE - [13:12] */
920 #define WM5100_TONE_RATE_SHIFT                      12  /* TONE_RATE - [13:12] */
921 #define WM5100_TONE_RATE_WIDTH                       2  /* TONE_RATE - [13:12] */
922 #define WM5100_TONE_OFFSET_MASK                 0x0300  /* TONE_OFFSET - [9:8] */
923 #define WM5100_TONE_OFFSET_SHIFT                     8  /* TONE_OFFSET - [9:8] */
924 #define WM5100_TONE_OFFSET_WIDTH                     2  /* TONE_OFFSET - [9:8] */
925 #define WM5100_TONE2_ENA                        0x0002  /* TONE2_ENA */
926 #define WM5100_TONE2_ENA_MASK                   0x0002  /* TONE2_ENA */
927 #define WM5100_TONE2_ENA_SHIFT                       1  /* TONE2_ENA */
928 #define WM5100_TONE2_ENA_WIDTH                       1  /* TONE2_ENA */
929 #define WM5100_TONE1_ENA                        0x0001  /* TONE1_ENA */
930 #define WM5100_TONE1_ENA_MASK                   0x0001  /* TONE1_ENA */
931 #define WM5100_TONE1_ENA_SHIFT                       0  /* TONE1_ENA */
932 #define WM5100_TONE1_ENA_WIDTH                       1  /* TONE1_ENA */
933 
934 /*
935  * R48 (0x30) - PWM Drive 1
936  */
937 #define WM5100_PWM_RATE_MASK                    0x3000  /* PWM_RATE - [13:12] */
938 #define WM5100_PWM_RATE_SHIFT                       12  /* PWM_RATE - [13:12] */
939 #define WM5100_PWM_RATE_WIDTH                        2  /* PWM_RATE - [13:12] */
940 #define WM5100_PWM_CLK_SEL_MASK                 0x0300  /* PWM_CLK_SEL - [9:8] */
941 #define WM5100_PWM_CLK_SEL_SHIFT                     8  /* PWM_CLK_SEL - [9:8] */
942 #define WM5100_PWM_CLK_SEL_WIDTH                     2  /* PWM_CLK_SEL - [9:8] */
943 #define WM5100_PWM2_OVD                         0x0020  /* PWM2_OVD */
944 #define WM5100_PWM2_OVD_MASK                    0x0020  /* PWM2_OVD */
945 #define WM5100_PWM2_OVD_SHIFT                        5  /* PWM2_OVD */
946 #define WM5100_PWM2_OVD_WIDTH                        1  /* PWM2_OVD */
947 #define WM5100_PWM1_OVD                         0x0010  /* PWM1_OVD */
948 #define WM5100_PWM1_OVD_MASK                    0x0010  /* PWM1_OVD */
949 #define WM5100_PWM1_OVD_SHIFT                        4  /* PWM1_OVD */
950 #define WM5100_PWM1_OVD_WIDTH                        1  /* PWM1_OVD */
951 #define WM5100_PWM2_ENA                         0x0002  /* PWM2_ENA */
952 #define WM5100_PWM2_ENA_MASK                    0x0002  /* PWM2_ENA */
953 #define WM5100_PWM2_ENA_SHIFT                        1  /* PWM2_ENA */
954 #define WM5100_PWM2_ENA_WIDTH                        1  /* PWM2_ENA */
955 #define WM5100_PWM1_ENA                         0x0001  /* PWM1_ENA */
956 #define WM5100_PWM1_ENA_MASK                    0x0001  /* PWM1_ENA */
957 #define WM5100_PWM1_ENA_SHIFT                        0  /* PWM1_ENA */
958 #define WM5100_PWM1_ENA_WIDTH                        1  /* PWM1_ENA */
959 
960 /*
961  * R49 (0x31) - PWM Drive 2
962  */
963 #define WM5100_PWM1_LVL_MASK                    0x03FF  /* PWM1_LVL - [9:0] */
964 #define WM5100_PWM1_LVL_SHIFT                        0  /* PWM1_LVL - [9:0] */
965 #define WM5100_PWM1_LVL_WIDTH                       10  /* PWM1_LVL - [9:0] */
966 
967 /*
968  * R50 (0x32) - PWM Drive 3
969  */
970 #define WM5100_PWM2_LVL_MASK                    0x03FF  /* PWM2_LVL - [9:0] */
971 #define WM5100_PWM2_LVL_SHIFT                        0  /* PWM2_LVL - [9:0] */
972 #define WM5100_PWM2_LVL_WIDTH                       10  /* PWM2_LVL - [9:0] */
973 
974 /*
975  * R256 (0x100) - Clocking 1
976  */
977 #define WM5100_CLK_32K_SRC_MASK                 0x000F  /* CLK_32K_SRC - [3:0] */
978 #define WM5100_CLK_32K_SRC_SHIFT                     0  /* CLK_32K_SRC - [3:0] */
979 #define WM5100_CLK_32K_SRC_WIDTH                     4  /* CLK_32K_SRC - [3:0] */
980 
981 /*
982  * R257 (0x101) - Clocking 3
983  */
984 #define WM5100_SYSCLK_FREQ_MASK                 0x0700  /* SYSCLK_FREQ - [10:8] */
985 #define WM5100_SYSCLK_FREQ_SHIFT                     8  /* SYSCLK_FREQ - [10:8] */
986 #define WM5100_SYSCLK_FREQ_WIDTH                     3  /* SYSCLK_FREQ - [10:8] */
987 #define WM5100_SYSCLK_ENA                       0x0040  /* SYSCLK_ENA */
988 #define WM5100_SYSCLK_ENA_MASK                  0x0040  /* SYSCLK_ENA */
989 #define WM5100_SYSCLK_ENA_SHIFT                      6  /* SYSCLK_ENA */
990 #define WM5100_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
991 #define WM5100_SYSCLK_SRC_MASK                  0x000F  /* SYSCLK_SRC - [3:0] */
992 #define WM5100_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC - [3:0] */
993 #define WM5100_SYSCLK_SRC_WIDTH                      4  /* SYSCLK_SRC - [3:0] */
994 
995 /*
996  * R258 (0x102) - Clocking 4
997  */
998 #define WM5100_SAMPLE_RATE_1_MASK               0x001F  /* SAMPLE_RATE_1 - [4:0] */
999 #define WM5100_SAMPLE_RATE_1_SHIFT                   0  /* SAMPLE_RATE_1 - [4:0] */
1000 #define WM5100_SAMPLE_RATE_1_WIDTH                   5  /* SAMPLE_RATE_1 - [4:0] */
1001 
1002 /*
1003  * R259 (0x103) - Clocking 5
1004  */
1005 #define WM5100_SAMPLE_RATE_2_MASK               0x001F  /* SAMPLE_RATE_2 - [4:0] */
1006 #define WM5100_SAMPLE_RATE_2_SHIFT                   0  /* SAMPLE_RATE_2 - [4:0] */
1007 #define WM5100_SAMPLE_RATE_2_WIDTH                   5  /* SAMPLE_RATE_2 - [4:0] */
1008 
1009 /*
1010  * R260 (0x104) - Clocking 6
1011  */
1012 #define WM5100_SAMPLE_RATE_3_MASK               0x001F  /* SAMPLE_RATE_3 - [4:0] */
1013 #define WM5100_SAMPLE_RATE_3_SHIFT                   0  /* SAMPLE_RATE_3 - [4:0] */
1014 #define WM5100_SAMPLE_RATE_3_WIDTH                   5  /* SAMPLE_RATE_3 - [4:0] */
1015 
1016 /*
1017  * R263 (0x107) - Clocking 7
1018  */
1019 #define WM5100_ASYNC_CLK_FREQ_MASK              0x0700  /* ASYNC_CLK_FREQ - [10:8] */
1020 #define WM5100_ASYNC_CLK_FREQ_SHIFT                  8  /* ASYNC_CLK_FREQ - [10:8] */
1021 #define WM5100_ASYNC_CLK_FREQ_WIDTH                  3  /* ASYNC_CLK_FREQ - [10:8] */
1022 #define WM5100_ASYNC_CLK_ENA                    0x0040  /* ASYNC_CLK_ENA */
1023 #define WM5100_ASYNC_CLK_ENA_MASK               0x0040  /* ASYNC_CLK_ENA */
1024 #define WM5100_ASYNC_CLK_ENA_SHIFT                   6  /* ASYNC_CLK_ENA */
1025 #define WM5100_ASYNC_CLK_ENA_WIDTH                   1  /* ASYNC_CLK_ENA */
1026 #define WM5100_ASYNC_CLK_SRC_MASK               0x000F  /* ASYNC_CLK_SRC - [3:0] */
1027 #define WM5100_ASYNC_CLK_SRC_SHIFT                   0  /* ASYNC_CLK_SRC - [3:0] */
1028 #define WM5100_ASYNC_CLK_SRC_WIDTH                   4  /* ASYNC_CLK_SRC - [3:0] */
1029 
1030 /*
1031  * R264 (0x108) - Clocking 8
1032  */
1033 #define WM5100_ASYNC_SAMPLE_RATE_MASK           0x001F  /* ASYNC_SAMPLE_RATE - [4:0] */
1034 #define WM5100_ASYNC_SAMPLE_RATE_SHIFT               0  /* ASYNC_SAMPLE_RATE - [4:0] */
1035 #define WM5100_ASYNC_SAMPLE_RATE_WIDTH               5  /* ASYNC_SAMPLE_RATE - [4:0] */
1036 
1037 /*
1038  * R288 (0x120) - ASRC_ENABLE
1039  */
1040 #define WM5100_ASRC2L_ENA                       0x0008  /* ASRC2L_ENA */
1041 #define WM5100_ASRC2L_ENA_MASK                  0x0008  /* ASRC2L_ENA */
1042 #define WM5100_ASRC2L_ENA_SHIFT                      3  /* ASRC2L_ENA */
1043 #define WM5100_ASRC2L_ENA_WIDTH                      1  /* ASRC2L_ENA */
1044 #define WM5100_ASRC2R_ENA                       0x0004  /* ASRC2R_ENA */
1045 #define WM5100_ASRC2R_ENA_MASK                  0x0004  /* ASRC2R_ENA */
1046 #define WM5100_ASRC2R_ENA_SHIFT                      2  /* ASRC2R_ENA */
1047 #define WM5100_ASRC2R_ENA_WIDTH                      1  /* ASRC2R_ENA */
1048 #define WM5100_ASRC1L_ENA                       0x0002  /* ASRC1L_ENA */
1049 #define WM5100_ASRC1L_ENA_MASK                  0x0002  /* ASRC1L_ENA */
1050 #define WM5100_ASRC1L_ENA_SHIFT                      1  /* ASRC1L_ENA */
1051 #define WM5100_ASRC1L_ENA_WIDTH                      1  /* ASRC1L_ENA */
1052 #define WM5100_ASRC1R_ENA                       0x0001  /* ASRC1R_ENA */
1053 #define WM5100_ASRC1R_ENA_MASK                  0x0001  /* ASRC1R_ENA */
1054 #define WM5100_ASRC1R_ENA_SHIFT                      0  /* ASRC1R_ENA */
1055 #define WM5100_ASRC1R_ENA_WIDTH                      1  /* ASRC1R_ENA */
1056 
1057 /*
1058  * R289 (0x121) - ASRC_STATUS
1059  */
1060 #define WM5100_ASRC2L_ENA_STS                   0x0008  /* ASRC2L_ENA_STS */
1061 #define WM5100_ASRC2L_ENA_STS_MASK              0x0008  /* ASRC2L_ENA_STS */
1062 #define WM5100_ASRC2L_ENA_STS_SHIFT                  3  /* ASRC2L_ENA_STS */
1063 #define WM5100_ASRC2L_ENA_STS_WIDTH                  1  /* ASRC2L_ENA_STS */
1064 #define WM5100_ASRC2R_ENA_STS                   0x0004  /* ASRC2R_ENA_STS */
1065 #define WM5100_ASRC2R_ENA_STS_MASK              0x0004  /* ASRC2R_ENA_STS */
1066 #define WM5100_ASRC2R_ENA_STS_SHIFT                  2  /* ASRC2R_ENA_STS */
1067 #define WM5100_ASRC2R_ENA_STS_WIDTH                  1  /* ASRC2R_ENA_STS */
1068 #define WM5100_ASRC1L_ENA_STS                   0x0002  /* ASRC1L_ENA_STS */
1069 #define WM5100_ASRC1L_ENA_STS_MASK              0x0002  /* ASRC1L_ENA_STS */
1070 #define WM5100_ASRC1L_ENA_STS_SHIFT                  1  /* ASRC1L_ENA_STS */
1071 #define WM5100_ASRC1L_ENA_STS_WIDTH                  1  /* ASRC1L_ENA_STS */
1072 #define WM5100_ASRC1R_ENA_STS                   0x0001  /* ASRC1R_ENA_STS */
1073 #define WM5100_ASRC1R_ENA_STS_MASK              0x0001  /* ASRC1R_ENA_STS */
1074 #define WM5100_ASRC1R_ENA_STS_SHIFT                  0  /* ASRC1R_ENA_STS */
1075 #define WM5100_ASRC1R_ENA_STS_WIDTH                  1  /* ASRC1R_ENA_STS */
1076 
1077 /*
1078  * R290 (0x122) - ASRC_RATE1
1079  */
1080 #define WM5100_ASRC_RATE1_MASK                  0x0006  /* ASRC_RATE1 - [2:1] */
1081 #define WM5100_ASRC_RATE1_SHIFT                      1  /* ASRC_RATE1 - [2:1] */
1082 #define WM5100_ASRC_RATE1_WIDTH                      2  /* ASRC_RATE1 - [2:1] */
1083 
1084 /*
1085  * R321 (0x141) - ISRC 1 CTRL 1
1086  */
1087 #define WM5100_ISRC1_DFS_ENA                    0x2000  /* ISRC1_DFS_ENA */
1088 #define WM5100_ISRC1_DFS_ENA_MASK               0x2000  /* ISRC1_DFS_ENA */
1089 #define WM5100_ISRC1_DFS_ENA_SHIFT                  13  /* ISRC1_DFS_ENA */
1090 #define WM5100_ISRC1_DFS_ENA_WIDTH                   1  /* ISRC1_DFS_ENA */
1091 #define WM5100_ISRC1_CLK_SEL_MASK               0x0300  /* ISRC1_CLK_SEL - [9:8] */
1092 #define WM5100_ISRC1_CLK_SEL_SHIFT                   8  /* ISRC1_CLK_SEL - [9:8] */
1093 #define WM5100_ISRC1_CLK_SEL_WIDTH                   2  /* ISRC1_CLK_SEL - [9:8] */
1094 #define WM5100_ISRC1_FSH_MASK                   0x000C  /* ISRC1_FSH - [3:2] */
1095 #define WM5100_ISRC1_FSH_SHIFT                       2  /* ISRC1_FSH - [3:2] */
1096 #define WM5100_ISRC1_FSH_WIDTH                       2  /* ISRC1_FSH - [3:2] */
1097 #define WM5100_ISRC1_FSL_MASK                   0x0003  /* ISRC1_FSL - [1:0] */
1098 #define WM5100_ISRC1_FSL_SHIFT                       0  /* ISRC1_FSL - [1:0] */
1099 #define WM5100_ISRC1_FSL_WIDTH                       2  /* ISRC1_FSL - [1:0] */
1100 
1101 /*
1102  * R322 (0x142) - ISRC 1 CTRL 2
1103  */
1104 #define WM5100_ISRC1_INT1_ENA                   0x8000  /* ISRC1_INT1_ENA */
1105 #define WM5100_ISRC1_INT1_ENA_MASK              0x8000  /* ISRC1_INT1_ENA */
1106 #define WM5100_ISRC1_INT1_ENA_SHIFT                 15  /* ISRC1_INT1_ENA */
1107 #define WM5100_ISRC1_INT1_ENA_WIDTH                  1  /* ISRC1_INT1_ENA */
1108 #define WM5100_ISRC1_INT2_ENA                   0x4000  /* ISRC1_INT2_ENA */
1109 #define WM5100_ISRC1_INT2_ENA_MASK              0x4000  /* ISRC1_INT2_ENA */
1110 #define WM5100_ISRC1_INT2_ENA_SHIFT                 14  /* ISRC1_INT2_ENA */
1111 #define WM5100_ISRC1_INT2_ENA_WIDTH                  1  /* ISRC1_INT2_ENA */
1112 #define WM5100_ISRC1_INT3_ENA                   0x2000  /* ISRC1_INT3_ENA */
1113 #define WM5100_ISRC1_INT3_ENA_MASK              0x2000  /* ISRC1_INT3_ENA */
1114 #define WM5100_ISRC1_INT3_ENA_SHIFT                 13  /* ISRC1_INT3_ENA */
1115 #define WM5100_ISRC1_INT3_ENA_WIDTH                  1  /* ISRC1_INT3_ENA */
1116 #define WM5100_ISRC1_INT4_ENA                   0x1000  /* ISRC1_INT4_ENA */
1117 #define WM5100_ISRC1_INT4_ENA_MASK              0x1000  /* ISRC1_INT4_ENA */
1118 #define WM5100_ISRC1_INT4_ENA_SHIFT                 12  /* ISRC1_INT4_ENA */
1119 #define WM5100_ISRC1_INT4_ENA_WIDTH                  1  /* ISRC1_INT4_ENA */
1120 #define WM5100_ISRC1_DEC1_ENA                   0x0200  /* ISRC1_DEC1_ENA */
1121 #define WM5100_ISRC1_DEC1_ENA_MASK              0x0200  /* ISRC1_DEC1_ENA */
1122 #define WM5100_ISRC1_DEC1_ENA_SHIFT                  9  /* ISRC1_DEC1_ENA */
1123 #define WM5100_ISRC1_DEC1_ENA_WIDTH                  1  /* ISRC1_DEC1_ENA */
1124 #define WM5100_ISRC1_DEC2_ENA                   0x0100  /* ISRC1_DEC2_ENA */
1125 #define WM5100_ISRC1_DEC2_ENA_MASK              0x0100  /* ISRC1_DEC2_ENA */
1126 #define WM5100_ISRC1_DEC2_ENA_SHIFT                  8  /* ISRC1_DEC2_ENA */
1127 #define WM5100_ISRC1_DEC2_ENA_WIDTH                  1  /* ISRC1_DEC2_ENA */
1128 #define WM5100_ISRC1_DEC3_ENA                   0x0080  /* ISRC1_DEC3_ENA */
1129 #define WM5100_ISRC1_DEC3_ENA_MASK              0x0080  /* ISRC1_DEC3_ENA */
1130 #define WM5100_ISRC1_DEC3_ENA_SHIFT                  7  /* ISRC1_DEC3_ENA */
1131 #define WM5100_ISRC1_DEC3_ENA_WIDTH                  1  /* ISRC1_DEC3_ENA */
1132 #define WM5100_ISRC1_DEC4_ENA                   0x0040  /* ISRC1_DEC4_ENA */
1133 #define WM5100_ISRC1_DEC4_ENA_MASK              0x0040  /* ISRC1_DEC4_ENA */
1134 #define WM5100_ISRC1_DEC4_ENA_SHIFT                  6  /* ISRC1_DEC4_ENA */
1135 #define WM5100_ISRC1_DEC4_ENA_WIDTH                  1  /* ISRC1_DEC4_ENA */
1136 #define WM5100_ISRC1_NOTCH_ENA                  0x0001  /* ISRC1_NOTCH_ENA */
1137 #define WM5100_ISRC1_NOTCH_ENA_MASK             0x0001  /* ISRC1_NOTCH_ENA */
1138 #define WM5100_ISRC1_NOTCH_ENA_SHIFT                 0  /* ISRC1_NOTCH_ENA */
1139 #define WM5100_ISRC1_NOTCH_ENA_WIDTH                 1  /* ISRC1_NOTCH_ENA */
1140 
1141 /*
1142  * R323 (0x143) - ISRC 2 CTRL1
1143  */
1144 #define WM5100_ISRC2_DFS_ENA                    0x2000  /* ISRC2_DFS_ENA */
1145 #define WM5100_ISRC2_DFS_ENA_MASK               0x2000  /* ISRC2_DFS_ENA */
1146 #define WM5100_ISRC2_DFS_ENA_SHIFT                  13  /* ISRC2_DFS_ENA */
1147 #define WM5100_ISRC2_DFS_ENA_WIDTH                   1  /* ISRC2_DFS_ENA */
1148 #define WM5100_ISRC2_CLK_SEL_MASK               0x0300  /* ISRC2_CLK_SEL - [9:8] */
1149 #define WM5100_ISRC2_CLK_SEL_SHIFT                   8  /* ISRC2_CLK_SEL - [9:8] */
1150 #define WM5100_ISRC2_CLK_SEL_WIDTH                   2  /* ISRC2_CLK_SEL - [9:8] */
1151 #define WM5100_ISRC2_FSH_MASK                   0x000C  /* ISRC2_FSH - [3:2] */
1152 #define WM5100_ISRC2_FSH_SHIFT                       2  /* ISRC2_FSH - [3:2] */
1153 #define WM5100_ISRC2_FSH_WIDTH                       2  /* ISRC2_FSH - [3:2] */
1154 #define WM5100_ISRC2_FSL_MASK                   0x0003  /* ISRC2_FSL - [1:0] */
1155 #define WM5100_ISRC2_FSL_SHIFT                       0  /* ISRC2_FSL - [1:0] */
1156 #define WM5100_ISRC2_FSL_WIDTH                       2  /* ISRC2_FSL - [1:0] */
1157 
1158 /*
1159  * R324 (0x144) - ISRC 2 CTRL 2
1160  */
1161 #define WM5100_ISRC2_INT1_ENA                   0x8000  /* ISRC2_INT1_ENA */
1162 #define WM5100_ISRC2_INT1_ENA_MASK              0x8000  /* ISRC2_INT1_ENA */
1163 #define WM5100_ISRC2_INT1_ENA_SHIFT                 15  /* ISRC2_INT1_ENA */
1164 #define WM5100_ISRC2_INT1_ENA_WIDTH                  1  /* ISRC2_INT1_ENA */
1165 #define WM5100_ISRC2_INT2_ENA                   0x4000  /* ISRC2_INT2_ENA */
1166 #define WM5100_ISRC2_INT2_ENA_MASK              0x4000  /* ISRC2_INT2_ENA */
1167 #define WM5100_ISRC2_INT2_ENA_SHIFT                 14  /* ISRC2_INT2_ENA */
1168 #define WM5100_ISRC2_INT2_ENA_WIDTH                  1  /* ISRC2_INT2_ENA */
1169 #define WM5100_ISRC2_INT3_ENA                   0x2000  /* ISRC2_INT3_ENA */
1170 #define WM5100_ISRC2_INT3_ENA_MASK              0x2000  /* ISRC2_INT3_ENA */
1171 #define WM5100_ISRC2_INT3_ENA_SHIFT                 13  /* ISRC2_INT3_ENA */
1172 #define WM5100_ISRC2_INT3_ENA_WIDTH                  1  /* ISRC2_INT3_ENA */
1173 #define WM5100_ISRC2_INT4_ENA                   0x1000  /* ISRC2_INT4_ENA */
1174 #define WM5100_ISRC2_INT4_ENA_MASK              0x1000  /* ISRC2_INT4_ENA */
1175 #define WM5100_ISRC2_INT4_ENA_SHIFT                 12  /* ISRC2_INT4_ENA */
1176 #define WM5100_ISRC2_INT4_ENA_WIDTH                  1  /* ISRC2_INT4_ENA */
1177 #define WM5100_ISRC2_DEC1_ENA                   0x0200  /* ISRC2_DEC1_ENA */
1178 #define WM5100_ISRC2_DEC1_ENA_MASK              0x0200  /* ISRC2_DEC1_ENA */
1179 #define WM5100_ISRC2_DEC1_ENA_SHIFT                  9  /* ISRC2_DEC1_ENA */
1180 #define WM5100_ISRC2_DEC1_ENA_WIDTH                  1  /* ISRC2_DEC1_ENA */
1181 #define WM5100_ISRC2_DEC2_ENA                   0x0100  /* ISRC2_DEC2_ENA */
1182 #define WM5100_ISRC2_DEC2_ENA_MASK              0x0100  /* ISRC2_DEC2_ENA */
1183 #define WM5100_ISRC2_DEC2_ENA_SHIFT                  8  /* ISRC2_DEC2_ENA */
1184 #define WM5100_ISRC2_DEC2_ENA_WIDTH                  1  /* ISRC2_DEC2_ENA */
1185 #define WM5100_ISRC2_DEC3_ENA                   0x0080  /* ISRC2_DEC3_ENA */
1186 #define WM5100_ISRC2_DEC3_ENA_MASK              0x0080  /* ISRC2_DEC3_ENA */
1187 #define WM5100_ISRC2_DEC3_ENA_SHIFT                  7  /* ISRC2_DEC3_ENA */
1188 #define WM5100_ISRC2_DEC3_ENA_WIDTH                  1  /* ISRC2_DEC3_ENA */
1189 #define WM5100_ISRC2_DEC4_ENA                   0x0040  /* ISRC2_DEC4_ENA */
1190 #define WM5100_ISRC2_DEC4_ENA_MASK              0x0040  /* ISRC2_DEC4_ENA */
1191 #define WM5100_ISRC2_DEC4_ENA_SHIFT                  6  /* ISRC2_DEC4_ENA */
1192 #define WM5100_ISRC2_DEC4_ENA_WIDTH                  1  /* ISRC2_DEC4_ENA */
1193 #define WM5100_ISRC2_NOTCH_ENA                  0x0001  /* ISRC2_NOTCH_ENA */
1194 #define WM5100_ISRC2_NOTCH_ENA_MASK             0x0001  /* ISRC2_NOTCH_ENA */
1195 #define WM5100_ISRC2_NOTCH_ENA_SHIFT                 0  /* ISRC2_NOTCH_ENA */
1196 #define WM5100_ISRC2_NOTCH_ENA_WIDTH                 1  /* ISRC2_NOTCH_ENA */
1197 
1198 /*
1199  * R386 (0x182) - FLL1 Control 1
1200  */
1201 #define WM5100_FLL1_ENA                         0x0001  /* FLL1_ENA */
1202 #define WM5100_FLL1_ENA_MASK                    0x0001  /* FLL1_ENA */
1203 #define WM5100_FLL1_ENA_SHIFT                        0  /* FLL1_ENA */
1204 #define WM5100_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
1205 
1206 /*
1207  * R387 (0x183) - FLL1 Control 2
1208  */
1209 #define WM5100_FLL1_OUTDIV_MASK                 0x3F00  /* FLL1_OUTDIV - [13:8] */
1210 #define WM5100_FLL1_OUTDIV_SHIFT                     8  /* FLL1_OUTDIV - [13:8] */
1211 #define WM5100_FLL1_OUTDIV_WIDTH                     6  /* FLL1_OUTDIV - [13:8] */
1212 #define WM5100_FLL1_FRATIO_MASK                 0x0007  /* FLL1_FRATIO - [2:0] */
1213 #define WM5100_FLL1_FRATIO_SHIFT                     0  /* FLL1_FRATIO - [2:0] */
1214 #define WM5100_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [2:0] */
1215 
1216 /*
1217  * R388 (0x184) - FLL1 Control 3
1218  */
1219 #define WM5100_FLL1_THETA_MASK                  0xFFFF  /* FLL1_THETA - [15:0] */
1220 #define WM5100_FLL1_THETA_SHIFT                      0  /* FLL1_THETA - [15:0] */
1221 #define WM5100_FLL1_THETA_WIDTH                     16  /* FLL1_THETA - [15:0] */
1222 
1223 /*
1224  * R390 (0x186) - FLL1 Control 5
1225  */
1226 #define WM5100_FLL1_N_MASK                      0x03FF  /* FLL1_N - [9:0] */
1227 #define WM5100_FLL1_N_SHIFT                          0  /* FLL1_N - [9:0] */
1228 #define WM5100_FLL1_N_WIDTH                         10  /* FLL1_N - [9:0] */
1229 
1230 /*
1231  * R391 (0x187) - FLL1 Control 6
1232  */
1233 #define WM5100_FLL1_REFCLK_DIV_MASK             0x00C0  /* FLL1_REFCLK_DIV - [7:6] */
1234 #define WM5100_FLL1_REFCLK_DIV_SHIFT                 6  /* FLL1_REFCLK_DIV - [7:6] */
1235 #define WM5100_FLL1_REFCLK_DIV_WIDTH                 2  /* FLL1_REFCLK_DIV - [7:6] */
1236 #define WM5100_FLL1_REFCLK_SRC_MASK             0x000F  /* FLL1_REFCLK_SRC - [3:0] */
1237 #define WM5100_FLL1_REFCLK_SRC_SHIFT                 0  /* FLL1_REFCLK_SRC - [3:0] */
1238 #define WM5100_FLL1_REFCLK_SRC_WIDTH                 4  /* FLL1_REFCLK_SRC - [3:0] */
1239 
1240 /*
1241  * R392 (0x188) - FLL1 EFS 1
1242  */
1243 #define WM5100_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
1244 #define WM5100_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
1245 #define WM5100_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
1246 
1247 /*
1248  * R418 (0x1A2) - FLL2 Control 1
1249  */
1250 #define WM5100_FLL2_ENA                         0x0001  /* FLL2_ENA */
1251 #define WM5100_FLL2_ENA_MASK                    0x0001  /* FLL2_ENA */
1252 #define WM5100_FLL2_ENA_SHIFT                        0  /* FLL2_ENA */
1253 #define WM5100_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
1254 
1255 /*
1256  * R419 (0x1A3) - FLL2 Control 2
1257  */
1258 #define WM5100_FLL2_OUTDIV_MASK                 0x3F00  /* FLL2_OUTDIV - [13:8] */
1259 #define WM5100_FLL2_OUTDIV_SHIFT                     8  /* FLL2_OUTDIV - [13:8] */
1260 #define WM5100_FLL2_OUTDIV_WIDTH                     6  /* FLL2_OUTDIV - [13:8] */
1261 #define WM5100_FLL2_FRATIO_MASK                 0x0007  /* FLL2_FRATIO - [2:0] */
1262 #define WM5100_FLL2_FRATIO_SHIFT                     0  /* FLL2_FRATIO - [2:0] */
1263 #define WM5100_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [2:0] */
1264 
1265 /*
1266  * R420 (0x1A4) - FLL2 Control 3
1267  */
1268 #define WM5100_FLL2_THETA_MASK                  0xFFFF  /* FLL2_THETA - [15:0] */
1269 #define WM5100_FLL2_THETA_SHIFT                      0  /* FLL2_THETA - [15:0] */
1270 #define WM5100_FLL2_THETA_WIDTH                     16  /* FLL2_THETA - [15:0] */
1271 
1272 /*
1273  * R422 (0x1A6) - FLL2 Control 5
1274  */
1275 #define WM5100_FLL2_N_MASK                      0x03FF  /* FLL2_N - [9:0] */
1276 #define WM5100_FLL2_N_SHIFT                          0  /* FLL2_N - [9:0] */
1277 #define WM5100_FLL2_N_WIDTH                         10  /* FLL2_N - [9:0] */
1278 
1279 /*
1280  * R423 (0x1A7) - FLL2 Control 6
1281  */
1282 #define WM5100_FLL2_REFCLK_DIV_MASK             0x00C0  /* FLL2_REFCLK_DIV - [7:6] */
1283 #define WM5100_FLL2_REFCLK_DIV_SHIFT                 6  /* FLL2_REFCLK_DIV - [7:6] */
1284 #define WM5100_FLL2_REFCLK_DIV_WIDTH                 2  /* FLL2_REFCLK_DIV - [7:6] */
1285 #define WM5100_FLL2_REFCLK_SRC_MASK             0x000F  /* FLL2_REFCLK_SRC - [3:0] */
1286 #define WM5100_FLL2_REFCLK_SRC_SHIFT                 0  /* FLL2_REFCLK_SRC - [3:0] */
1287 #define WM5100_FLL2_REFCLK_SRC_WIDTH                 4  /* FLL2_REFCLK_SRC - [3:0] */
1288 
1289 /*
1290  * R424 (0x1A8) - FLL2 EFS 1
1291  */
1292 #define WM5100_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
1293 #define WM5100_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
1294 #define WM5100_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
1295 
1296 /*
1297  * R512 (0x200) - Mic Charge Pump 1
1298  */
1299 #define WM5100_CP2_BYPASS                       0x0020  /* CP2_BYPASS */
1300 #define WM5100_CP2_BYPASS_MASK                  0x0020  /* CP2_BYPASS */
1301 #define WM5100_CP2_BYPASS_SHIFT                      5  /* CP2_BYPASS */
1302 #define WM5100_CP2_BYPASS_WIDTH                      1  /* CP2_BYPASS */
1303 #define WM5100_CP2_ENA                          0x0001  /* CP2_ENA */
1304 #define WM5100_CP2_ENA_MASK                     0x0001  /* CP2_ENA */
1305 #define WM5100_CP2_ENA_SHIFT                         0  /* CP2_ENA */
1306 #define WM5100_CP2_ENA_WIDTH                         1  /* CP2_ENA */
1307 
1308 /*
1309  * R513 (0x201) - Mic Charge Pump 2
1310  */
1311 #define WM5100_LDO2_VSEL_MASK                   0xF800  /* LDO2_VSEL - [15:11] */
1312 #define WM5100_LDO2_VSEL_SHIFT                      11  /* LDO2_VSEL - [15:11] */
1313 #define WM5100_LDO2_VSEL_WIDTH                       5  /* LDO2_VSEL - [15:11] */
1314 
1315 /*
1316  * R514 (0x202) - HP Charge Pump 1
1317  */
1318 #define WM5100_CP1_ENA                          0x0001  /* CP1_ENA */
1319 #define WM5100_CP1_ENA_MASK                     0x0001  /* CP1_ENA */
1320 #define WM5100_CP1_ENA_SHIFT                         0  /* CP1_ENA */
1321 #define WM5100_CP1_ENA_WIDTH                         1  /* CP1_ENA */
1322 
1323 /*
1324  * R529 (0x211) - LDO1 Control
1325  */
1326 #define WM5100_LDO1_BYPASS                      0x0002  /* LDO1_BYPASS */
1327 #define WM5100_LDO1_BYPASS_MASK                 0x0002  /* LDO1_BYPASS */
1328 #define WM5100_LDO1_BYPASS_SHIFT                     1  /* LDO1_BYPASS */
1329 #define WM5100_LDO1_BYPASS_WIDTH                     1  /* LDO1_BYPASS */
1330 
1331 /*
1332  * R533 (0x215) - Mic Bias Ctrl 1
1333  */
1334 #define WM5100_MICB1_DISCH                      0x0040  /* MICB1_DISCH */
1335 #define WM5100_MICB1_DISCH_MASK                 0x0040  /* MICB1_DISCH */
1336 #define WM5100_MICB1_DISCH_SHIFT                     6  /* MICB1_DISCH */
1337 #define WM5100_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
1338 #define WM5100_MICB1_RATE                       0x0020  /* MICB1_RATE */
1339 #define WM5100_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
1340 #define WM5100_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
1341 #define WM5100_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
1342 #define WM5100_MICB1_LVL_MASK                   0x001C  /* MICB1_LVL - [4:2] */
1343 #define WM5100_MICB1_LVL_SHIFT                       2  /* MICB1_LVL - [4:2] */
1344 #define WM5100_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [4:2] */
1345 #define WM5100_MICB1_BYPASS                     0x0002  /* MICB1_BYPASS */
1346 #define WM5100_MICB1_BYPASS_MASK                0x0002  /* MICB1_BYPASS */
1347 #define WM5100_MICB1_BYPASS_SHIFT                    1  /* MICB1_BYPASS */
1348 #define WM5100_MICB1_BYPASS_WIDTH                    1  /* MICB1_BYPASS */
1349 #define WM5100_MICB1_ENA                        0x0001  /* MICB1_ENA */
1350 #define WM5100_MICB1_ENA_MASK                   0x0001  /* MICB1_ENA */
1351 #define WM5100_MICB1_ENA_SHIFT                       0  /* MICB1_ENA */
1352 #define WM5100_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
1353 
1354 /*
1355  * R534 (0x216) - Mic Bias Ctrl 2
1356  */
1357 #define WM5100_MICB2_DISCH                      0x0040  /* MICB2_DISCH */
1358 #define WM5100_MICB2_DISCH_MASK                 0x0040  /* MICB2_DISCH */
1359 #define WM5100_MICB2_DISCH_SHIFT                     6  /* MICB2_DISCH */
1360 #define WM5100_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
1361 #define WM5100_MICB2_RATE                       0x0020  /* MICB2_RATE */
1362 #define WM5100_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
1363 #define WM5100_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
1364 #define WM5100_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
1365 #define WM5100_MICB2_LVL_MASK                   0x001C  /* MICB2_LVL - [4:2] */
1366 #define WM5100_MICB2_LVL_SHIFT                       2  /* MICB2_LVL - [4:2] */
1367 #define WM5100_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [4:2] */
1368 #define WM5100_MICB2_BYPASS                     0x0002  /* MICB2_BYPASS */
1369 #define WM5100_MICB2_BYPASS_MASK                0x0002  /* MICB2_BYPASS */
1370 #define WM5100_MICB2_BYPASS_SHIFT                    1  /* MICB2_BYPASS */
1371 #define WM5100_MICB2_BYPASS_WIDTH                    1  /* MICB2_BYPASS */
1372 #define WM5100_MICB2_ENA                        0x0001  /* MICB2_ENA */
1373 #define WM5100_MICB2_ENA_MASK                   0x0001  /* MICB2_ENA */
1374 #define WM5100_MICB2_ENA_SHIFT                       0  /* MICB2_ENA */
1375 #define WM5100_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
1376 
1377 /*
1378  * R535 (0x217) - Mic Bias Ctrl 3
1379  */
1380 #define WM5100_MICB3_DISCH                      0x0040  /* MICB3_DISCH */
1381 #define WM5100_MICB3_DISCH_MASK                 0x0040  /* MICB3_DISCH */
1382 #define WM5100_MICB3_DISCH_SHIFT                     6  /* MICB3_DISCH */
1383 #define WM5100_MICB3_DISCH_WIDTH                     1  /* MICB3_DISCH */
1384 #define WM5100_MICB3_RATE                       0x0020  /* MICB3_RATE */
1385 #define WM5100_MICB3_RATE_MASK                  0x0020  /* MICB3_RATE */
1386 #define WM5100_MICB3_RATE_SHIFT                      5  /* MICB3_RATE */
1387 #define WM5100_MICB3_RATE_WIDTH                      1  /* MICB3_RATE */
1388 #define WM5100_MICB3_LVL_MASK                   0x001C  /* MICB3_LVL - [4:2] */
1389 #define WM5100_MICB3_LVL_SHIFT                       2  /* MICB3_LVL - [4:2] */
1390 #define WM5100_MICB3_LVL_WIDTH                       3  /* MICB3_LVL - [4:2] */
1391 #define WM5100_MICB3_BYPASS                     0x0002  /* MICB3_BYPASS */
1392 #define WM5100_MICB3_BYPASS_MASK                0x0002  /* MICB3_BYPASS */
1393 #define WM5100_MICB3_BYPASS_SHIFT                    1  /* MICB3_BYPASS */
1394 #define WM5100_MICB3_BYPASS_WIDTH                    1  /* MICB3_BYPASS */
1395 #define WM5100_MICB3_ENA                        0x0001  /* MICB3_ENA */
1396 #define WM5100_MICB3_ENA_MASK                   0x0001  /* MICB3_ENA */
1397 #define WM5100_MICB3_ENA_SHIFT                       0  /* MICB3_ENA */
1398 #define WM5100_MICB3_ENA_WIDTH                       1  /* MICB3_ENA */
1399 
1400 /*
1401  * R640 (0x280) - Accessory Detect Mode 1
1402  */
1403 #define WM5100_ACCDET_BIAS_SRC_MASK             0xC000  /* ACCDET_BIAS_SRC - [15:14] */
1404 #define WM5100_ACCDET_BIAS_SRC_SHIFT                14  /* ACCDET_BIAS_SRC - [15:14] */
1405 #define WM5100_ACCDET_BIAS_SRC_WIDTH                 2  /* ACCDET_BIAS_SRC - [15:14] */
1406 #define WM5100_ACCDET_SRC                       0x2000  /* ACCDET_SRC */
1407 #define WM5100_ACCDET_SRC_MASK                  0x2000  /* ACCDET_SRC */
1408 #define WM5100_ACCDET_SRC_SHIFT                     13  /* ACCDET_SRC */
1409 #define WM5100_ACCDET_SRC_WIDTH                      1  /* ACCDET_SRC */
1410 #define WM5100_ACCDET_MODE_MASK                 0x0003  /* ACCDET_MODE - [1:0] */
1411 #define WM5100_ACCDET_MODE_SHIFT                     0  /* ACCDET_MODE - [1:0] */
1412 #define WM5100_ACCDET_MODE_WIDTH                     2  /* ACCDET_MODE - [1:0] */
1413 
1414 /*
1415  * R648 (0x288) - Headphone Detect 1
1416  */
1417 #define WM5100_HP_HOLDTIME_MASK                 0x00E0  /* HP_HOLDTIME - [7:5] */
1418 #define WM5100_HP_HOLDTIME_SHIFT                     5  /* HP_HOLDTIME - [7:5] */
1419 #define WM5100_HP_HOLDTIME_WIDTH                     3  /* HP_HOLDTIME - [7:5] */
1420 #define WM5100_HP_CLK_DIV_MASK                  0x0018  /* HP_CLK_DIV - [4:3] */
1421 #define WM5100_HP_CLK_DIV_SHIFT                      3  /* HP_CLK_DIV - [4:3] */
1422 #define WM5100_HP_CLK_DIV_WIDTH                      2  /* HP_CLK_DIV - [4:3] */
1423 #define WM5100_HP_STEP_SIZE                     0x0002  /* HP_STEP_SIZE */
1424 #define WM5100_HP_STEP_SIZE_MASK                0x0002  /* HP_STEP_SIZE */
1425 #define WM5100_HP_STEP_SIZE_SHIFT                    1  /* HP_STEP_SIZE */
1426 #define WM5100_HP_STEP_SIZE_WIDTH                    1  /* HP_STEP_SIZE */
1427 #define WM5100_HP_POLL                          0x0001  /* HP_POLL */
1428 #define WM5100_HP_POLL_MASK                     0x0001  /* HP_POLL */
1429 #define WM5100_HP_POLL_SHIFT                         0  /* HP_POLL */
1430 #define WM5100_HP_POLL_WIDTH                         1  /* HP_POLL */
1431 
1432 /*
1433  * R649 (0x289) - Headphone Detect 2
1434  */
1435 #define WM5100_HP_DONE                          0x0080  /* HP_DONE */
1436 #define WM5100_HP_DONE_MASK                     0x0080  /* HP_DONE */
1437 #define WM5100_HP_DONE_SHIFT                         7  /* HP_DONE */
1438 #define WM5100_HP_DONE_WIDTH                         1  /* HP_DONE */
1439 #define WM5100_HP_LVL_MASK                      0x007F  /* HP_LVL - [6:0] */
1440 #define WM5100_HP_LVL_SHIFT                          0  /* HP_LVL - [6:0] */
1441 #define WM5100_HP_LVL_WIDTH                          7  /* HP_LVL - [6:0] */
1442 
1443 /*
1444  * R656 (0x290) - Mic Detect 1
1445  */
1446 #define WM5100_ACCDET_BIAS_STARTTIME_MASK       0xF000  /* ACCDET_BIAS_STARTTIME - [15:12] */
1447 #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT          12  /* ACCDET_BIAS_STARTTIME - [15:12] */
1448 #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH           4  /* ACCDET_BIAS_STARTTIME - [15:12] */
1449 #define WM5100_ACCDET_RATE_MASK                 0x0F00  /* ACCDET_RATE - [11:8] */
1450 #define WM5100_ACCDET_RATE_SHIFT                     8  /* ACCDET_RATE - [11:8] */
1451 #define WM5100_ACCDET_RATE_WIDTH                     4  /* ACCDET_RATE - [11:8] */
1452 #define WM5100_ACCDET_DBTIME                    0x0002  /* ACCDET_DBTIME */
1453 #define WM5100_ACCDET_DBTIME_MASK               0x0002  /* ACCDET_DBTIME */
1454 #define WM5100_ACCDET_DBTIME_SHIFT                   1  /* ACCDET_DBTIME */
1455 #define WM5100_ACCDET_DBTIME_WIDTH                   1  /* ACCDET_DBTIME */
1456 #define WM5100_ACCDET_ENA                       0x0001  /* ACCDET_ENA */
1457 #define WM5100_ACCDET_ENA_MASK                  0x0001  /* ACCDET_ENA */
1458 #define WM5100_ACCDET_ENA_SHIFT                      0  /* ACCDET_ENA */
1459 #define WM5100_ACCDET_ENA_WIDTH                      1  /* ACCDET_ENA */
1460 
1461 /*
1462  * R657 (0x291) - Mic Detect 2
1463  */
1464 #define WM5100_ACCDET_LVL_SEL_MASK              0x00FF  /* ACCDET_LVL_SEL - [7:0] */
1465 #define WM5100_ACCDET_LVL_SEL_SHIFT                  0  /* ACCDET_LVL_SEL - [7:0] */
1466 #define WM5100_ACCDET_LVL_SEL_WIDTH                  8  /* ACCDET_LVL_SEL - [7:0] */
1467 
1468 /*
1469  * R658 (0x292) - Mic Detect 3
1470  */
1471 #define WM5100_ACCDET_LVL_MASK                  0x07FC  /* ACCDET_LVL - [10:2] */
1472 #define WM5100_ACCDET_LVL_SHIFT                      2  /* ACCDET_LVL - [10:2] */
1473 #define WM5100_ACCDET_LVL_WIDTH                      9  /* ACCDET_LVL - [10:2] */
1474 #define WM5100_ACCDET_VALID                     0x0002  /* ACCDET_VALID */
1475 #define WM5100_ACCDET_VALID_MASK                0x0002  /* ACCDET_VALID */
1476 #define WM5100_ACCDET_VALID_SHIFT                    1  /* ACCDET_VALID */
1477 #define WM5100_ACCDET_VALID_WIDTH                    1  /* ACCDET_VALID */
1478 #define WM5100_ACCDET_STS                       0x0001  /* ACCDET_STS */
1479 #define WM5100_ACCDET_STS_MASK                  0x0001  /* ACCDET_STS */
1480 #define WM5100_ACCDET_STS_SHIFT                      0  /* ACCDET_STS */
1481 #define WM5100_ACCDET_STS_WIDTH                      1  /* ACCDET_STS */
1482 
1483 /*
1484  * R699 (0x2BB) - Misc Control
1485  */
1486 #define WM5100_HPCOM_SRC                         0x200  /* HPCOM_SRC */
1487 #define WM5100_HPCOM_SRC_SHIFT                       9  /* HPCOM_SRC */
1488 
1489 /*
1490  * R769 (0x301) - Input Enables
1491  */
1492 #define WM5100_IN4L_ENA                         0x0080  /* IN4L_ENA */
1493 #define WM5100_IN4L_ENA_MASK                    0x0080  /* IN4L_ENA */
1494 #define WM5100_IN4L_ENA_SHIFT                        7  /* IN4L_ENA */
1495 #define WM5100_IN4L_ENA_WIDTH                        1  /* IN4L_ENA */
1496 #define WM5100_IN4R_ENA                         0x0040  /* IN4R_ENA */
1497 #define WM5100_IN4R_ENA_MASK                    0x0040  /* IN4R_ENA */
1498 #define WM5100_IN4R_ENA_SHIFT                        6  /* IN4R_ENA */
1499 #define WM5100_IN4R_ENA_WIDTH                        1  /* IN4R_ENA */
1500 #define WM5100_IN3L_ENA                         0x0020  /* IN3L_ENA */
1501 #define WM5100_IN3L_ENA_MASK                    0x0020  /* IN3L_ENA */
1502 #define WM5100_IN3L_ENA_SHIFT                        5  /* IN3L_ENA */
1503 #define WM5100_IN3L_ENA_WIDTH                        1  /* IN3L_ENA */
1504 #define WM5100_IN3R_ENA                         0x0010  /* IN3R_ENA */
1505 #define WM5100_IN3R_ENA_MASK                    0x0010  /* IN3R_ENA */
1506 #define WM5100_IN3R_ENA_SHIFT                        4  /* IN3R_ENA */
1507 #define WM5100_IN3R_ENA_WIDTH                        1  /* IN3R_ENA */
1508 #define WM5100_IN2L_ENA                         0x0008  /* IN2L_ENA */
1509 #define WM5100_IN2L_ENA_MASK                    0x0008  /* IN2L_ENA */
1510 #define WM5100_IN2L_ENA_SHIFT                        3  /* IN2L_ENA */
1511 #define WM5100_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
1512 #define WM5100_IN2R_ENA                         0x0004  /* IN2R_ENA */
1513 #define WM5100_IN2R_ENA_MASK                    0x0004  /* IN2R_ENA */
1514 #define WM5100_IN2R_ENA_SHIFT                        2  /* IN2R_ENA */
1515 #define WM5100_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
1516 #define WM5100_IN1L_ENA                         0x0002  /* IN1L_ENA */
1517 #define WM5100_IN1L_ENA_MASK                    0x0002  /* IN1L_ENA */
1518 #define WM5100_IN1L_ENA_SHIFT                        1  /* IN1L_ENA */
1519 #define WM5100_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
1520 #define WM5100_IN1R_ENA                         0x0001  /* IN1R_ENA */
1521 #define WM5100_IN1R_ENA_MASK                    0x0001  /* IN1R_ENA */
1522 #define WM5100_IN1R_ENA_SHIFT                        0  /* IN1R_ENA */
1523 #define WM5100_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
1524 
1525 /*
1526  * R770 (0x302) - Input Enables Status
1527  */
1528 #define WM5100_IN4L_ENA_STS                     0x0080  /* IN4L_ENA_STS */
1529 #define WM5100_IN4L_ENA_STS_MASK                0x0080  /* IN4L_ENA_STS */
1530 #define WM5100_IN4L_ENA_STS_SHIFT                    7  /* IN4L_ENA_STS */
1531 #define WM5100_IN4L_ENA_STS_WIDTH                    1  /* IN4L_ENA_STS */
1532 #define WM5100_IN4R_ENA_STS                     0x0040  /* IN4R_ENA_STS */
1533 #define WM5100_IN4R_ENA_STS_MASK                0x0040  /* IN4R_ENA_STS */
1534 #define WM5100_IN4R_ENA_STS_SHIFT                    6  /* IN4R_ENA_STS */
1535 #define WM5100_IN4R_ENA_STS_WIDTH                    1  /* IN4R_ENA_STS */
1536 #define WM5100_IN3L_ENA_STS                     0x0020  /* IN3L_ENA_STS */
1537 #define WM5100_IN3L_ENA_STS_MASK                0x0020  /* IN3L_ENA_STS */
1538 #define WM5100_IN3L_ENA_STS_SHIFT                    5  /* IN3L_ENA_STS */
1539 #define WM5100_IN3L_ENA_STS_WIDTH                    1  /* IN3L_ENA_STS */
1540 #define WM5100_IN3R_ENA_STS                     0x0010  /* IN3R_ENA_STS */
1541 #define WM5100_IN3R_ENA_STS_MASK                0x0010  /* IN3R_ENA_STS */
1542 #define WM5100_IN3R_ENA_STS_SHIFT                    4  /* IN3R_ENA_STS */
1543 #define WM5100_IN3R_ENA_STS_WIDTH                    1  /* IN3R_ENA_STS */
1544 #define WM5100_IN2L_ENA_STS                     0x0008  /* IN2L_ENA_STS */
1545 #define WM5100_IN2L_ENA_STS_MASK                0x0008  /* IN2L_ENA_STS */
1546 #define WM5100_IN2L_ENA_STS_SHIFT                    3  /* IN2L_ENA_STS */
1547 #define WM5100_IN2L_ENA_STS_WIDTH                    1  /* IN2L_ENA_STS */
1548 #define WM5100_IN2R_ENA_STS                     0x0004  /* IN2R_ENA_STS */
1549 #define WM5100_IN2R_ENA_STS_MASK                0x0004  /* IN2R_ENA_STS */
1550 #define WM5100_IN2R_ENA_STS_SHIFT                    2  /* IN2R_ENA_STS */
1551 #define WM5100_IN2R_ENA_STS_WIDTH                    1  /* IN2R_ENA_STS */
1552 #define WM5100_IN1L_ENA_STS                     0x0002  /* IN1L_ENA_STS */
1553 #define WM5100_IN1L_ENA_STS_MASK                0x0002  /* IN1L_ENA_STS */
1554 #define WM5100_IN1L_ENA_STS_SHIFT                    1  /* IN1L_ENA_STS */
1555 #define WM5100_IN1L_ENA_STS_WIDTH                    1  /* IN1L_ENA_STS */
1556 #define WM5100_IN1R_ENA_STS                     0x0001  /* IN1R_ENA_STS */
1557 #define WM5100_IN1R_ENA_STS_MASK                0x0001  /* IN1R_ENA_STS */
1558 #define WM5100_IN1R_ENA_STS_SHIFT                    0  /* IN1R_ENA_STS */
1559 #define WM5100_IN1R_ENA_STS_WIDTH                    1  /* IN1R_ENA_STS */
1560 
1561 /*
1562  * R784 (0x310) - IN1L Control
1563  */
1564 #define WM5100_IN_RATE_MASK                     0xC000  /* IN_RATE - [15:14] */
1565 #define WM5100_IN_RATE_SHIFT                        14  /* IN_RATE - [15:14] */
1566 #define WM5100_IN_RATE_WIDTH                         2  /* IN_RATE - [15:14] */
1567 #define WM5100_IN1_OSR                          0x2000  /* IN1_OSR */
1568 #define WM5100_IN1_OSR_MASK                     0x2000  /* IN1_OSR */
1569 #define WM5100_IN1_OSR_SHIFT                        13  /* IN1_OSR */
1570 #define WM5100_IN1_OSR_WIDTH                         1  /* IN1_OSR */
1571 #define WM5100_IN1_DMIC_SUP_MASK                0x1800  /* IN1_DMIC_SUP - [12:11] */
1572 #define WM5100_IN1_DMIC_SUP_SHIFT                   11  /* IN1_DMIC_SUP - [12:11] */
1573 #define WM5100_IN1_DMIC_SUP_WIDTH                    2  /* IN1_DMIC_SUP - [12:11] */
1574 #define WM5100_IN1_MODE_MASK                    0x0600  /* IN1_MODE - [10:9] */
1575 #define WM5100_IN1_MODE_SHIFT                        9  /* IN1_MODE - [10:9] */
1576 #define WM5100_IN1_MODE_WIDTH                        2  /* IN1_MODE - [10:9] */
1577 #define WM5100_IN1L_PGA_VOL_MASK                0x00FE  /* IN1L_PGA_VOL - [7:1] */
1578 #define WM5100_IN1L_PGA_VOL_SHIFT                    1  /* IN1L_PGA_VOL - [7:1] */
1579 #define WM5100_IN1L_PGA_VOL_WIDTH                    7  /* IN1L_PGA_VOL - [7:1] */
1580 
1581 /*
1582  * R785 (0x311) - IN1R Control
1583  */
1584 #define WM5100_IN1R_PGA_VOL_MASK                0x00FE  /* IN1R_PGA_VOL - [7:1] */
1585 #define WM5100_IN1R_PGA_VOL_SHIFT                    1  /* IN1R_PGA_VOL - [7:1] */
1586 #define WM5100_IN1R_PGA_VOL_WIDTH                    7  /* IN1R_PGA_VOL - [7:1] */
1587 
1588 /*
1589  * R786 (0x312) - IN2L Control
1590  */
1591 #define WM5100_IN2_OSR                          0x2000  /* IN2_OSR */
1592 #define WM5100_IN2_OSR_MASK                     0x2000  /* IN2_OSR */
1593 #define WM5100_IN2_OSR_SHIFT                        13  /* IN2_OSR */
1594 #define WM5100_IN2_OSR_WIDTH                         1  /* IN2_OSR */
1595 #define WM5100_IN2_DMIC_SUP_MASK                0x1800  /* IN2_DMIC_SUP - [12:11] */
1596 #define WM5100_IN2_DMIC_SUP_SHIFT                   11  /* IN2_DMIC_SUP - [12:11] */
1597 #define WM5100_IN2_DMIC_SUP_WIDTH                    2  /* IN2_DMIC_SUP - [12:11] */
1598 #define WM5100_IN2_MODE_MASK                    0x0600  /* IN2_MODE - [10:9] */
1599 #define WM5100_IN2_MODE_SHIFT                        9  /* IN2_MODE - [10:9] */
1600 #define WM5100_IN2_MODE_WIDTH                        2  /* IN2_MODE - [10:9] */
1601 #define WM5100_IN2L_PGA_VOL_MASK                0x00FE  /* IN2L_PGA_VOL - [7:1] */
1602 #define WM5100_IN2L_PGA_VOL_SHIFT                    1  /* IN2L_PGA_VOL - [7:1] */
1603 #define WM5100_IN2L_PGA_VOL_WIDTH                    7  /* IN2L_PGA_VOL - [7:1] */
1604 
1605 /*
1606  * R787 (0x313) - IN2R Control
1607  */
1608 #define WM5100_IN2R_PGA_VOL_MASK                0x00FE  /* IN2R_PGA_VOL - [7:1] */
1609 #define WM5100_IN2R_PGA_VOL_SHIFT                    1  /* IN2R_PGA_VOL - [7:1] */
1610 #define WM5100_IN2R_PGA_VOL_WIDTH                    7  /* IN2R_PGA_VOL - [7:1] */
1611 
1612 /*
1613  * R788 (0x314) - IN3L Control
1614  */
1615 #define WM5100_IN3_OSR                          0x2000  /* IN3_OSR */
1616 #define WM5100_IN3_OSR_MASK                     0x2000  /* IN3_OSR */
1617 #define WM5100_IN3_OSR_SHIFT                        13  /* IN3_OSR */
1618 #define WM5100_IN3_OSR_WIDTH                         1  /* IN3_OSR */
1619 #define WM5100_IN3_DMIC_SUP_MASK                0x1800  /* IN3_DMIC_SUP - [12:11] */
1620 #define WM5100_IN3_DMIC_SUP_SHIFT                   11  /* IN3_DMIC_SUP - [12:11] */
1621 #define WM5100_IN3_DMIC_SUP_WIDTH                    2  /* IN3_DMIC_SUP - [12:11] */
1622 #define WM5100_IN3_MODE_MASK                    0x0600  /* IN3_MODE - [10:9] */
1623 #define WM5100_IN3_MODE_SHIFT                        9  /* IN3_MODE - [10:9] */
1624 #define WM5100_IN3_MODE_WIDTH                        2  /* IN3_MODE - [10:9] */
1625 #define WM5100_IN3L_PGA_VOL_MASK                0x00FE  /* IN3L_PGA_VOL - [7:1] */
1626 #define WM5100_IN3L_PGA_VOL_SHIFT                    1  /* IN3L_PGA_VOL - [7:1] */
1627 #define WM5100_IN3L_PGA_VOL_WIDTH                    7  /* IN3L_PGA_VOL - [7:1] */
1628 
1629 /*
1630  * R789 (0x315) - IN3R Control
1631  */
1632 #define WM5100_IN3R_PGA_VOL_MASK                0x00FE  /* IN3R_PGA_VOL - [7:1] */
1633 #define WM5100_IN3R_PGA_VOL_SHIFT                    1  /* IN3R_PGA_VOL - [7:1] */
1634 #define WM5100_IN3R_PGA_VOL_WIDTH                    7  /* IN3R_PGA_VOL - [7:1] */
1635 
1636 /*
1637  * R790 (0x316) - IN4L Control
1638  */
1639 #define WM5100_IN4_OSR                          0x2000  /* IN4_OSR */
1640 #define WM5100_IN4_OSR_MASK                     0x2000  /* IN4_OSR */
1641 #define WM5100_IN4_OSR_SHIFT                        13  /* IN4_OSR */
1642 #define WM5100_IN4_OSR_WIDTH                         1  /* IN4_OSR */
1643 #define WM5100_IN4_DMIC_SUP_MASK                0x1800  /* IN4_DMIC_SUP - [12:11] */
1644 #define WM5100_IN4_DMIC_SUP_SHIFT                   11  /* IN4_DMIC_SUP - [12:11] */
1645 #define WM5100_IN4_DMIC_SUP_WIDTH                    2  /* IN4_DMIC_SUP - [12:11] */
1646 #define WM5100_IN4_MODE_MASK                    0x0600  /* IN4_MODE - [10:9] */
1647 #define WM5100_IN4_MODE_SHIFT                        9  /* IN4_MODE - [10:9] */
1648 #define WM5100_IN4_MODE_WIDTH                        2  /* IN4_MODE - [10:9] */
1649 #define WM5100_IN4L_PGA_VOL_MASK                0x00FE  /* IN4L_PGA_VOL - [7:1] */
1650 #define WM5100_IN4L_PGA_VOL_SHIFT                    1  /* IN4L_PGA_VOL - [7:1] */
1651 #define WM5100_IN4L_PGA_VOL_WIDTH                    7  /* IN4L_PGA_VOL - [7:1] */
1652 
1653 /*
1654  * R791 (0x317) - IN4R Control
1655  */
1656 #define WM5100_IN4R_PGA_VOL_MASK                0x00FE  /* IN4R_PGA_VOL - [7:1] */
1657 #define WM5100_IN4R_PGA_VOL_SHIFT                    1  /* IN4R_PGA_VOL - [7:1] */
1658 #define WM5100_IN4R_PGA_VOL_WIDTH                    7  /* IN4R_PGA_VOL - [7:1] */
1659 
1660 /*
1661  * R792 (0x318) - RXANC_SRC
1662  */
1663 #define WM5100_IN_RXANC_SEL_MASK                0x0007  /* IN_RXANC_SEL - [2:0] */
1664 #define WM5100_IN_RXANC_SEL_SHIFT                    0  /* IN_RXANC_SEL - [2:0] */
1665 #define WM5100_IN_RXANC_SEL_WIDTH                    3  /* IN_RXANC_SEL - [2:0] */
1666 
1667 /*
1668  * R793 (0x319) - Input Volume Ramp
1669  */
1670 #define WM5100_IN_VD_RAMP_MASK                  0x0070  /* IN_VD_RAMP - [6:4] */
1671 #define WM5100_IN_VD_RAMP_SHIFT                      4  /* IN_VD_RAMP - [6:4] */
1672 #define WM5100_IN_VD_RAMP_WIDTH                      3  /* IN_VD_RAMP - [6:4] */
1673 #define WM5100_IN_VI_RAMP_MASK                  0x0007  /* IN_VI_RAMP - [2:0] */
1674 #define WM5100_IN_VI_RAMP_SHIFT                      0  /* IN_VI_RAMP - [2:0] */
1675 #define WM5100_IN_VI_RAMP_WIDTH                      3  /* IN_VI_RAMP - [2:0] */
1676 
1677 /*
1678  * R800 (0x320) - ADC Digital Volume 1L
1679  */
1680 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1681 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1682 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1683 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1684 #define WM5100_IN1L_MUTE                        0x0100  /* IN1L_MUTE */
1685 #define WM5100_IN1L_MUTE_MASK                   0x0100  /* IN1L_MUTE */
1686 #define WM5100_IN1L_MUTE_SHIFT                       8  /* IN1L_MUTE */
1687 #define WM5100_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
1688 #define WM5100_IN1L_VOL_MASK                    0x00FF  /* IN1L_VOL - [7:0] */
1689 #define WM5100_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [7:0] */
1690 #define WM5100_IN1L_VOL_WIDTH                        8  /* IN1L_VOL - [7:0] */
1691 
1692 /*
1693  * R801 (0x321) - ADC Digital Volume 1R
1694  */
1695 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1696 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1697 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1698 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1699 #define WM5100_IN1R_MUTE                        0x0100  /* IN1R_MUTE */
1700 #define WM5100_IN1R_MUTE_MASK                   0x0100  /* IN1R_MUTE */
1701 #define WM5100_IN1R_MUTE_SHIFT                       8  /* IN1R_MUTE */
1702 #define WM5100_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
1703 #define WM5100_IN1R_VOL_MASK                    0x00FF  /* IN1R_VOL - [7:0] */
1704 #define WM5100_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [7:0] */
1705 #define WM5100_IN1R_VOL_WIDTH                        8  /* IN1R_VOL - [7:0] */
1706 
1707 /*
1708  * R802 (0x322) - ADC Digital Volume 2L
1709  */
1710 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1711 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1712 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1713 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1714 #define WM5100_IN2L_MUTE                        0x0100  /* IN2L_MUTE */
1715 #define WM5100_IN2L_MUTE_MASK                   0x0100  /* IN2L_MUTE */
1716 #define WM5100_IN2L_MUTE_SHIFT                       8  /* IN2L_MUTE */
1717 #define WM5100_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
1718 #define WM5100_IN2L_VOL_MASK                    0x00FF  /* IN2L_VOL - [7:0] */
1719 #define WM5100_IN2L_VOL_SHIFT                        0  /* IN2L_VOL - [7:0] */
1720 #define WM5100_IN2L_VOL_WIDTH                        8  /* IN2L_VOL - [7:0] */
1721 
1722 /*
1723  * R803 (0x323) - ADC Digital Volume 2R
1724  */
1725 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1726 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1727 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1728 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1729 #define WM5100_IN2R_MUTE                        0x0100  /* IN2R_MUTE */
1730 #define WM5100_IN2R_MUTE_MASK                   0x0100  /* IN2R_MUTE */
1731 #define WM5100_IN2R_MUTE_SHIFT                       8  /* IN2R_MUTE */
1732 #define WM5100_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
1733 #define WM5100_IN2R_VOL_MASK                    0x00FF  /* IN2R_VOL - [7:0] */
1734 #define WM5100_IN2R_VOL_SHIFT                        0  /* IN2R_VOL - [7:0] */
1735 #define WM5100_IN2R_VOL_WIDTH                        8  /* IN2R_VOL - [7:0] */
1736 
1737 /*
1738  * R804 (0x324) - ADC Digital Volume 3L
1739  */
1740 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1741 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1742 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1743 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1744 #define WM5100_IN3L_MUTE                        0x0100  /* IN3L_MUTE */
1745 #define WM5100_IN3L_MUTE_MASK                   0x0100  /* IN3L_MUTE */
1746 #define WM5100_IN3L_MUTE_SHIFT                       8  /* IN3L_MUTE */
1747 #define WM5100_IN3L_MUTE_WIDTH                       1  /* IN3L_MUTE */
1748 #define WM5100_IN3L_VOL_MASK                    0x00FF  /* IN3L_VOL - [7:0] */
1749 #define WM5100_IN3L_VOL_SHIFT                        0  /* IN3L_VOL - [7:0] */
1750 #define WM5100_IN3L_VOL_WIDTH                        8  /* IN3L_VOL - [7:0] */
1751 
1752 /*
1753  * R805 (0x325) - ADC Digital Volume 3R
1754  */
1755 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1756 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1757 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1758 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1759 #define WM5100_IN3R_MUTE                        0x0100  /* IN3R_MUTE */
1760 #define WM5100_IN3R_MUTE_MASK                   0x0100  /* IN3R_MUTE */
1761 #define WM5100_IN3R_MUTE_SHIFT                       8  /* IN3R_MUTE */
1762 #define WM5100_IN3R_MUTE_WIDTH                       1  /* IN3R_MUTE */
1763 #define WM5100_IN3R_VOL_MASK                    0x00FF  /* IN3R_VOL - [7:0] */
1764 #define WM5100_IN3R_VOL_SHIFT                        0  /* IN3R_VOL - [7:0] */
1765 #define WM5100_IN3R_VOL_WIDTH                        8  /* IN3R_VOL - [7:0] */
1766 
1767 /*
1768  * R806 (0x326) - ADC Digital Volume 4L
1769  */
1770 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1771 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1772 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1773 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1774 #define WM5100_IN4L_MUTE                        0x0100  /* IN4L_MUTE */
1775 #define WM5100_IN4L_MUTE_MASK                   0x0100  /* IN4L_MUTE */
1776 #define WM5100_IN4L_MUTE_SHIFT                       8  /* IN4L_MUTE */
1777 #define WM5100_IN4L_MUTE_WIDTH                       1  /* IN4L_MUTE */
1778 #define WM5100_IN4L_VOL_MASK                    0x00FF  /* IN4L_VOL - [7:0] */
1779 #define WM5100_IN4L_VOL_SHIFT                        0  /* IN4L_VOL - [7:0] */
1780 #define WM5100_IN4L_VOL_WIDTH                        8  /* IN4L_VOL - [7:0] */
1781 
1782 /*
1783  * R807 (0x327) - ADC Digital Volume 4R
1784  */
1785 #define WM5100_IN_VU                            0x0200  /* IN_VU */
1786 #define WM5100_IN_VU_MASK                       0x0200  /* IN_VU */
1787 #define WM5100_IN_VU_SHIFT                           9  /* IN_VU */
1788 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1789 #define WM5100_IN4R_MUTE                        0x0100  /* IN4R_MUTE */
1790 #define WM5100_IN4R_MUTE_MASK                   0x0100  /* IN4R_MUTE */
1791 #define WM5100_IN4R_MUTE_SHIFT                       8  /* IN4R_MUTE */
1792 #define WM5100_IN4R_MUTE_WIDTH                       1  /* IN4R_MUTE */
1793 #define WM5100_IN4R_VOL_MASK                    0x00FF  /* IN4R_VOL - [7:0] */
1794 #define WM5100_IN4R_VOL_SHIFT                        0  /* IN4R_VOL - [7:0] */
1795 #define WM5100_IN4R_VOL_WIDTH                        8  /* IN4R_VOL - [7:0] */
1796 
1797 /*
1798  * R1025 (0x401) - Output Enables 2
1799  */
1800 #define WM5100_OUT6L_ENA                        0x0800  /* OUT6L_ENA */
1801 #define WM5100_OUT6L_ENA_MASK                   0x0800  /* OUT6L_ENA */
1802 #define WM5100_OUT6L_ENA_SHIFT                      11  /* OUT6L_ENA */
1803 #define WM5100_OUT6L_ENA_WIDTH                       1  /* OUT6L_ENA */
1804 #define WM5100_OUT6R_ENA                        0x0400  /* OUT6R_ENA */
1805 #define WM5100_OUT6R_ENA_MASK                   0x0400  /* OUT6R_ENA */
1806 #define WM5100_OUT6R_ENA_SHIFT                      10  /* OUT6R_ENA */
1807 #define WM5100_OUT6R_ENA_WIDTH                       1  /* OUT6R_ENA */
1808 #define WM5100_OUT5L_ENA                        0x0200  /* OUT5L_ENA */
1809 #define WM5100_OUT5L_ENA_MASK                   0x0200  /* OUT5L_ENA */
1810 #define WM5100_OUT5L_ENA_SHIFT                       9  /* OUT5L_ENA */
1811 #define WM5100_OUT5L_ENA_WIDTH                       1  /* OUT5L_ENA */
1812 #define WM5100_OUT5R_ENA                        0x0100  /* OUT5R_ENA */
1813 #define WM5100_OUT5R_ENA_MASK                   0x0100  /* OUT5R_ENA */
1814 #define WM5100_OUT5R_ENA_SHIFT                       8  /* OUT5R_ENA */
1815 #define WM5100_OUT5R_ENA_WIDTH                       1  /* OUT5R_ENA */
1816 #define WM5100_OUT4L_ENA                        0x0080  /* OUT4L_ENA */
1817 #define WM5100_OUT4L_ENA_MASK                   0x0080  /* OUT4L_ENA */
1818 #define WM5100_OUT4L_ENA_SHIFT                       7  /* OUT4L_ENA */
1819 #define WM5100_OUT4L_ENA_WIDTH                       1  /* OUT4L_ENA */
1820 #define WM5100_OUT4R_ENA                        0x0040  /* OUT4R_ENA */
1821 #define WM5100_OUT4R_ENA_MASK                   0x0040  /* OUT4R_ENA */
1822 #define WM5100_OUT4R_ENA_SHIFT                       6  /* OUT4R_ENA */
1823 #define WM5100_OUT4R_ENA_WIDTH                       1  /* OUT4R_ENA */
1824 
1825 /*
1826  * R1026 (0x402) - Output Status 1
1827  */
1828 #define WM5100_OUT3L_ENA_STS                    0x0020  /* OUT3L_ENA_STS */
1829 #define WM5100_OUT3L_ENA_STS_MASK               0x0020  /* OUT3L_ENA_STS */
1830 #define WM5100_OUT3L_ENA_STS_SHIFT                   5  /* OUT3L_ENA_STS */
1831 #define WM5100_OUT3L_ENA_STS_WIDTH                   1  /* OUT3L_ENA_STS */
1832 #define WM5100_OUT3R_ENA_STS                    0x0010  /* OUT3R_ENA_STS */
1833 #define WM5100_OUT3R_ENA_STS_MASK               0x0010  /* OUT3R_ENA_STS */
1834 #define WM5100_OUT3R_ENA_STS_SHIFT                   4  /* OUT3R_ENA_STS */
1835 #define WM5100_OUT3R_ENA_STS_WIDTH                   1  /* OUT3R_ENA_STS */
1836 #define WM5100_OUT2L_ENA_STS                    0x0008  /* OUT2L_ENA_STS */
1837 #define WM5100_OUT2L_ENA_STS_MASK               0x0008  /* OUT2L_ENA_STS */
1838 #define WM5100_OUT2L_ENA_STS_SHIFT                   3  /* OUT2L_ENA_STS */
1839 #define WM5100_OUT2L_ENA_STS_WIDTH                   1  /* OUT2L_ENA_STS */
1840 #define WM5100_OUT2R_ENA_STS                    0x0004  /* OUT2R_ENA_STS */
1841 #define WM5100_OUT2R_ENA_STS_MASK               0x0004  /* OUT2R_ENA_STS */
1842 #define WM5100_OUT2R_ENA_STS_SHIFT                   2  /* OUT2R_ENA_STS */
1843 #define WM5100_OUT2R_ENA_STS_WIDTH                   1  /* OUT2R_ENA_STS */
1844 #define WM5100_OUT1L_ENA_STS                    0x0002  /* OUT1L_ENA_STS */
1845 #define WM5100_OUT1L_ENA_STS_MASK               0x0002  /* OUT1L_ENA_STS */
1846 #define WM5100_OUT1L_ENA_STS_SHIFT                   1  /* OUT1L_ENA_STS */
1847 #define WM5100_OUT1L_ENA_STS_WIDTH                   1  /* OUT1L_ENA_STS */
1848 #define WM5100_OUT1R_ENA_STS                    0x0001  /* OUT1R_ENA_STS */
1849 #define WM5100_OUT1R_ENA_STS_MASK               0x0001  /* OUT1R_ENA_STS */
1850 #define WM5100_OUT1R_ENA_STS_SHIFT                   0  /* OUT1R_ENA_STS */
1851 #define WM5100_OUT1R_ENA_STS_WIDTH                   1  /* OUT1R_ENA_STS */
1852 
1853 /*
1854  * R1027 (0x403) - Output Status 2
1855  */
1856 #define WM5100_OUT6L_ENA_STS                    0x0800  /* OUT6L_ENA_STS */
1857 #define WM5100_OUT6L_ENA_STS_MASK               0x0800  /* OUT6L_ENA_STS */
1858 #define WM5100_OUT6L_ENA_STS_SHIFT                  11  /* OUT6L_ENA_STS */
1859 #define WM5100_OUT6L_ENA_STS_WIDTH                   1  /* OUT6L_ENA_STS */
1860 #define WM5100_OUT6R_ENA_STS                    0x0400  /* OUT6R_ENA_STS */
1861 #define WM5100_OUT6R_ENA_STS_MASK               0x0400  /* OUT6R_ENA_STS */
1862 #define WM5100_OUT6R_ENA_STS_SHIFT                  10  /* OUT6R_ENA_STS */
1863 #define WM5100_OUT6R_ENA_STS_WIDTH                   1  /* OUT6R_ENA_STS */
1864 #define WM5100_OUT5L_ENA_STS                    0x0200  /* OUT5L_ENA_STS */
1865 #define WM5100_OUT5L_ENA_STS_MASK               0x0200  /* OUT5L_ENA_STS */
1866 #define WM5100_OUT5L_ENA_STS_SHIFT                   9  /* OUT5L_ENA_STS */
1867 #define WM5100_OUT5L_ENA_STS_WIDTH                   1  /* OUT5L_ENA_STS */
1868 #define WM5100_OUT5R_ENA_STS                    0x0100  /* OUT5R_ENA_STS */
1869 #define WM5100_OUT5R_ENA_STS_MASK               0x0100  /* OUT5R_ENA_STS */
1870 #define WM5100_OUT5R_ENA_STS_SHIFT                   8  /* OUT5R_ENA_STS */
1871 #define WM5100_OUT5R_ENA_STS_WIDTH                   1  /* OUT5R_ENA_STS */
1872 #define WM5100_OUT4L_ENA_STS                    0x0080  /* OUT4L_ENA_STS */
1873 #define WM5100_OUT4L_ENA_STS_MASK               0x0080  /* OUT4L_ENA_STS */
1874 #define WM5100_OUT4L_ENA_STS_SHIFT                   7  /* OUT4L_ENA_STS */
1875 #define WM5100_OUT4L_ENA_STS_WIDTH                   1  /* OUT4L_ENA_STS */
1876 #define WM5100_OUT4R_ENA_STS                    0x0040  /* OUT4R_ENA_STS */
1877 #define WM5100_OUT4R_ENA_STS_MASK               0x0040  /* OUT4R_ENA_STS */
1878 #define WM5100_OUT4R_ENA_STS_SHIFT                   6  /* OUT4R_ENA_STS */
1879 #define WM5100_OUT4R_ENA_STS_WIDTH                   1  /* OUT4R_ENA_STS */
1880 
1881 /*
1882  * R1032 (0x408) - Channel Enables 1
1883  */
1884 #define WM5100_HP3L_ENA                         0x0020  /* HP3L_ENA */
1885 #define WM5100_HP3L_ENA_MASK                    0x0020  /* HP3L_ENA */
1886 #define WM5100_HP3L_ENA_SHIFT                        5  /* HP3L_ENA */
1887 #define WM5100_HP3L_ENA_WIDTH                        1  /* HP3L_ENA */
1888 #define WM5100_HP3R_ENA                         0x0010  /* HP3R_ENA */
1889 #define WM5100_HP3R_ENA_MASK                    0x0010  /* HP3R_ENA */
1890 #define WM5100_HP3R_ENA_SHIFT                        4  /* HP3R_ENA */
1891 #define WM5100_HP3R_ENA_WIDTH                        1  /* HP3R_ENA */
1892 #define WM5100_HP2L_ENA                         0x0008  /* HP2L_ENA */
1893 #define WM5100_HP2L_ENA_MASK                    0x0008  /* HP2L_ENA */
1894 #define WM5100_HP2L_ENA_SHIFT                        3  /* HP2L_ENA */
1895 #define WM5100_HP2L_ENA_WIDTH                        1  /* HP2L_ENA */
1896 #define WM5100_HP2R_ENA                         0x0004  /* HP2R_ENA */
1897 #define WM5100_HP2R_ENA_MASK                    0x0004  /* HP2R_ENA */
1898 #define WM5100_HP2R_ENA_SHIFT                        2  /* HP2R_ENA */
1899 #define WM5100_HP2R_ENA_WIDTH                        1  /* HP2R_ENA */
1900 #define WM5100_HP1L_ENA                         0x0002  /* HP1L_ENA */
1901 #define WM5100_HP1L_ENA_MASK                    0x0002  /* HP1L_ENA */
1902 #define WM5100_HP1L_ENA_SHIFT                        1  /* HP1L_ENA */
1903 #define WM5100_HP1L_ENA_WIDTH                        1  /* HP1L_ENA */
1904 #define WM5100_HP1R_ENA                         0x0001  /* HP1R_ENA */
1905 #define WM5100_HP1R_ENA_MASK                    0x0001  /* HP1R_ENA */
1906 #define WM5100_HP1R_ENA_SHIFT                        0  /* HP1R_ENA */
1907 #define WM5100_HP1R_ENA_WIDTH                        1  /* HP1R_ENA */
1908 
1909 /*
1910  * R1040 (0x410) - Out Volume 1L
1911  */
1912 #define WM5100_OUT_RATE_MASK                    0xC000  /* OUT_RATE - [15:14] */
1913 #define WM5100_OUT_RATE_SHIFT                       14  /* OUT_RATE - [15:14] */
1914 #define WM5100_OUT_RATE_WIDTH                        2  /* OUT_RATE - [15:14] */
1915 #define WM5100_OUT1_OSR                         0x2000  /* OUT1_OSR */
1916 #define WM5100_OUT1_OSR_MASK                    0x2000  /* OUT1_OSR */
1917 #define WM5100_OUT1_OSR_SHIFT                       13  /* OUT1_OSR */
1918 #define WM5100_OUT1_OSR_WIDTH                        1  /* OUT1_OSR */
1919 #define WM5100_OUT1_MONO                        0x1000  /* OUT1_MONO */
1920 #define WM5100_OUT1_MONO_MASK                   0x1000  /* OUT1_MONO */
1921 #define WM5100_OUT1_MONO_SHIFT                      12  /* OUT1_MONO */
1922 #define WM5100_OUT1_MONO_WIDTH                       1  /* OUT1_MONO */
1923 #define WM5100_OUT1L_ANC_SRC                    0x0800  /* OUT1L_ANC_SRC */
1924 #define WM5100_OUT1L_ANC_SRC_MASK               0x0800  /* OUT1L_ANC_SRC */
1925 #define WM5100_OUT1L_ANC_SRC_SHIFT                  11  /* OUT1L_ANC_SRC */
1926 #define WM5100_OUT1L_ANC_SRC_WIDTH                   1  /* OUT1L_ANC_SRC */
1927 #define WM5100_OUT1L_PGA_VOL_MASK               0x00FE  /* OUT1L_PGA_VOL - [7:1] */
1928 #define WM5100_OUT1L_PGA_VOL_SHIFT                   1  /* OUT1L_PGA_VOL - [7:1] */
1929 #define WM5100_OUT1L_PGA_VOL_WIDTH                   7  /* OUT1L_PGA_VOL - [7:1] */
1930 
1931 /*
1932  * R1041 (0x411) - Out Volume 1R
1933  */
1934 #define WM5100_OUT1R_ANC_SRC                    0x0800  /* OUT1R_ANC_SRC */
1935 #define WM5100_OUT1R_ANC_SRC_MASK               0x0800  /* OUT1R_ANC_SRC */
1936 #define WM5100_OUT1R_ANC_SRC_SHIFT                  11  /* OUT1R_ANC_SRC */
1937 #define WM5100_OUT1R_ANC_SRC_WIDTH                   1  /* OUT1R_ANC_SRC */
1938 #define WM5100_OUT1R_PGA_VOL_MASK               0x00FE  /* OUT1R_PGA_VOL - [7:1] */
1939 #define WM5100_OUT1R_PGA_VOL_SHIFT                   1  /* OUT1R_PGA_VOL - [7:1] */
1940 #define WM5100_OUT1R_PGA_VOL_WIDTH                   7  /* OUT1R_PGA_VOL - [7:1] */
1941 
1942 /*
1943  * R1042 (0x412) - DAC Volume Limit 1L
1944  */
1945 #define WM5100_OUT1L_VOL_LIM_MASK               0x00FF  /* OUT1L_VOL_LIM - [7:0] */
1946 #define WM5100_OUT1L_VOL_LIM_SHIFT                   0  /* OUT1L_VOL_LIM - [7:0] */
1947 #define WM5100_OUT1L_VOL_LIM_WIDTH                   8  /* OUT1L_VOL_LIM - [7:0] */
1948 
1949 /*
1950  * R1043 (0x413) - DAC Volume Limit 1R
1951  */
1952 #define WM5100_OUT1R_VOL_LIM_MASK               0x00FF  /* OUT1R_VOL_LIM - [7:0] */
1953 #define WM5100_OUT1R_VOL_LIM_SHIFT                   0  /* OUT1R_VOL_LIM - [7:0] */
1954 #define WM5100_OUT1R_VOL_LIM_WIDTH                   8  /* OUT1R_VOL_LIM - [7:0] */
1955 
1956 /*
1957  * R1044 (0x414) - Out Volume 2L
1958  */
1959 #define WM5100_OUT2_OSR                         0x2000  /* OUT2_OSR */
1960 #define WM5100_OUT2_OSR_MASK                    0x2000  /* OUT2_OSR */
1961 #define WM5100_OUT2_OSR_SHIFT                       13  /* OUT2_OSR */
1962 #define WM5100_OUT2_OSR_WIDTH                        1  /* OUT2_OSR */
1963 #define WM5100_OUT2_MONO                        0x1000  /* OUT2_MONO */
1964 #define WM5100_OUT2_MONO_MASK                   0x1000  /* OUT2_MONO */
1965 #define WM5100_OUT2_MONO_SHIFT                      12  /* OUT2_MONO */
1966 #define WM5100_OUT2_MONO_WIDTH                       1  /* OUT2_MONO */
1967 #define WM5100_OUT2L_ANC_SRC                    0x0800  /* OUT2L_ANC_SRC */
1968 #define WM5100_OUT2L_ANC_SRC_MASK               0x0800  /* OUT2L_ANC_SRC */
1969 #define WM5100_OUT2L_ANC_SRC_SHIFT                  11  /* OUT2L_ANC_SRC */
1970 #define WM5100_OUT2L_ANC_SRC_WIDTH                   1  /* OUT2L_ANC_SRC */
1971 #define WM5100_OUT2L_PGA_VOL_MASK               0x00FE  /* OUT2L_PGA_VOL - [7:1] */
1972 #define WM5100_OUT2L_PGA_VOL_SHIFT                   1  /* OUT2L_PGA_VOL - [7:1] */
1973 #define WM5100_OUT2L_PGA_VOL_WIDTH                   7  /* OUT2L_PGA_VOL - [7:1] */
1974 
1975 /*
1976  * R1045 (0x415) - Out Volume 2R
1977  */
1978 #define WM5100_OUT2R_ANC_SRC                    0x0800  /* OUT2R_ANC_SRC */
1979 #define WM5100_OUT2R_ANC_SRC_MASK               0x0800  /* OUT2R_ANC_SRC */
1980 #define WM5100_OUT2R_ANC_SRC_SHIFT                  11  /* OUT2R_ANC_SRC */
1981 #define WM5100_OUT2R_ANC_SRC_WIDTH                   1  /* OUT2R_ANC_SRC */
1982 #define WM5100_OUT2R_PGA_VOL_MASK               0x00FE  /* OUT2R_PGA_VOL - [7:1] */
1983 #define WM5100_OUT2R_PGA_VOL_SHIFT                   1  /* OUT2R_PGA_VOL - [7:1] */
1984 #define WM5100_OUT2R_PGA_VOL_WIDTH                   7  /* OUT2R_PGA_VOL - [7:1] */
1985 
1986 /*
1987  * R1046 (0x416) - DAC Volume Limit 2L
1988  */
1989 #define WM5100_OUT2L_VOL_LIM_MASK               0x00FF  /* OUT2L_VOL_LIM - [7:0] */
1990 #define WM5100_OUT2L_VOL_LIM_SHIFT                   0  /* OUT2L_VOL_LIM - [7:0] */
1991 #define WM5100_OUT2L_VOL_LIM_WIDTH                   8  /* OUT2L_VOL_LIM - [7:0] */
1992 
1993 /*
1994  * R1047 (0x417) - DAC Volume Limit 2R
1995  */
1996 #define WM5100_OUT2R_VOL_LIM_MASK               0x00FF  /* OUT2R_VOL_LIM - [7:0] */
1997 #define WM5100_OUT2R_VOL_LIM_SHIFT                   0  /* OUT2R_VOL_LIM - [7:0] */
1998 #define WM5100_OUT2R_VOL_LIM_WIDTH                   8  /* OUT2R_VOL_LIM - [7:0] */
1999 
2000 /*
2001  * R1048 (0x418) - Out Volume 3L
2002  */
2003 #define WM5100_OUT3_OSR                         0x2000  /* OUT3_OSR */
2004 #define WM5100_OUT3_OSR_MASK                    0x2000  /* OUT3_OSR */
2005 #define WM5100_OUT3_OSR_SHIFT                       13  /* OUT3_OSR */
2006 #define WM5100_OUT3_OSR_WIDTH                        1  /* OUT3_OSR */
2007 #define WM5100_OUT3_MONO                        0x1000  /* OUT3_MONO */
2008 #define WM5100_OUT3_MONO_MASK                   0x1000  /* OUT3_MONO */
2009 #define WM5100_OUT3_MONO_SHIFT                      12  /* OUT3_MONO */
2010 #define WM5100_OUT3_MONO_WIDTH                       1  /* OUT3_MONO */
2011 #define WM5100_OUT3L_ANC_SRC                    0x0800  /* OUT3L_ANC_SRC */
2012 #define WM5100_OUT3L_ANC_SRC_MASK               0x0800  /* OUT3L_ANC_SRC */
2013 #define WM5100_OUT3L_ANC_SRC_SHIFT                  11  /* OUT3L_ANC_SRC */
2014 #define WM5100_OUT3L_ANC_SRC_WIDTH                   1  /* OUT3L_ANC_SRC */
2015 #define WM5100_OUT3L_PGA_VOL_MASK               0x00FE  /* OUT3L_PGA_VOL - [7:1] */
2016 #define WM5100_OUT3L_PGA_VOL_SHIFT                   1  /* OUT3L_PGA_VOL - [7:1] */
2017 #define WM5100_OUT3L_PGA_VOL_WIDTH                   7  /* OUT3L_PGA_VOL - [7:1] */
2018 
2019 /*
2020  * R1049 (0x419) - Out Volume 3R
2021  */
2022 #define WM5100_OUT3R_ANC_SRC                    0x0800  /* OUT3R_ANC_SRC */
2023 #define WM5100_OUT3R_ANC_SRC_MASK               0x0800  /* OUT3R_ANC_SRC */
2024 #define WM5100_OUT3R_ANC_SRC_SHIFT                  11  /* OUT3R_ANC_SRC */
2025 #define WM5100_OUT3R_ANC_SRC_WIDTH                   1  /* OUT3R_ANC_SRC */
2026 #define WM5100_OUT3R_PGA_VOL_MASK               0x00FE  /* OUT3R_PGA_VOL - [7:1] */
2027 #define WM5100_OUT3R_PGA_VOL_SHIFT                   1  /* OUT3R_PGA_VOL - [7:1] */
2028 #define WM5100_OUT3R_PGA_VOL_WIDTH                   7  /* OUT3R_PGA_VOL - [7:1] */
2029 
2030 /*
2031  * R1050 (0x41A) - DAC Volume Limit 3L
2032  */
2033 #define WM5100_OUT3L_VOL_LIM_MASK               0x00FF  /* OUT3L_VOL_LIM - [7:0] */
2034 #define WM5100_OUT3L_VOL_LIM_SHIFT                   0  /* OUT3L_VOL_LIM - [7:0] */
2035 #define WM5100_OUT3L_VOL_LIM_WIDTH                   8  /* OUT3L_VOL_LIM - [7:0] */
2036 
2037 /*
2038  * R1051 (0x41B) - DAC Volume Limit 3R
2039  */
2040 #define WM5100_OUT3R_VOL_LIM_MASK               0x00FF  /* OUT3R_VOL_LIM - [7:0] */
2041 #define WM5100_OUT3R_VOL_LIM_SHIFT                   0  /* OUT3R_VOL_LIM - [7:0] */
2042 #define WM5100_OUT3R_VOL_LIM_WIDTH                   8  /* OUT3R_VOL_LIM - [7:0] */
2043 
2044 /*
2045  * R1052 (0x41C) - Out Volume 4L
2046  */
2047 #define WM5100_OUT4_OSR                         0x2000  /* OUT4_OSR */
2048 #define WM5100_OUT4_OSR_MASK                    0x2000  /* OUT4_OSR */
2049 #define WM5100_OUT4_OSR_SHIFT                       13  /* OUT4_OSR */
2050 #define WM5100_OUT4_OSR_WIDTH                        1  /* OUT4_OSR */
2051 #define WM5100_OUT4L_ANC_SRC                    0x0800  /* OUT4L_ANC_SRC */
2052 #define WM5100_OUT4L_ANC_SRC_MASK               0x0800  /* OUT4L_ANC_SRC */
2053 #define WM5100_OUT4L_ANC_SRC_SHIFT                  11  /* OUT4L_ANC_SRC */
2054 #define WM5100_OUT4L_ANC_SRC_WIDTH                   1  /* OUT4L_ANC_SRC */
2055 #define WM5100_OUT4L_VOL_LIM_MASK               0x00FF  /* OUT4L_VOL_LIM - [7:0] */
2056 #define WM5100_OUT4L_VOL_LIM_SHIFT                   0  /* OUT4L_VOL_LIM - [7:0] */
2057 #define WM5100_OUT4L_VOL_LIM_WIDTH                   8  /* OUT4L_VOL_LIM - [7:0] */
2058 
2059 /*
2060  * R1053 (0x41D) - Out Volume 4R
2061  */
2062 #define WM5100_OUT4R_ANC_SRC                    0x0800  /* OUT4R_ANC_SRC */
2063 #define WM5100_OUT4R_ANC_SRC_MASK               0x0800  /* OUT4R_ANC_SRC */
2064 #define WM5100_OUT4R_ANC_SRC_SHIFT                  11  /* OUT4R_ANC_SRC */
2065 #define WM5100_OUT4R_ANC_SRC_WIDTH                   1  /* OUT4R_ANC_SRC */
2066 #define WM5100_OUT4R_VOL_LIM_MASK               0x00FF  /* OUT4R_VOL_LIM - [7:0] */
2067 #define WM5100_OUT4R_VOL_LIM_SHIFT                   0  /* OUT4R_VOL_LIM - [7:0] */
2068 #define WM5100_OUT4R_VOL_LIM_WIDTH                   8  /* OUT4R_VOL_LIM - [7:0] */
2069 
2070 /*
2071  * R1054 (0x41E) - DAC Volume Limit 5L
2072  */
2073 #define WM5100_OUT5_OSR                         0x2000  /* OUT5_OSR */
2074 #define WM5100_OUT5_OSR_MASK                    0x2000  /* OUT5_OSR */
2075 #define WM5100_OUT5_OSR_SHIFT                       13  /* OUT5_OSR */
2076 #define WM5100_OUT5_OSR_WIDTH                        1  /* OUT5_OSR */
2077 #define WM5100_OUT5L_ANC_SRC                    0x0800  /* OUT5L_ANC_SRC */
2078 #define WM5100_OUT5L_ANC_SRC_MASK               0x0800  /* OUT5L_ANC_SRC */
2079 #define WM5100_OUT5L_ANC_SRC_SHIFT                  11  /* OUT5L_ANC_SRC */
2080 #define WM5100_OUT5L_ANC_SRC_WIDTH                   1  /* OUT5L_ANC_SRC */
2081 #define WM5100_OUT5L_VOL_LIM_MASK               0x00FF  /* OUT5L_VOL_LIM - [7:0] */
2082 #define WM5100_OUT5L_VOL_LIM_SHIFT                   0  /* OUT5L_VOL_LIM - [7:0] */
2083 #define WM5100_OUT5L_VOL_LIM_WIDTH                   8  /* OUT5L_VOL_LIM - [7:0] */
2084 
2085 /*
2086  * R1055 (0x41F) - DAC Volume Limit 5R
2087  */
2088 #define WM5100_OUT5R_ANC_SRC                    0x0800  /* OUT5R_ANC_SRC */
2089 #define WM5100_OUT5R_ANC_SRC_MASK               0x0800  /* OUT5R_ANC_SRC */
2090 #define WM5100_OUT5R_ANC_SRC_SHIFT                  11  /* OUT5R_ANC_SRC */
2091 #define WM5100_OUT5R_ANC_SRC_WIDTH                   1  /* OUT5R_ANC_SRC */
2092 #define WM5100_OUT5R_VOL_LIM_MASK               0x00FF  /* OUT5R_VOL_LIM - [7:0] */
2093 #define WM5100_OUT5R_VOL_LIM_SHIFT                   0  /* OUT5R_VOL_LIM - [7:0] */
2094 #define WM5100_OUT5R_VOL_LIM_WIDTH                   8  /* OUT5R_VOL_LIM - [7:0] */
2095 
2096 /*
2097  * R1056 (0x420) - DAC Volume Limit 6L
2098  */
2099 #define WM5100_OUT6_OSR                         0x2000  /* OUT6_OSR */
2100 #define WM5100_OUT6_OSR_MASK                    0x2000  /* OUT6_OSR */
2101 #define WM5100_OUT6_OSR_SHIFT                       13  /* OUT6_OSR */
2102 #define WM5100_OUT6_OSR_WIDTH                        1  /* OUT6_OSR */
2103 #define WM5100_OUT6L_ANC_SRC                    0x0800  /* OUT6L_ANC_SRC */
2104 #define WM5100_OUT6L_ANC_SRC_MASK               0x0800  /* OUT6L_ANC_SRC */
2105 #define WM5100_OUT6L_ANC_SRC_SHIFT                  11  /* OUT6L_ANC_SRC */
2106 #define WM5100_OUT6L_ANC_SRC_WIDTH                   1  /* OUT6L_ANC_SRC */
2107 #define WM5100_OUT6L_VOL_LIM_MASK               0x00FF  /* OUT6L_VOL_LIM - [7:0] */
2108 #define WM5100_OUT6L_VOL_LIM_SHIFT                   0  /* OUT6L_VOL_LIM - [7:0] */
2109 #define WM5100_OUT6L_VOL_LIM_WIDTH                   8  /* OUT6L_VOL_LIM - [7:0] */
2110 
2111 /*
2112  * R1057 (0x421) - DAC Volume Limit 6R
2113  */
2114 #define WM5100_OUT6R_ANC_SRC                    0x0800  /* OUT6R_ANC_SRC */
2115 #define WM5100_OUT6R_ANC_SRC_MASK               0x0800  /* OUT6R_ANC_SRC */
2116 #define WM5100_OUT6R_ANC_SRC_SHIFT                  11  /* OUT6R_ANC_SRC */
2117 #define WM5100_OUT6R_ANC_SRC_WIDTH                   1  /* OUT6R_ANC_SRC */
2118 #define WM5100_OUT6R_VOL_LIM_MASK               0x00FF  /* OUT6R_VOL_LIM - [7:0] */
2119 #define WM5100_OUT6R_VOL_LIM_SHIFT                   0  /* OUT6R_VOL_LIM - [7:0] */
2120 #define WM5100_OUT6R_VOL_LIM_WIDTH                   8  /* OUT6R_VOL_LIM - [7:0] */
2121 
2122 /*
2123  * R1088 (0x440) - DAC AEC Control 1
2124  */
2125 #define WM5100_AEC_LOOPBACK_SRC_MASK            0x003C  /* AEC_LOOPBACK_SRC - [5:2] */
2126 #define WM5100_AEC_LOOPBACK_SRC_SHIFT                2  /* AEC_LOOPBACK_SRC - [5:2] */
2127 #define WM5100_AEC_LOOPBACK_SRC_WIDTH                4  /* AEC_LOOPBACK_SRC - [5:2] */
2128 #define WM5100_AEC_ENA_STS                      0x0002  /* AEC_ENA_STS */
2129 #define WM5100_AEC_ENA_STS_MASK                 0x0002  /* AEC_ENA_STS */
2130 #define WM5100_AEC_ENA_STS_SHIFT                     1  /* AEC_ENA_STS */
2131 #define WM5100_AEC_ENA_STS_WIDTH                     1  /* AEC_ENA_STS */
2132 #define WM5100_AEC_LOOPBACK_ENA                 0x0001  /* AEC_LOOPBACK_ENA */
2133 #define WM5100_AEC_LOOPBACK_ENA_MASK            0x0001  /* AEC_LOOPBACK_ENA */
2134 #define WM5100_AEC_LOOPBACK_ENA_SHIFT                0  /* AEC_LOOPBACK_ENA */
2135 #define WM5100_AEC_LOOPBACK_ENA_WIDTH                1  /* AEC_LOOPBACK_ENA */
2136 
2137 /*
2138  * R1089 (0x441) - Output Volume Ramp
2139  */
2140 #define WM5100_OUT_VD_RAMP_MASK                 0x0070  /* OUT_VD_RAMP - [6:4] */
2141 #define WM5100_OUT_VD_RAMP_SHIFT                     4  /* OUT_VD_RAMP - [6:4] */
2142 #define WM5100_OUT_VD_RAMP_WIDTH                     3  /* OUT_VD_RAMP - [6:4] */
2143 #define WM5100_OUT_VI_RAMP_MASK                 0x0007  /* OUT_VI_RAMP - [2:0] */
2144 #define WM5100_OUT_VI_RAMP_SHIFT                     0  /* OUT_VI_RAMP - [2:0] */
2145 #define WM5100_OUT_VI_RAMP_WIDTH                     3  /* OUT_VI_RAMP - [2:0] */
2146 
2147 /*
2148  * R1152 (0x480) - DAC Digital Volume 1L
2149  */
2150 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2151 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2152 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2153 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2154 #define WM5100_OUT1L_MUTE                       0x0100  /* OUT1L_MUTE */
2155 #define WM5100_OUT1L_MUTE_MASK                  0x0100  /* OUT1L_MUTE */
2156 #define WM5100_OUT1L_MUTE_SHIFT                      8  /* OUT1L_MUTE */
2157 #define WM5100_OUT1L_MUTE_WIDTH                      1  /* OUT1L_MUTE */
2158 #define WM5100_OUT1L_VOL_MASK                   0x00FF  /* OUT1L_VOL - [7:0] */
2159 #define WM5100_OUT1L_VOL_SHIFT                       0  /* OUT1L_VOL - [7:0] */
2160 #define WM5100_OUT1L_VOL_WIDTH                       8  /* OUT1L_VOL - [7:0] */
2161 
2162 /*
2163  * R1153 (0x481) - DAC Digital Volume 1R
2164  */
2165 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2166 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2167 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2168 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2169 #define WM5100_OUT1R_MUTE                       0x0100  /* OUT1R_MUTE */
2170 #define WM5100_OUT1R_MUTE_MASK                  0x0100  /* OUT1R_MUTE */
2171 #define WM5100_OUT1R_MUTE_SHIFT                      8  /* OUT1R_MUTE */
2172 #define WM5100_OUT1R_MUTE_WIDTH                      1  /* OUT1R_MUTE */
2173 #define WM5100_OUT1R_VOL_MASK                   0x00FF  /* OUT1R_VOL - [7:0] */
2174 #define WM5100_OUT1R_VOL_SHIFT                       0  /* OUT1R_VOL - [7:0] */
2175 #define WM5100_OUT1R_VOL_WIDTH                       8  /* OUT1R_VOL - [7:0] */
2176 
2177 /*
2178  * R1154 (0x482) - DAC Digital Volume 2L
2179  */
2180 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2181 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2182 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2183 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2184 #define WM5100_OUT2L_MUTE                       0x0100  /* OUT2L_MUTE */
2185 #define WM5100_OUT2L_MUTE_MASK                  0x0100  /* OUT2L_MUTE */
2186 #define WM5100_OUT2L_MUTE_SHIFT                      8  /* OUT2L_MUTE */
2187 #define WM5100_OUT2L_MUTE_WIDTH                      1  /* OUT2L_MUTE */
2188 #define WM5100_OUT2L_VOL_MASK                   0x00FF  /* OUT2L_VOL - [7:0] */
2189 #define WM5100_OUT2L_VOL_SHIFT                       0  /* OUT2L_VOL - [7:0] */
2190 #define WM5100_OUT2L_VOL_WIDTH                       8  /* OUT2L_VOL - [7:0] */
2191 
2192 /*
2193  * R1155 (0x483) - DAC Digital Volume 2R
2194  */
2195 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2196 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2197 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2198 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2199 #define WM5100_OUT2R_MUTE                       0x0100  /* OUT2R_MUTE */
2200 #define WM5100_OUT2R_MUTE_MASK                  0x0100  /* OUT2R_MUTE */
2201 #define WM5100_OUT2R_MUTE_SHIFT                      8  /* OUT2R_MUTE */
2202 #define WM5100_OUT2R_MUTE_WIDTH                      1  /* OUT2R_MUTE */
2203 #define WM5100_OUT2R_VOL_MASK                   0x00FF  /* OUT2R_VOL - [7:0] */
2204 #define WM5100_OUT2R_VOL_SHIFT                       0  /* OUT2R_VOL - [7:0] */
2205 #define WM5100_OUT2R_VOL_WIDTH                       8  /* OUT2R_VOL - [7:0] */
2206 
2207 /*
2208  * R1156 (0x484) - DAC Digital Volume 3L
2209  */
2210 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2211 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2212 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2213 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2214 #define WM5100_OUT3L_MUTE                       0x0100  /* OUT3L_MUTE */
2215 #define WM5100_OUT3L_MUTE_MASK                  0x0100  /* OUT3L_MUTE */
2216 #define WM5100_OUT3L_MUTE_SHIFT                      8  /* OUT3L_MUTE */
2217 #define WM5100_OUT3L_MUTE_WIDTH                      1  /* OUT3L_MUTE */
2218 #define WM5100_OUT3L_VOL_MASK                   0x00FF  /* OUT3L_VOL - [7:0] */
2219 #define WM5100_OUT3L_VOL_SHIFT                       0  /* OUT3L_VOL - [7:0] */
2220 #define WM5100_OUT3L_VOL_WIDTH                       8  /* OUT3L_VOL - [7:0] */
2221 
2222 /*
2223  * R1157 (0x485) - DAC Digital Volume 3R
2224  */
2225 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2226 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2227 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2228 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2229 #define WM5100_OUT3R_MUTE                       0x0100  /* OUT3R_MUTE */
2230 #define WM5100_OUT3R_MUTE_MASK                  0x0100  /* OUT3R_MUTE */
2231 #define WM5100_OUT3R_MUTE_SHIFT                      8  /* OUT3R_MUTE */
2232 #define WM5100_OUT3R_MUTE_WIDTH                      1  /* OUT3R_MUTE */
2233 #define WM5100_OUT3R_VOL_MASK                   0x00FF  /* OUT3R_VOL - [7:0] */
2234 #define WM5100_OUT3R_VOL_SHIFT                       0  /* OUT3R_VOL - [7:0] */
2235 #define WM5100_OUT3R_VOL_WIDTH                       8  /* OUT3R_VOL - [7:0] */
2236 
2237 /*
2238  * R1158 (0x486) - DAC Digital Volume 4L
2239  */
2240 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2241 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2242 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2243 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2244 #define WM5100_OUT4L_MUTE                       0x0100  /* OUT4L_MUTE */
2245 #define WM5100_OUT4L_MUTE_MASK                  0x0100  /* OUT4L_MUTE */
2246 #define WM5100_OUT4L_MUTE_SHIFT                      8  /* OUT4L_MUTE */
2247 #define WM5100_OUT4L_MUTE_WIDTH                      1  /* OUT4L_MUTE */
2248 #define WM5100_OUT4L_VOL_MASK                   0x00FF  /* OUT4L_VOL - [7:0] */
2249 #define WM5100_OUT4L_VOL_SHIFT                       0  /* OUT4L_VOL - [7:0] */
2250 #define WM5100_OUT4L_VOL_WIDTH                       8  /* OUT4L_VOL - [7:0] */
2251 
2252 /*
2253  * R1159 (0x487) - DAC Digital Volume 4R
2254  */
2255 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2256 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2257 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2258 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2259 #define WM5100_OUT4R_MUTE                       0x0100  /* OUT4R_MUTE */
2260 #define WM5100_OUT4R_MUTE_MASK                  0x0100  /* OUT4R_MUTE */
2261 #define WM5100_OUT4R_MUTE_SHIFT                      8  /* OUT4R_MUTE */
2262 #define WM5100_OUT4R_MUTE_WIDTH                      1  /* OUT4R_MUTE */
2263 #define WM5100_OUT4R_VOL_MASK                   0x00FF  /* OUT4R_VOL - [7:0] */
2264 #define WM5100_OUT4R_VOL_SHIFT                       0  /* OUT4R_VOL - [7:0] */
2265 #define WM5100_OUT4R_VOL_WIDTH                       8  /* OUT4R_VOL - [7:0] */
2266 
2267 /*
2268  * R1160 (0x488) - DAC Digital Volume 5L
2269  */
2270 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2271 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2272 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2273 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2274 #define WM5100_OUT5L_MUTE                       0x0100  /* OUT5L_MUTE */
2275 #define WM5100_OUT5L_MUTE_MASK                  0x0100  /* OUT5L_MUTE */
2276 #define WM5100_OUT5L_MUTE_SHIFT                      8  /* OUT5L_MUTE */
2277 #define WM5100_OUT5L_MUTE_WIDTH                      1  /* OUT5L_MUTE */
2278 #define WM5100_OUT5L_VOL_MASK                   0x00FF  /* OUT5L_VOL - [7:0] */
2279 #define WM5100_OUT5L_VOL_SHIFT                       0  /* OUT5L_VOL - [7:0] */
2280 #define WM5100_OUT5L_VOL_WIDTH                       8  /* OUT5L_VOL - [7:0] */
2281 
2282 /*
2283  * R1161 (0x489) - DAC Digital Volume 5R
2284  */
2285 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2286 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2287 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2288 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2289 #define WM5100_OUT5R_MUTE                       0x0100  /* OUT5R_MUTE */
2290 #define WM5100_OUT5R_MUTE_MASK                  0x0100  /* OUT5R_MUTE */
2291 #define WM5100_OUT5R_MUTE_SHIFT                      8  /* OUT5R_MUTE */
2292 #define WM5100_OUT5R_MUTE_WIDTH                      1  /* OUT5R_MUTE */
2293 #define WM5100_OUT5R_VOL_MASK                   0x00FF  /* OUT5R_VOL - [7:0] */
2294 #define WM5100_OUT5R_VOL_SHIFT                       0  /* OUT5R_VOL - [7:0] */
2295 #define WM5100_OUT5R_VOL_WIDTH                       8  /* OUT5R_VOL - [7:0] */
2296 
2297 /*
2298  * R1162 (0x48A) - DAC Digital Volume 6L
2299  */
2300 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2301 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2302 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2303 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2304 #define WM5100_OUT6L_MUTE                       0x0100  /* OUT6L_MUTE */
2305 #define WM5100_OUT6L_MUTE_MASK                  0x0100  /* OUT6L_MUTE */
2306 #define WM5100_OUT6L_MUTE_SHIFT                      8  /* OUT6L_MUTE */
2307 #define WM5100_OUT6L_MUTE_WIDTH                      1  /* OUT6L_MUTE */
2308 #define WM5100_OUT6L_VOL_MASK                   0x00FF  /* OUT6L_VOL - [7:0] */
2309 #define WM5100_OUT6L_VOL_SHIFT                       0  /* OUT6L_VOL - [7:0] */
2310 #define WM5100_OUT6L_VOL_WIDTH                       8  /* OUT6L_VOL - [7:0] */
2311 
2312 /*
2313  * R1163 (0x48B) - DAC Digital Volume 6R
2314  */
2315 #define WM5100_OUT_VU                           0x0200  /* OUT_VU */
2316 #define WM5100_OUT_VU_MASK                      0x0200  /* OUT_VU */
2317 #define WM5100_OUT_VU_SHIFT                          9  /* OUT_VU */
2318 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2319 #define WM5100_OUT6R_MUTE                       0x0100  /* OUT6R_MUTE */
2320 #define WM5100_OUT6R_MUTE_MASK                  0x0100  /* OUT6R_MUTE */
2321 #define WM5100_OUT6R_MUTE_SHIFT                      8  /* OUT6R_MUTE */
2322 #define WM5100_OUT6R_MUTE_WIDTH                      1  /* OUT6R_MUTE */
2323 #define WM5100_OUT6R_VOL_MASK                   0x00FF  /* OUT6R_VOL - [7:0] */
2324 #define WM5100_OUT6R_VOL_SHIFT                       0  /* OUT6R_VOL - [7:0] */
2325 #define WM5100_OUT6R_VOL_WIDTH                       8  /* OUT6R_VOL - [7:0] */
2326 
2327 /*
2328  * R1216 (0x4C0) - PDM SPK1 CTRL 1
2329  */
2330 #define WM5100_SPK1R_MUTE                       0x2000  /* SPK1R_MUTE */
2331 #define WM5100_SPK1R_MUTE_MASK                  0x2000  /* SPK1R_MUTE */
2332 #define WM5100_SPK1R_MUTE_SHIFT                     13  /* SPK1R_MUTE */
2333 #define WM5100_SPK1R_MUTE_WIDTH                      1  /* SPK1R_MUTE */
2334 #define WM5100_SPK1L_MUTE                       0x1000  /* SPK1L_MUTE */
2335 #define WM5100_SPK1L_MUTE_MASK                  0x1000  /* SPK1L_MUTE */
2336 #define WM5100_SPK1L_MUTE_SHIFT                     12  /* SPK1L_MUTE */
2337 #define WM5100_SPK1L_MUTE_WIDTH                      1  /* SPK1L_MUTE */
2338 #define WM5100_SPK1_MUTE_ENDIAN                 0x0100  /* SPK1_MUTE_ENDIAN */
2339 #define WM5100_SPK1_MUTE_ENDIAN_MASK            0x0100  /* SPK1_MUTE_ENDIAN */
2340 #define WM5100_SPK1_MUTE_ENDIAN_SHIFT                8  /* SPK1_MUTE_ENDIAN */
2341 #define WM5100_SPK1_MUTE_ENDIAN_WIDTH                1  /* SPK1_MUTE_ENDIAN */
2342 #define WM5100_SPK1_MUTE_SEQ1_MASK              0x00FF  /* SPK1_MUTE_SEQ1 - [7:0] */
2343 #define WM5100_SPK1_MUTE_SEQ1_SHIFT                  0  /* SPK1_MUTE_SEQ1 - [7:0] */
2344 #define WM5100_SPK1_MUTE_SEQ1_WIDTH                  8  /* SPK1_MUTE_SEQ1 - [7:0] */
2345 
2346 /*
2347  * R1217 (0x4C1) - PDM SPK1 CTRL 2
2348  */
2349 #define WM5100_SPK1_FMT                         0x0001  /* SPK1_FMT */
2350 #define WM5100_SPK1_FMT_MASK                    0x0001  /* SPK1_FMT */
2351 #define WM5100_SPK1_FMT_SHIFT                        0  /* SPK1_FMT */
2352 #define WM5100_SPK1_FMT_WIDTH                        1  /* SPK1_FMT */
2353 
2354 /*
2355  * R1218 (0x4C2) - PDM SPK2 CTRL 1
2356  */
2357 #define WM5100_SPK2R_MUTE                       0x2000  /* SPK2R_MUTE */
2358 #define WM5100_SPK2R_MUTE_MASK                  0x2000  /* SPK2R_MUTE */
2359 #define WM5100_SPK2R_MUTE_SHIFT                     13  /* SPK2R_MUTE */
2360 #define WM5100_SPK2R_MUTE_WIDTH                      1  /* SPK2R_MUTE */
2361 #define WM5100_SPK2L_MUTE                       0x1000  /* SPK2L_MUTE */
2362 #define WM5100_SPK2L_MUTE_MASK                  0x1000  /* SPK2L_MUTE */
2363 #define WM5100_SPK2L_MUTE_SHIFT                     12  /* SPK2L_MUTE */
2364 #define WM5100_SPK2L_MUTE_WIDTH                      1  /* SPK2L_MUTE */
2365 #define WM5100_SPK2_MUTE_ENDIAN                 0x0100  /* SPK2_MUTE_ENDIAN */
2366 #define WM5100_SPK2_MUTE_ENDIAN_MASK            0x0100  /* SPK2_MUTE_ENDIAN */
2367 #define WM5100_SPK2_MUTE_ENDIAN_SHIFT                8  /* SPK2_MUTE_ENDIAN */
2368 #define WM5100_SPK2_MUTE_ENDIAN_WIDTH                1  /* SPK2_MUTE_ENDIAN */
2369 #define WM5100_SPK2_MUTE_SEQ1_MASK              0x00FF  /* SPK2_MUTE_SEQ1 - [7:0] */
2370 #define WM5100_SPK2_MUTE_SEQ1_SHIFT                  0  /* SPK2_MUTE_SEQ1 - [7:0] */
2371 #define WM5100_SPK2_MUTE_SEQ1_WIDTH                  8  /* SPK2_MUTE_SEQ1 - [7:0] */
2372 
2373 /*
2374  * R1219 (0x4C3) - PDM SPK2 CTRL 2
2375  */
2376 #define WM5100_SPK2_FMT                         0x0001  /* SPK2_FMT */
2377 #define WM5100_SPK2_FMT_MASK                    0x0001  /* SPK2_FMT */
2378 #define WM5100_SPK2_FMT_SHIFT                        0  /* SPK2_FMT */
2379 #define WM5100_SPK2_FMT_WIDTH                        1  /* SPK2_FMT */
2380 
2381 /*
2382  * R1280 (0x500) - Audio IF 1_1
2383  */
2384 #define WM5100_AIF1_BCLK_INV                    0x0080  /* AIF1_BCLK_INV */
2385 #define WM5100_AIF1_BCLK_INV_MASK               0x0080  /* AIF1_BCLK_INV */
2386 #define WM5100_AIF1_BCLK_INV_SHIFT                   7  /* AIF1_BCLK_INV */
2387 #define WM5100_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
2388 #define WM5100_AIF1_BCLK_FRC                    0x0040  /* AIF1_BCLK_FRC */
2389 #define WM5100_AIF1_BCLK_FRC_MASK               0x0040  /* AIF1_BCLK_FRC */
2390 #define WM5100_AIF1_BCLK_FRC_SHIFT                   6  /* AIF1_BCLK_FRC */
2391 #define WM5100_AIF1_BCLK_FRC_WIDTH                   1  /* AIF1_BCLK_FRC */
2392 #define WM5100_AIF1_BCLK_MSTR                   0x0020  /* AIF1_BCLK_MSTR */
2393 #define WM5100_AIF1_BCLK_MSTR_MASK              0x0020  /* AIF1_BCLK_MSTR */
2394 #define WM5100_AIF1_BCLK_MSTR_SHIFT                  5  /* AIF1_BCLK_MSTR */
2395 #define WM5100_AIF1_BCLK_MSTR_WIDTH                  1  /* AIF1_BCLK_MSTR */
2396 #define WM5100_AIF1_BCLK_FREQ_MASK              0x001F  /* AIF1_BCLK_FREQ - [4:0] */
2397 #define WM5100_AIF1_BCLK_FREQ_SHIFT                  0  /* AIF1_BCLK_FREQ - [4:0] */
2398 #define WM5100_AIF1_BCLK_FREQ_WIDTH                  5  /* AIF1_BCLK_FREQ - [4:0] */
2399 
2400 /*
2401  * R1281 (0x501) - Audio IF 1_2
2402  */
2403 #define WM5100_AIF1TX_DAT_TRI                   0x0020  /* AIF1TX_DAT_TRI */
2404 #define WM5100_AIF1TX_DAT_TRI_MASK              0x0020  /* AIF1TX_DAT_TRI */
2405 #define WM5100_AIF1TX_DAT_TRI_SHIFT                  5  /* AIF1TX_DAT_TRI */
2406 #define WM5100_AIF1TX_DAT_TRI_WIDTH                  1  /* AIF1TX_DAT_TRI */
2407 #define WM5100_AIF1TX_LRCLK_SRC                 0x0008  /* AIF1TX_LRCLK_SRC */
2408 #define WM5100_AIF1TX_LRCLK_SRC_MASK            0x0008  /* AIF1TX_LRCLK_SRC */
2409 #define WM5100_AIF1TX_LRCLK_SRC_SHIFT                3  /* AIF1TX_LRCLK_SRC */
2410 #define WM5100_AIF1TX_LRCLK_SRC_WIDTH                1  /* AIF1TX_LRCLK_SRC */
2411 #define WM5100_AIF1TX_LRCLK_INV                 0x0004  /* AIF1TX_LRCLK_INV */
2412 #define WM5100_AIF1TX_LRCLK_INV_MASK            0x0004  /* AIF1TX_LRCLK_INV */
2413 #define WM5100_AIF1TX_LRCLK_INV_SHIFT                2  /* AIF1TX_LRCLK_INV */
2414 #define WM5100_AIF1TX_LRCLK_INV_WIDTH                1  /* AIF1TX_LRCLK_INV */
2415 #define WM5100_AIF1TX_LRCLK_FRC                 0x0002  /* AIF1TX_LRCLK_FRC */
2416 #define WM5100_AIF1TX_LRCLK_FRC_MASK            0x0002  /* AIF1TX_LRCLK_FRC */
2417 #define WM5100_AIF1TX_LRCLK_FRC_SHIFT                1  /* AIF1TX_LRCLK_FRC */
2418 #define WM5100_AIF1TX_LRCLK_FRC_WIDTH                1  /* AIF1TX_LRCLK_FRC */
2419 #define WM5100_AIF1TX_LRCLK_MSTR                0x0001  /* AIF1TX_LRCLK_MSTR */
2420 #define WM5100_AIF1TX_LRCLK_MSTR_MASK           0x0001  /* AIF1TX_LRCLK_MSTR */
2421 #define WM5100_AIF1TX_LRCLK_MSTR_SHIFT               0  /* AIF1TX_LRCLK_MSTR */
2422 #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH               1  /* AIF1TX_LRCLK_MSTR */
2423 
2424 /*
2425  * R1282 (0x502) - Audio IF 1_3
2426  */
2427 #define WM5100_AIF1RX_LRCLK_INV                 0x0004  /* AIF1RX_LRCLK_INV */
2428 #define WM5100_AIF1RX_LRCLK_INV_MASK            0x0004  /* AIF1RX_LRCLK_INV */
2429 #define WM5100_AIF1RX_LRCLK_INV_SHIFT                2  /* AIF1RX_LRCLK_INV */
2430 #define WM5100_AIF1RX_LRCLK_INV_WIDTH                1  /* AIF1RX_LRCLK_INV */
2431 #define WM5100_AIF1RX_LRCLK_FRC                 0x0002  /* AIF1RX_LRCLK_FRC */
2432 #define WM5100_AIF1RX_LRCLK_FRC_MASK            0x0002  /* AIF1RX_LRCLK_FRC */
2433 #define WM5100_AIF1RX_LRCLK_FRC_SHIFT                1  /* AIF1RX_LRCLK_FRC */
2434 #define WM5100_AIF1RX_LRCLK_FRC_WIDTH                1  /* AIF1RX_LRCLK_FRC */
2435 #define WM5100_AIF1RX_LRCLK_MSTR                0x0001  /* AIF1RX_LRCLK_MSTR */
2436 #define WM5100_AIF1RX_LRCLK_MSTR_MASK           0x0001  /* AIF1RX_LRCLK_MSTR */
2437 #define WM5100_AIF1RX_LRCLK_MSTR_SHIFT               0  /* AIF1RX_LRCLK_MSTR */
2438 #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH               1  /* AIF1RX_LRCLK_MSTR */
2439 
2440 /*
2441  * R1283 (0x503) - Audio IF 1_4
2442  */
2443 #define WM5100_AIF1_TRI                         0x0040  /* AIF1_TRI */
2444 #define WM5100_AIF1_TRI_MASK                    0x0040  /* AIF1_TRI */
2445 #define WM5100_AIF1_TRI_SHIFT                        6  /* AIF1_TRI */
2446 #define WM5100_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
2447 #define WM5100_AIF1_RATE_MASK                   0x0003  /* AIF1_RATE - [1:0] */
2448 #define WM5100_AIF1_RATE_SHIFT                       0  /* AIF1_RATE - [1:0] */
2449 #define WM5100_AIF1_RATE_WIDTH                       2  /* AIF1_RATE - [1:0] */
2450 
2451 /*
2452  * R1284 (0x504) - Audio IF 1_5
2453  */
2454 #define WM5100_AIF1_FMT_MASK                    0x0007  /* AIF1_FMT - [2:0] */
2455 #define WM5100_AIF1_FMT_SHIFT                        0  /* AIF1_FMT - [2:0] */
2456 #define WM5100_AIF1_FMT_WIDTH                        3  /* AIF1_FMT - [2:0] */
2457 
2458 /*
2459  * R1285 (0x505) - Audio IF 1_6
2460  */
2461 #define WM5100_AIF1TX_BCPF_MASK                 0x1FFF  /* AIF1TX_BCPF - [12:0] */
2462 #define WM5100_AIF1TX_BCPF_SHIFT                     0  /* AIF1TX_BCPF - [12:0] */
2463 #define WM5100_AIF1TX_BCPF_WIDTH                    13  /* AIF1TX_BCPF - [12:0] */
2464 
2465 /*
2466  * R1286 (0x506) - Audio IF 1_7
2467  */
2468 #define WM5100_AIF1RX_BCPF_MASK                 0x1FFF  /* AIF1RX_BCPF - [12:0] */
2469 #define WM5100_AIF1RX_BCPF_SHIFT                     0  /* AIF1RX_BCPF - [12:0] */
2470 #define WM5100_AIF1RX_BCPF_WIDTH                    13  /* AIF1RX_BCPF - [12:0] */
2471 
2472 /*
2473  * R1287 (0x507) - Audio IF 1_8
2474  */
2475 #define WM5100_AIF1TX_WL_MASK                   0x3F00  /* AIF1TX_WL - [13:8] */
2476 #define WM5100_AIF1TX_WL_SHIFT                       8  /* AIF1TX_WL - [13:8] */
2477 #define WM5100_AIF1TX_WL_WIDTH                       6  /* AIF1TX_WL - [13:8] */
2478 #define WM5100_AIF1TX_SLOT_LEN_MASK             0x00FF  /* AIF1TX_SLOT_LEN - [7:0] */
2479 #define WM5100_AIF1TX_SLOT_LEN_SHIFT                 0  /* AIF1TX_SLOT_LEN - [7:0] */
2480 #define WM5100_AIF1TX_SLOT_LEN_WIDTH                 8  /* AIF1TX_SLOT_LEN - [7:0] */
2481 
2482 /*
2483  * R1288 (0x508) - Audio IF 1_9
2484  */
2485 #define WM5100_AIF1RX_WL_MASK                   0x3F00  /* AIF1RX_WL - [13:8] */
2486 #define WM5100_AIF1RX_WL_SHIFT                       8  /* AIF1RX_WL - [13:8] */
2487 #define WM5100_AIF1RX_WL_WIDTH                       6  /* AIF1RX_WL - [13:8] */
2488 #define WM5100_AIF1RX_SLOT_LEN_MASK             0x00FF  /* AIF1RX_SLOT_LEN - [7:0] */
2489 #define WM5100_AIF1RX_SLOT_LEN_SHIFT                 0  /* AIF1RX_SLOT_LEN - [7:0] */
2490 #define WM5100_AIF1RX_SLOT_LEN_WIDTH                 8  /* AIF1RX_SLOT_LEN - [7:0] */
2491 
2492 /*
2493  * R1289 (0x509) - Audio IF 1_10
2494  */
2495 #define WM5100_AIF1TX1_SLOT_MASK                0x003F  /* AIF1TX1_SLOT - [5:0] */
2496 #define WM5100_AIF1TX1_SLOT_SHIFT                    0  /* AIF1TX1_SLOT - [5:0] */
2497 #define WM5100_AIF1TX1_SLOT_WIDTH                    6  /* AIF1TX1_SLOT - [5:0] */
2498 
2499 /*
2500  * R1290 (0x50A) - Audio IF 1_11
2501  */
2502 #define WM5100_AIF1TX2_SLOT_MASK                0x003F  /* AIF1TX2_SLOT - [5:0] */
2503 #define WM5100_AIF1TX2_SLOT_SHIFT                    0  /* AIF1TX2_SLOT - [5:0] */
2504 #define WM5100_AIF1TX2_SLOT_WIDTH                    6  /* AIF1TX2_SLOT - [5:0] */
2505 
2506 /*
2507  * R1291 (0x50B) - Audio IF 1_12
2508  */
2509 #define WM5100_AIF1TX3_SLOT_MASK                0x003F  /* AIF1TX3_SLOT - [5:0] */
2510 #define WM5100_AIF1TX3_SLOT_SHIFT                    0  /* AIF1TX3_SLOT - [5:0] */
2511 #define WM5100_AIF1TX3_SLOT_WIDTH                    6  /* AIF1TX3_SLOT - [5:0] */
2512 
2513 /*
2514  * R1292 (0x50C) - Audio IF 1_13
2515  */
2516 #define WM5100_AIF1TX4_SLOT_MASK                0x003F  /* AIF1TX4_SLOT - [5:0] */
2517 #define WM5100_AIF1TX4_SLOT_SHIFT                    0  /* AIF1TX4_SLOT - [5:0] */
2518 #define WM5100_AIF1TX4_SLOT_WIDTH                    6  /* AIF1TX4_SLOT - [5:0] */
2519 
2520 /*
2521  * R1293 (0x50D) - Audio IF 1_14
2522  */
2523 #define WM5100_AIF1TX5_SLOT_MASK                0x003F  /* AIF1TX5_SLOT - [5:0] */
2524 #define WM5100_AIF1TX5_SLOT_SHIFT                    0  /* AIF1TX5_SLOT - [5:0] */
2525 #define WM5100_AIF1TX5_SLOT_WIDTH                    6  /* AIF1TX5_SLOT - [5:0] */
2526 
2527 /*
2528  * R1294 (0x50E) - Audio IF 1_15
2529  */
2530 #define WM5100_AIF1TX6_SLOT_MASK                0x003F  /* AIF1TX6_SLOT - [5:0] */
2531 #define WM5100_AIF1TX6_SLOT_SHIFT                    0  /* AIF1TX6_SLOT - [5:0] */
2532 #define WM5100_AIF1TX6_SLOT_WIDTH                    6  /* AIF1TX6_SLOT - [5:0] */
2533 
2534 /*
2535  * R1295 (0x50F) - Audio IF 1_16
2536  */
2537 #define WM5100_AIF1TX7_SLOT_MASK                0x003F  /* AIF1TX7_SLOT - [5:0] */
2538 #define WM5100_AIF1TX7_SLOT_SHIFT                    0  /* AIF1TX7_SLOT - [5:0] */
2539 #define WM5100_AIF1TX7_SLOT_WIDTH                    6  /* AIF1TX7_SLOT - [5:0] */
2540 
2541 /*
2542  * R1296 (0x510) - Audio IF 1_17
2543  */
2544 #define WM5100_AIF1TX8_SLOT_MASK                0x003F  /* AIF1TX8_SLOT - [5:0] */
2545 #define WM5100_AIF1TX8_SLOT_SHIFT                    0  /* AIF1TX8_SLOT - [5:0] */
2546 #define WM5100_AIF1TX8_SLOT_WIDTH                    6  /* AIF1TX8_SLOT - [5:0] */
2547 
2548 /*
2549  * R1297 (0x511) - Audio IF 1_18
2550  */
2551 #define WM5100_AIF1RX1_SLOT_MASK                0x003F  /* AIF1RX1_SLOT - [5:0] */
2552 #define WM5100_AIF1RX1_SLOT_SHIFT                    0  /* AIF1RX1_SLOT - [5:0] */
2553 #define WM5100_AIF1RX1_SLOT_WIDTH                    6  /* AIF1RX1_SLOT - [5:0] */
2554 
2555 /*
2556  * R1298 (0x512) - Audio IF 1_19
2557  */
2558 #define WM5100_AIF1RX2_SLOT_MASK                0x003F  /* AIF1RX2_SLOT - [5:0] */
2559 #define WM5100_AIF1RX2_SLOT_SHIFT                    0  /* AIF1RX2_SLOT - [5:0] */
2560 #define WM5100_AIF1RX2_SLOT_WIDTH                    6  /* AIF1RX2_SLOT - [5:0] */
2561 
2562 /*
2563  * R1299 (0x513) - Audio IF 1_20
2564  */
2565 #define WM5100_AIF1RX3_SLOT_MASK                0x003F  /* AIF1RX3_SLOT - [5:0] */
2566 #define WM5100_AIF1RX3_SLOT_SHIFT                    0  /* AIF1RX3_SLOT - [5:0] */
2567 #define WM5100_AIF1RX3_SLOT_WIDTH                    6  /* AIF1RX3_SLOT - [5:0] */
2568 
2569 /*
2570  * R1300 (0x514) - Audio IF 1_21
2571  */
2572 #define WM5100_AIF1RX4_SLOT_MASK                0x003F  /* AIF1RX4_SLOT - [5:0] */
2573 #define WM5100_AIF1RX4_SLOT_SHIFT                    0  /* AIF1RX4_SLOT - [5:0] */
2574 #define WM5100_AIF1RX4_SLOT_WIDTH                    6  /* AIF1RX4_SLOT - [5:0] */
2575 
2576 /*
2577  * R1301 (0x515) - Audio IF 1_22
2578  */
2579 #define WM5100_AIF1RX5_SLOT_MASK                0x003F  /* AIF1RX5_SLOT - [5:0] */
2580 #define WM5100_AIF1RX5_SLOT_SHIFT                    0  /* AIF1RX5_SLOT - [5:0] */
2581 #define WM5100_AIF1RX5_SLOT_WIDTH                    6  /* AIF1RX5_SLOT - [5:0] */
2582 
2583 /*
2584  * R1302 (0x516) - Audio IF 1_23
2585  */
2586 #define WM5100_AIF1RX6_SLOT_MASK                0x003F  /* AIF1RX6_SLOT - [5:0] */
2587 #define WM5100_AIF1RX6_SLOT_SHIFT                    0  /* AIF1RX6_SLOT - [5:0] */
2588 #define WM5100_AIF1RX6_SLOT_WIDTH                    6  /* AIF1RX6_SLOT - [5:0] */
2589 
2590 /*
2591  * R1303 (0x517) - Audio IF 1_24
2592  */
2593 #define WM5100_AIF1RX7_SLOT_MASK                0x003F  /* AIF1RX7_SLOT - [5:0] */
2594 #define WM5100_AIF1RX7_SLOT_SHIFT                    0  /* AIF1RX7_SLOT - [5:0] */
2595 #define WM5100_AIF1RX7_SLOT_WIDTH                    6  /* AIF1RX7_SLOT - [5:0] */
2596 
2597 /*
2598  * R1304 (0x518) - Audio IF 1_25
2599  */
2600 #define WM5100_AIF1RX8_SLOT_MASK                0x003F  /* AIF1RX8_SLOT - [5:0] */
2601 #define WM5100_AIF1RX8_SLOT_SHIFT                    0  /* AIF1RX8_SLOT - [5:0] */
2602 #define WM5100_AIF1RX8_SLOT_WIDTH                    6  /* AIF1RX8_SLOT - [5:0] */
2603 
2604 /*
2605  * R1305 (0x519) - Audio IF 1_26
2606  */
2607 #define WM5100_AIF1TX8_ENA                      0x0080  /* AIF1TX8_ENA */
2608 #define WM5100_AIF1TX8_ENA_MASK                 0x0080  /* AIF1TX8_ENA */
2609 #define WM5100_AIF1TX8_ENA_SHIFT                     7  /* AIF1TX8_ENA */
2610 #define WM5100_AIF1TX8_ENA_WIDTH                     1  /* AIF1TX8_ENA */
2611 #define WM5100_AIF1TX7_ENA                      0x0040  /* AIF1TX7_ENA */
2612 #define WM5100_AIF1TX7_ENA_MASK                 0x0040  /* AIF1TX7_ENA */
2613 #define WM5100_AIF1TX7_ENA_SHIFT                     6  /* AIF1TX7_ENA */
2614 #define WM5100_AIF1TX7_ENA_WIDTH                     1  /* AIF1TX7_ENA */
2615 #define WM5100_AIF1TX6_ENA                      0x0020  /* AIF1TX6_ENA */
2616 #define WM5100_AIF1TX6_ENA_MASK                 0x0020  /* AIF1TX6_ENA */
2617 #define WM5100_AIF1TX6_ENA_SHIFT                     5  /* AIF1TX6_ENA */
2618 #define WM5100_AIF1TX6_ENA_WIDTH                     1  /* AIF1TX6_ENA */
2619 #define WM5100_AIF1TX5_ENA                      0x0010  /* AIF1TX5_ENA */
2620 #define WM5100_AIF1TX5_ENA_MASK                 0x0010  /* AIF1TX5_ENA */
2621 #define WM5100_AIF1TX5_ENA_SHIFT                     4  /* AIF1TX5_ENA */
2622 #define WM5100_AIF1TX5_ENA_WIDTH                     1  /* AIF1TX5_ENA */
2623 #define WM5100_AIF1TX4_ENA                      0x0008  /* AIF1TX4_ENA */
2624 #define WM5100_AIF1TX4_ENA_MASK                 0x0008  /* AIF1TX4_ENA */
2625 #define WM5100_AIF1TX4_ENA_SHIFT                     3  /* AIF1TX4_ENA */
2626 #define WM5100_AIF1TX4_ENA_WIDTH                     1  /* AIF1TX4_ENA */
2627 #define WM5100_AIF1TX3_ENA                      0x0004  /* AIF1TX3_ENA */
2628 #define WM5100_AIF1TX3_ENA_MASK                 0x0004  /* AIF1TX3_ENA */
2629 #define WM5100_AIF1TX3_ENA_SHIFT                     2  /* AIF1TX3_ENA */
2630 #define WM5100_AIF1TX3_ENA_WIDTH                     1  /* AIF1TX3_ENA */
2631 #define WM5100_AIF1TX2_ENA                      0x0002  /* AIF1TX2_ENA */
2632 #define WM5100_AIF1TX2_ENA_MASK                 0x0002  /* AIF1TX2_ENA */
2633 #define WM5100_AIF1TX2_ENA_SHIFT                     1  /* AIF1TX2_ENA */
2634 #define WM5100_AIF1TX2_ENA_WIDTH                     1  /* AIF1TX2_ENA */
2635 #define WM5100_AIF1TX1_ENA                      0x0001  /* AIF1TX1_ENA */
2636 #define WM5100_AIF1TX1_ENA_MASK                 0x0001  /* AIF1TX1_ENA */
2637 #define WM5100_AIF1TX1_ENA_SHIFT                     0  /* AIF1TX1_ENA */
2638 #define WM5100_AIF1TX1_ENA_WIDTH                     1  /* AIF1TX1_ENA */
2639 
2640 /*
2641  * R1306 (0x51A) - Audio IF 1_27
2642  */
2643 #define WM5100_AIF1RX8_ENA                      0x0080  /* AIF1RX8_ENA */
2644 #define WM5100_AIF1RX8_ENA_MASK                 0x0080  /* AIF1RX8_ENA */
2645 #define WM5100_AIF1RX8_ENA_SHIFT                     7  /* AIF1RX8_ENA */
2646 #define WM5100_AIF1RX8_ENA_WIDTH                     1  /* AIF1RX8_ENA */
2647 #define WM5100_AIF1RX7_ENA                      0x0040  /* AIF1RX7_ENA */
2648 #define WM5100_AIF1RX7_ENA_MASK                 0x0040  /* AIF1RX7_ENA */
2649 #define WM5100_AIF1RX7_ENA_SHIFT                     6  /* AIF1RX7_ENA */
2650 #define WM5100_AIF1RX7_ENA_WIDTH                     1  /* AIF1RX7_ENA */
2651 #define WM5100_AIF1RX6_ENA                      0x0020  /* AIF1RX6_ENA */
2652 #define WM5100_AIF1RX6_ENA_MASK                 0x0020  /* AIF1RX6_ENA */
2653 #define WM5100_AIF1RX6_ENA_SHIFT                     5  /* AIF1RX6_ENA */
2654 #define WM5100_AIF1RX6_ENA_WIDTH                     1  /* AIF1RX6_ENA */
2655 #define WM5100_AIF1RX5_ENA                      0x0010  /* AIF1RX5_ENA */
2656 #define WM5100_AIF1RX5_ENA_MASK                 0x0010  /* AIF1RX5_ENA */
2657 #define WM5100_AIF1RX5_ENA_SHIFT                     4  /* AIF1RX5_ENA */
2658 #define WM5100_AIF1RX5_ENA_WIDTH                     1  /* AIF1RX5_ENA */
2659 #define WM5100_AIF1RX4_ENA                      0x0008  /* AIF1RX4_ENA */
2660 #define WM5100_AIF1RX4_ENA_MASK                 0x0008  /* AIF1RX4_ENA */
2661 #define WM5100_AIF1RX4_ENA_SHIFT                     3  /* AIF1RX4_ENA */
2662 #define WM5100_AIF1RX4_ENA_WIDTH                     1  /* AIF1RX4_ENA */
2663 #define WM5100_AIF1RX3_ENA                      0x0004  /* AIF1RX3_ENA */
2664 #define WM5100_AIF1RX3_ENA_MASK                 0x0004  /* AIF1RX3_ENA */
2665 #define WM5100_AIF1RX3_ENA_SHIFT                     2  /* AIF1RX3_ENA */
2666 #define WM5100_AIF1RX3_ENA_WIDTH                     1  /* AIF1RX3_ENA */
2667 #define WM5100_AIF1RX2_ENA                      0x0002  /* AIF1RX2_ENA */
2668 #define WM5100_AIF1RX2_ENA_MASK                 0x0002  /* AIF1RX2_ENA */
2669 #define WM5100_AIF1RX2_ENA_SHIFT                     1  /* AIF1RX2_ENA */
2670 #define WM5100_AIF1RX2_ENA_WIDTH                     1  /* AIF1RX2_ENA */
2671 #define WM5100_AIF1RX1_ENA                      0x0001  /* AIF1RX1_ENA */
2672 #define WM5100_AIF1RX1_ENA_MASK                 0x0001  /* AIF1RX1_ENA */
2673 #define WM5100_AIF1RX1_ENA_SHIFT                     0  /* AIF1RX1_ENA */
2674 #define WM5100_AIF1RX1_ENA_WIDTH                     1  /* AIF1RX1_ENA */
2675 
2676 /*
2677  * R1344 (0x540) - Audio IF 2_1
2678  */
2679 #define WM5100_AIF2_BCLK_INV                    0x0080  /* AIF2_BCLK_INV */
2680 #define WM5100_AIF2_BCLK_INV_MASK               0x0080  /* AIF2_BCLK_INV */
2681 #define WM5100_AIF2_BCLK_INV_SHIFT                   7  /* AIF2_BCLK_INV */
2682 #define WM5100_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
2683 #define WM5100_AIF2_BCLK_FRC                    0x0040  /* AIF2_BCLK_FRC */
2684 #define WM5100_AIF2_BCLK_FRC_MASK               0x0040  /* AIF2_BCLK_FRC */
2685 #define WM5100_AIF2_BCLK_FRC_SHIFT                   6  /* AIF2_BCLK_FRC */
2686 #define WM5100_AIF2_BCLK_FRC_WIDTH                   1  /* AIF2_BCLK_FRC */
2687 #define WM5100_AIF2_BCLK_MSTR                   0x0020  /* AIF2_BCLK_MSTR */
2688 #define WM5100_AIF2_BCLK_MSTR_MASK              0x0020  /* AIF2_BCLK_MSTR */
2689 #define WM5100_AIF2_BCLK_MSTR_SHIFT                  5  /* AIF2_BCLK_MSTR */
2690 #define WM5100_AIF2_BCLK_MSTR_WIDTH                  1  /* AIF2_BCLK_MSTR */
2691 #define WM5100_AIF2_BCLK_FREQ_MASK              0x001F  /* AIF2_BCLK_FREQ - [4:0] */
2692 #define WM5100_AIF2_BCLK_FREQ_SHIFT                  0  /* AIF2_BCLK_FREQ - [4:0] */
2693 #define WM5100_AIF2_BCLK_FREQ_WIDTH                  5  /* AIF2_BCLK_FREQ - [4:0] */
2694 
2695 /*
2696  * R1345 (0x541) - Audio IF 2_2
2697  */
2698 #define WM5100_AIF2TX_DAT_TRI                   0x0020  /* AIF2TX_DAT_TRI */
2699 #define WM5100_AIF2TX_DAT_TRI_MASK              0x0020  /* AIF2TX_DAT_TRI */
2700 #define WM5100_AIF2TX_DAT_TRI_SHIFT                  5  /* AIF2TX_DAT_TRI */
2701 #define WM5100_AIF2TX_DAT_TRI_WIDTH                  1  /* AIF2TX_DAT_TRI */
2702 #define WM5100_AIF2TX_LRCLK_SRC                 0x0008  /* AIF2TX_LRCLK_SRC */
2703 #define WM5100_AIF2TX_LRCLK_SRC_MASK            0x0008  /* AIF2TX_LRCLK_SRC */
2704 #define WM5100_AIF2TX_LRCLK_SRC_SHIFT                3  /* AIF2TX_LRCLK_SRC */
2705 #define WM5100_AIF2TX_LRCLK_SRC_WIDTH                1  /* AIF2TX_LRCLK_SRC */
2706 #define WM5100_AIF2TX_LRCLK_INV                 0x0004  /* AIF2TX_LRCLK_INV */
2707 #define WM5100_AIF2TX_LRCLK_INV_MASK            0x0004  /* AIF2TX_LRCLK_INV */
2708 #define WM5100_AIF2TX_LRCLK_INV_SHIFT                2  /* AIF2TX_LRCLK_INV */
2709 #define WM5100_AIF2TX_LRCLK_INV_WIDTH                1  /* AIF2TX_LRCLK_INV */
2710 #define WM5100_AIF2TX_LRCLK_FRC                 0x0002  /* AIF2TX_LRCLK_FRC */
2711 #define WM5100_AIF2TX_LRCLK_FRC_MASK            0x0002  /* AIF2TX_LRCLK_FRC */
2712 #define WM5100_AIF2TX_LRCLK_FRC_SHIFT                1  /* AIF2TX_LRCLK_FRC */
2713 #define WM5100_AIF2TX_LRCLK_FRC_WIDTH                1  /* AIF2TX_LRCLK_FRC */
2714 #define WM5100_AIF2TX_LRCLK_MSTR                0x0001  /* AIF2TX_LRCLK_MSTR */
2715 #define WM5100_AIF2TX_LRCLK_MSTR_MASK           0x0001  /* AIF2TX_LRCLK_MSTR */
2716 #define WM5100_AIF2TX_LRCLK_MSTR_SHIFT               0  /* AIF2TX_LRCLK_MSTR */
2717 #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH               1  /* AIF2TX_LRCLK_MSTR */
2718 
2719 /*
2720  * R1346 (0x542) - Audio IF 2_3
2721  */
2722 #define WM5100_AIF2RX_LRCLK_INV                 0x0004  /* AIF2RX_LRCLK_INV */
2723 #define WM5100_AIF2RX_LRCLK_INV_MASK            0x0004  /* AIF2RX_LRCLK_INV */
2724 #define WM5100_AIF2RX_LRCLK_INV_SHIFT                2  /* AIF2RX_LRCLK_INV */
2725 #define WM5100_AIF2RX_LRCLK_INV_WIDTH                1  /* AIF2RX_LRCLK_INV */
2726 #define WM5100_AIF2RX_LRCLK_FRC                 0x0002  /* AIF2RX_LRCLK_FRC */
2727 #define WM5100_AIF2RX_LRCLK_FRC_MASK            0x0002  /* AIF2RX_LRCLK_FRC */
2728 #define WM5100_AIF2RX_LRCLK_FRC_SHIFT                1  /* AIF2RX_LRCLK_FRC */
2729 #define WM5100_AIF2RX_LRCLK_FRC_WIDTH                1  /* AIF2RX_LRCLK_FRC */
2730 #define WM5100_AIF2RX_LRCLK_MSTR                0x0001  /* AIF2RX_LRCLK_MSTR */
2731 #define WM5100_AIF2RX_LRCLK_MSTR_MASK           0x0001  /* AIF2RX_LRCLK_MSTR */
2732 #define WM5100_AIF2RX_LRCLK_MSTR_SHIFT               0  /* AIF2RX_LRCLK_MSTR */
2733 #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH               1  /* AIF2RX_LRCLK_MSTR */
2734 
2735 /*
2736  * R1347 (0x543) - Audio IF 2_4
2737  */
2738 #define WM5100_AIF2_TRI                         0x0040  /* AIF2_TRI */
2739 #define WM5100_AIF2_TRI_MASK                    0x0040  /* AIF2_TRI */
2740 #define WM5100_AIF2_TRI_SHIFT                        6  /* AIF2_TRI */
2741 #define WM5100_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
2742 #define WM5100_AIF2_RATE_MASK                   0x0003  /* AIF2_RATE - [1:0] */
2743 #define WM5100_AIF2_RATE_SHIFT                       0  /* AIF2_RATE - [1:0] */
2744 #define WM5100_AIF2_RATE_WIDTH                       2  /* AIF2_RATE - [1:0] */
2745 
2746 /*
2747  * R1348 (0x544) - Audio IF 2_5
2748  */
2749 #define WM5100_AIF2_FMT_MASK                    0x0007  /* AIF2_FMT - [2:0] */
2750 #define WM5100_AIF2_FMT_SHIFT                        0  /* AIF2_FMT - [2:0] */
2751 #define WM5100_AIF2_FMT_WIDTH                        3  /* AIF2_FMT - [2:0] */
2752 
2753 /*
2754  * R1349 (0x545) - Audio IF 2_6
2755  */
2756 #define WM5100_AIF2TX_BCPF_MASK                 0x1FFF  /* AIF2TX_BCPF - [12:0] */
2757 #define WM5100_AIF2TX_BCPF_SHIFT                     0  /* AIF2TX_BCPF - [12:0] */
2758 #define WM5100_AIF2TX_BCPF_WIDTH                    13  /* AIF2TX_BCPF - [12:0] */
2759 
2760 /*
2761  * R1350 (0x546) - Audio IF 2_7
2762  */
2763 #define WM5100_AIF2RX_BCPF_MASK                 0x1FFF  /* AIF2RX_BCPF - [12:0] */
2764 #define WM5100_AIF2RX_BCPF_SHIFT                     0  /* AIF2RX_BCPF - [12:0] */
2765 #define WM5100_AIF2RX_BCPF_WIDTH                    13  /* AIF2RX_BCPF - [12:0] */
2766 
2767 /*
2768  * R1351 (0x547) - Audio IF 2_8
2769  */
2770 #define WM5100_AIF2TX_WL_MASK                   0x3F00  /* AIF2TX_WL - [13:8] */
2771 #define WM5100_AIF2TX_WL_SHIFT                       8  /* AIF2TX_WL - [13:8] */
2772 #define WM5100_AIF2TX_WL_WIDTH                       6  /* AIF2TX_WL - [13:8] */
2773 #define WM5100_AIF2TX_SLOT_LEN_MASK             0x00FF  /* AIF2TX_SLOT_LEN - [7:0] */
2774 #define WM5100_AIF2TX_SLOT_LEN_SHIFT                 0  /* AIF2TX_SLOT_LEN - [7:0] */
2775 #define WM5100_AIF2TX_SLOT_LEN_WIDTH                 8  /* AIF2TX_SLOT_LEN - [7:0] */
2776 
2777 /*
2778  * R1352 (0x548) - Audio IF 2_9
2779  */
2780 #define WM5100_AIF2RX_WL_MASK                   0x3F00  /* AIF2RX_WL - [13:8] */
2781 #define WM5100_AIF2RX_WL_SHIFT                       8  /* AIF2RX_WL - [13:8] */
2782 #define WM5100_AIF2RX_WL_WIDTH                       6  /* AIF2RX_WL - [13:8] */
2783 #define WM5100_AIF2RX_SLOT_LEN_MASK             0x00FF  /* AIF2RX_SLOT_LEN - [7:0] */
2784 #define WM5100_AIF2RX_SLOT_LEN_SHIFT                 0  /* AIF2RX_SLOT_LEN - [7:0] */
2785 #define WM5100_AIF2RX_SLOT_LEN_WIDTH                 8  /* AIF2RX_SLOT_LEN - [7:0] */
2786 
2787 /*
2788  * R1353 (0x549) - Audio IF 2_10
2789  */
2790 #define WM5100_AIF2TX1_SLOT_MASK                0x003F  /* AIF2TX1_SLOT - [5:0] */
2791 #define WM5100_AIF2TX1_SLOT_SHIFT                    0  /* AIF2TX1_SLOT - [5:0] */
2792 #define WM5100_AIF2TX1_SLOT_WIDTH                    6  /* AIF2TX1_SLOT - [5:0] */
2793 
2794 /*
2795  * R1354 (0x54A) - Audio IF 2_11
2796  */
2797 #define WM5100_AIF2TX2_SLOT_MASK                0x003F  /* AIF2TX2_SLOT - [5:0] */
2798 #define WM5100_AIF2TX2_SLOT_SHIFT                    0  /* AIF2TX2_SLOT - [5:0] */
2799 #define WM5100_AIF2TX2_SLOT_WIDTH                    6  /* AIF2TX2_SLOT - [5:0] */
2800 
2801 /*
2802  * R1361 (0x551) - Audio IF 2_18
2803  */
2804 #define WM5100_AIF2RX1_SLOT_MASK                0x003F  /* AIF2RX1_SLOT - [5:0] */
2805 #define WM5100_AIF2RX1_SLOT_SHIFT                    0  /* AIF2RX1_SLOT - [5:0] */
2806 #define WM5100_AIF2RX1_SLOT_WIDTH                    6  /* AIF2RX1_SLOT - [5:0] */
2807 
2808 /*
2809  * R1362 (0x552) - Audio IF 2_19
2810  */
2811 #define WM5100_AIF2RX2_SLOT_MASK                0x003F  /* AIF2RX2_SLOT - [5:0] */
2812 #define WM5100_AIF2RX2_SLOT_SHIFT                    0  /* AIF2RX2_SLOT - [5:0] */
2813 #define WM5100_AIF2RX2_SLOT_WIDTH                    6  /* AIF2RX2_SLOT - [5:0] */
2814 
2815 /*
2816  * R1369 (0x559) - Audio IF 2_26
2817  */
2818 #define WM5100_AIF2TX2_ENA                      0x0002  /* AIF2TX2_ENA */
2819 #define WM5100_AIF2TX2_ENA_MASK                 0x0002  /* AIF2TX2_ENA */
2820 #define WM5100_AIF2TX2_ENA_SHIFT                     1  /* AIF2TX2_ENA */
2821 #define WM5100_AIF2TX2_ENA_WIDTH                     1  /* AIF2TX2_ENA */
2822 #define WM5100_AIF2TX1_ENA                      0x0001  /* AIF2TX1_ENA */
2823 #define WM5100_AIF2TX1_ENA_MASK                 0x0001  /* AIF2TX1_ENA */
2824 #define WM5100_AIF2TX1_ENA_SHIFT                     0  /* AIF2TX1_ENA */
2825 #define WM5100_AIF2TX1_ENA_WIDTH                     1  /* AIF2TX1_ENA */
2826 
2827 /*
2828  * R1370 (0x55A) - Audio IF 2_27
2829  */
2830 #define WM5100_AIF2RX2_ENA                      0x0002  /* AIF2RX2_ENA */
2831 #define WM5100_AIF2RX2_ENA_MASK                 0x0002  /* AIF2RX2_ENA */
2832 #define WM5100_AIF2RX2_ENA_SHIFT                     1  /* AIF2RX2_ENA */
2833 #define WM5100_AIF2RX2_ENA_WIDTH                     1  /* AIF2RX2_ENA */
2834 #define WM5100_AIF2RX1_ENA                      0x0001  /* AIF2RX1_ENA */
2835 #define WM5100_AIF2RX1_ENA_MASK                 0x0001  /* AIF2RX1_ENA */
2836 #define WM5100_AIF2RX1_ENA_SHIFT                     0  /* AIF2RX1_ENA */
2837 #define WM5100_AIF2RX1_ENA_WIDTH                     1  /* AIF2RX1_ENA */
2838 
2839 /*
2840  * R1408 (0x580) - Audio IF 3_1
2841  */
2842 #define WM5100_AIF3_BCLK_INV                    0x0080  /* AIF3_BCLK_INV */
2843 #define WM5100_AIF3_BCLK_INV_MASK               0x0080  /* AIF3_BCLK_INV */
2844 #define WM5100_AIF3_BCLK_INV_SHIFT                   7  /* AIF3_BCLK_INV */
2845 #define WM5100_AIF3_BCLK_INV_WIDTH                   1  /* AIF3_BCLK_INV */
2846 #define WM5100_AIF3_BCLK_FRC                    0x0040  /* AIF3_BCLK_FRC */
2847 #define WM5100_AIF3_BCLK_FRC_MASK               0x0040  /* AIF3_BCLK_FRC */
2848 #define WM5100_AIF3_BCLK_FRC_SHIFT                   6  /* AIF3_BCLK_FRC */
2849 #define WM5100_AIF3_BCLK_FRC_WIDTH                   1  /* AIF3_BCLK_FRC */
2850 #define WM5100_AIF3_BCLK_MSTR                   0x0020  /* AIF3_BCLK_MSTR */
2851 #define WM5100_AIF3_BCLK_MSTR_MASK              0x0020  /* AIF3_BCLK_MSTR */
2852 #define WM5100_AIF3_BCLK_MSTR_SHIFT                  5  /* AIF3_BCLK_MSTR */
2853 #define WM5100_AIF3_BCLK_MSTR_WIDTH                  1  /* AIF3_BCLK_MSTR */
2854 #define WM5100_AIF3_BCLK_FREQ_MASK              0x001F  /* AIF3_BCLK_FREQ - [4:0] */
2855 #define WM5100_AIF3_BCLK_FREQ_SHIFT                  0  /* AIF3_BCLK_FREQ - [4:0] */
2856 #define WM5100_AIF3_BCLK_FREQ_WIDTH                  5  /* AIF3_BCLK_FREQ - [4:0] */
2857 
2858 /*
2859  * R1409 (0x581) - Audio IF 3_2
2860  */
2861 #define WM5100_AIF3TX_DAT_TRI                   0x0020  /* AIF3TX_DAT_TRI */
2862 #define WM5100_AIF3TX_DAT_TRI_MASK              0x0020  /* AIF3TX_DAT_TRI */
2863 #define WM5100_AIF3TX_DAT_TRI_SHIFT                  5  /* AIF3TX_DAT_TRI */
2864 #define WM5100_AIF3TX_DAT_TRI_WIDTH                  1  /* AIF3TX_DAT_TRI */
2865 #define WM5100_AIF3TX_LRCLK_SRC                 0x0008  /* AIF3TX_LRCLK_SRC */
2866 #define WM5100_AIF3TX_LRCLK_SRC_MASK            0x0008  /* AIF3TX_LRCLK_SRC */
2867 #define WM5100_AIF3TX_LRCLK_SRC_SHIFT                3  /* AIF3TX_LRCLK_SRC */
2868 #define WM5100_AIF3TX_LRCLK_SRC_WIDTH                1  /* AIF3TX_LRCLK_SRC */
2869 #define WM5100_AIF3TX_LRCLK_INV                 0x0004  /* AIF3TX_LRCLK_INV */
2870 #define WM5100_AIF3TX_LRCLK_INV_MASK            0x0004  /* AIF3TX_LRCLK_INV */
2871 #define WM5100_AIF3TX_LRCLK_INV_SHIFT                2  /* AIF3TX_LRCLK_INV */
2872 #define WM5100_AIF3TX_LRCLK_INV_WIDTH                1  /* AIF3TX_LRCLK_INV */
2873 #define WM5100_AIF3TX_LRCLK_FRC                 0x0002  /* AIF3TX_LRCLK_FRC */
2874 #define WM5100_AIF3TX_LRCLK_FRC_MASK            0x0002  /* AIF3TX_LRCLK_FRC */
2875 #define WM5100_AIF3TX_LRCLK_FRC_SHIFT                1  /* AIF3TX_LRCLK_FRC */
2876 #define WM5100_AIF3TX_LRCLK_FRC_WIDTH                1  /* AIF3TX_LRCLK_FRC */
2877 #define WM5100_AIF3TX_LRCLK_MSTR                0x0001  /* AIF3TX_LRCLK_MSTR */
2878 #define WM5100_AIF3TX_LRCLK_MSTR_MASK           0x0001  /* AIF3TX_LRCLK_MSTR */
2879 #define WM5100_AIF3TX_LRCLK_MSTR_SHIFT               0  /* AIF3TX_LRCLK_MSTR */
2880 #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH               1  /* AIF3TX_LRCLK_MSTR */
2881 
2882 /*
2883  * R1410 (0x582) - Audio IF 3_3
2884  */
2885 #define WM5100_AIF3RX_LRCLK_INV                 0x0004  /* AIF3RX_LRCLK_INV */
2886 #define WM5100_AIF3RX_LRCLK_INV_MASK            0x0004  /* AIF3RX_LRCLK_INV */
2887 #define WM5100_AIF3RX_LRCLK_INV_SHIFT                2  /* AIF3RX_LRCLK_INV */
2888 #define WM5100_AIF3RX_LRCLK_INV_WIDTH                1  /* AIF3RX_LRCLK_INV */
2889 #define WM5100_AIF3RX_LRCLK_FRC                 0x0002  /* AIF3RX_LRCLK_FRC */
2890 #define WM5100_AIF3RX_LRCLK_FRC_MASK            0x0002  /* AIF3RX_LRCLK_FRC */
2891 #define WM5100_AIF3RX_LRCLK_FRC_SHIFT                1  /* AIF3RX_LRCLK_FRC */
2892 #define WM5100_AIF3RX_LRCLK_FRC_WIDTH                1  /* AIF3RX_LRCLK_FRC */
2893 #define WM5100_AIF3RX_LRCLK_MSTR                0x0001  /* AIF3RX_LRCLK_MSTR */
2894 #define WM5100_AIF3RX_LRCLK_MSTR_MASK           0x0001  /* AIF3RX_LRCLK_MSTR */
2895 #define WM5100_AIF3RX_LRCLK_MSTR_SHIFT               0  /* AIF3RX_LRCLK_MSTR */
2896 #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH               1  /* AIF3RX_LRCLK_MSTR */
2897 
2898 /*
2899  * R1411 (0x583) - Audio IF 3_4
2900  */
2901 #define WM5100_AIF3_TRI                         0x0040  /* AIF3_TRI */
2902 #define WM5100_AIF3_TRI_MASK                    0x0040  /* AIF3_TRI */
2903 #define WM5100_AIF3_TRI_SHIFT                        6  /* AIF3_TRI */
2904 #define WM5100_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
2905 #define WM5100_AIF3_RATE_MASK                   0x0003  /* AIF3_RATE - [1:0] */
2906 #define WM5100_AIF3_RATE_SHIFT                       0  /* AIF3_RATE - [1:0] */
2907 #define WM5100_AIF3_RATE_WIDTH                       2  /* AIF3_RATE - [1:0] */
2908 
2909 /*
2910  * R1412 (0x584) - Audio IF 3_5
2911  */
2912 #define WM5100_AIF3_FMT_MASK                    0x0007  /* AIF3_FMT - [2:0] */
2913 #define WM5100_AIF3_FMT_SHIFT                        0  /* AIF3_FMT - [2:0] */
2914 #define WM5100_AIF3_FMT_WIDTH                        3  /* AIF3_FMT - [2:0] */
2915 
2916 /*
2917  * R1413 (0x585) - Audio IF 3_6
2918  */
2919 #define WM5100_AIF3TX_BCPF_MASK                 0x1FFF  /* AIF3TX_BCPF - [12:0] */
2920 #define WM5100_AIF3TX_BCPF_SHIFT                     0  /* AIF3TX_BCPF - [12:0] */
2921 #define WM5100_AIF3TX_BCPF_WIDTH                    13  /* AIF3TX_BCPF - [12:0] */
2922 
2923 /*
2924  * R1414 (0x586) - Audio IF 3_7
2925  */
2926 #define WM5100_AIF3RX_BCPF_MASK                 0x1FFF  /* AIF3RX_BCPF - [12:0] */
2927 #define WM5100_AIF3RX_BCPF_SHIFT                     0  /* AIF3RX_BCPF - [12:0] */
2928 #define WM5100_AIF3RX_BCPF_WIDTH                    13  /* AIF3RX_BCPF - [12:0] */
2929 
2930 /*
2931  * R1415 (0x587) - Audio IF 3_8
2932  */
2933 #define WM5100_AIF3TX_WL_MASK                   0x3F00  /* AIF3TX_WL - [13:8] */
2934 #define WM5100_AIF3TX_WL_SHIFT                       8  /* AIF3TX_WL - [13:8] */
2935 #define WM5100_AIF3TX_WL_WIDTH                       6  /* AIF3TX_WL - [13:8] */
2936 #define WM5100_AIF3TX_SLOT_LEN_MASK             0x00FF  /* AIF3TX_SLOT_LEN - [7:0] */
2937 #define WM5100_AIF3TX_SLOT_LEN_SHIFT                 0  /* AIF3TX_SLOT_LEN - [7:0] */
2938 #define WM5100_AIF3TX_SLOT_LEN_WIDTH                 8  /* AIF3TX_SLOT_LEN - [7:0] */
2939 
2940 /*
2941  * R1416 (0x588) - Audio IF 3_9
2942  */
2943 #define WM5100_AIF3RX_WL_MASK                   0x3F00  /* AIF3RX_WL - [13:8] */
2944 #define WM5100_AIF3RX_WL_SHIFT                       8  /* AIF3RX_WL - [13:8] */
2945 #define WM5100_AIF3RX_WL_WIDTH                       6  /* AIF3RX_WL - [13:8] */
2946 #define WM5100_AIF3RX_SLOT_LEN_MASK             0x00FF  /* AIF3RX_SLOT_LEN - [7:0] */
2947 #define WM5100_AIF3RX_SLOT_LEN_SHIFT                 0  /* AIF3RX_SLOT_LEN - [7:0] */
2948 #define WM5100_AIF3RX_SLOT_LEN_WIDTH                 8  /* AIF3RX_SLOT_LEN - [7:0] */
2949 
2950 /*
2951  * R1417 (0x589) - Audio IF 3_10
2952  */
2953 #define WM5100_AIF3TX1_SLOT_MASK                0x003F  /* AIF3TX1_SLOT - [5:0] */
2954 #define WM5100_AIF3TX1_SLOT_SHIFT                    0  /* AIF3TX1_SLOT - [5:0] */
2955 #define WM5100_AIF3TX1_SLOT_WIDTH                    6  /* AIF3TX1_SLOT - [5:0] */
2956 
2957 /*
2958  * R1418 (0x58A) - Audio IF 3_11
2959  */
2960 #define WM5100_AIF3TX2_SLOT_MASK                0x003F  /* AIF3TX2_SLOT - [5:0] */
2961 #define WM5100_AIF3TX2_SLOT_SHIFT                    0  /* AIF3TX2_SLOT - [5:0] */
2962 #define WM5100_AIF3TX2_SLOT_WIDTH                    6  /* AIF3TX2_SLOT - [5:0] */
2963 
2964 /*
2965  * R1425 (0x591) - Audio IF 3_18
2966  */
2967 #define WM5100_AIF3RX1_SLOT_MASK                0x003F  /* AIF3RX1_SLOT - [5:0] */
2968 #define WM5100_AIF3RX1_SLOT_SHIFT                    0  /* AIF3RX1_SLOT - [5:0] */
2969 #define WM5100_AIF3RX1_SLOT_WIDTH                    6  /* AIF3RX1_SLOT - [5:0] */
2970 
2971 /*
2972  * R1426 (0x592) - Audio IF 3_19
2973  */
2974 #define WM5100_AIF3RX2_SLOT_MASK                0x003F  /* AIF3RX2_SLOT - [5:0] */
2975 #define WM5100_AIF3RX2_SLOT_SHIFT                    0  /* AIF3RX2_SLOT - [5:0] */
2976 #define WM5100_AIF3RX2_SLOT_WIDTH                    6  /* AIF3RX2_SLOT - [5:0] */
2977 
2978 /*
2979  * R1433 (0x599) - Audio IF 3_26
2980  */
2981 #define WM5100_AIF3TX2_ENA                      0x0002  /* AIF3TX2_ENA */
2982 #define WM5100_AIF3TX2_ENA_MASK                 0x0002  /* AIF3TX2_ENA */
2983 #define WM5100_AIF3TX2_ENA_SHIFT                     1  /* AIF3TX2_ENA */
2984 #define WM5100_AIF3TX2_ENA_WIDTH                     1  /* AIF3TX2_ENA */
2985 #define WM5100_AIF3TX1_ENA                      0x0001  /* AIF3TX1_ENA */
2986 #define WM5100_AIF3TX1_ENA_MASK                 0x0001  /* AIF3TX1_ENA */
2987 #define WM5100_AIF3TX1_ENA_SHIFT                     0  /* AIF3TX1_ENA */
2988 #define WM5100_AIF3TX1_ENA_WIDTH                     1  /* AIF3TX1_ENA */
2989 
2990 /*
2991  * R1434 (0x59A) - Audio IF 3_27
2992  */
2993 #define WM5100_AIF3RX2_ENA                      0x0002  /* AIF3RX2_ENA */
2994 #define WM5100_AIF3RX2_ENA_MASK                 0x0002  /* AIF3RX2_ENA */
2995 #define WM5100_AIF3RX2_ENA_SHIFT                     1  /* AIF3RX2_ENA */
2996 #define WM5100_AIF3RX2_ENA_WIDTH                     1  /* AIF3RX2_ENA */
2997 #define WM5100_AIF3RX1_ENA                      0x0001  /* AIF3RX1_ENA */
2998 #define WM5100_AIF3RX1_ENA_MASK                 0x0001  /* AIF3RX1_ENA */
2999 #define WM5100_AIF3RX1_ENA_SHIFT                     0  /* AIF3RX1_ENA */
3000 #define WM5100_AIF3RX1_ENA_WIDTH                     1  /* AIF3RX1_ENA */
3001 
3002 #define WM5100_MIXER_VOL_MASK                0x00FE  /* MIXER_VOL - [7:1] */
3003 #define WM5100_MIXER_VOL_SHIFT                    1  /* MIXER_VOL - [7:1] */
3004 #define WM5100_MIXER_VOL_WIDTH                    7  /* MIXER_VOL - [7:1] */
3005 
3006 /*
3007  * R3072 (0xC00) - GPIO CTRL 1
3008  */
3009 #define WM5100_GP1_DIR                          0x8000  /* GP1_DIR */
3010 #define WM5100_GP1_DIR_MASK                     0x8000  /* GP1_DIR */
3011 #define WM5100_GP1_DIR_SHIFT                        15  /* GP1_DIR */
3012 #define WM5100_GP1_DIR_WIDTH                         1  /* GP1_DIR */
3013 #define WM5100_GP1_PU                           0x4000  /* GP1_PU */
3014 #define WM5100_GP1_PU_MASK                      0x4000  /* GP1_PU */
3015 #define WM5100_GP1_PU_SHIFT                         14  /* GP1_PU */
3016 #define WM5100_GP1_PU_WIDTH                          1  /* GP1_PU */
3017 #define WM5100_GP1_PD                           0x2000  /* GP1_PD */
3018 #define WM5100_GP1_PD_MASK                      0x2000  /* GP1_PD */
3019 #define WM5100_GP1_PD_SHIFT                         13  /* GP1_PD */
3020 #define WM5100_GP1_PD_WIDTH                          1  /* GP1_PD */
3021 #define WM5100_GP1_POL                          0x0400  /* GP1_POL */
3022 #define WM5100_GP1_POL_MASK                     0x0400  /* GP1_POL */
3023 #define WM5100_GP1_POL_SHIFT                        10  /* GP1_POL */
3024 #define WM5100_GP1_POL_WIDTH                         1  /* GP1_POL */
3025 #define WM5100_GP1_OP_CFG                       0x0200  /* GP1_OP_CFG */
3026 #define WM5100_GP1_OP_CFG_MASK                  0x0200  /* GP1_OP_CFG */
3027 #define WM5100_GP1_OP_CFG_SHIFT                      9  /* GP1_OP_CFG */
3028 #define WM5100_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
3029 #define WM5100_GP1_DB                           0x0100  /* GP1_DB */
3030 #define WM5100_GP1_DB_MASK                      0x0100  /* GP1_DB */
3031 #define WM5100_GP1_DB_SHIFT                          8  /* GP1_DB */
3032 #define WM5100_GP1_DB_WIDTH                          1  /* GP1_DB */
3033 #define WM5100_GP1_LVL                          0x0040  /* GP1_LVL */
3034 #define WM5100_GP1_LVL_MASK                     0x0040  /* GP1_LVL */
3035 #define WM5100_GP1_LVL_SHIFT                         6  /* GP1_LVL */
3036 #define WM5100_GP1_LVL_WIDTH                         1  /* GP1_LVL */
3037 #define WM5100_GP1_FN_MASK                      0x003F  /* GP1_FN - [5:0] */
3038 #define WM5100_GP1_FN_SHIFT                          0  /* GP1_FN - [5:0] */
3039 #define WM5100_GP1_FN_WIDTH                          6  /* GP1_FN - [5:0] */
3040 
3041 /*
3042  * R3073 (0xC01) - GPIO CTRL 2
3043  */
3044 #define WM5100_GP2_DIR                          0x8000  /* GP2_DIR */
3045 #define WM5100_GP2_DIR_MASK                     0x8000  /* GP2_DIR */
3046 #define WM5100_GP2_DIR_SHIFT                        15  /* GP2_DIR */
3047 #define WM5100_GP2_DIR_WIDTH                         1  /* GP2_DIR */
3048 #define WM5100_GP2_PU                           0x4000  /* GP2_PU */
3049 #define WM5100_GP2_PU_MASK                      0x4000  /* GP2_PU */
3050 #define WM5100_GP2_PU_SHIFT                         14  /* GP2_PU */
3051 #define WM5100_GP2_PU_WIDTH                          1  /* GP2_PU */
3052 #define WM5100_GP2_PD                           0x2000  /* GP2_PD */
3053 #define WM5100_GP2_PD_MASK                      0x2000  /* GP2_PD */
3054 #define WM5100_GP2_PD_SHIFT                         13  /* GP2_PD */
3055 #define WM5100_GP2_PD_WIDTH                          1  /* GP2_PD */
3056 #define WM5100_GP2_POL                          0x0400  /* GP2_POL */
3057 #define WM5100_GP2_POL_MASK                     0x0400  /* GP2_POL */
3058 #define WM5100_GP2_POL_SHIFT                        10  /* GP2_POL */
3059 #define WM5100_GP2_POL_WIDTH                         1  /* GP2_POL */
3060 #define WM5100_GP2_OP_CFG                       0x0200  /* GP2_OP_CFG */
3061 #define WM5100_GP2_OP_CFG_MASK                  0x0200  /* GP2_OP_CFG */
3062 #define WM5100_GP2_OP_CFG_SHIFT                      9  /* GP2_OP_CFG */
3063 #define WM5100_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
3064 #define WM5100_GP2_DB                           0x0100  /* GP2_DB */
3065 #define WM5100_GP2_DB_MASK                      0x0100  /* GP2_DB */
3066 #define WM5100_GP2_DB_SHIFT                          8  /* GP2_DB */
3067 #define WM5100_GP2_DB_WIDTH                          1  /* GP2_DB */
3068 #define WM5100_GP2_LVL                          0x0040  /* GP2_LVL */
3069 #define WM5100_GP2_LVL_MASK                     0x0040  /* GP2_LVL */
3070 #define WM5100_GP2_LVL_SHIFT                         6  /* GP2_LVL */
3071 #define WM5100_GP2_LVL_WIDTH                         1  /* GP2_LVL */
3072 #define WM5100_GP2_FN_MASK                      0x003F  /* GP2_FN - [5:0] */
3073 #define WM5100_GP2_FN_SHIFT                          0  /* GP2_FN - [5:0] */
3074 #define WM5100_GP2_FN_WIDTH                          6  /* GP2_FN - [5:0] */
3075 
3076 /*
3077  * R3074 (0xC02) - GPIO CTRL 3
3078  */
3079 #define WM5100_GP3_DIR                          0x8000  /* GP3_DIR */
3080 #define WM5100_GP3_DIR_MASK                     0x8000  /* GP3_DIR */
3081 #define WM5100_GP3_DIR_SHIFT                        15  /* GP3_DIR */
3082 #define WM5100_GP3_DIR_WIDTH                         1  /* GP3_DIR */
3083 #define WM5100_GP3_PU                           0x4000  /* GP3_PU */
3084 #define WM5100_GP3_PU_MASK                      0x4000  /* GP3_PU */
3085 #define WM5100_GP3_PU_SHIFT                         14  /* GP3_PU */
3086 #define WM5100_GP3_PU_WIDTH                          1  /* GP3_PU */
3087 #define WM5100_GP3_PD                           0x2000  /* GP3_PD */
3088 #define WM5100_GP3_PD_MASK                      0x2000  /* GP3_PD */
3089 #define WM5100_GP3_PD_SHIFT                         13  /* GP3_PD */
3090 #define WM5100_GP3_PD_WIDTH                          1  /* GP3_PD */
3091 #define WM5100_GP3_POL                          0x0400  /* GP3_POL */
3092 #define WM5100_GP3_POL_MASK                     0x0400  /* GP3_POL */
3093 #define WM5100_GP3_POL_SHIFT                        10  /* GP3_POL */
3094 #define WM5100_GP3_POL_WIDTH                         1  /* GP3_POL */
3095 #define WM5100_GP3_OP_CFG                       0x0200  /* GP3_OP_CFG */
3096 #define WM5100_GP3_OP_CFG_MASK                  0x0200  /* GP3_OP_CFG */
3097 #define WM5100_GP3_OP_CFG_SHIFT                      9  /* GP3_OP_CFG */
3098 #define WM5100_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
3099 #define WM5100_GP3_DB                           0x0100  /* GP3_DB */
3100 #define WM5100_GP3_DB_MASK                      0x0100  /* GP3_DB */
3101 #define WM5100_GP3_DB_SHIFT                          8  /* GP3_DB */
3102 #define WM5100_GP3_DB_WIDTH                          1  /* GP3_DB */
3103 #define WM5100_GP3_LVL                          0x0040  /* GP3_LVL */
3104 #define WM5100_GP3_LVL_MASK                     0x0040  /* GP3_LVL */
3105 #define WM5100_GP3_LVL_SHIFT                         6  /* GP3_LVL */
3106 #define WM5100_GP3_LVL_WIDTH                         1  /* GP3_LVL */
3107 #define WM5100_GP3_FN_MASK                      0x003F  /* GP3_FN - [5:0] */
3108 #define WM5100_GP3_FN_SHIFT                          0  /* GP3_FN - [5:0] */
3109 #define WM5100_GP3_FN_WIDTH                          6  /* GP3_FN - [5:0] */
3110 
3111 /*
3112  * R3075 (0xC03) - GPIO CTRL 4
3113  */
3114 #define WM5100_GP4_DIR                          0x8000  /* GP4_DIR */
3115 #define WM5100_GP4_DIR_MASK                     0x8000  /* GP4_DIR */
3116 #define WM5100_GP4_DIR_SHIFT                        15  /* GP4_DIR */
3117 #define WM5100_GP4_DIR_WIDTH                         1  /* GP4_DIR */
3118 #define WM5100_GP4_PU                           0x4000  /* GP4_PU */
3119 #define WM5100_GP4_PU_MASK                      0x4000  /* GP4_PU */
3120 #define WM5100_GP4_PU_SHIFT                         14  /* GP4_PU */
3121 #define WM5100_GP4_PU_WIDTH                          1  /* GP4_PU */
3122 #define WM5100_GP4_PD                           0x2000  /* GP4_PD */
3123 #define WM5100_GP4_PD_MASK                      0x2000  /* GP4_PD */
3124 #define WM5100_GP4_PD_SHIFT                         13  /* GP4_PD */
3125 #define WM5100_GP4_PD_WIDTH                          1  /* GP4_PD */
3126 #define WM5100_GP4_POL                          0x0400  /* GP4_POL */
3127 #define WM5100_GP4_POL_MASK                     0x0400  /* GP4_POL */
3128 #define WM5100_GP4_POL_SHIFT                        10  /* GP4_POL */
3129 #define WM5100_GP4_POL_WIDTH                         1  /* GP4_POL */
3130 #define WM5100_GP4_OP_CFG                       0x0200  /* GP4_OP_CFG */
3131 #define WM5100_GP4_OP_CFG_MASK                  0x0200  /* GP4_OP_CFG */
3132 #define WM5100_GP4_OP_CFG_SHIFT                      9  /* GP4_OP_CFG */
3133 #define WM5100_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
3134 #define WM5100_GP4_DB                           0x0100  /* GP4_DB */
3135 #define WM5100_GP4_DB_MASK                      0x0100  /* GP4_DB */
3136 #define WM5100_GP4_DB_SHIFT                          8  /* GP4_DB */
3137 #define WM5100_GP4_DB_WIDTH                          1  /* GP4_DB */
3138 #define WM5100_GP4_LVL                          0x0040  /* GP4_LVL */
3139 #define WM5100_GP4_LVL_MASK                     0x0040  /* GP4_LVL */
3140 #define WM5100_GP4_LVL_SHIFT                         6  /* GP4_LVL */
3141 #define WM5100_GP4_LVL_WIDTH                         1  /* GP4_LVL */
3142 #define WM5100_GP4_FN_MASK                      0x003F  /* GP4_FN - [5:0] */
3143 #define WM5100_GP4_FN_SHIFT                          0  /* GP4_FN - [5:0] */
3144 #define WM5100_GP4_FN_WIDTH                          6  /* GP4_FN - [5:0] */
3145 
3146 /*
3147  * R3076 (0xC04) - GPIO CTRL 5
3148  */
3149 #define WM5100_GP5_DIR                          0x8000  /* GP5_DIR */
3150 #define WM5100_GP5_DIR_MASK                     0x8000  /* GP5_DIR */
3151 #define WM5100_GP5_DIR_SHIFT                        15  /* GP5_DIR */
3152 #define WM5100_GP5_DIR_WIDTH                         1  /* GP5_DIR */
3153 #define WM5100_GP5_PU                           0x4000  /* GP5_PU */
3154 #define WM5100_GP5_PU_MASK                      0x4000  /* GP5_PU */
3155 #define WM5100_GP5_PU_SHIFT                         14  /* GP5_PU */
3156 #define WM5100_GP5_PU_WIDTH                          1  /* GP5_PU */
3157 #define WM5100_GP5_PD                           0x2000  /* GP5_PD */
3158 #define WM5100_GP5_PD_MASK                      0x2000  /* GP5_PD */
3159 #define WM5100_GP5_PD_SHIFT                         13  /* GP5_PD */
3160 #define WM5100_GP5_PD_WIDTH                          1  /* GP5_PD */
3161 #define WM5100_GP5_POL                          0x0400  /* GP5_POL */
3162 #define WM5100_GP5_POL_MASK                     0x0400  /* GP5_POL */
3163 #define WM5100_GP5_POL_SHIFT                        10  /* GP5_POL */
3164 #define WM5100_GP5_POL_WIDTH                         1  /* GP5_POL */
3165 #define WM5100_GP5_OP_CFG                       0x0200  /* GP5_OP_CFG */
3166 #define WM5100_GP5_OP_CFG_MASK                  0x0200  /* GP5_OP_CFG */
3167 #define WM5100_GP5_OP_CFG_SHIFT                      9  /* GP5_OP_CFG */
3168 #define WM5100_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
3169 #define WM5100_GP5_DB                           0x0100  /* GP5_DB */
3170 #define WM5100_GP5_DB_MASK                      0x0100  /* GP5_DB */
3171 #define WM5100_GP5_DB_SHIFT                          8  /* GP5_DB */
3172 #define WM5100_GP5_DB_WIDTH                          1  /* GP5_DB */
3173 #define WM5100_GP5_LVL                          0x0040  /* GP5_LVL */
3174 #define WM5100_GP5_LVL_MASK                     0x0040  /* GP5_LVL */
3175 #define WM5100_GP5_LVL_SHIFT                         6  /* GP5_LVL */
3176 #define WM5100_GP5_LVL_WIDTH                         1  /* GP5_LVL */
3177 #define WM5100_GP5_FN_MASK                      0x003F  /* GP5_FN - [5:0] */
3178 #define WM5100_GP5_FN_SHIFT                          0  /* GP5_FN - [5:0] */
3179 #define WM5100_GP5_FN_WIDTH                          6  /* GP5_FN - [5:0] */
3180 
3181 /*
3182  * R3077 (0xC05) - GPIO CTRL 6
3183  */
3184 #define WM5100_GP6_DIR                          0x8000  /* GP6_DIR */
3185 #define WM5100_GP6_DIR_MASK                     0x8000  /* GP6_DIR */
3186 #define WM5100_GP6_DIR_SHIFT                        15  /* GP6_DIR */
3187 #define WM5100_GP6_DIR_WIDTH                         1  /* GP6_DIR */
3188 #define WM5100_GP6_PU                           0x4000  /* GP6_PU */
3189 #define WM5100_GP6_PU_MASK                      0x4000  /* GP6_PU */
3190 #define WM5100_GP6_PU_SHIFT                         14  /* GP6_PU */
3191 #define WM5100_GP6_PU_WIDTH                          1  /* GP6_PU */
3192 #define WM5100_GP6_PD                           0x2000  /* GP6_PD */
3193 #define WM5100_GP6_PD_MASK                      0x2000  /* GP6_PD */
3194 #define WM5100_GP6_PD_SHIFT                         13  /* GP6_PD */
3195 #define WM5100_GP6_PD_WIDTH                          1  /* GP6_PD */
3196 #define WM5100_GP6_POL                          0x0400  /* GP6_POL */
3197 #define WM5100_GP6_POL_MASK                     0x0400  /* GP6_POL */
3198 #define WM5100_GP6_POL_SHIFT                        10  /* GP6_POL */
3199 #define WM5100_GP6_POL_WIDTH                         1  /* GP6_POL */
3200 #define WM5100_GP6_OP_CFG                       0x0200  /* GP6_OP_CFG */
3201 #define WM5100_GP6_OP_CFG_MASK                  0x0200  /* GP6_OP_CFG */
3202 #define WM5100_GP6_OP_CFG_SHIFT                      9  /* GP6_OP_CFG */
3203 #define WM5100_GP6_OP_CFG_WIDTH                      1  /* GP6_OP_CFG */
3204 #define WM5100_GP6_DB                           0x0100  /* GP6_DB */
3205 #define WM5100_GP6_DB_MASK                      0x0100  /* GP6_DB */
3206 #define WM5100_GP6_DB_SHIFT                          8  /* GP6_DB */
3207 #define WM5100_GP6_DB_WIDTH                          1  /* GP6_DB */
3208 #define WM5100_GP6_LVL                          0x0040  /* GP6_LVL */
3209 #define WM5100_GP6_LVL_MASK                     0x0040  /* GP6_LVL */
3210 #define WM5100_GP6_LVL_SHIFT                         6  /* GP6_LVL */
3211 #define WM5100_GP6_LVL_WIDTH                         1  /* GP6_LVL */
3212 #define WM5100_GP6_FN_MASK                      0x003F  /* GP6_FN - [5:0] */
3213 #define WM5100_GP6_FN_SHIFT                          0  /* GP6_FN - [5:0] */
3214 #define WM5100_GP6_FN_WIDTH                          6  /* GP6_FN - [5:0] */
3215 
3216 /*
3217  * R3107 (0xC23) - Misc Pad Ctrl 1
3218  */
3219 #define WM5100_LDO1ENA_PD                       0x8000  /* LDO1ENA_PD */
3220 #define WM5100_LDO1ENA_PD_MASK                  0x8000  /* LDO1ENA_PD */
3221 #define WM5100_LDO1ENA_PD_SHIFT                     15  /* LDO1ENA_PD */
3222 #define WM5100_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
3223 #define WM5100_MCLK2_PD                         0x2000  /* MCLK2_PD */
3224 #define WM5100_MCLK2_PD_MASK                    0x2000  /* MCLK2_PD */
3225 #define WM5100_MCLK2_PD_SHIFT                       13  /* MCLK2_PD */
3226 #define WM5100_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
3227 #define WM5100_MCLK1_PD                         0x1000  /* MCLK1_PD */
3228 #define WM5100_MCLK1_PD_MASK                    0x1000  /* MCLK1_PD */
3229 #define WM5100_MCLK1_PD_SHIFT                       12  /* MCLK1_PD */
3230 #define WM5100_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
3231 #define WM5100_RESET_PU                         0x0002  /* RESET_PU */
3232 #define WM5100_RESET_PU_MASK                    0x0002  /* RESET_PU */
3233 #define WM5100_RESET_PU_SHIFT                        1  /* RESET_PU */
3234 #define WM5100_RESET_PU_WIDTH                        1  /* RESET_PU */
3235 #define WM5100_ADDR_PD                          0x0001  /* ADDR_PD */
3236 #define WM5100_ADDR_PD_MASK                     0x0001  /* ADDR_PD */
3237 #define WM5100_ADDR_PD_SHIFT                         0  /* ADDR_PD */
3238 #define WM5100_ADDR_PD_WIDTH                         1  /* ADDR_PD */
3239 
3240 /*
3241  * R3108 (0xC24) - Misc Pad Ctrl 2
3242  */
3243 #define WM5100_DMICDAT4_PD                      0x0008  /* DMICDAT4_PD */
3244 #define WM5100_DMICDAT4_PD_MASK                 0x0008  /* DMICDAT4_PD */
3245 #define WM5100_DMICDAT4_PD_SHIFT                     3  /* DMICDAT4_PD */
3246 #define WM5100_DMICDAT4_PD_WIDTH                     1  /* DMICDAT4_PD */
3247 #define WM5100_DMICDAT3_PD                      0x0004  /* DMICDAT3_PD */
3248 #define WM5100_DMICDAT3_PD_MASK                 0x0004  /* DMICDAT3_PD */
3249 #define WM5100_DMICDAT3_PD_SHIFT                     2  /* DMICDAT3_PD */
3250 #define WM5100_DMICDAT3_PD_WIDTH                     1  /* DMICDAT3_PD */
3251 #define WM5100_DMICDAT2_PD                      0x0002  /* DMICDAT2_PD */
3252 #define WM5100_DMICDAT2_PD_MASK                 0x0002  /* DMICDAT2_PD */
3253 #define WM5100_DMICDAT2_PD_SHIFT                     1  /* DMICDAT2_PD */
3254 #define WM5100_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
3255 #define WM5100_DMICDAT1_PD                      0x0001  /* DMICDAT1_PD */
3256 #define WM5100_DMICDAT1_PD_MASK                 0x0001  /* DMICDAT1_PD */
3257 #define WM5100_DMICDAT1_PD_SHIFT                     0  /* DMICDAT1_PD */
3258 #define WM5100_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
3259 
3260 /*
3261  * R3109 (0xC25) - Misc Pad Ctrl 3
3262  */
3263 #define WM5100_AIF1RXLRCLK_PU                   0x0020  /* AIF1RXLRCLK_PU */
3264 #define WM5100_AIF1RXLRCLK_PU_MASK              0x0020  /* AIF1RXLRCLK_PU */
3265 #define WM5100_AIF1RXLRCLK_PU_SHIFT                  5  /* AIF1RXLRCLK_PU */
3266 #define WM5100_AIF1RXLRCLK_PU_WIDTH                  1  /* AIF1RXLRCLK_PU */
3267 #define WM5100_AIF1RXLRCLK_PD                   0x0010  /* AIF1RXLRCLK_PD */
3268 #define WM5100_AIF1RXLRCLK_PD_MASK              0x0010  /* AIF1RXLRCLK_PD */
3269 #define WM5100_AIF1RXLRCLK_PD_SHIFT                  4  /* AIF1RXLRCLK_PD */
3270 #define WM5100_AIF1RXLRCLK_PD_WIDTH                  1  /* AIF1RXLRCLK_PD */
3271 #define WM5100_AIF1BCLK_PU                      0x0008  /* AIF1BCLK_PU */
3272 #define WM5100_AIF1BCLK_PU_MASK                 0x0008  /* AIF1BCLK_PU */
3273 #define WM5100_AIF1BCLK_PU_SHIFT                     3  /* AIF1BCLK_PU */
3274 #define WM5100_AIF1BCLK_PU_WIDTH                     1  /* AIF1BCLK_PU */
3275 #define WM5100_AIF1BCLK_PD                      0x0004  /* AIF1BCLK_PD */
3276 #define WM5100_AIF1BCLK_PD_MASK                 0x0004  /* AIF1BCLK_PD */
3277 #define WM5100_AIF1BCLK_PD_SHIFT                     2  /* AIF1BCLK_PD */
3278 #define WM5100_AIF1BCLK_PD_WIDTH                     1  /* AIF1BCLK_PD */
3279 #define WM5100_AIF1RXDAT_PU                     0x0002  /* AIF1RXDAT_PU */
3280 #define WM5100_AIF1RXDAT_PU_MASK                0x0002  /* AIF1RXDAT_PU */
3281 #define WM5100_AIF1RXDAT_PU_SHIFT                    1  /* AIF1RXDAT_PU */
3282 #define WM5100_AIF1RXDAT_PU_WIDTH                    1  /* AIF1RXDAT_PU */
3283 #define WM5100_AIF1RXDAT_PD                     0x0001  /* AIF1RXDAT_PD */
3284 #define WM5100_AIF1RXDAT_PD_MASK                0x0001  /* AIF1RXDAT_PD */
3285 #define WM5100_AIF1RXDAT_PD_SHIFT                    0  /* AIF1RXDAT_PD */
3286 #define WM5100_AIF1RXDAT_PD_WIDTH                    1  /* AIF1RXDAT_PD */
3287 
3288 /*
3289  * R3110 (0xC26) - Misc Pad Ctrl 4
3290  */
3291 #define WM5100_AIF2RXLRCLK_PU                   0x0020  /* AIF2RXLRCLK_PU */
3292 #define WM5100_AIF2RXLRCLK_PU_MASK              0x0020  /* AIF2RXLRCLK_PU */
3293 #define WM5100_AIF2RXLRCLK_PU_SHIFT                  5  /* AIF2RXLRCLK_PU */
3294 #define WM5100_AIF2RXLRCLK_PU_WIDTH                  1  /* AIF2RXLRCLK_PU */
3295 #define WM5100_AIF2RXLRCLK_PD                   0x0010  /* AIF2RXLRCLK_PD */
3296 #define WM5100_AIF2RXLRCLK_PD_MASK              0x0010  /* AIF2RXLRCLK_PD */
3297 #define WM5100_AIF2RXLRCLK_PD_SHIFT                  4  /* AIF2RXLRCLK_PD */
3298 #define WM5100_AIF2RXLRCLK_PD_WIDTH                  1  /* AIF2RXLRCLK_PD */
3299 #define WM5100_AIF2BCLK_PU                      0x0008  /* AIF2BCLK_PU */
3300 #define WM5100_AIF2BCLK_PU_MASK                 0x0008  /* AIF2BCLK_PU */
3301 #define WM5100_AIF2BCLK_PU_SHIFT                     3  /* AIF2BCLK_PU */
3302 #define WM5100_AIF2BCLK_PU_WIDTH                     1  /* AIF2BCLK_PU */
3303 #define WM5100_AIF2BCLK_PD                      0x0004  /* AIF2BCLK_PD */
3304 #define WM5100_AIF2BCLK_PD_MASK                 0x0004  /* AIF2BCLK_PD */
3305 #define WM5100_AIF2BCLK_PD_SHIFT                     2  /* AIF2BCLK_PD */
3306 #define WM5100_AIF2BCLK_PD_WIDTH                     1  /* AIF2BCLK_PD */
3307 #define WM5100_AIF2RXDAT_PU                     0x0002  /* AIF2RXDAT_PU */
3308 #define WM5100_AIF2RXDAT_PU_MASK                0x0002  /* AIF2RXDAT_PU */
3309 #define WM5100_AIF2RXDAT_PU_SHIFT                    1  /* AIF2RXDAT_PU */
3310 #define WM5100_AIF2RXDAT_PU_WIDTH                    1  /* AIF2RXDAT_PU */
3311 #define WM5100_AIF2RXDAT_PD                     0x0001  /* AIF2RXDAT_PD */
3312 #define WM5100_AIF2RXDAT_PD_MASK                0x0001  /* AIF2RXDAT_PD */
3313 #define WM5100_AIF2RXDAT_PD_SHIFT                    0  /* AIF2RXDAT_PD */
3314 #define WM5100_AIF2RXDAT_PD_WIDTH                    1  /* AIF2RXDAT_PD */
3315 
3316 /*
3317  * R3111 (0xC27) - Misc Pad Ctrl 5
3318  */
3319 #define WM5100_AIF3RXLRCLK_PU                   0x0020  /* AIF3RXLRCLK_PU */
3320 #define WM5100_AIF3RXLRCLK_PU_MASK              0x0020  /* AIF3RXLRCLK_PU */
3321 #define WM5100_AIF3RXLRCLK_PU_SHIFT                  5  /* AIF3RXLRCLK_PU */
3322 #define WM5100_AIF3RXLRCLK_PU_WIDTH                  1  /* AIF3RXLRCLK_PU */
3323 #define WM5100_AIF3RXLRCLK_PD                   0x0010  /* AIF3RXLRCLK_PD */
3324 #define WM5100_AIF3RXLRCLK_PD_MASK              0x0010  /* AIF3RXLRCLK_PD */
3325 #define WM5100_AIF3RXLRCLK_PD_SHIFT                  4  /* AIF3RXLRCLK_PD */
3326 #define WM5100_AIF3RXLRCLK_PD_WIDTH                  1  /* AIF3RXLRCLK_PD */
3327 #define WM5100_AIF3BCLK_PU                      0x0008  /* AIF3BCLK_PU */
3328 #define WM5100_AIF3BCLK_PU_MASK                 0x0008  /* AIF3BCLK_PU */
3329 #define WM5100_AIF3BCLK_PU_SHIFT                     3  /* AIF3BCLK_PU */
3330 #define WM5100_AIF3BCLK_PU_WIDTH                     1  /* AIF3BCLK_PU */
3331 #define WM5100_AIF3BCLK_PD                      0x0004  /* AIF3BCLK_PD */
3332 #define WM5100_AIF3BCLK_PD_MASK                 0x0004  /* AIF3BCLK_PD */
3333 #define WM5100_AIF3BCLK_PD_SHIFT                     2  /* AIF3BCLK_PD */
3334 #define WM5100_AIF3BCLK_PD_WIDTH                     1  /* AIF3BCLK_PD */
3335 #define WM5100_AIF3RXDAT_PU                     0x0002  /* AIF3RXDAT_PU */
3336 #define WM5100_AIF3RXDAT_PU_MASK                0x0002  /* AIF3RXDAT_PU */
3337 #define WM5100_AIF3RXDAT_PU_SHIFT                    1  /* AIF3RXDAT_PU */
3338 #define WM5100_AIF3RXDAT_PU_WIDTH                    1  /* AIF3RXDAT_PU */
3339 #define WM5100_AIF3RXDAT_PD                     0x0001  /* AIF3RXDAT_PD */
3340 #define WM5100_AIF3RXDAT_PD_MASK                0x0001  /* AIF3RXDAT_PD */
3341 #define WM5100_AIF3RXDAT_PD_SHIFT                    0  /* AIF3RXDAT_PD */
3342 #define WM5100_AIF3RXDAT_PD_WIDTH                    1  /* AIF3RXDAT_PD */
3343 
3344 /*
3345  * R3112 (0xC28) - Misc GPIO 1
3346  */
3347 #define WM5100_OPCLK_SEL_MASK                   0x0003  /* OPCLK_SEL - [1:0] */
3348 #define WM5100_OPCLK_SEL_SHIFT                       0  /* OPCLK_SEL - [1:0] */
3349 #define WM5100_OPCLK_SEL_WIDTH                       2  /* OPCLK_SEL - [1:0] */
3350 
3351 /*
3352  * R3328 (0xD00) - Interrupt Status 1
3353  */
3354 #define WM5100_GP6_EINT                         0x0020  /* GP6_EINT */
3355 #define WM5100_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
3356 #define WM5100_GP6_EINT_SHIFT                        5  /* GP6_EINT */
3357 #define WM5100_GP6_EINT_WIDTH                        1  /* GP6_EINT */
3358 #define WM5100_GP5_EINT                         0x0010  /* GP5_EINT */
3359 #define WM5100_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
3360 #define WM5100_GP5_EINT_SHIFT                        4  /* GP5_EINT */
3361 #define WM5100_GP5_EINT_WIDTH                        1  /* GP5_EINT */
3362 #define WM5100_GP4_EINT                         0x0008  /* GP4_EINT */
3363 #define WM5100_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
3364 #define WM5100_GP4_EINT_SHIFT                        3  /* GP4_EINT */
3365 #define WM5100_GP4_EINT_WIDTH                        1  /* GP4_EINT */
3366 #define WM5100_GP3_EINT                         0x0004  /* GP3_EINT */
3367 #define WM5100_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
3368 #define WM5100_GP3_EINT_SHIFT                        2  /* GP3_EINT */
3369 #define WM5100_GP3_EINT_WIDTH                        1  /* GP3_EINT */
3370 #define WM5100_GP2_EINT                         0x0002  /* GP2_EINT */
3371 #define WM5100_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
3372 #define WM5100_GP2_EINT_SHIFT                        1  /* GP2_EINT */
3373 #define WM5100_GP2_EINT_WIDTH                        1  /* GP2_EINT */
3374 #define WM5100_GP1_EINT                         0x0001  /* GP1_EINT */
3375 #define WM5100_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
3376 #define WM5100_GP1_EINT_SHIFT                        0  /* GP1_EINT */
3377 #define WM5100_GP1_EINT_WIDTH                        1  /* GP1_EINT */
3378 
3379 /*
3380  * R3329 (0xD01) - Interrupt Status 2
3381  */
3382 #define WM5100_DSP_IRQ6_EINT                    0x0020  /* DSP_IRQ6_EINT */
3383 #define WM5100_DSP_IRQ6_EINT_MASK               0x0020  /* DSP_IRQ6_EINT */
3384 #define WM5100_DSP_IRQ6_EINT_SHIFT                   5  /* DSP_IRQ6_EINT */
3385 #define WM5100_DSP_IRQ6_EINT_WIDTH                   1  /* DSP_IRQ6_EINT */
3386 #define WM5100_DSP_IRQ5_EINT                    0x0010  /* DSP_IRQ5_EINT */
3387 #define WM5100_DSP_IRQ5_EINT_MASK               0x0010  /* DSP_IRQ5_EINT */
3388 #define WM5100_DSP_IRQ5_EINT_SHIFT                   4  /* DSP_IRQ5_EINT */
3389 #define WM5100_DSP_IRQ5_EINT_WIDTH                   1  /* DSP_IRQ5_EINT */
3390 #define WM5100_DSP_IRQ4_EINT                    0x0008  /* DSP_IRQ4_EINT */
3391 #define WM5100_DSP_IRQ4_EINT_MASK               0x0008  /* DSP_IRQ4_EINT */
3392 #define WM5100_DSP_IRQ4_EINT_SHIFT                   3  /* DSP_IRQ4_EINT */
3393 #define WM5100_DSP_IRQ4_EINT_WIDTH                   1  /* DSP_IRQ4_EINT */
3394 #define WM5100_DSP_IRQ3_EINT                    0x0004  /* DSP_IRQ3_EINT */
3395 #define WM5100_DSP_IRQ3_EINT_MASK               0x0004  /* DSP_IRQ3_EINT */
3396 #define WM5100_DSP_IRQ3_EINT_SHIFT                   2  /* DSP_IRQ3_EINT */
3397 #define WM5100_DSP_IRQ3_EINT_WIDTH                   1  /* DSP_IRQ3_EINT */
3398 #define WM5100_DSP_IRQ2_EINT                    0x0002  /* DSP_IRQ2_EINT */
3399 #define WM5100_DSP_IRQ2_EINT_MASK               0x0002  /* DSP_IRQ2_EINT */
3400 #define WM5100_DSP_IRQ2_EINT_SHIFT                   1  /* DSP_IRQ2_EINT */
3401 #define WM5100_DSP_IRQ2_EINT_WIDTH                   1  /* DSP_IRQ2_EINT */
3402 #define WM5100_DSP_IRQ1_EINT                    0x0001  /* DSP_IRQ1_EINT */
3403 #define WM5100_DSP_IRQ1_EINT_MASK               0x0001  /* DSP_IRQ1_EINT */
3404 #define WM5100_DSP_IRQ1_EINT_SHIFT                   0  /* DSP_IRQ1_EINT */
3405 #define WM5100_DSP_IRQ1_EINT_WIDTH                   1  /* DSP_IRQ1_EINT */
3406 
3407 /*
3408  * R3330 (0xD02) - Interrupt Status 3
3409  */
3410 #define WM5100_SPK_SHUTDOWN_WARN_EINT           0x8000  /* SPK_SHUTDOWN_WARN_EINT */
3411 #define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK      0x8000  /* SPK_SHUTDOWN_WARN_EINT */
3412 #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT         15  /* SPK_SHUTDOWN_WARN_EINT */
3413 #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH          1  /* SPK_SHUTDOWN_WARN_EINT */
3414 #define WM5100_SPK_SHUTDOWN_EINT                0x4000  /* SPK_SHUTDOWN_EINT */
3415 #define WM5100_SPK_SHUTDOWN_EINT_MASK           0x4000  /* SPK_SHUTDOWN_EINT */
3416 #define WM5100_SPK_SHUTDOWN_EINT_SHIFT              14  /* SPK_SHUTDOWN_EINT */
3417 #define WM5100_SPK_SHUTDOWN_EINT_WIDTH               1  /* SPK_SHUTDOWN_EINT */
3418 #define WM5100_HPDET_EINT                       0x2000  /* HPDET_EINT */
3419 #define WM5100_HPDET_EINT_MASK                  0x2000  /* HPDET_EINT */
3420 #define WM5100_HPDET_EINT_SHIFT                     13  /* HPDET_EINT */
3421 #define WM5100_HPDET_EINT_WIDTH                      1  /* HPDET_EINT */
3422 #define WM5100_ACCDET_EINT                      0x1000  /* ACCDET_EINT */
3423 #define WM5100_ACCDET_EINT_MASK                 0x1000  /* ACCDET_EINT */
3424 #define WM5100_ACCDET_EINT_SHIFT                    12  /* ACCDET_EINT */
3425 #define WM5100_ACCDET_EINT_WIDTH                     1  /* ACCDET_EINT */
3426 #define WM5100_DRC_SIG_DET_EINT                 0x0200  /* DRC_SIG_DET_EINT */
3427 #define WM5100_DRC_SIG_DET_EINT_MASK            0x0200  /* DRC_SIG_DET_EINT */
3428 #define WM5100_DRC_SIG_DET_EINT_SHIFT                9  /* DRC_SIG_DET_EINT */
3429 #define WM5100_DRC_SIG_DET_EINT_WIDTH                1  /* DRC_SIG_DET_EINT */
3430 #define WM5100_ASRC2_LOCK_EINT                  0x0100  /* ASRC2_LOCK_EINT */
3431 #define WM5100_ASRC2_LOCK_EINT_MASK             0x0100  /* ASRC2_LOCK_EINT */
3432 #define WM5100_ASRC2_LOCK_EINT_SHIFT                 8  /* ASRC2_LOCK_EINT */
3433 #define WM5100_ASRC2_LOCK_EINT_WIDTH                 1  /* ASRC2_LOCK_EINT */
3434 #define WM5100_ASRC1_LOCK_EINT                  0x0080  /* ASRC1_LOCK_EINT */
3435 #define WM5100_ASRC1_LOCK_EINT_MASK             0x0080  /* ASRC1_LOCK_EINT */
3436 #define WM5100_ASRC1_LOCK_EINT_SHIFT                 7  /* ASRC1_LOCK_EINT */
3437 #define WM5100_ASRC1_LOCK_EINT_WIDTH                 1  /* ASRC1_LOCK_EINT */
3438 #define WM5100_FLL2_LOCK_EINT                   0x0008  /* FLL2_LOCK_EINT */
3439 #define WM5100_FLL2_LOCK_EINT_MASK              0x0008  /* FLL2_LOCK_EINT */
3440 #define WM5100_FLL2_LOCK_EINT_SHIFT                  3  /* FLL2_LOCK_EINT */
3441 #define WM5100_FLL2_LOCK_EINT_WIDTH                  1  /* FLL2_LOCK_EINT */
3442 #define WM5100_FLL1_LOCK_EINT                   0x0004  /* FLL1_LOCK_EINT */
3443 #define WM5100_FLL1_LOCK_EINT_MASK              0x0004  /* FLL1_LOCK_EINT */
3444 #define WM5100_FLL1_LOCK_EINT_SHIFT                  2  /* FLL1_LOCK_EINT */
3445 #define WM5100_FLL1_LOCK_EINT_WIDTH                  1  /* FLL1_LOCK_EINT */
3446 #define WM5100_CLKGEN_ERR_EINT                  0x0002  /* CLKGEN_ERR_EINT */
3447 #define WM5100_CLKGEN_ERR_EINT_MASK             0x0002  /* CLKGEN_ERR_EINT */
3448 #define WM5100_CLKGEN_ERR_EINT_SHIFT                 1  /* CLKGEN_ERR_EINT */
3449 #define WM5100_CLKGEN_ERR_EINT_WIDTH                 1  /* CLKGEN_ERR_EINT */
3450 #define WM5100_CLKGEN_ERR_ASYNC_EINT            0x0001  /* CLKGEN_ERR_ASYNC_EINT */
3451 #define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK       0x0001  /* CLKGEN_ERR_ASYNC_EINT */
3452 #define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT           0  /* CLKGEN_ERR_ASYNC_EINT */
3453 #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH           1  /* CLKGEN_ERR_ASYNC_EINT */
3454 
3455 /*
3456  * R3331 (0xD03) - Interrupt Status 4
3457  */
3458 #define WM5100_AIF3_ERR_EINT                    0x2000  /* AIF3_ERR_EINT */
3459 #define WM5100_AIF3_ERR_EINT_MASK               0x2000  /* AIF3_ERR_EINT */
3460 #define WM5100_AIF3_ERR_EINT_SHIFT                  13  /* AIF3_ERR_EINT */
3461 #define WM5100_AIF3_ERR_EINT_WIDTH                   1  /* AIF3_ERR_EINT */
3462 #define WM5100_AIF2_ERR_EINT                    0x1000  /* AIF2_ERR_EINT */
3463 #define WM5100_AIF2_ERR_EINT_MASK               0x1000  /* AIF2_ERR_EINT */
3464 #define WM5100_AIF2_ERR_EINT_SHIFT                  12  /* AIF2_ERR_EINT */
3465 #define WM5100_AIF2_ERR_EINT_WIDTH                   1  /* AIF2_ERR_EINT */
3466 #define WM5100_AIF1_ERR_EINT                    0x0800  /* AIF1_ERR_EINT */
3467 #define WM5100_AIF1_ERR_EINT_MASK               0x0800  /* AIF1_ERR_EINT */
3468 #define WM5100_AIF1_ERR_EINT_SHIFT                  11  /* AIF1_ERR_EINT */
3469 #define WM5100_AIF1_ERR_EINT_WIDTH                   1  /* AIF1_ERR_EINT */
3470 #define WM5100_CTRLIF_ERR_EINT                  0x0400  /* CTRLIF_ERR_EINT */
3471 #define WM5100_CTRLIF_ERR_EINT_MASK             0x0400  /* CTRLIF_ERR_EINT */
3472 #define WM5100_CTRLIF_ERR_EINT_SHIFT                10  /* CTRLIF_ERR_EINT */
3473 #define WM5100_CTRLIF_ERR_EINT_WIDTH                 1  /* CTRLIF_ERR_EINT */
3474 #define WM5100_ISRC2_UNDERCLOCKED_EINT          0x0200  /* ISRC2_UNDERCLOCKED_EINT */
3475 #define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK     0x0200  /* ISRC2_UNDERCLOCKED_EINT */
3476 #define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT         9  /* ISRC2_UNDERCLOCKED_EINT */
3477 #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH         1  /* ISRC2_UNDERCLOCKED_EINT */
3478 #define WM5100_ISRC1_UNDERCLOCKED_EINT          0x0100  /* ISRC1_UNDERCLOCKED_EINT */
3479 #define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK     0x0100  /* ISRC1_UNDERCLOCKED_EINT */
3480 #define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT         8  /* ISRC1_UNDERCLOCKED_EINT */
3481 #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH         1  /* ISRC1_UNDERCLOCKED_EINT */
3482 #define WM5100_FX_UNDERCLOCKED_EINT             0x0080  /* FX_UNDERCLOCKED_EINT */
3483 #define WM5100_FX_UNDERCLOCKED_EINT_MASK        0x0080  /* FX_UNDERCLOCKED_EINT */
3484 #define WM5100_FX_UNDERCLOCKED_EINT_SHIFT            7  /* FX_UNDERCLOCKED_EINT */
3485 #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH            1  /* FX_UNDERCLOCKED_EINT */
3486 #define WM5100_AIF3_UNDERCLOCKED_EINT           0x0040  /* AIF3_UNDERCLOCKED_EINT */
3487 #define WM5100_AIF3_UNDERCLOCKED_EINT_MASK      0x0040  /* AIF3_UNDERCLOCKED_EINT */
3488 #define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT          6  /* AIF3_UNDERCLOCKED_EINT */
3489 #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH          1  /* AIF3_UNDERCLOCKED_EINT */
3490 #define WM5100_AIF2_UNDERCLOCKED_EINT           0x0020  /* AIF2_UNDERCLOCKED_EINT */
3491 #define WM5100_AIF2_UNDERCLOCKED_EINT_MASK      0x0020  /* AIF2_UNDERCLOCKED_EINT */
3492 #define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT          5  /* AIF2_UNDERCLOCKED_EINT */
3493 #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH          1  /* AIF2_UNDERCLOCKED_EINT */
3494 #define WM5100_AIF1_UNDERCLOCKED_EINT           0x0010  /* AIF1_UNDERCLOCKED_EINT */
3495 #define WM5100_AIF1_UNDERCLOCKED_EINT_MASK      0x0010  /* AIF1_UNDERCLOCKED_EINT */
3496 #define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT          4  /* AIF1_UNDERCLOCKED_EINT */
3497 #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH          1  /* AIF1_UNDERCLOCKED_EINT */
3498 #define WM5100_ASRC_UNDERCLOCKED_EINT           0x0008  /* ASRC_UNDERCLOCKED_EINT */
3499 #define WM5100_ASRC_UNDERCLOCKED_EINT_MASK      0x0008  /* ASRC_UNDERCLOCKED_EINT */
3500 #define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT          3  /* ASRC_UNDERCLOCKED_EINT */
3501 #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH          1  /* ASRC_UNDERCLOCKED_EINT */
3502 #define WM5100_DAC_UNDERCLOCKED_EINT            0x0004  /* DAC_UNDERCLOCKED_EINT */
3503 #define WM5100_DAC_UNDERCLOCKED_EINT_MASK       0x0004  /* DAC_UNDERCLOCKED_EINT */
3504 #define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT           2  /* DAC_UNDERCLOCKED_EINT */
3505 #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH           1  /* DAC_UNDERCLOCKED_EINT */
3506 #define WM5100_ADC_UNDERCLOCKED_EINT            0x0002  /* ADC_UNDERCLOCKED_EINT */
3507 #define WM5100_ADC_UNDERCLOCKED_EINT_MASK       0x0002  /* ADC_UNDERCLOCKED_EINT */
3508 #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT           1  /* ADC_UNDERCLOCKED_EINT */
3509 #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH           1  /* ADC_UNDERCLOCKED_EINT */
3510 #define WM5100_MIXER_UNDERCLOCKED_EINT          0x0001  /* MIXER_UNDERCLOCKED_EINT */
3511 #define WM5100_MIXER_UNDERCLOCKED_EINT_MASK     0x0001  /* MIXER_UNDERCLOCKED_EINT */
3512 #define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT         0  /* MIXER_UNDERCLOCKED_EINT */
3513 #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH         1  /* MIXER_UNDERCLOCKED_EINT */
3514 
3515 /*
3516  * R3332 (0xD04) - Interrupt Raw Status 2
3517  */
3518 #define WM5100_DSP_IRQ6_STS                     0x0020  /* DSP_IRQ6_STS */
3519 #define WM5100_DSP_IRQ6_STS_MASK                0x0020  /* DSP_IRQ6_STS */
3520 #define WM5100_DSP_IRQ6_STS_SHIFT                    5  /* DSP_IRQ6_STS */
3521 #define WM5100_DSP_IRQ6_STS_WIDTH                    1  /* DSP_IRQ6_STS */
3522 #define WM5100_DSP_IRQ5_STS                     0x0010  /* DSP_IRQ5_STS */
3523 #define WM5100_DSP_IRQ5_STS_MASK                0x0010  /* DSP_IRQ5_STS */
3524 #define WM5100_DSP_IRQ5_STS_SHIFT                    4  /* DSP_IRQ5_STS */
3525 #define WM5100_DSP_IRQ5_STS_WIDTH                    1  /* DSP_IRQ5_STS */
3526 #define WM5100_DSP_IRQ4_STS                     0x0008  /* DSP_IRQ4_STS */
3527 #define WM5100_DSP_IRQ4_STS_MASK                0x0008  /* DSP_IRQ4_STS */
3528 #define WM5100_DSP_IRQ4_STS_SHIFT                    3  /* DSP_IRQ4_STS */
3529 #define WM5100_DSP_IRQ4_STS_WIDTH                    1  /* DSP_IRQ4_STS */
3530 #define WM5100_DSP_IRQ3_STS                     0x0004  /* DSP_IRQ3_STS */
3531 #define WM5100_DSP_IRQ3_STS_MASK                0x0004  /* DSP_IRQ3_STS */
3532 #define WM5100_DSP_IRQ3_STS_SHIFT                    2  /* DSP_IRQ3_STS */
3533 #define WM5100_DSP_IRQ3_STS_WIDTH                    1  /* DSP_IRQ3_STS */
3534 #define WM5100_DSP_IRQ2_STS                     0x0002  /* DSP_IRQ2_STS */
3535 #define WM5100_DSP_IRQ2_STS_MASK                0x0002  /* DSP_IRQ2_STS */
3536 #define WM5100_DSP_IRQ2_STS_SHIFT                    1  /* DSP_IRQ2_STS */
3537 #define WM5100_DSP_IRQ2_STS_WIDTH                    1  /* DSP_IRQ2_STS */
3538 #define WM5100_DSP_IRQ1_STS                     0x0001  /* DSP_IRQ1_STS */
3539 #define WM5100_DSP_IRQ1_STS_MASK                0x0001  /* DSP_IRQ1_STS */
3540 #define WM5100_DSP_IRQ1_STS_SHIFT                    0  /* DSP_IRQ1_STS */
3541 #define WM5100_DSP_IRQ1_STS_WIDTH                    1  /* DSP_IRQ1_STS */
3542 
3543 /*
3544  * R3333 (0xD05) - Interrupt Raw Status 3
3545  */
3546 #define WM5100_SPK_SHUTDOWN_WARN_STS            0x8000  /* SPK_SHUTDOWN_WARN_STS */
3547 #define WM5100_SPK_SHUTDOWN_WARN_STS_MASK       0x8000  /* SPK_SHUTDOWN_WARN_STS */
3548 #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT          15  /* SPK_SHUTDOWN_WARN_STS */
3549 #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH           1  /* SPK_SHUTDOWN_WARN_STS */
3550 #define WM5100_SPK_SHUTDOWN_STS                 0x4000  /* SPK_SHUTDOWN_STS */
3551 #define WM5100_SPK_SHUTDOWN_STS_MASK            0x4000  /* SPK_SHUTDOWN_STS */
3552 #define WM5100_SPK_SHUTDOWN_STS_SHIFT               14  /* SPK_SHUTDOWN_STS */
3553 #define WM5100_SPK_SHUTDOWN_STS_WIDTH                1  /* SPK_SHUTDOWN_STS */
3554 #define WM5100_HPDET_STS                        0x2000  /* HPDET_STS */
3555 #define WM5100_HPDET_STS_MASK                   0x2000  /* HPDET_STS */
3556 #define WM5100_HPDET_STS_SHIFT                      13  /* HPDET_STS */
3557 #define WM5100_HPDET_STS_WIDTH                       1  /* HPDET_STS */
3558 #define WM5100_DRC_SID_DET_STS                  0x0200  /* DRC_SID_DET_STS */
3559 #define WM5100_DRC_SID_DET_STS_MASK             0x0200  /* DRC_SID_DET_STS */
3560 #define WM5100_DRC_SID_DET_STS_SHIFT                 9  /* DRC_SID_DET_STS */
3561 #define WM5100_DRC_SID_DET_STS_WIDTH                 1  /* DRC_SID_DET_STS */
3562 #define WM5100_ASRC2_LOCK_STS                   0x0100  /* ASRC2_LOCK_STS */
3563 #define WM5100_ASRC2_LOCK_STS_MASK              0x0100  /* ASRC2_LOCK_STS */
3564 #define WM5100_ASRC2_LOCK_STS_SHIFT                  8  /* ASRC2_LOCK_STS */
3565 #define WM5100_ASRC2_LOCK_STS_WIDTH                  1  /* ASRC2_LOCK_STS */
3566 #define WM5100_ASRC1_LOCK_STS                   0x0080  /* ASRC1_LOCK_STS */
3567 #define WM5100_ASRC1_LOCK_STS_MASK              0x0080  /* ASRC1_LOCK_STS */
3568 #define WM5100_ASRC1_LOCK_STS_SHIFT                  7  /* ASRC1_LOCK_STS */
3569 #define WM5100_ASRC1_LOCK_STS_WIDTH                  1  /* ASRC1_LOCK_STS */
3570 #define WM5100_FLL2_LOCK_STS                    0x0008  /* FLL2_LOCK_STS */
3571 #define WM5100_FLL2_LOCK_STS_MASK               0x0008  /* FLL2_LOCK_STS */
3572 #define WM5100_FLL2_LOCK_STS_SHIFT                   3  /* FLL2_LOCK_STS */
3573 #define WM5100_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
3574 #define WM5100_FLL1_LOCK_STS                    0x0004  /* FLL1_LOCK_STS */
3575 #define WM5100_FLL1_LOCK_STS_MASK               0x0004  /* FLL1_LOCK_STS */
3576 #define WM5100_FLL1_LOCK_STS_SHIFT                   2  /* FLL1_LOCK_STS */
3577 #define WM5100_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
3578 #define WM5100_CLKGEN_ERR_STS                   0x0002  /* CLKGEN_ERR_STS */
3579 #define WM5100_CLKGEN_ERR_STS_MASK              0x0002  /* CLKGEN_ERR_STS */
3580 #define WM5100_CLKGEN_ERR_STS_SHIFT                  1  /* CLKGEN_ERR_STS */
3581 #define WM5100_CLKGEN_ERR_STS_WIDTH                  1  /* CLKGEN_ERR_STS */
3582 #define WM5100_CLKGEN_ERR_ASYNC_STS             0x0001  /* CLKGEN_ERR_ASYNC_STS */
3583 #define WM5100_CLKGEN_ERR_ASYNC_STS_MASK        0x0001  /* CLKGEN_ERR_ASYNC_STS */
3584 #define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT            0  /* CLKGEN_ERR_ASYNC_STS */
3585 #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH            1  /* CLKGEN_ERR_ASYNC_STS */
3586 
3587 /*
3588  * R3334 (0xD06) - Interrupt Raw Status 4
3589  */
3590 #define WM5100_AIF3_ERR_STS                     0x2000  /* AIF3_ERR_STS */
3591 #define WM5100_AIF3_ERR_STS_MASK                0x2000  /* AIF3_ERR_STS */
3592 #define WM5100_AIF3_ERR_STS_SHIFT                   13  /* AIF3_ERR_STS */
3593 #define WM5100_AIF3_ERR_STS_WIDTH                    1  /* AIF3_ERR_STS */
3594 #define WM5100_AIF2_ERR_STS                     0x1000  /* AIF2_ERR_STS */
3595 #define WM5100_AIF2_ERR_STS_MASK                0x1000  /* AIF2_ERR_STS */
3596 #define WM5100_AIF2_ERR_STS_SHIFT                   12  /* AIF2_ERR_STS */
3597 #define WM5100_AIF2_ERR_STS_WIDTH                    1  /* AIF2_ERR_STS */
3598 #define WM5100_AIF1_ERR_STS                     0x0800  /* AIF1_ERR_STS */
3599 #define WM5100_AIF1_ERR_STS_MASK                0x0800  /* AIF1_ERR_STS */
3600 #define WM5100_AIF1_ERR_STS_SHIFT                   11  /* AIF1_ERR_STS */
3601 #define WM5100_AIF1_ERR_STS_WIDTH                    1  /* AIF1_ERR_STS */
3602 #define WM5100_CTRLIF_ERR_STS                   0x0400  /* CTRLIF_ERR_STS */
3603 #define WM5100_CTRLIF_ERR_STS_MASK              0x0400  /* CTRLIF_ERR_STS */
3604 #define WM5100_CTRLIF_ERR_STS_SHIFT                 10  /* CTRLIF_ERR_STS */
3605 #define WM5100_CTRLIF_ERR_STS_WIDTH                  1  /* CTRLIF_ERR_STS */
3606 #define WM5100_ISRC2_UNDERCLOCKED_STS           0x0200  /* ISRC2_UNDERCLOCKED_STS */
3607 #define WM5100_ISRC2_UNDERCLOCKED_STS_MASK      0x0200  /* ISRC2_UNDERCLOCKED_STS */
3608 #define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT          9  /* ISRC2_UNDERCLOCKED_STS */
3609 #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH          1  /* ISRC2_UNDERCLOCKED_STS */
3610 #define WM5100_ISRC1_UNDERCLOCKED_STS           0x0100  /* ISRC1_UNDERCLOCKED_STS */
3611 #define WM5100_ISRC1_UNDERCLOCKED_STS_MASK      0x0100  /* ISRC1_UNDERCLOCKED_STS */
3612 #define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT          8  /* ISRC1_UNDERCLOCKED_STS */
3613 #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH          1  /* ISRC1_UNDERCLOCKED_STS */
3614 #define WM5100_FX_UNDERCLOCKED_STS              0x0080  /* FX_UNDERCLOCKED_STS */
3615 #define WM5100_FX_UNDERCLOCKED_STS_MASK         0x0080  /* FX_UNDERCLOCKED_STS */
3616 #define WM5100_FX_UNDERCLOCKED_STS_SHIFT             7  /* FX_UNDERCLOCKED_STS */
3617 #define WM5100_FX_UNDERCLOCKED_STS_WIDTH             1  /* FX_UNDERCLOCKED_STS */
3618 #define WM5100_AIF3_UNDERCLOCKED_STS            0x0040  /* AIF3_UNDERCLOCKED_STS */
3619 #define WM5100_AIF3_UNDERCLOCKED_STS_MASK       0x0040  /* AIF3_UNDERCLOCKED_STS */
3620 #define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT           6  /* AIF3_UNDERCLOCKED_STS */
3621 #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH           1  /* AIF3_UNDERCLOCKED_STS */
3622 #define WM5100_AIF2_UNDERCLOCKED_STS            0x0020  /* AIF2_UNDERCLOCKED_STS */
3623 #define WM5100_AIF2_UNDERCLOCKED_STS_MASK       0x0020  /* AIF2_UNDERCLOCKED_STS */
3624 #define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT           5  /* AIF2_UNDERCLOCKED_STS */
3625 #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH           1  /* AIF2_UNDERCLOCKED_STS */
3626 #define WM5100_AIF1_UNDERCLOCKED_STS            0x0010  /* AIF1_UNDERCLOCKED_STS */
3627 #define WM5100_AIF1_UNDERCLOCKED_STS_MASK       0x0010  /* AIF1_UNDERCLOCKED_STS */
3628 #define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT           4  /* AIF1_UNDERCLOCKED_STS */
3629 #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH           1  /* AIF1_UNDERCLOCKED_STS */
3630 #define WM5100_ASRC_UNDERCLOCKED_STS            0x0008  /* ASRC_UNDERCLOCKED_STS */
3631 #define WM5100_ASRC_UNDERCLOCKED_STS_MASK       0x0008  /* ASRC_UNDERCLOCKED_STS */
3632 #define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT           3  /* ASRC_UNDERCLOCKED_STS */
3633 #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH           1  /* ASRC_UNDERCLOCKED_STS */
3634 #define WM5100_DAC_UNDERCLOCKED_STS             0x0004  /* DAC_UNDERCLOCKED_STS */
3635 #define WM5100_DAC_UNDERCLOCKED_STS_MASK        0x0004  /* DAC_UNDERCLOCKED_STS */
3636 #define WM5100_DAC_UNDERCLOCKED_STS_SHIFT            2  /* DAC_UNDERCLOCKED_STS */
3637 #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH            1  /* DAC_UNDERCLOCKED_STS */
3638 #define WM5100_ADC_UNDERCLOCKED_STS             0x0002  /* ADC_UNDERCLOCKED_STS */
3639 #define WM5100_ADC_UNDERCLOCKED_STS_MASK        0x0002  /* ADC_UNDERCLOCKED_STS */
3640 #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT            1  /* ADC_UNDERCLOCKED_STS */
3641 #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH            1  /* ADC_UNDERCLOCKED_STS */
3642 #define WM5100_MIXER_UNDERCLOCKED_STS           0x0001  /* MIXER_UNDERCLOCKED_STS */
3643 #define WM5100_MIXER_UNDERCLOCKED_STS_MASK      0x0001  /* MIXER_UNDERCLOCKED_STS */
3644 #define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT          0  /* MIXER_UNDERCLOCKED_STS */
3645 #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH          1  /* MIXER_UNDERCLOCKED_STS */
3646 
3647 /*
3648  * R3335 (0xD07) - Interrupt Status 1 Mask
3649  */
3650 #define WM5100_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
3651 #define WM5100_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
3652 #define WM5100_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
3653 #define WM5100_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
3654 #define WM5100_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
3655 #define WM5100_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
3656 #define WM5100_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
3657 #define WM5100_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
3658 #define WM5100_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
3659 #define WM5100_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
3660 #define WM5100_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
3661 #define WM5100_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
3662 #define WM5100_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
3663 #define WM5100_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
3664 #define WM5100_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
3665 #define WM5100_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
3666 #define WM5100_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
3667 #define WM5100_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
3668 #define WM5100_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
3669 #define WM5100_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
3670 #define WM5100_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
3671 #define WM5100_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
3672 #define WM5100_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
3673 #define WM5100_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
3674 
3675 /*
3676  * R3336 (0xD08) - Interrupt Status 2 Mask
3677  */
3678 #define WM5100_IM_DSP_IRQ6_EINT                 0x0020  /* IM_DSP_IRQ6_EINT */
3679 #define WM5100_IM_DSP_IRQ6_EINT_MASK            0x0020  /* IM_DSP_IRQ6_EINT */
3680 #define WM5100_IM_DSP_IRQ6_EINT_SHIFT                5  /* IM_DSP_IRQ6_EINT */
3681 #define WM5100_IM_DSP_IRQ6_EINT_WIDTH                1  /* IM_DSP_IRQ6_EINT */
3682 #define WM5100_IM_DSP_IRQ5_EINT                 0x0010  /* IM_DSP_IRQ5_EINT */
3683 #define WM5100_IM_DSP_IRQ5_EINT_MASK            0x0010  /* IM_DSP_IRQ5_EINT */
3684 #define WM5100_IM_DSP_IRQ5_EINT_SHIFT                4  /* IM_DSP_IRQ5_EINT */
3685 #define WM5100_IM_DSP_IRQ5_EINT_WIDTH                1  /* IM_DSP_IRQ5_EINT */
3686 #define WM5100_IM_DSP_IRQ4_EINT                 0x0008  /* IM_DSP_IRQ4_EINT */
3687 #define WM5100_IM_DSP_IRQ4_EINT_MASK            0x0008  /* IM_DSP_IRQ4_EINT */
3688 #define WM5100_IM_DSP_IRQ4_EINT_SHIFT                3  /* IM_DSP_IRQ4_EINT */
3689 #define WM5100_IM_DSP_IRQ4_EINT_WIDTH                1  /* IM_DSP_IRQ4_EINT */
3690 #define WM5100_IM_DSP_IRQ3_EINT                 0x0004  /* IM_DSP_IRQ3_EINT */
3691 #define WM5100_IM_DSP_IRQ3_EINT_MASK            0x0004  /* IM_DSP_IRQ3_EINT */
3692 #define WM5100_IM_DSP_IRQ3_EINT_SHIFT                2  /* IM_DSP_IRQ3_EINT */
3693 #define WM5100_IM_DSP_IRQ3_EINT_WIDTH                1  /* IM_DSP_IRQ3_EINT */
3694 #define WM5100_IM_DSP_IRQ2_EINT                 0x0002  /* IM_DSP_IRQ2_EINT */
3695 #define WM5100_IM_DSP_IRQ2_EINT_MASK            0x0002  /* IM_DSP_IRQ2_EINT */
3696 #define WM5100_IM_DSP_IRQ2_EINT_SHIFT                1  /* IM_DSP_IRQ2_EINT */
3697 #define WM5100_IM_DSP_IRQ2_EINT_WIDTH                1  /* IM_DSP_IRQ2_EINT */
3698 #define WM5100_IM_DSP_IRQ1_EINT                 0x0001  /* IM_DSP_IRQ1_EINT */
3699 #define WM5100_IM_DSP_IRQ1_EINT_MASK            0x0001  /* IM_DSP_IRQ1_EINT */
3700 #define WM5100_IM_DSP_IRQ1_EINT_SHIFT                0  /* IM_DSP_IRQ1_EINT */
3701 #define WM5100_IM_DSP_IRQ1_EINT_WIDTH                1  /* IM_DSP_IRQ1_EINT */
3702 
3703 /*
3704  * R3337 (0xD09) - Interrupt Status 3 Mask
3705  */
3706 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT        0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT */
3707 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK   0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT */
3708 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT      15  /* IM_SPK_SHUTDOWN_WARN_EINT */
3709 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH       1  /* IM_SPK_SHUTDOWN_WARN_EINT */
3710 #define WM5100_IM_SPK_SHUTDOWN_EINT             0x4000  /* IM_SPK_SHUTDOWN_EINT */
3711 #define WM5100_IM_SPK_SHUTDOWN_EINT_MASK        0x4000  /* IM_SPK_SHUTDOWN_EINT */
3712 #define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT           14  /* IM_SPK_SHUTDOWN_EINT */
3713 #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH            1  /* IM_SPK_SHUTDOWN_EINT */
3714 #define WM5100_IM_HPDET_EINT                    0x2000  /* IM_HPDET_EINT */
3715 #define WM5100_IM_HPDET_EINT_MASK               0x2000  /* IM_HPDET_EINT */
3716 #define WM5100_IM_HPDET_EINT_SHIFT                  13  /* IM_HPDET_EINT */
3717 #define WM5100_IM_HPDET_EINT_WIDTH                   1  /* IM_HPDET_EINT */
3718 #define WM5100_IM_ACCDET_EINT                   0x1000  /* IM_ACCDET_EINT */
3719 #define WM5100_IM_ACCDET_EINT_MASK              0x1000  /* IM_ACCDET_EINT */
3720 #define WM5100_IM_ACCDET_EINT_SHIFT                 12  /* IM_ACCDET_EINT */
3721 #define WM5100_IM_ACCDET_EINT_WIDTH                  1  /* IM_ACCDET_EINT */
3722 #define WM5100_IM_DRC_SIG_DET_EINT              0x0200  /* IM_DRC_SIG_DET_EINT */
3723 #define WM5100_IM_DRC_SIG_DET_EINT_MASK         0x0200  /* IM_DRC_SIG_DET_EINT */
3724 #define WM5100_IM_DRC_SIG_DET_EINT_SHIFT             9  /* IM_DRC_SIG_DET_EINT */
3725 #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH             1  /* IM_DRC_SIG_DET_EINT */
3726 #define WM5100_IM_ASRC2_LOCK_EINT               0x0100  /* IM_ASRC2_LOCK_EINT */
3727 #define WM5100_IM_ASRC2_LOCK_EINT_MASK          0x0100  /* IM_ASRC2_LOCK_EINT */
3728 #define WM5100_IM_ASRC2_LOCK_EINT_SHIFT              8  /* IM_ASRC2_LOCK_EINT */
3729 #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH              1  /* IM_ASRC2_LOCK_EINT */
3730 #define WM5100_IM_ASRC1_LOCK_EINT               0x0080  /* IM_ASRC1_LOCK_EINT */
3731 #define WM5100_IM_ASRC1_LOCK_EINT_MASK          0x0080  /* IM_ASRC1_LOCK_EINT */
3732 #define WM5100_IM_ASRC1_LOCK_EINT_SHIFT              7  /* IM_ASRC1_LOCK_EINT */
3733 #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH              1  /* IM_ASRC1_LOCK_EINT */
3734 #define WM5100_IM_FLL2_LOCK_EINT                0x0008  /* IM_FLL2_LOCK_EINT */
3735 #define WM5100_IM_FLL2_LOCK_EINT_MASK           0x0008  /* IM_FLL2_LOCK_EINT */
3736 #define WM5100_IM_FLL2_LOCK_EINT_SHIFT               3  /* IM_FLL2_LOCK_EINT */
3737 #define WM5100_IM_FLL2_LOCK_EINT_WIDTH               1  /* IM_FLL2_LOCK_EINT */
3738 #define WM5100_IM_FLL1_LOCK_EINT                0x0004  /* IM_FLL1_LOCK_EINT */
3739 #define WM5100_IM_FLL1_LOCK_EINT_MASK           0x0004  /* IM_FLL1_LOCK_EINT */
3740 #define WM5100_IM_FLL1_LOCK_EINT_SHIFT               2  /* IM_FLL1_LOCK_EINT */
3741 #define WM5100_IM_FLL1_LOCK_EINT_WIDTH               1  /* IM_FLL1_LOCK_EINT */
3742 #define WM5100_IM_CLKGEN_ERR_EINT               0x0002  /* IM_CLKGEN_ERR_EINT */
3743 #define WM5100_IM_CLKGEN_ERR_EINT_MASK          0x0002  /* IM_CLKGEN_ERR_EINT */
3744 #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT              1  /* IM_CLKGEN_ERR_EINT */
3745 #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH              1  /* IM_CLKGEN_ERR_EINT */
3746 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT         0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT */
3747 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK    0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT */
3748 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT        0  /* IM_CLKGEN_ERR_ASYNC_EINT */
3749 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH        1  /* IM_CLKGEN_ERR_ASYNC_EINT */
3750 
3751 /*
3752  * R3338 (0xD0A) - Interrupt Status 4 Mask
3753  */
3754 #define WM5100_IM_AIF3_ERR_EINT                 0x2000  /* IM_AIF3_ERR_EINT */
3755 #define WM5100_IM_AIF3_ERR_EINT_MASK            0x2000  /* IM_AIF3_ERR_EINT */
3756 #define WM5100_IM_AIF3_ERR_EINT_SHIFT               13  /* IM_AIF3_ERR_EINT */
3757 #define WM5100_IM_AIF3_ERR_EINT_WIDTH                1  /* IM_AIF3_ERR_EINT */
3758 #define WM5100_IM_AIF2_ERR_EINT                 0x1000  /* IM_AIF2_ERR_EINT */
3759 #define WM5100_IM_AIF2_ERR_EINT_MASK            0x1000  /* IM_AIF2_ERR_EINT */
3760 #define WM5100_IM_AIF2_ERR_EINT_SHIFT               12  /* IM_AIF2_ERR_EINT */
3761 #define WM5100_IM_AIF2_ERR_EINT_WIDTH                1  /* IM_AIF2_ERR_EINT */
3762 #define WM5100_IM_AIF1_ERR_EINT                 0x0800  /* IM_AIF1_ERR_EINT */
3763 #define WM5100_IM_AIF1_ERR_EINT_MASK            0x0800  /* IM_AIF1_ERR_EINT */
3764 #define WM5100_IM_AIF1_ERR_EINT_SHIFT               11  /* IM_AIF1_ERR_EINT */
3765 #define WM5100_IM_AIF1_ERR_EINT_WIDTH                1  /* IM_AIF1_ERR_EINT */
3766 #define WM5100_IM_CTRLIF_ERR_EINT               0x0400  /* IM_CTRLIF_ERR_EINT */
3767 #define WM5100_IM_CTRLIF_ERR_EINT_MASK          0x0400  /* IM_CTRLIF_ERR_EINT */
3768 #define WM5100_IM_CTRLIF_ERR_EINT_SHIFT             10  /* IM_CTRLIF_ERR_EINT */
3769 #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH              1  /* IM_CTRLIF_ERR_EINT */
3770 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT       0x0200  /* IM_ISRC2_UNDERCLOCKED_EINT */
3771 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK  0x0200  /* IM_ISRC2_UNDERCLOCKED_EINT */
3772 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT      9  /* IM_ISRC2_UNDERCLOCKED_EINT */
3773 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH      1  /* IM_ISRC2_UNDERCLOCKED_EINT */
3774 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT       0x0100  /* IM_ISRC1_UNDERCLOCKED_EINT */
3775 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK  0x0100  /* IM_ISRC1_UNDERCLOCKED_EINT */
3776 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT      8  /* IM_ISRC1_UNDERCLOCKED_EINT */
3777 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH      1  /* IM_ISRC1_UNDERCLOCKED_EINT */
3778 #define WM5100_IM_FX_UNDERCLOCKED_EINT          0x0080  /* IM_FX_UNDERCLOCKED_EINT */
3779 #define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK     0x0080  /* IM_FX_UNDERCLOCKED_EINT */
3780 #define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT         7  /* IM_FX_UNDERCLOCKED_EINT */
3781 #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH         1  /* IM_FX_UNDERCLOCKED_EINT */
3782 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT        0x0040  /* IM_AIF3_UNDERCLOCKED_EINT */
3783 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK   0x0040  /* IM_AIF3_UNDERCLOCKED_EINT */
3784 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT       6  /* IM_AIF3_UNDERCLOCKED_EINT */
3785 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF3_UNDERCLOCKED_EINT */
3786 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT        0x0020  /* IM_AIF2_UNDERCLOCKED_EINT */
3787 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK   0x0020  /* IM_AIF2_UNDERCLOCKED_EINT */
3788 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT       5  /* IM_AIF2_UNDERCLOCKED_EINT */
3789 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF2_UNDERCLOCKED_EINT */
3790 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT        0x0010  /* IM_AIF1_UNDERCLOCKED_EINT */
3791 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK   0x0010  /* IM_AIF1_UNDERCLOCKED_EINT */
3792 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT       4  /* IM_AIF1_UNDERCLOCKED_EINT */
3793 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF1_UNDERCLOCKED_EINT */
3794 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT        0x0008  /* IM_ASRC_UNDERCLOCKED_EINT */
3795 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK   0x0008  /* IM_ASRC_UNDERCLOCKED_EINT */
3796 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT       3  /* IM_ASRC_UNDERCLOCKED_EINT */
3797 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH       1  /* IM_ASRC_UNDERCLOCKED_EINT */
3798 #define WM5100_IM_DAC_UNDERCLOCKED_EINT         0x0004  /* IM_DAC_UNDERCLOCKED_EINT */
3799 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK    0x0004  /* IM_DAC_UNDERCLOCKED_EINT */
3800 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT        2  /* IM_DAC_UNDERCLOCKED_EINT */
3801 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH        1  /* IM_DAC_UNDERCLOCKED_EINT */
3802 #define WM5100_IM_ADC_UNDERCLOCKED_EINT         0x0002  /* IM_ADC_UNDERCLOCKED_EINT */
3803 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK    0x0002  /* IM_ADC_UNDERCLOCKED_EINT */
3804 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT        1  /* IM_ADC_UNDERCLOCKED_EINT */
3805 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH        1  /* IM_ADC_UNDERCLOCKED_EINT */
3806 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT       0x0001  /* IM_MIXER_UNDERCLOCKED_EINT */
3807 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK  0x0001  /* IM_MIXER_UNDERCLOCKED_EINT */
3808 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT      0  /* IM_MIXER_UNDERCLOCKED_EINT */
3809 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH      1  /* IM_MIXER_UNDERCLOCKED_EINT */
3810 
3811 /*
3812  * R3359 (0xD1F) - Interrupt Control
3813  */
3814 #define WM5100_IM_IRQ                           0x0001  /* IM_IRQ */
3815 #define WM5100_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
3816 #define WM5100_IM_IRQ_SHIFT                          0  /* IM_IRQ */
3817 #define WM5100_IM_IRQ_WIDTH                          1  /* IM_IRQ */
3818 
3819 /*
3820  * R3360 (0xD20) - IRQ Debounce 1
3821  */
3822 #define WM5100_SPK_SHUTDOWN_WARN_DB             0x0200  /* SPK_SHUTDOWN_WARN_DB */
3823 #define WM5100_SPK_SHUTDOWN_WARN_DB_MASK        0x0200  /* SPK_SHUTDOWN_WARN_DB */
3824 #define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT            9  /* SPK_SHUTDOWN_WARN_DB */
3825 #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH            1  /* SPK_SHUTDOWN_WARN_DB */
3826 #define WM5100_SPK_SHUTDOWN_DB                  0x0100  /* SPK_SHUTDOWN_DB */
3827 #define WM5100_SPK_SHUTDOWN_DB_MASK             0x0100  /* SPK_SHUTDOWN_DB */
3828 #define WM5100_SPK_SHUTDOWN_DB_SHIFT                 8  /* SPK_SHUTDOWN_DB */
3829 #define WM5100_SPK_SHUTDOWN_DB_WIDTH                 1  /* SPK_SHUTDOWN_DB */
3830 #define WM5100_FLL1_LOCK_IRQ_DB                 0x0008  /* FLL1_LOCK_IRQ_DB */
3831 #define WM5100_FLL1_LOCK_IRQ_DB_MASK            0x0008  /* FLL1_LOCK_IRQ_DB */
3832 #define WM5100_FLL1_LOCK_IRQ_DB_SHIFT                3  /* FLL1_LOCK_IRQ_DB */
3833 #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH                1  /* FLL1_LOCK_IRQ_DB */
3834 #define WM5100_FLL2_LOCK_IRQ_DB                 0x0004  /* FLL2_LOCK_IRQ_DB */
3835 #define WM5100_FLL2_LOCK_IRQ_DB_MASK            0x0004  /* FLL2_LOCK_IRQ_DB */
3836 #define WM5100_FLL2_LOCK_IRQ_DB_SHIFT                2  /* FLL2_LOCK_IRQ_DB */
3837 #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH                1  /* FLL2_LOCK_IRQ_DB */
3838 #define WM5100_CLKGEN_ERR_IRQ_DB                0x0002  /* CLKGEN_ERR_IRQ_DB */
3839 #define WM5100_CLKGEN_ERR_IRQ_DB_MASK           0x0002  /* CLKGEN_ERR_IRQ_DB */
3840 #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT               1  /* CLKGEN_ERR_IRQ_DB */
3841 #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH               1  /* CLKGEN_ERR_IRQ_DB */
3842 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB          0x0001  /* CLKGEN_ERR_ASYNC_IRQ_DB */
3843 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK     0x0001  /* CLKGEN_ERR_ASYNC_IRQ_DB */
3844 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT         0  /* CLKGEN_ERR_ASYNC_IRQ_DB */
3845 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH         1  /* CLKGEN_ERR_ASYNC_IRQ_DB */
3846 
3847 /*
3848  * R3361 (0xD21) - IRQ Debounce 2
3849  */
3850 #define WM5100_AIF_ERR_DB                       0x0001  /* AIF_ERR_DB */
3851 #define WM5100_AIF_ERR_DB_MASK                  0x0001  /* AIF_ERR_DB */
3852 #define WM5100_AIF_ERR_DB_SHIFT                      0  /* AIF_ERR_DB */
3853 #define WM5100_AIF_ERR_DB_WIDTH                      1  /* AIF_ERR_DB */
3854 
3855 /*
3856  * R3584 (0xE00) - FX_Ctrl
3857  */
3858 #define WM5100_FX_STS_MASK                      0xFFC0  /* FX_STS - [15:6] */
3859 #define WM5100_FX_STS_SHIFT                          6  /* FX_STS - [15:6] */
3860 #define WM5100_FX_STS_WIDTH                         10  /* FX_STS - [15:6] */
3861 #define WM5100_FX_RATE_MASK                     0x0003  /* FX_RATE - [1:0] */
3862 #define WM5100_FX_RATE_SHIFT                         0  /* FX_RATE - [1:0] */
3863 #define WM5100_FX_RATE_WIDTH                         2  /* FX_RATE - [1:0] */
3864 
3865 /*
3866  * R3600 (0xE10) - EQ1_1
3867  */
3868 #define WM5100_EQ1_B1_GAIN_MASK                 0xF800  /* EQ1_B1_GAIN - [15:11] */
3869 #define WM5100_EQ1_B1_GAIN_SHIFT                    11  /* EQ1_B1_GAIN - [15:11] */
3870 #define WM5100_EQ1_B1_GAIN_WIDTH                     5  /* EQ1_B1_GAIN - [15:11] */
3871 #define WM5100_EQ1_B2_GAIN_MASK                 0x07C0  /* EQ1_B2_GAIN - [10:6] */
3872 #define WM5100_EQ1_B2_GAIN_SHIFT                     6  /* EQ1_B2_GAIN - [10:6] */
3873 #define WM5100_EQ1_B2_GAIN_WIDTH                     5  /* EQ1_B2_GAIN - [10:6] */
3874 #define WM5100_EQ1_B3_GAIN_MASK                 0x003E  /* EQ1_B3_GAIN - [5:1] */
3875 #define WM5100_EQ1_B3_GAIN_SHIFT                     1  /* EQ1_B3_GAIN - [5:1] */
3876 #define WM5100_EQ1_B3_GAIN_WIDTH                     5  /* EQ1_B3_GAIN - [5:1] */
3877 #define WM5100_EQ1_ENA                          0x0001  /* EQ1_ENA */
3878 #define WM5100_EQ1_ENA_MASK                     0x0001  /* EQ1_ENA */
3879 #define WM5100_EQ1_ENA_SHIFT                         0  /* EQ1_ENA */
3880 #define WM5100_EQ1_ENA_WIDTH                         1  /* EQ1_ENA */
3881 
3882 /*
3883  * R3601 (0xE11) - EQ1_2
3884  */
3885 #define WM5100_EQ1_B4_GAIN_MASK                 0xF800  /* EQ1_B4_GAIN - [15:11] */
3886 #define WM5100_EQ1_B4_GAIN_SHIFT                    11  /* EQ1_B4_GAIN - [15:11] */
3887 #define WM5100_EQ1_B4_GAIN_WIDTH                     5  /* EQ1_B4_GAIN - [15:11] */
3888 #define WM5100_EQ1_B5_GAIN_MASK                 0x07C0  /* EQ1_B5_GAIN - [10:6] */
3889 #define WM5100_EQ1_B5_GAIN_SHIFT                     6  /* EQ1_B5_GAIN - [10:6] */
3890 #define WM5100_EQ1_B5_GAIN_WIDTH                     5  /* EQ1_B5_GAIN - [10:6] */
3891 
3892 /*
3893  * R3602 (0xE12) - EQ1_3
3894  */
3895 #define WM5100_EQ1_B1_A_MASK                    0xFFFF  /* EQ1_B1_A - [15:0] */
3896 #define WM5100_EQ1_B1_A_SHIFT                        0  /* EQ1_B1_A - [15:0] */
3897 #define WM5100_EQ1_B1_A_WIDTH                       16  /* EQ1_B1_A - [15:0] */
3898 
3899 /*
3900  * R3603 (0xE13) - EQ1_4
3901  */
3902 #define WM5100_EQ1_B1_B_MASK                    0xFFFF  /* EQ1_B1_B - [15:0] */
3903 #define WM5100_EQ1_B1_B_SHIFT                        0  /* EQ1_B1_B - [15:0] */
3904 #define WM5100_EQ1_B1_B_WIDTH                       16  /* EQ1_B1_B - [15:0] */
3905 
3906 /*
3907  * R3604 (0xE14) - EQ1_5
3908  */
3909 #define WM5100_EQ1_B1_PG_MASK                   0xFFFF  /* EQ1_B1_PG - [15:0] */
3910 #define WM5100_EQ1_B1_PG_SHIFT                       0  /* EQ1_B1_PG - [15:0] */
3911 #define WM5100_EQ1_B1_PG_WIDTH                      16  /* EQ1_B1_PG - [15:0] */
3912 
3913 /*
3914  * R3605 (0xE15) - EQ1_6
3915  */
3916 #define WM5100_EQ1_B2_A_MASK                    0xFFFF  /* EQ1_B2_A - [15:0] */
3917 #define WM5100_EQ1_B2_A_SHIFT                        0  /* EQ1_B2_A - [15:0] */
3918 #define WM5100_EQ1_B2_A_WIDTH                       16  /* EQ1_B2_A - [15:0] */
3919 
3920 /*
3921  * R3606 (0xE16) - EQ1_7
3922  */
3923 #define WM5100_EQ1_B2_B_MASK                    0xFFFF  /* EQ1_B2_B - [15:0] */
3924 #define WM5100_EQ1_B2_B_SHIFT                        0  /* EQ1_B2_B - [15:0] */
3925 #define WM5100_EQ1_B2_B_WIDTH                       16  /* EQ1_B2_B - [15:0] */
3926 
3927 /*
3928  * R3607 (0xE17) - EQ1_8
3929  */
3930 #define WM5100_EQ1_B2_C_MASK                    0xFFFF  /* EQ1_B2_C - [15:0] */
3931 #define WM5100_EQ1_B2_C_SHIFT                        0  /* EQ1_B2_C - [15:0] */
3932 #define WM5100_EQ1_B2_C_WIDTH                       16  /* EQ1_B2_C - [15:0] */
3933 
3934 /*
3935  * R3608 (0xE18) - EQ1_9
3936  */
3937 #define WM5100_EQ1_B2_PG_MASK                   0xFFFF  /* EQ1_B2_PG - [15:0] */
3938 #define WM5100_EQ1_B2_PG_SHIFT                       0  /* EQ1_B2_PG - [15:0] */
3939 #define WM5100_EQ1_B2_PG_WIDTH                      16  /* EQ1_B2_PG - [15:0] */
3940 
3941 /*
3942  * R3609 (0xE19) - EQ1_10
3943  */
3944 #define WM5100_EQ1_B3_A_MASK                    0xFFFF  /* EQ1_B3_A - [15:0] */
3945 #define WM5100_EQ1_B3_A_SHIFT                        0  /* EQ1_B3_A - [15:0] */
3946 #define WM5100_EQ1_B3_A_WIDTH                       16  /* EQ1_B3_A - [15:0] */
3947 
3948 /*
3949  * R3610 (0xE1A) - EQ1_11
3950  */
3951 #define WM5100_EQ1_B3_B_MASK                    0xFFFF  /* EQ1_B3_B - [15:0] */
3952 #define WM5100_EQ1_B3_B_SHIFT                        0  /* EQ1_B3_B - [15:0] */
3953 #define WM5100_EQ1_B3_B_WIDTH                       16  /* EQ1_B3_B - [15:0] */
3954 
3955 /*
3956  * R3611 (0xE1B) - EQ1_12
3957  */
3958 #define WM5100_EQ1_B3_C_MASK                    0xFFFF  /* EQ1_B3_C - [15:0] */
3959 #define WM5100_EQ1_B3_C_SHIFT                        0  /* EQ1_B3_C - [15:0] */
3960 #define WM5100_EQ1_B3_C_WIDTH                       16  /* EQ1_B3_C - [15:0] */
3961 
3962 /*
3963  * R3612 (0xE1C) - EQ1_13
3964  */
3965 #define WM5100_EQ1_B3_PG_MASK                   0xFFFF  /* EQ1_B3_PG - [15:0] */
3966 #define WM5100_EQ1_B3_PG_SHIFT                       0  /* EQ1_B3_PG - [15:0] */
3967 #define WM5100_EQ1_B3_PG_WIDTH                      16  /* EQ1_B3_PG - [15:0] */
3968 
3969 /*
3970  * R3613 (0xE1D) - EQ1_14
3971  */
3972 #define WM5100_EQ1_B4_A_MASK                    0xFFFF  /* EQ1_B4_A - [15:0] */
3973 #define WM5100_EQ1_B4_A_SHIFT                        0  /* EQ1_B4_A - [15:0] */
3974 #define WM5100_EQ1_B4_A_WIDTH                       16  /* EQ1_B4_A - [15:0] */
3975 
3976 /*
3977  * R3614 (0xE1E) - EQ1_15
3978  */
3979 #define WM5100_EQ1_B4_B_MASK                    0xFFFF  /* EQ1_B4_B - [15:0] */
3980 #define WM5100_EQ1_B4_B_SHIFT                        0  /* EQ1_B4_B - [15:0] */
3981 #define WM5100_EQ1_B4_B_WIDTH                       16  /* EQ1_B4_B - [15:0] */
3982 
3983 /*
3984  * R3615 (0xE1F) - EQ1_16
3985  */
3986 #define WM5100_EQ1_B4_C_MASK                    0xFFFF  /* EQ1_B4_C - [15:0] */
3987 #define WM5100_EQ1_B4_C_SHIFT                        0  /* EQ1_B4_C - [15:0] */
3988 #define WM5100_EQ1_B4_C_WIDTH                       16  /* EQ1_B4_C - [15:0] */
3989 
3990 /*
3991  * R3616 (0xE20) - EQ1_17
3992  */
3993 #define WM5100_EQ1_B4_PG_MASK                   0xFFFF  /* EQ1_B4_PG - [15:0] */
3994 #define WM5100_EQ1_B4_PG_SHIFT                       0  /* EQ1_B4_PG - [15:0] */
3995 #define WM5100_EQ1_B4_PG_WIDTH                      16  /* EQ1_B4_PG - [15:0] */
3996 
3997 /*
3998  * R3617 (0xE21) - EQ1_18
3999  */
4000 #define WM5100_EQ1_B5_A_MASK                    0xFFFF  /* EQ1_B5_A - [15:0] */
4001 #define WM5100_EQ1_B5_A_SHIFT                        0  /* EQ1_B5_A - [15:0] */
4002 #define WM5100_EQ1_B5_A_WIDTH                       16  /* EQ1_B5_A - [15:0] */
4003 
4004 /*
4005  * R3618 (0xE22) - EQ1_19
4006  */
4007 #define WM5100_EQ1_B5_B_MASK                    0xFFFF  /* EQ1_B5_B - [15:0] */
4008 #define WM5100_EQ1_B5_B_SHIFT                        0  /* EQ1_B5_B - [15:0] */
4009 #define WM5100_EQ1_B5_B_WIDTH                       16  /* EQ1_B5_B - [15:0] */
4010 
4011 /*
4012  * R3619 (0xE23) - EQ1_20
4013  */
4014 #define WM5100_EQ1_B5_PG_MASK                   0xFFFF  /* EQ1_B5_PG - [15:0] */
4015 #define WM5100_EQ1_B5_PG_SHIFT                       0  /* EQ1_B5_PG - [15:0] */
4016 #define WM5100_EQ1_B5_PG_WIDTH                      16  /* EQ1_B5_PG - [15:0] */
4017 
4018 /*
4019  * R3622 (0xE26) - EQ2_1
4020  */
4021 #define WM5100_EQ2_B1_GAIN_MASK                 0xF800  /* EQ2_B1_GAIN - [15:11] */
4022 #define WM5100_EQ2_B1_GAIN_SHIFT                    11  /* EQ2_B1_GAIN - [15:11] */
4023 #define WM5100_EQ2_B1_GAIN_WIDTH                     5  /* EQ2_B1_GAIN - [15:11] */
4024 #define WM5100_EQ2_B2_GAIN_MASK                 0x07C0  /* EQ2_B2_GAIN - [10:6] */
4025 #define WM5100_EQ2_B2_GAIN_SHIFT                     6  /* EQ2_B2_GAIN - [10:6] */
4026 #define WM5100_EQ2_B2_GAIN_WIDTH                     5  /* EQ2_B2_GAIN - [10:6] */
4027 #define WM5100_EQ2_B3_GAIN_MASK                 0x003E  /* EQ2_B3_GAIN - [5:1] */
4028 #define WM5100_EQ2_B3_GAIN_SHIFT                     1  /* EQ2_B3_GAIN - [5:1] */
4029 #define WM5100_EQ2_B3_GAIN_WIDTH                     5  /* EQ2_B3_GAIN - [5:1] */
4030 #define WM5100_EQ2_ENA                          0x0001  /* EQ2_ENA */
4031 #define WM5100_EQ2_ENA_MASK                     0x0001  /* EQ2_ENA */
4032 #define WM5100_EQ2_ENA_SHIFT                         0  /* EQ2_ENA */
4033 #define WM5100_EQ2_ENA_WIDTH                         1  /* EQ2_ENA */
4034 
4035 /*
4036  * R3623 (0xE27) - EQ2_2
4037  */
4038 #define WM5100_EQ2_B4_GAIN_MASK                 0xF800  /* EQ2_B4_GAIN - [15:11] */
4039 #define WM5100_EQ2_B4_GAIN_SHIFT                    11  /* EQ2_B4_GAIN - [15:11] */
4040 #define WM5100_EQ2_B4_GAIN_WIDTH                     5  /* EQ2_B4_GAIN - [15:11] */
4041 #define WM5100_EQ2_B5_GAIN_MASK                 0x07C0  /* EQ2_B5_GAIN - [10:6] */
4042 #define WM5100_EQ2_B5_GAIN_SHIFT                     6  /* EQ2_B5_GAIN - [10:6] */
4043 #define WM5100_EQ2_B5_GAIN_WIDTH                     5  /* EQ2_B5_GAIN - [10:6] */
4044 
4045 /*
4046  * R3624 (0xE28) - EQ2_3
4047  */
4048 #define WM5100_EQ2_B1_A_MASK                    0xFFFF  /* EQ2_B1_A - [15:0] */
4049 #define WM5100_EQ2_B1_A_SHIFT                        0  /* EQ2_B1_A - [15:0] */
4050 #define WM5100_EQ2_B1_A_WIDTH                       16  /* EQ2_B1_A - [15:0] */
4051 
4052 /*
4053  * R3625 (0xE29) - EQ2_4
4054  */
4055 #define WM5100_EQ2_B1_B_MASK                    0xFFFF  /* EQ2_B1_B - [15:0] */
4056 #define WM5100_EQ2_B1_B_SHIFT                        0  /* EQ2_B1_B - [15:0] */
4057 #define WM5100_EQ2_B1_B_WIDTH                       16  /* EQ2_B1_B - [15:0] */
4058 
4059 /*
4060  * R3626 (0xE2A) - EQ2_5
4061  */
4062 #define WM5100_EQ2_B1_PG_MASK                   0xFFFF  /* EQ2_B1_PG - [15:0] */
4063 #define WM5100_EQ2_B1_PG_SHIFT                       0  /* EQ2_B1_PG - [15:0] */
4064 #define WM5100_EQ2_B1_PG_WIDTH                      16  /* EQ2_B1_PG - [15:0] */
4065 
4066 /*
4067  * R3627 (0xE2B) - EQ2_6
4068  */
4069 #define WM5100_EQ2_B2_A_MASK                    0xFFFF  /* EQ2_B2_A - [15:0] */
4070 #define WM5100_EQ2_B2_A_SHIFT                        0  /* EQ2_B2_A - [15:0] */
4071 #define WM5100_EQ2_B2_A_WIDTH                       16  /* EQ2_B2_A - [15:0] */
4072 
4073 /*
4074  * R3628 (0xE2C) - EQ2_7
4075  */
4076 #define WM5100_EQ2_B2_B_MASK                    0xFFFF  /* EQ2_B2_B - [15:0] */
4077 #define WM5100_EQ2_B2_B_SHIFT                        0  /* EQ2_B2_B - [15:0] */
4078 #define WM5100_EQ2_B2_B_WIDTH                       16  /* EQ2_B2_B - [15:0] */
4079 
4080 /*
4081  * R3629 (0xE2D) - EQ2_8
4082  */
4083 #define WM5100_EQ2_B2_C_MASK                    0xFFFF  /* EQ2_B2_C - [15:0] */
4084 #define WM5100_EQ2_B2_C_SHIFT                        0  /* EQ2_B2_C - [15:0] */
4085 #define WM5100_EQ2_B2_C_WIDTH                       16  /* EQ2_B2_C - [15:0] */
4086 
4087 /*
4088  * R3630 (0xE2E) - EQ2_9
4089  */
4090 #define WM5100_EQ2_B2_PG_MASK                   0xFFFF  /* EQ2_B2_PG - [15:0] */
4091 #define WM5100_EQ2_B2_PG_SHIFT                       0  /* EQ2_B2_PG - [15:0] */
4092 #define WM5100_EQ2_B2_PG_WIDTH                      16  /* EQ2_B2_PG - [15:0] */
4093 
4094 /*
4095  * R3631 (0xE2F) - EQ2_10
4096  */
4097 #define WM5100_EQ2_B3_A_MASK                    0xFFFF  /* EQ2_B3_A - [15:0] */
4098 #define WM5100_EQ2_B3_A_SHIFT                        0  /* EQ2_B3_A - [15:0] */
4099 #define WM5100_EQ2_B3_A_WIDTH                       16  /* EQ2_B3_A - [15:0] */
4100 
4101 /*
4102  * R3632 (0xE30) - EQ2_11
4103  */
4104 #define WM5100_EQ2_B3_B_MASK                    0xFFFF  /* EQ2_B3_B - [15:0] */
4105 #define WM5100_EQ2_B3_B_SHIFT                        0  /* EQ2_B3_B - [15:0] */
4106 #define WM5100_EQ2_B3_B_WIDTH                       16  /* EQ2_B3_B - [15:0] */
4107 
4108 /*
4109  * R3633 (0xE31) - EQ2_12
4110  */
4111 #define WM5100_EQ2_B3_C_MASK                    0xFFFF  /* EQ2_B3_C - [15:0] */
4112 #define WM5100_EQ2_B3_C_SHIFT                        0  /* EQ2_B3_C - [15:0] */
4113 #define WM5100_EQ2_B3_C_WIDTH                       16  /* EQ2_B3_C - [15:0] */
4114 
4115 /*
4116  * R3634 (0xE32) - EQ2_13
4117  */
4118 #define WM5100_EQ2_B3_PG_MASK                   0xFFFF  /* EQ2_B3_PG - [15:0] */
4119 #define WM5100_EQ2_B3_PG_SHIFT                       0  /* EQ2_B3_PG - [15:0] */
4120 #define WM5100_EQ2_B3_PG_WIDTH                      16  /* EQ2_B3_PG - [15:0] */
4121 
4122 /*
4123  * R3635 (0xE33) - EQ2_14
4124  */
4125 #define WM5100_EQ2_B4_A_MASK                    0xFFFF  /* EQ2_B4_A - [15:0] */
4126 #define WM5100_EQ2_B4_A_SHIFT                        0  /* EQ2_B4_A - [15:0] */
4127 #define WM5100_EQ2_B4_A_WIDTH                       16  /* EQ2_B4_A - [15:0] */
4128 
4129 /*
4130  * R3636 (0xE34) - EQ2_15
4131  */
4132 #define WM5100_EQ2_B4_B_MASK                    0xFFFF  /* EQ2_B4_B - [15:0] */
4133 #define WM5100_EQ2_B4_B_SHIFT                        0  /* EQ2_B4_B - [15:0] */
4134 #define WM5100_EQ2_B4_B_WIDTH                       16  /* EQ2_B4_B - [15:0] */
4135 
4136 /*
4137  * R3637 (0xE35) - EQ2_16
4138  */
4139 #define WM5100_EQ2_B4_C_MASK                    0xFFFF  /* EQ2_B4_C - [15:0] */
4140 #define WM5100_EQ2_B4_C_SHIFT                        0  /* EQ2_B4_C - [15:0] */
4141 #define WM5100_EQ2_B4_C_WIDTH                       16  /* EQ2_B4_C - [15:0] */
4142 
4143 /*
4144  * R3638 (0xE36) - EQ2_17
4145  */
4146 #define WM5100_EQ2_B4_PG_MASK                   0xFFFF  /* EQ2_B4_PG - [15:0] */
4147 #define WM5100_EQ2_B4_PG_SHIFT                       0  /* EQ2_B4_PG - [15:0] */
4148 #define WM5100_EQ2_B4_PG_WIDTH                      16  /* EQ2_B4_PG - [15:0] */
4149 
4150 /*
4151  * R3639 (0xE37) - EQ2_18
4152  */
4153 #define WM5100_EQ2_B5_A_MASK                    0xFFFF  /* EQ2_B5_A - [15:0] */
4154 #define WM5100_EQ2_B5_A_SHIFT                        0  /* EQ2_B5_A - [15:0] */
4155 #define WM5100_EQ2_B5_A_WIDTH                       16  /* EQ2_B5_A - [15:0] */
4156 
4157 /*
4158  * R3640 (0xE38) - EQ2_19
4159  */
4160 #define WM5100_EQ2_B5_B_MASK                    0xFFFF  /* EQ2_B5_B - [15:0] */
4161 #define WM5100_EQ2_B5_B_SHIFT                        0  /* EQ2_B5_B - [15:0] */
4162 #define WM5100_EQ2_B5_B_WIDTH                       16  /* EQ2_B5_B - [15:0] */
4163 
4164 /*
4165  * R3641 (0xE39) - EQ2_20
4166  */
4167 #define WM5100_EQ2_B5_PG_MASK                   0xFFFF  /* EQ2_B5_PG - [15:0] */
4168 #define WM5100_EQ2_B5_PG_SHIFT                       0  /* EQ2_B5_PG - [15:0] */
4169 #define WM5100_EQ2_B5_PG_WIDTH                      16  /* EQ2_B5_PG - [15:0] */
4170 
4171 /*
4172  * R3644 (0xE3C) - EQ3_1
4173  */
4174 #define WM5100_EQ3_B1_GAIN_MASK                 0xF800  /* EQ3_B1_GAIN - [15:11] */
4175 #define WM5100_EQ3_B1_GAIN_SHIFT                    11  /* EQ3_B1_GAIN - [15:11] */
4176 #define WM5100_EQ3_B1_GAIN_WIDTH                     5  /* EQ3_B1_GAIN - [15:11] */
4177 #define WM5100_EQ3_B2_GAIN_MASK                 0x07C0  /* EQ3_B2_GAIN - [10:6] */
4178 #define WM5100_EQ3_B2_GAIN_SHIFT                     6  /* EQ3_B2_GAIN - [10:6] */
4179 #define WM5100_EQ3_B2_GAIN_WIDTH                     5  /* EQ3_B2_GAIN - [10:6] */
4180 #define WM5100_EQ3_B3_GAIN_MASK                 0x003E  /* EQ3_B3_GAIN - [5:1] */
4181 #define WM5100_EQ3_B3_GAIN_SHIFT                     1  /* EQ3_B3_GAIN - [5:1] */
4182 #define WM5100_EQ3_B3_GAIN_WIDTH                     5  /* EQ3_B3_GAIN - [5:1] */
4183 #define WM5100_EQ3_ENA                          0x0001  /* EQ3_ENA */
4184 #define WM5100_EQ3_ENA_MASK                     0x0001  /* EQ3_ENA */
4185 #define WM5100_EQ3_ENA_SHIFT                         0  /* EQ3_ENA */
4186 #define WM5100_EQ3_ENA_WIDTH                         1  /* EQ3_ENA */
4187 
4188 /*
4189  * R3645 (0xE3D) - EQ3_2
4190  */
4191 #define WM5100_EQ3_B4_GAIN_MASK                 0xF800  /* EQ3_B4_GAIN - [15:11] */
4192 #define WM5100_EQ3_B4_GAIN_SHIFT                    11  /* EQ3_B4_GAIN - [15:11] */
4193 #define WM5100_EQ3_B4_GAIN_WIDTH                     5  /* EQ3_B4_GAIN - [15:11] */
4194 #define WM5100_EQ3_B5_GAIN_MASK                 0x07C0  /* EQ3_B5_GAIN - [10:6] */
4195 #define WM5100_EQ3_B5_GAIN_SHIFT                     6  /* EQ3_B5_GAIN - [10:6] */
4196 #define WM5100_EQ3_B5_GAIN_WIDTH                     5  /* EQ3_B5_GAIN - [10:6] */
4197 
4198 /*
4199  * R3646 (0xE3E) - EQ3_3
4200  */
4201 #define WM5100_EQ3_B1_A_MASK                    0xFFFF  /* EQ3_B1_A - [15:0] */
4202 #define WM5100_EQ3_B1_A_SHIFT                        0  /* EQ3_B1_A - [15:0] */
4203 #define WM5100_EQ3_B1_A_WIDTH                       16  /* EQ3_B1_A - [15:0] */
4204 
4205 /*
4206  * R3647 (0xE3F) - EQ3_4
4207  */
4208 #define WM5100_EQ3_B1_B_MASK                    0xFFFF  /* EQ3_B1_B - [15:0] */
4209 #define WM5100_EQ3_B1_B_SHIFT                        0  /* EQ3_B1_B - [15:0] */
4210 #define WM5100_EQ3_B1_B_WIDTH                       16  /* EQ3_B1_B - [15:0] */
4211 
4212 /*
4213  * R3648 (0xE40) - EQ3_5
4214  */
4215 #define WM5100_EQ3_B1_PG_MASK                   0xFFFF  /* EQ3_B1_PG - [15:0] */
4216 #define WM5100_EQ3_B1_PG_SHIFT                       0  /* EQ3_B1_PG - [15:0] */
4217 #define WM5100_EQ3_B1_PG_WIDTH                      16  /* EQ3_B1_PG - [15:0] */
4218 
4219 /*
4220  * R3649 (0xE41) - EQ3_6
4221  */
4222 #define WM5100_EQ3_B2_A_MASK                    0xFFFF  /* EQ3_B2_A - [15:0] */
4223 #define WM5100_EQ3_B2_A_SHIFT                        0  /* EQ3_B2_A - [15:0] */
4224 #define WM5100_EQ3_B2_A_WIDTH                       16  /* EQ3_B2_A - [15:0] */
4225 
4226 /*
4227  * R3650 (0xE42) - EQ3_7
4228  */
4229 #define WM5100_EQ3_B2_B_MASK                    0xFFFF  /* EQ3_B2_B - [15:0] */
4230 #define WM5100_EQ3_B2_B_SHIFT                        0  /* EQ3_B2_B - [15:0] */
4231 #define WM5100_EQ3_B2_B_WIDTH                       16  /* EQ3_B2_B - [15:0] */
4232 
4233 /*
4234  * R3651 (0xE43) - EQ3_8
4235  */
4236 #define WM5100_EQ3_B2_C_MASK                    0xFFFF  /* EQ3_B2_C - [15:0] */
4237 #define WM5100_EQ3_B2_C_SHIFT                        0  /* EQ3_B2_C - [15:0] */
4238 #define WM5100_EQ3_B2_C_WIDTH                       16  /* EQ3_B2_C - [15:0] */
4239 
4240 /*
4241  * R3652 (0xE44) - EQ3_9
4242  */
4243 #define WM5100_EQ3_B2_PG_MASK                   0xFFFF  /* EQ3_B2_PG - [15:0] */
4244 #define WM5100_EQ3_B2_PG_SHIFT                       0  /* EQ3_B2_PG - [15:0] */
4245 #define WM5100_EQ3_B2_PG_WIDTH                      16  /* EQ3_B2_PG - [15:0] */
4246 
4247 /*
4248  * R3653 (0xE45) - EQ3_10
4249  */
4250 #define WM5100_EQ3_B3_A_MASK                    0xFFFF  /* EQ3_B3_A - [15:0] */
4251 #define WM5100_EQ3_B3_A_SHIFT                        0  /* EQ3_B3_A - [15:0] */
4252 #define WM5100_EQ3_B3_A_WIDTH                       16  /* EQ3_B3_A - [15:0] */
4253 
4254 /*
4255  * R3654 (0xE46) - EQ3_11
4256  */
4257 #define WM5100_EQ3_B3_B_MASK                    0xFFFF  /* EQ3_B3_B - [15:0] */
4258 #define WM5100_EQ3_B3_B_SHIFT                        0  /* EQ3_B3_B - [15:0] */
4259 #define WM5100_EQ3_B3_B_WIDTH                       16  /* EQ3_B3_B - [15:0] */
4260 
4261 /*
4262  * R3655 (0xE47) - EQ3_12
4263  */
4264 #define WM5100_EQ3_B3_C_MASK                    0xFFFF  /* EQ3_B3_C - [15:0] */
4265 #define WM5100_EQ3_B3_C_SHIFT                        0  /* EQ3_B3_C - [15:0] */
4266 #define WM5100_EQ3_B3_C_WIDTH                       16  /* EQ3_B3_C - [15:0] */
4267 
4268 /*
4269  * R3656 (0xE48) - EQ3_13
4270  */
4271 #define WM5100_EQ3_B3_PG_MASK                   0xFFFF  /* EQ3_B3_PG - [15:0] */
4272 #define WM5100_EQ3_B3_PG_SHIFT                       0  /* EQ3_B3_PG - [15:0] */
4273 #define WM5100_EQ3_B3_PG_WIDTH                      16  /* EQ3_B3_PG - [15:0] */
4274 
4275 /*
4276  * R3657 (0xE49) - EQ3_14
4277  */
4278 #define WM5100_EQ3_B4_A_MASK                    0xFFFF  /* EQ3_B4_A - [15:0] */
4279 #define WM5100_EQ3_B4_A_SHIFT                        0  /* EQ3_B4_A - [15:0] */
4280 #define WM5100_EQ3_B4_A_WIDTH                       16  /* EQ3_B4_A - [15:0] */
4281 
4282 /*
4283  * R3658 (0xE4A) - EQ3_15
4284  */
4285 #define WM5100_EQ3_B4_B_MASK                    0xFFFF  /* EQ3_B4_B - [15:0] */
4286 #define WM5100_EQ3_B4_B_SHIFT                        0  /* EQ3_B4_B - [15:0] */
4287 #define WM5100_EQ3_B4_B_WIDTH                       16  /* EQ3_B4_B - [15:0] */
4288 
4289 /*
4290  * R3659 (0xE4B) - EQ3_16
4291  */
4292 #define WM5100_EQ3_B4_C_MASK                    0xFFFF  /* EQ3_B4_C - [15:0] */
4293 #define WM5100_EQ3_B4_C_SHIFT                        0  /* EQ3_B4_C - [15:0] */
4294 #define WM5100_EQ3_B4_C_WIDTH                       16  /* EQ3_B4_C - [15:0] */
4295 
4296 /*
4297  * R3660 (0xE4C) - EQ3_17
4298  */
4299 #define WM5100_EQ3_B4_PG_MASK                   0xFFFF  /* EQ3_B4_PG - [15:0] */
4300 #define WM5100_EQ3_B4_PG_SHIFT                       0  /* EQ3_B4_PG - [15:0] */
4301 #define WM5100_EQ3_B4_PG_WIDTH                      16  /* EQ3_B4_PG - [15:0] */
4302 
4303 /*
4304  * R3661 (0xE4D) - EQ3_18
4305  */
4306 #define WM5100_EQ3_B5_A_MASK                    0xFFFF  /* EQ3_B5_A - [15:0] */
4307 #define WM5100_EQ3_B5_A_SHIFT                        0  /* EQ3_B5_A - [15:0] */
4308 #define WM5100_EQ3_B5_A_WIDTH                       16  /* EQ3_B5_A - [15:0] */
4309 
4310 /*
4311  * R3662 (0xE4E) - EQ3_19
4312  */
4313 #define WM5100_EQ3_B5_B_MASK                    0xFFFF  /* EQ3_B5_B - [15:0] */
4314 #define WM5100_EQ3_B5_B_SHIFT                        0  /* EQ3_B5_B - [15:0] */
4315 #define WM5100_EQ3_B5_B_WIDTH                       16  /* EQ3_B5_B - [15:0] */
4316 
4317 /*
4318  * R3663 (0xE4F) - EQ3_20
4319  */
4320 #define WM5100_EQ3_B5_PG_MASK                   0xFFFF  /* EQ3_B5_PG - [15:0] */
4321 #define WM5100_EQ3_B5_PG_SHIFT                       0  /* EQ3_B5_PG - [15:0] */
4322 #define WM5100_EQ3_B5_PG_WIDTH                      16  /* EQ3_B5_PG - [15:0] */
4323 
4324 /*
4325  * R3666 (0xE52) - EQ4_1
4326  */
4327 #define WM5100_EQ4_B1_GAIN_MASK                 0xF800  /* EQ4_B1_GAIN - [15:11] */
4328 #define WM5100_EQ4_B1_GAIN_SHIFT                    11  /* EQ4_B1_GAIN - [15:11] */
4329 #define WM5100_EQ4_B1_GAIN_WIDTH                     5  /* EQ4_B1_GAIN - [15:11] */
4330 #define WM5100_EQ4_B2_GAIN_MASK                 0x07C0  /* EQ4_B2_GAIN - [10:6] */
4331 #define WM5100_EQ4_B2_GAIN_SHIFT                     6  /* EQ4_B2_GAIN - [10:6] */
4332 #define WM5100_EQ4_B2_GAIN_WIDTH                     5  /* EQ4_B2_GAIN - [10:6] */
4333 #define WM5100_EQ4_B3_GAIN_MASK                 0x003E  /* EQ4_B3_GAIN - [5:1] */
4334 #define WM5100_EQ4_B3_GAIN_SHIFT                     1  /* EQ4_B3_GAIN - [5:1] */
4335 #define WM5100_EQ4_B3_GAIN_WIDTH                     5  /* EQ4_B3_GAIN - [5:1] */
4336 #define WM5100_EQ4_ENA                          0x0001  /* EQ4_ENA */
4337 #define WM5100_EQ4_ENA_MASK                     0x0001  /* EQ4_ENA */
4338 #define WM5100_EQ4_ENA_SHIFT                         0  /* EQ4_ENA */
4339 #define WM5100_EQ4_ENA_WIDTH                         1  /* EQ4_ENA */
4340 
4341 /*
4342  * R3667 (0xE53) - EQ4_2
4343  */
4344 #define WM5100_EQ4_B4_GAIN_MASK                 0xF800  /* EQ4_B4_GAIN - [15:11] */
4345 #define WM5100_EQ4_B4_GAIN_SHIFT                    11  /* EQ4_B4_GAIN - [15:11] */
4346 #define WM5100_EQ4_B4_GAIN_WIDTH                     5  /* EQ4_B4_GAIN - [15:11] */
4347 #define WM5100_EQ4_B5_GAIN_MASK                 0x07C0  /* EQ4_B5_GAIN - [10:6] */
4348 #define WM5100_EQ4_B5_GAIN_SHIFT                     6  /* EQ4_B5_GAIN - [10:6] */
4349 #define WM5100_EQ4_B5_GAIN_WIDTH                     5  /* EQ4_B5_GAIN - [10:6] */
4350 
4351 /*
4352  * R3668 (0xE54) - EQ4_3
4353  */
4354 #define WM5100_EQ4_B1_A_MASK                    0xFFFF  /* EQ4_B1_A - [15:0] */
4355 #define WM5100_EQ4_B1_A_SHIFT                        0  /* EQ4_B1_A - [15:0] */
4356 #define WM5100_EQ4_B1_A_WIDTH                       16  /* EQ4_B1_A - [15:0] */
4357 
4358 /*
4359  * R3669 (0xE55) - EQ4_4
4360  */
4361 #define WM5100_EQ4_B1_B_MASK                    0xFFFF  /* EQ4_B1_B - [15:0] */
4362 #define WM5100_EQ4_B1_B_SHIFT                        0  /* EQ4_B1_B - [15:0] */
4363 #define WM5100_EQ4_B1_B_WIDTH                       16  /* EQ4_B1_B - [15:0] */
4364 
4365 /*
4366  * R3670 (0xE56) - EQ4_5
4367  */
4368 #define WM5100_EQ4_B1_PG_MASK                   0xFFFF  /* EQ4_B1_PG - [15:0] */
4369 #define WM5100_EQ4_B1_PG_SHIFT                       0  /* EQ4_B1_PG - [15:0] */
4370 #define WM5100_EQ4_B1_PG_WIDTH                      16  /* EQ4_B1_PG - [15:0] */
4371 
4372 /*
4373  * R3671 (0xE57) - EQ4_6
4374  */
4375 #define WM5100_EQ4_B2_A_MASK                    0xFFFF  /* EQ4_B2_A - [15:0] */
4376 #define WM5100_EQ4_B2_A_SHIFT                        0  /* EQ4_B2_A - [15:0] */
4377 #define WM5100_EQ4_B2_A_WIDTH                       16  /* EQ4_B2_A - [15:0] */
4378 
4379 /*
4380  * R3672 (0xE58) - EQ4_7
4381  */
4382 #define WM5100_EQ4_B2_B_MASK                    0xFFFF  /* EQ4_B2_B - [15:0] */
4383 #define WM5100_EQ4_B2_B_SHIFT                        0  /* EQ4_B2_B - [15:0] */
4384 #define WM5100_EQ4_B2_B_WIDTH                       16  /* EQ4_B2_B - [15:0] */
4385 
4386 /*
4387  * R3673 (0xE59) - EQ4_8
4388  */
4389 #define WM5100_EQ4_B2_C_MASK                    0xFFFF  /* EQ4_B2_C - [15:0] */
4390 #define WM5100_EQ4_B2_C_SHIFT                        0  /* EQ4_B2_C - [15:0] */
4391 #define WM5100_EQ4_B2_C_WIDTH                       16  /* EQ4_B2_C - [15:0] */
4392 
4393 /*
4394  * R3674 (0xE5A) - EQ4_9
4395  */
4396 #define WM5100_EQ4_B2_PG_MASK                   0xFFFF  /* EQ4_B2_PG - [15:0] */
4397 #define WM5100_EQ4_B2_PG_SHIFT                       0  /* EQ4_B2_PG - [15:0] */
4398 #define WM5100_EQ4_B2_PG_WIDTH                      16  /* EQ4_B2_PG - [15:0] */
4399 
4400 /*
4401  * R3675 (0xE5B) - EQ4_10
4402  */
4403 #define WM5100_EQ4_B3_A_MASK                    0xFFFF  /* EQ4_B3_A - [15:0] */
4404 #define WM5100_EQ4_B3_A_SHIFT                        0  /* EQ4_B3_A - [15:0] */
4405 #define WM5100_EQ4_B3_A_WIDTH                       16  /* EQ4_B3_A - [15:0] */
4406 
4407 /*
4408  * R3676 (0xE5C) - EQ4_11
4409  */
4410 #define WM5100_EQ4_B3_B_MASK                    0xFFFF  /* EQ4_B3_B - [15:0] */
4411 #define WM5100_EQ4_B3_B_SHIFT                        0  /* EQ4_B3_B - [15:0] */
4412 #define WM5100_EQ4_B3_B_WIDTH                       16  /* EQ4_B3_B - [15:0] */
4413 
4414 /*
4415  * R3677 (0xE5D) - EQ4_12
4416  */
4417 #define WM5100_EQ4_B3_C_MASK                    0xFFFF  /* EQ4_B3_C - [15:0] */
4418 #define WM5100_EQ4_B3_C_SHIFT                        0  /* EQ4_B3_C - [15:0] */
4419 #define WM5100_EQ4_B3_C_WIDTH                       16  /* EQ4_B3_C - [15:0] */
4420 
4421 /*
4422  * R3678 (0xE5E) - EQ4_13
4423  */
4424 #define WM5100_EQ4_B3_PG_MASK                   0xFFFF  /* EQ4_B3_PG - [15:0] */
4425 #define WM5100_EQ4_B3_PG_SHIFT                       0  /* EQ4_B3_PG - [15:0] */
4426 #define WM5100_EQ4_B3_PG_WIDTH                      16  /* EQ4_B3_PG - [15:0] */
4427 
4428 /*
4429  * R3679 (0xE5F) - EQ4_14
4430  */
4431 #define WM5100_EQ4_B4_A_MASK                    0xFFFF  /* EQ4_B4_A - [15:0] */
4432 #define WM5100_EQ4_B4_A_SHIFT                        0  /* EQ4_B4_A - [15:0] */
4433 #define WM5100_EQ4_B4_A_WIDTH                       16  /* EQ4_B4_A - [15:0] */
4434 
4435 /*
4436  * R3680 (0xE60) - EQ4_15
4437  */
4438 #define WM5100_EQ4_B4_B_MASK                    0xFFFF  /* EQ4_B4_B - [15:0] */
4439 #define WM5100_EQ4_B4_B_SHIFT                        0  /* EQ4_B4_B - [15:0] */
4440 #define WM5100_EQ4_B4_B_WIDTH                       16  /* EQ4_B4_B - [15:0] */
4441 
4442 /*
4443  * R3681 (0xE61) - EQ4_16
4444  */
4445 #define WM5100_EQ4_B4_C_MASK                    0xFFFF  /* EQ4_B4_C - [15:0] */
4446 #define WM5100_EQ4_B4_C_SHIFT                        0  /* EQ4_B4_C - [15:0] */
4447 #define WM5100_EQ4_B4_C_WIDTH                       16  /* EQ4_B4_C - [15:0] */
4448 
4449 /*
4450  * R3682 (0xE62) - EQ4_17
4451  */
4452 #define WM5100_EQ4_B4_PG_MASK                   0xFFFF  /* EQ4_B4_PG - [15:0] */
4453 #define WM5100_EQ4_B4_PG_SHIFT                       0  /* EQ4_B4_PG - [15:0] */
4454 #define WM5100_EQ4_B4_PG_WIDTH                      16  /* EQ4_B4_PG - [15:0] */
4455 
4456 /*
4457  * R3683 (0xE63) - EQ4_18
4458  */
4459 #define WM5100_EQ4_B5_A_MASK                    0xFFFF  /* EQ4_B5_A - [15:0] */
4460 #define WM5100_EQ4_B5_A_SHIFT                        0  /* EQ4_B5_A - [15:0] */
4461 #define WM5100_EQ4_B5_A_WIDTH                       16  /* EQ4_B5_A - [15:0] */
4462 
4463 /*
4464  * R3684 (0xE64) - EQ4_19
4465  */
4466 #define WM5100_EQ4_B5_B_MASK                    0xFFFF  /* EQ4_B5_B - [15:0] */
4467 #define WM5100_EQ4_B5_B_SHIFT                        0  /* EQ4_B5_B - [15:0] */
4468 #define WM5100_EQ4_B5_B_WIDTH                       16  /* EQ4_B5_B - [15:0] */
4469 
4470 /*
4471  * R3685 (0xE65) - EQ4_20
4472  */
4473 #define WM5100_EQ4_B5_PG_MASK                   0xFFFF  /* EQ4_B5_PG - [15:0] */
4474 #define WM5100_EQ4_B5_PG_SHIFT                       0  /* EQ4_B5_PG - [15:0] */
4475 #define WM5100_EQ4_B5_PG_WIDTH                      16  /* EQ4_B5_PG - [15:0] */
4476 
4477 /*
4478  * R3712 (0xE80) - DRC1 ctrl1
4479  */
4480 #define WM5100_DRC_SIG_DET_RMS_MASK             0xF800  /* DRC_SIG_DET_RMS - [15:11] */
4481 #define WM5100_DRC_SIG_DET_RMS_SHIFT                11  /* DRC_SIG_DET_RMS - [15:11] */
4482 #define WM5100_DRC_SIG_DET_RMS_WIDTH                 5  /* DRC_SIG_DET_RMS - [15:11] */
4483 #define WM5100_DRC_SIG_DET_PK_MASK              0x0600  /* DRC_SIG_DET_PK - [10:9] */
4484 #define WM5100_DRC_SIG_DET_PK_SHIFT                  9  /* DRC_SIG_DET_PK - [10:9] */
4485 #define WM5100_DRC_SIG_DET_PK_WIDTH                  2  /* DRC_SIG_DET_PK - [10:9] */
4486 #define WM5100_DRC_NG_ENA                       0x0100  /* DRC_NG_ENA */
4487 #define WM5100_DRC_NG_ENA_MASK                  0x0100  /* DRC_NG_ENA */
4488 #define WM5100_DRC_NG_ENA_SHIFT                      8  /* DRC_NG_ENA */
4489 #define WM5100_DRC_NG_ENA_WIDTH                      1  /* DRC_NG_ENA */
4490 #define WM5100_DRC_SIG_DET_MODE                 0x0080  /* DRC_SIG_DET_MODE */
4491 #define WM5100_DRC_SIG_DET_MODE_MASK            0x0080  /* DRC_SIG_DET_MODE */
4492 #define WM5100_DRC_SIG_DET_MODE_SHIFT                7  /* DRC_SIG_DET_MODE */
4493 #define WM5100_DRC_SIG_DET_MODE_WIDTH                1  /* DRC_SIG_DET_MODE */
4494 #define WM5100_DRC_SIG_DET                      0x0040  /* DRC_SIG_DET */
4495 #define WM5100_DRC_SIG_DET_MASK                 0x0040  /* DRC_SIG_DET */
4496 #define WM5100_DRC_SIG_DET_SHIFT                     6  /* DRC_SIG_DET */
4497 #define WM5100_DRC_SIG_DET_WIDTH                     1  /* DRC_SIG_DET */
4498 #define WM5100_DRC_KNEE2_OP_ENA                 0x0020  /* DRC_KNEE2_OP_ENA */
4499 #define WM5100_DRC_KNEE2_OP_ENA_MASK            0x0020  /* DRC_KNEE2_OP_ENA */
4500 #define WM5100_DRC_KNEE2_OP_ENA_SHIFT                5  /* DRC_KNEE2_OP_ENA */
4501 #define WM5100_DRC_KNEE2_OP_ENA_WIDTH                1  /* DRC_KNEE2_OP_ENA */
4502 #define WM5100_DRC_QR                           0x0010  /* DRC_QR */
4503 #define WM5100_DRC_QR_MASK                      0x0010  /* DRC_QR */
4504 #define WM5100_DRC_QR_SHIFT                          4  /* DRC_QR */
4505 #define WM5100_DRC_QR_WIDTH                          1  /* DRC_QR */
4506 #define WM5100_DRC_ANTICLIP                     0x0008  /* DRC_ANTICLIP */
4507 #define WM5100_DRC_ANTICLIP_MASK                0x0008  /* DRC_ANTICLIP */
4508 #define WM5100_DRC_ANTICLIP_SHIFT                    3  /* DRC_ANTICLIP */
4509 #define WM5100_DRC_ANTICLIP_WIDTH                    1  /* DRC_ANTICLIP */
4510 #define WM5100_DRCL_ENA                         0x0002  /* DRCL_ENA */
4511 #define WM5100_DRCL_ENA_MASK                    0x0002  /* DRCL_ENA */
4512 #define WM5100_DRCL_ENA_SHIFT                        1  /* DRCL_ENA */
4513 #define WM5100_DRCL_ENA_WIDTH                        1  /* DRCL_ENA */
4514 #define WM5100_DRCR_ENA                         0x0001  /* DRCR_ENA */
4515 #define WM5100_DRCR_ENA_MASK                    0x0001  /* DRCR_ENA */
4516 #define WM5100_DRCR_ENA_SHIFT                        0  /* DRCR_ENA */
4517 #define WM5100_DRCR_ENA_WIDTH                        1  /* DRCR_ENA */
4518 
4519 /*
4520  * R3713 (0xE81) - DRC1 ctrl2
4521  */
4522 #define WM5100_DRC_ATK_MASK                     0x1E00  /* DRC_ATK - [12:9] */
4523 #define WM5100_DRC_ATK_SHIFT                         9  /* DRC_ATK - [12:9] */
4524 #define WM5100_DRC_ATK_WIDTH                         4  /* DRC_ATK - [12:9] */
4525 #define WM5100_DRC_DCY_MASK                     0x01E0  /* DRC_DCY - [8:5] */
4526 #define WM5100_DRC_DCY_SHIFT                         5  /* DRC_DCY - [8:5] */
4527 #define WM5100_DRC_DCY_WIDTH                         4  /* DRC_DCY - [8:5] */
4528 #define WM5100_DRC_MINGAIN_MASK                 0x001C  /* DRC_MINGAIN - [4:2] */
4529 #define WM5100_DRC_MINGAIN_SHIFT                     2  /* DRC_MINGAIN - [4:2] */
4530 #define WM5100_DRC_MINGAIN_WIDTH                     3  /* DRC_MINGAIN - [4:2] */
4531 #define WM5100_DRC_MAXGAIN_MASK                 0x0003  /* DRC_MAXGAIN - [1:0] */
4532 #define WM5100_DRC_MAXGAIN_SHIFT                     0  /* DRC_MAXGAIN - [1:0] */
4533 #define WM5100_DRC_MAXGAIN_WIDTH                     2  /* DRC_MAXGAIN - [1:0] */
4534 
4535 /*
4536  * R3714 (0xE82) - DRC1 ctrl3
4537  */
4538 #define WM5100_DRC_NG_MINGAIN_MASK              0xF000  /* DRC_NG_MINGAIN - [15:12] */
4539 #define WM5100_DRC_NG_MINGAIN_SHIFT                 12  /* DRC_NG_MINGAIN - [15:12] */
4540 #define WM5100_DRC_NG_MINGAIN_WIDTH                  4  /* DRC_NG_MINGAIN - [15:12] */
4541 #define WM5100_DRC_NG_EXP_MASK                  0x0C00  /* DRC_NG_EXP - [11:10] */
4542 #define WM5100_DRC_NG_EXP_SHIFT                     10  /* DRC_NG_EXP - [11:10] */
4543 #define WM5100_DRC_NG_EXP_WIDTH                      2  /* DRC_NG_EXP - [11:10] */
4544 #define WM5100_DRC_QR_THR_MASK                  0x0300  /* DRC_QR_THR - [9:8] */
4545 #define WM5100_DRC_QR_THR_SHIFT                      8  /* DRC_QR_THR - [9:8] */
4546 #define WM5100_DRC_QR_THR_WIDTH                      2  /* DRC_QR_THR - [9:8] */
4547 #define WM5100_DRC_QR_DCY_MASK                  0x00C0  /* DRC_QR_DCY - [7:6] */
4548 #define WM5100_DRC_QR_DCY_SHIFT                      6  /* DRC_QR_DCY - [7:6] */
4549 #define WM5100_DRC_QR_DCY_WIDTH                      2  /* DRC_QR_DCY - [7:6] */
4550 #define WM5100_DRC_HI_COMP_MASK                 0x0038  /* DRC_HI_COMP - [5:3] */
4551 #define WM5100_DRC_HI_COMP_SHIFT                     3  /* DRC_HI_COMP - [5:3] */
4552 #define WM5100_DRC_HI_COMP_WIDTH                     3  /* DRC_HI_COMP - [5:3] */
4553 #define WM5100_DRC_LO_COMP_MASK                 0x0007  /* DRC_LO_COMP - [2:0] */
4554 #define WM5100_DRC_LO_COMP_SHIFT                     0  /* DRC_LO_COMP - [2:0] */
4555 #define WM5100_DRC_LO_COMP_WIDTH                     3  /* DRC_LO_COMP - [2:0] */
4556 
4557 /*
4558  * R3715 (0xE83) - DRC1 ctrl4
4559  */
4560 #define WM5100_DRC_KNEE_IP_MASK                 0x07E0  /* DRC_KNEE_IP - [10:5] */
4561 #define WM5100_DRC_KNEE_IP_SHIFT                     5  /* DRC_KNEE_IP - [10:5] */
4562 #define WM5100_DRC_KNEE_IP_WIDTH                     6  /* DRC_KNEE_IP - [10:5] */
4563 #define WM5100_DRC_KNEE_OP_MASK                 0x001F  /* DRC_KNEE_OP - [4:0] */
4564 #define WM5100_DRC_KNEE_OP_SHIFT                     0  /* DRC_KNEE_OP - [4:0] */
4565 #define WM5100_DRC_KNEE_OP_WIDTH                     5  /* DRC_KNEE_OP - [4:0] */
4566 
4567 /*
4568  * R3716 (0xE84) - DRC1 ctrl5
4569  */
4570 #define WM5100_DRC_KNEE2_IP_MASK                0x03E0  /* DRC_KNEE2_IP - [9:5] */
4571 #define WM5100_DRC_KNEE2_IP_SHIFT                    5  /* DRC_KNEE2_IP - [9:5] */
4572 #define WM5100_DRC_KNEE2_IP_WIDTH                    5  /* DRC_KNEE2_IP - [9:5] */
4573 #define WM5100_DRC_KNEE2_OP_MASK                0x001F  /* DRC_KNEE2_OP - [4:0] */
4574 #define WM5100_DRC_KNEE2_OP_SHIFT                    0  /* DRC_KNEE2_OP - [4:0] */
4575 #define WM5100_DRC_KNEE2_OP_WIDTH                    5  /* DRC_KNEE2_OP - [4:0] */
4576 
4577 /*
4578  * R3776 (0xEC0) - HPLPF1_1
4579  */
4580 #define WM5100_LHPF1_MODE                       0x0002  /* LHPF1_MODE */
4581 #define WM5100_LHPF1_MODE_MASK                  0x0002  /* LHPF1_MODE */
4582 #define WM5100_LHPF1_MODE_SHIFT                      1  /* LHPF1_MODE */
4583 #define WM5100_LHPF1_MODE_WIDTH                      1  /* LHPF1_MODE */
4584 #define WM5100_LHPF1_ENA                        0x0001  /* LHPF1_ENA */
4585 #define WM5100_LHPF1_ENA_MASK                   0x0001  /* LHPF1_ENA */
4586 #define WM5100_LHPF1_ENA_SHIFT                       0  /* LHPF1_ENA */
4587 #define WM5100_LHPF1_ENA_WIDTH                       1  /* LHPF1_ENA */
4588 
4589 /*
4590  * R3777 (0xEC1) - HPLPF1_2
4591  */
4592 #define WM5100_LHPF1_COEFF_MASK                 0xFFFF  /* LHPF1_COEFF - [15:0] */
4593 #define WM5100_LHPF1_COEFF_SHIFT                     0  /* LHPF1_COEFF - [15:0] */
4594 #define WM5100_LHPF1_COEFF_WIDTH                    16  /* LHPF1_COEFF - [15:0] */
4595 
4596 /*
4597  * R3780 (0xEC4) - HPLPF2_1
4598  */
4599 #define WM5100_LHPF2_MODE                       0x0002  /* LHPF2_MODE */
4600 #define WM5100_LHPF2_MODE_MASK                  0x0002  /* LHPF2_MODE */
4601 #define WM5100_LHPF2_MODE_SHIFT                      1  /* LHPF2_MODE */
4602 #define WM5100_LHPF2_MODE_WIDTH                      1  /* LHPF2_MODE */
4603 #define WM5100_LHPF2_ENA                        0x0001  /* LHPF2_ENA */
4604 #define WM5100_LHPF2_ENA_MASK                   0x0001  /* LHPF2_ENA */
4605 #define WM5100_LHPF2_ENA_SHIFT                       0  /* LHPF2_ENA */
4606 #define WM5100_LHPF2_ENA_WIDTH                       1  /* LHPF2_ENA */
4607 
4608 /*
4609  * R3781 (0xEC5) - HPLPF2_2
4610  */
4611 #define WM5100_LHPF2_COEFF_MASK                 0xFFFF  /* LHPF2_COEFF - [15:0] */
4612 #define WM5100_LHPF2_COEFF_SHIFT                     0  /* LHPF2_COEFF - [15:0] */
4613 #define WM5100_LHPF2_COEFF_WIDTH                    16  /* LHPF2_COEFF - [15:0] */
4614 
4615 /*
4616  * R3784 (0xEC8) - HPLPF3_1
4617  */
4618 #define WM5100_LHPF3_MODE                       0x0002  /* LHPF3_MODE */
4619 #define WM5100_LHPF3_MODE_MASK                  0x0002  /* LHPF3_MODE */
4620 #define WM5100_LHPF3_MODE_SHIFT                      1  /* LHPF3_MODE */
4621 #define WM5100_LHPF3_MODE_WIDTH                      1  /* LHPF3_MODE */
4622 #define WM5100_LHPF3_ENA                        0x0001  /* LHPF3_ENA */
4623 #define WM5100_LHPF3_ENA_MASK                   0x0001  /* LHPF3_ENA */
4624 #define WM5100_LHPF3_ENA_SHIFT                       0  /* LHPF3_ENA */
4625 #define WM5100_LHPF3_ENA_WIDTH                       1  /* LHPF3_ENA */
4626 
4627 /*
4628  * R3785 (0xEC9) - HPLPF3_2
4629  */
4630 #define WM5100_LHPF3_COEFF_MASK                 0xFFFF  /* LHPF3_COEFF - [15:0] */
4631 #define WM5100_LHPF3_COEFF_SHIFT                     0  /* LHPF3_COEFF - [15:0] */
4632 #define WM5100_LHPF3_COEFF_WIDTH                    16  /* LHPF3_COEFF - [15:0] */
4633 
4634 /*
4635  * R3788 (0xECC) - HPLPF4_1
4636  */
4637 #define WM5100_LHPF4_MODE                       0x0002  /* LHPF4_MODE */
4638 #define WM5100_LHPF4_MODE_MASK                  0x0002  /* LHPF4_MODE */
4639 #define WM5100_LHPF4_MODE_SHIFT                      1  /* LHPF4_MODE */
4640 #define WM5100_LHPF4_MODE_WIDTH                      1  /* LHPF4_MODE */
4641 #define WM5100_LHPF4_ENA                        0x0001  /* LHPF4_ENA */
4642 #define WM5100_LHPF4_ENA_MASK                   0x0001  /* LHPF4_ENA */
4643 #define WM5100_LHPF4_ENA_SHIFT                       0  /* LHPF4_ENA */
4644 #define WM5100_LHPF4_ENA_WIDTH                       1  /* LHPF4_ENA */
4645 
4646 /*
4647  * R3789 (0xECD) - HPLPF4_2
4648  */
4649 #define WM5100_LHPF4_COEFF_MASK                 0xFFFF  /* LHPF4_COEFF - [15:0] */
4650 #define WM5100_LHPF4_COEFF_SHIFT                     0  /* LHPF4_COEFF - [15:0] */
4651 #define WM5100_LHPF4_COEFF_WIDTH                    16  /* LHPF4_COEFF - [15:0] */
4652 
4653 /*
4654  * R4132 (0x1024) - DSP2 Control 30
4655  */
4656 #define WM5100_DSP2_RATE_MASK                   0xC000  /* DSP2_RATE - [15:14] */
4657 #define WM5100_DSP2_RATE_SHIFT                      14  /* DSP2_RATE - [15:14] */
4658 #define WM5100_DSP2_RATE_WIDTH                       2  /* DSP2_RATE - [15:14] */
4659 #define WM5100_DSP2_DBG_CLK_ENA                 0x0008  /* DSP2_DBG_CLK_ENA */
4660 #define WM5100_DSP2_DBG_CLK_ENA_MASK            0x0008  /* DSP2_DBG_CLK_ENA */
4661 #define WM5100_DSP2_DBG_CLK_ENA_SHIFT                3  /* DSP2_DBG_CLK_ENA */
4662 #define WM5100_DSP2_DBG_CLK_ENA_WIDTH                1  /* DSP2_DBG_CLK_ENA */
4663 #define WM5100_DSP2_SYS_ENA                     0x0004  /* DSP2_SYS_ENA */
4664 #define WM5100_DSP2_SYS_ENA_MASK                0x0004  /* DSP2_SYS_ENA */
4665 #define WM5100_DSP2_SYS_ENA_SHIFT                    2  /* DSP2_SYS_ENA */
4666 #define WM5100_DSP2_SYS_ENA_WIDTH                    1  /* DSP2_SYS_ENA */
4667 #define WM5100_DSP2_CORE_ENA                    0x0002  /* DSP2_CORE_ENA */
4668 #define WM5100_DSP2_CORE_ENA_MASK               0x0002  /* DSP2_CORE_ENA */
4669 #define WM5100_DSP2_CORE_ENA_SHIFT                   1  /* DSP2_CORE_ENA */
4670 #define WM5100_DSP2_CORE_ENA_WIDTH                   1  /* DSP2_CORE_ENA */
4671 #define WM5100_DSP2_START                       0x0001  /* DSP2_START */
4672 #define WM5100_DSP2_START_MASK                  0x0001  /* DSP2_START */
4673 #define WM5100_DSP2_START_SHIFT                      0  /* DSP2_START */
4674 #define WM5100_DSP2_START_WIDTH                      1  /* DSP2_START */
4675 
4676 /*
4677  * R3876 (0xF24) - DSP1 Control 30
4678  */
4679 #define WM5100_DSP1_RATE_MASK                   0xC000  /* DSP1_RATE - [15:14] */
4680 #define WM5100_DSP1_RATE_SHIFT                      14  /* DSP1_RATE - [15:14] */
4681 #define WM5100_DSP1_RATE_WIDTH                       2  /* DSP1_RATE - [15:14] */
4682 #define WM5100_DSP1_DBG_CLK_ENA                 0x0008  /* DSP1_DBG_CLK_ENA */
4683 #define WM5100_DSP1_DBG_CLK_ENA_MASK            0x0008  /* DSP1_DBG_CLK_ENA */
4684 #define WM5100_DSP1_DBG_CLK_ENA_SHIFT                3  /* DSP1_DBG_CLK_ENA */
4685 #define WM5100_DSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
4686 #define WM5100_DSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
4687 #define WM5100_DSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
4688 #define WM5100_DSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
4689 #define WM5100_DSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
4690 #define WM5100_DSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
4691 #define WM5100_DSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
4692 #define WM5100_DSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
4693 #define WM5100_DSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
4694 #define WM5100_DSP1_START                       0x0001  /* DSP1_START */
4695 #define WM5100_DSP1_START_MASK                  0x0001  /* DSP1_START */
4696 #define WM5100_DSP1_START_SHIFT                      0  /* DSP1_START */
4697 #define WM5100_DSP1_START_WIDTH                      1  /* DSP1_START */
4698 
4699 /*
4700  * R4388 (0x1124) - DSP3 Control 30
4701  */
4702 #define WM5100_DSP3_RATE_MASK                   0xC000  /* DSP3_RATE - [15:14] */
4703 #define WM5100_DSP3_RATE_SHIFT                      14  /* DSP3_RATE - [15:14] */
4704 #define WM5100_DSP3_RATE_WIDTH                       2  /* DSP3_RATE - [15:14] */
4705 #define WM5100_DSP3_DBG_CLK_ENA                 0x0008  /* DSP3_DBG_CLK_ENA */
4706 #define WM5100_DSP3_DBG_CLK_ENA_MASK            0x0008  /* DSP3_DBG_CLK_ENA */
4707 #define WM5100_DSP3_DBG_CLK_ENA_SHIFT                3  /* DSP3_DBG_CLK_ENA */
4708 #define WM5100_DSP3_DBG_CLK_ENA_WIDTH                1  /* DSP3_DBG_CLK_ENA */
4709 #define WM5100_DSP3_SYS_ENA                     0x0004  /* DSP3_SYS_ENA */
4710 #define WM5100_DSP3_SYS_ENA_MASK                0x0004  /* DSP3_SYS_ENA */
4711 #define WM5100_DSP3_SYS_ENA_SHIFT                    2  /* DSP3_SYS_ENA */
4712 #define WM5100_DSP3_SYS_ENA_WIDTH                    1  /* DSP3_SYS_ENA */
4713 #define WM5100_DSP3_CORE_ENA                    0x0002  /* DSP3_CORE_ENA */
4714 #define WM5100_DSP3_CORE_ENA_MASK               0x0002  /* DSP3_CORE_ENA */
4715 #define WM5100_DSP3_CORE_ENA_SHIFT                   1  /* DSP3_CORE_ENA */
4716 #define WM5100_DSP3_CORE_ENA_WIDTH                   1  /* DSP3_CORE_ENA */
4717 #define WM5100_DSP3_START                       0x0001  /* DSP3_START */
4718 #define WM5100_DSP3_START_MASK                  0x0001  /* DSP3_START */
4719 #define WM5100_DSP3_START_SHIFT                      0  /* DSP3_START */
4720 #define WM5100_DSP3_START_WIDTH                      1  /* DSP3_START */
4721 
4722 /*
4723  * R16384 (0x4000) - DSP1 DM 0
4724  */
4725 #define WM5100_DSP1_DM_START_1_MASK             0x00FF  /* DSP1_DM_START - [7:0] */
4726 #define WM5100_DSP1_DM_START_1_SHIFT                 0  /* DSP1_DM_START - [7:0] */
4727 #define WM5100_DSP1_DM_START_1_WIDTH                 8  /* DSP1_DM_START - [7:0] */
4728 
4729 /*
4730  * R16385 (0x4001) - DSP1 DM 1
4731  */
4732 #define WM5100_DSP1_DM_START_MASK               0xFFFF  /* DSP1_DM_START - [15:0] */
4733 #define WM5100_DSP1_DM_START_SHIFT                   0  /* DSP1_DM_START - [15:0] */
4734 #define WM5100_DSP1_DM_START_WIDTH                  16  /* DSP1_DM_START - [15:0] */
4735 
4736 /*
4737  * R16386 (0x4002) - DSP1 DM 2
4738  */
4739 #define WM5100_DSP1_DM_1_1_MASK                 0x00FF  /* DSP1_DM_1 - [7:0] */
4740 #define WM5100_DSP1_DM_1_1_SHIFT                     0  /* DSP1_DM_1 - [7:0] */
4741 #define WM5100_DSP1_DM_1_1_WIDTH                     8  /* DSP1_DM_1 - [7:0] */
4742 
4743 /*
4744  * R16387 (0x4003) - DSP1 DM 3
4745  */
4746 #define WM5100_DSP1_DM_1_MASK                   0xFFFF  /* DSP1_DM_1 - [15:0] */
4747 #define WM5100_DSP1_DM_1_SHIFT                       0  /* DSP1_DM_1 - [15:0] */
4748 #define WM5100_DSP1_DM_1_WIDTH                      16  /* DSP1_DM_1 - [15:0] */
4749 
4750 /*
4751  * R16892 (0x41FC) - DSP1 DM 508
4752  */
4753 #define WM5100_DSP1_DM_254_1_MASK               0x00FF  /* DSP1_DM_254 - [7:0] */
4754 #define WM5100_DSP1_DM_254_1_SHIFT                   0  /* DSP1_DM_254 - [7:0] */
4755 #define WM5100_DSP1_DM_254_1_WIDTH                   8  /* DSP1_DM_254 - [7:0] */
4756 
4757 /*
4758  * R16893 (0x41FD) - DSP1 DM 509
4759  */
4760 #define WM5100_DSP1_DM_254_MASK                 0xFFFF  /* DSP1_DM_254 - [15:0] */
4761 #define WM5100_DSP1_DM_254_SHIFT                     0  /* DSP1_DM_254 - [15:0] */
4762 #define WM5100_DSP1_DM_254_WIDTH                    16  /* DSP1_DM_254 - [15:0] */
4763 
4764 /*
4765  * R16894 (0x41FE) - DSP1 DM 510
4766  */
4767 #define WM5100_DSP1_DM_END_1_MASK               0x00FF  /* DSP1_DM_END - [7:0] */
4768 #define WM5100_DSP1_DM_END_1_SHIFT                   0  /* DSP1_DM_END - [7:0] */
4769 #define WM5100_DSP1_DM_END_1_WIDTH                   8  /* DSP1_DM_END - [7:0] */
4770 
4771 /*
4772  * R16895 (0x41FF) - DSP1 DM 511
4773  */
4774 #define WM5100_DSP1_DM_END_MASK                 0xFFFF  /* DSP1_DM_END - [15:0] */
4775 #define WM5100_DSP1_DM_END_SHIFT                     0  /* DSP1_DM_END - [15:0] */
4776 #define WM5100_DSP1_DM_END_WIDTH                    16  /* DSP1_DM_END - [15:0] */
4777 
4778 /*
4779  * R18432 (0x4800) - DSP1 PM 0
4780  */
4781 #define WM5100_DSP1_PM_START_2_MASK             0x00FF  /* DSP1_PM_START - [7:0] */
4782 #define WM5100_DSP1_PM_START_2_SHIFT                 0  /* DSP1_PM_START - [7:0] */
4783 #define WM5100_DSP1_PM_START_2_WIDTH                 8  /* DSP1_PM_START - [7:0] */
4784 
4785 /*
4786  * R18433 (0x4801) - DSP1 PM 1
4787  */
4788 #define WM5100_DSP1_PM_START_1_MASK             0xFFFF  /* DSP1_PM_START - [15:0] */
4789 #define WM5100_DSP1_PM_START_1_SHIFT                 0  /* DSP1_PM_START - [15:0] */
4790 #define WM5100_DSP1_PM_START_1_WIDTH                16  /* DSP1_PM_START - [15:0] */
4791 
4792 /*
4793  * R18434 (0x4802) - DSP1 PM 2
4794  */
4795 #define WM5100_DSP1_PM_START_MASK               0xFFFF  /* DSP1_PM_START - [15:0] */
4796 #define WM5100_DSP1_PM_START_SHIFT                   0  /* DSP1_PM_START - [15:0] */
4797 #define WM5100_DSP1_PM_START_WIDTH                  16  /* DSP1_PM_START - [15:0] */
4798 
4799 /*
4800  * R18435 (0x4803) - DSP1 PM 3
4801  */
4802 #define WM5100_DSP1_PM_1_2_MASK                 0x00FF  /* DSP1_PM_1 - [7:0] */
4803 #define WM5100_DSP1_PM_1_2_SHIFT                     0  /* DSP1_PM_1 - [7:0] */
4804 #define WM5100_DSP1_PM_1_2_WIDTH                     8  /* DSP1_PM_1 - [7:0] */
4805 
4806 /*
4807  * R18436 (0x4804) - DSP1 PM 4
4808  */
4809 #define WM5100_DSP1_PM_1_1_MASK                 0xFFFF  /* DSP1_PM_1 - [15:0] */
4810 #define WM5100_DSP1_PM_1_1_SHIFT                     0  /* DSP1_PM_1 - [15:0] */
4811 #define WM5100_DSP1_PM_1_1_WIDTH                    16  /* DSP1_PM_1 - [15:0] */
4812 
4813 /*
4814  * R18437 (0x4805) - DSP1 PM 5
4815  */
4816 #define WM5100_DSP1_PM_1_MASK                   0xFFFF  /* DSP1_PM_1 - [15:0] */
4817 #define WM5100_DSP1_PM_1_SHIFT                       0  /* DSP1_PM_1 - [15:0] */
4818 #define WM5100_DSP1_PM_1_WIDTH                      16  /* DSP1_PM_1 - [15:0] */
4819 
4820 /*
4821  * R19962 (0x4DFA) - DSP1 PM 1530
4822  */
4823 #define WM5100_DSP1_PM_510_2_MASK               0x00FF  /* DSP1_PM_510 - [7:0] */
4824 #define WM5100_DSP1_PM_510_2_SHIFT                   0  /* DSP1_PM_510 - [7:0] */
4825 #define WM5100_DSP1_PM_510_2_WIDTH                   8  /* DSP1_PM_510 - [7:0] */
4826 
4827 /*
4828  * R19963 (0x4DFB) - DSP1 PM 1531
4829  */
4830 #define WM5100_DSP1_PM_510_1_MASK               0xFFFF  /* DSP1_PM_510 - [15:0] */
4831 #define WM5100_DSP1_PM_510_1_SHIFT                   0  /* DSP1_PM_510 - [15:0] */
4832 #define WM5100_DSP1_PM_510_1_WIDTH                  16  /* DSP1_PM_510 - [15:0] */
4833 
4834 /*
4835  * R19964 (0x4DFC) - DSP1 PM 1532
4836  */
4837 #define WM5100_DSP1_PM_510_MASK                 0xFFFF  /* DSP1_PM_510 - [15:0] */
4838 #define WM5100_DSP1_PM_510_SHIFT                     0  /* DSP1_PM_510 - [15:0] */
4839 #define WM5100_DSP1_PM_510_WIDTH                    16  /* DSP1_PM_510 - [15:0] */
4840 
4841 /*
4842  * R19965 (0x4DFD) - DSP1 PM 1533
4843  */
4844 #define WM5100_DSP1_PM_END_2_MASK               0x00FF  /* DSP1_PM_END - [7:0] */
4845 #define WM5100_DSP1_PM_END_2_SHIFT                   0  /* DSP1_PM_END - [7:0] */
4846 #define WM5100_DSP1_PM_END_2_WIDTH                   8  /* DSP1_PM_END - [7:0] */
4847 
4848 /*
4849  * R19966 (0x4DFE) - DSP1 PM 1534
4850  */
4851 #define WM5100_DSP1_PM_END_1_MASK               0xFFFF  /* DSP1_PM_END - [15:0] */
4852 #define WM5100_DSP1_PM_END_1_SHIFT                   0  /* DSP1_PM_END - [15:0] */
4853 #define WM5100_DSP1_PM_END_1_WIDTH                  16  /* DSP1_PM_END - [15:0] */
4854 
4855 /*
4856  * R19967 (0x4DFF) - DSP1 PM 1535
4857  */
4858 #define WM5100_DSP1_PM_END_MASK                 0xFFFF  /* DSP1_PM_END - [15:0] */
4859 #define WM5100_DSP1_PM_END_SHIFT                     0  /* DSP1_PM_END - [15:0] */
4860 #define WM5100_DSP1_PM_END_WIDTH                    16  /* DSP1_PM_END - [15:0] */
4861 
4862 /*
4863  * R20480 (0x5000) - DSP1 ZM 0
4864  */
4865 #define WM5100_DSP1_ZM_START_1_MASK             0x00FF  /* DSP1_ZM_START - [7:0] */
4866 #define WM5100_DSP1_ZM_START_1_SHIFT                 0  /* DSP1_ZM_START - [7:0] */
4867 #define WM5100_DSP1_ZM_START_1_WIDTH                 8  /* DSP1_ZM_START - [7:0] */
4868 
4869 /*
4870  * R20481 (0x5001) - DSP1 ZM 1
4871  */
4872 #define WM5100_DSP1_ZM_START_MASK               0xFFFF  /* DSP1_ZM_START - [15:0] */
4873 #define WM5100_DSP1_ZM_START_SHIFT                   0  /* DSP1_ZM_START - [15:0] */
4874 #define WM5100_DSP1_ZM_START_WIDTH                  16  /* DSP1_ZM_START - [15:0] */
4875 
4876 /*
4877  * R20482 (0x5002) - DSP1 ZM 2
4878  */
4879 #define WM5100_DSP1_ZM_1_1_MASK                 0x00FF  /* DSP1_ZM_1 - [7:0] */
4880 #define WM5100_DSP1_ZM_1_1_SHIFT                     0  /* DSP1_ZM_1 - [7:0] */
4881 #define WM5100_DSP1_ZM_1_1_WIDTH                     8  /* DSP1_ZM_1 - [7:0] */
4882 
4883 /*
4884  * R20483 (0x5003) - DSP1 ZM 3
4885  */
4886 #define WM5100_DSP1_ZM_1_MASK                   0xFFFF  /* DSP1_ZM_1 - [15:0] */
4887 #define WM5100_DSP1_ZM_1_SHIFT                       0  /* DSP1_ZM_1 - [15:0] */
4888 #define WM5100_DSP1_ZM_1_WIDTH                      16  /* DSP1_ZM_1 - [15:0] */
4889 
4890 /*
4891  * R22524 (0x57FC) - DSP1 ZM 2044
4892  */
4893 #define WM5100_DSP1_ZM_1022_1_MASK              0x00FF  /* DSP1_ZM_1022 - [7:0] */
4894 #define WM5100_DSP1_ZM_1022_1_SHIFT                  0  /* DSP1_ZM_1022 - [7:0] */
4895 #define WM5100_DSP1_ZM_1022_1_WIDTH                  8  /* DSP1_ZM_1022 - [7:0] */
4896 
4897 /*
4898  * R22525 (0x57FD) - DSP1 ZM 2045
4899  */
4900 #define WM5100_DSP1_ZM_1022_MASK                0xFFFF  /* DSP1_ZM_1022 - [15:0] */
4901 #define WM5100_DSP1_ZM_1022_SHIFT                    0  /* DSP1_ZM_1022 - [15:0] */
4902 #define WM5100_DSP1_ZM_1022_WIDTH                   16  /* DSP1_ZM_1022 - [15:0] */
4903 
4904 /*
4905  * R22526 (0x57FE) - DSP1 ZM 2046
4906  */
4907 #define WM5100_DSP1_ZM_END_1_MASK               0x00FF  /* DSP1_ZM_END - [7:0] */
4908 #define WM5100_DSP1_ZM_END_1_SHIFT                   0  /* DSP1_ZM_END - [7:0] */
4909 #define WM5100_DSP1_ZM_END_1_WIDTH                   8  /* DSP1_ZM_END - [7:0] */
4910 
4911 /*
4912  * R22527 (0x57FF) - DSP1 ZM 2047
4913  */
4914 #define WM5100_DSP1_ZM_END_MASK                 0xFFFF  /* DSP1_ZM_END - [15:0] */
4915 #define WM5100_DSP1_ZM_END_SHIFT                     0  /* DSP1_ZM_END - [15:0] */
4916 #define WM5100_DSP1_ZM_END_WIDTH                    16  /* DSP1_ZM_END - [15:0] */
4917 
4918 /*
4919  * R24576 (0x6000) - DSP2 DM 0
4920  */
4921 #define WM5100_DSP2_DM_START_1_MASK             0x00FF  /* DSP2_DM_START - [7:0] */
4922 #define WM5100_DSP2_DM_START_1_SHIFT                 0  /* DSP2_DM_START - [7:0] */
4923 #define WM5100_DSP2_DM_START_1_WIDTH                 8  /* DSP2_DM_START - [7:0] */
4924 
4925 /*
4926  * R24577 (0x6001) - DSP2 DM 1
4927  */
4928 #define WM5100_DSP2_DM_START_MASK               0xFFFF  /* DSP2_DM_START - [15:0] */
4929 #define WM5100_DSP2_DM_START_SHIFT                   0  /* DSP2_DM_START - [15:0] */
4930 #define WM5100_DSP2_DM_START_WIDTH                  16  /* DSP2_DM_START - [15:0] */
4931 
4932 /*
4933  * R24578 (0x6002) - DSP2 DM 2
4934  */
4935 #define WM5100_DSP2_DM_1_1_MASK                 0x00FF  /* DSP2_DM_1 - [7:0] */
4936 #define WM5100_DSP2_DM_1_1_SHIFT                     0  /* DSP2_DM_1 - [7:0] */
4937 #define WM5100_DSP2_DM_1_1_WIDTH                     8  /* DSP2_DM_1 - [7:0] */
4938 
4939 /*
4940  * R24579 (0x6003) - DSP2 DM 3
4941  */
4942 #define WM5100_DSP2_DM_1_MASK                   0xFFFF  /* DSP2_DM_1 - [15:0] */
4943 #define WM5100_DSP2_DM_1_SHIFT                       0  /* DSP2_DM_1 - [15:0] */
4944 #define WM5100_DSP2_DM_1_WIDTH                      16  /* DSP2_DM_1 - [15:0] */
4945 
4946 /*
4947  * R25084 (0x61FC) - DSP2 DM 508
4948  */
4949 #define WM5100_DSP2_DM_254_1_MASK               0x00FF  /* DSP2_DM_254 - [7:0] */
4950 #define WM5100_DSP2_DM_254_1_SHIFT                   0  /* DSP2_DM_254 - [7:0] */
4951 #define WM5100_DSP2_DM_254_1_WIDTH                   8  /* DSP2_DM_254 - [7:0] */
4952 
4953 /*
4954  * R25085 (0x61FD) - DSP2 DM 509
4955  */
4956 #define WM5100_DSP2_DM_254_MASK                 0xFFFF  /* DSP2_DM_254 - [15:0] */
4957 #define WM5100_DSP2_DM_254_SHIFT                     0  /* DSP2_DM_254 - [15:0] */
4958 #define WM5100_DSP2_DM_254_WIDTH                    16  /* DSP2_DM_254 - [15:0] */
4959 
4960 /*
4961  * R25086 (0x61FE) - DSP2 DM 510
4962  */
4963 #define WM5100_DSP2_DM_END_1_MASK               0x00FF  /* DSP2_DM_END - [7:0] */
4964 #define WM5100_DSP2_DM_END_1_SHIFT                   0  /* DSP2_DM_END - [7:0] */
4965 #define WM5100_DSP2_DM_END_1_WIDTH                   8  /* DSP2_DM_END - [7:0] */
4966 
4967 /*
4968  * R25087 (0x61FF) - DSP2 DM 511
4969  */
4970 #define WM5100_DSP2_DM_END_MASK                 0xFFFF  /* DSP2_DM_END - [15:0] */
4971 #define WM5100_DSP2_DM_END_SHIFT                     0  /* DSP2_DM_END - [15:0] */
4972 #define WM5100_DSP2_DM_END_WIDTH                    16  /* DSP2_DM_END - [15:0] */
4973 
4974 /*
4975  * R26624 (0x6800) - DSP2 PM 0
4976  */
4977 #define WM5100_DSP2_PM_START_2_MASK             0x00FF  /* DSP2_PM_START - [7:0] */
4978 #define WM5100_DSP2_PM_START_2_SHIFT                 0  /* DSP2_PM_START - [7:0] */
4979 #define WM5100_DSP2_PM_START_2_WIDTH                 8  /* DSP2_PM_START - [7:0] */
4980 
4981 /*
4982  * R26625 (0x6801) - DSP2 PM 1
4983  */
4984 #define WM5100_DSP2_PM_START_1_MASK             0xFFFF  /* DSP2_PM_START - [15:0] */
4985 #define WM5100_DSP2_PM_START_1_SHIFT                 0  /* DSP2_PM_START - [15:0] */
4986 #define WM5100_DSP2_PM_START_1_WIDTH                16  /* DSP2_PM_START - [15:0] */
4987 
4988 /*
4989  * R26626 (0x6802) - DSP2 PM 2
4990  */
4991 #define WM5100_DSP2_PM_START_MASK               0xFFFF  /* DSP2_PM_START - [15:0] */
4992 #define WM5100_DSP2_PM_START_SHIFT                   0  /* DSP2_PM_START - [15:0] */
4993 #define WM5100_DSP2_PM_START_WIDTH                  16  /* DSP2_PM_START - [15:0] */
4994 
4995 /*
4996  * R26627 (0x6803) - DSP2 PM 3
4997  */
4998 #define WM5100_DSP2_PM_1_2_MASK                 0x00FF  /* DSP2_PM_1 - [7:0] */
4999 #define WM5100_DSP2_PM_1_2_SHIFT                     0  /* DSP2_PM_1 - [7:0] */
5000 #define WM5100_DSP2_PM_1_2_WIDTH                     8  /* DSP2_PM_1 - [7:0] */
5001 
5002 /*
5003  * R26628 (0x6804) - DSP2 PM 4
5004  */
5005 #define WM5100_DSP2_PM_1_1_MASK                 0xFFFF  /* DSP2_PM_1 - [15:0] */
5006 #define WM5100_DSP2_PM_1_1_SHIFT                     0  /* DSP2_PM_1 - [15:0] */
5007 #define WM5100_DSP2_PM_1_1_WIDTH                    16  /* DSP2_PM_1 - [15:0] */
5008 
5009 /*
5010  * R26629 (0x6805) - DSP2 PM 5
5011  */
5012 #define WM5100_DSP2_PM_1_MASK                   0xFFFF  /* DSP2_PM_1 - [15:0] */
5013 #define WM5100_DSP2_PM_1_SHIFT                       0  /* DSP2_PM_1 - [15:0] */
5014 #define WM5100_DSP2_PM_1_WIDTH                      16  /* DSP2_PM_1 - [15:0] */
5015 
5016 /*
5017  * R28154 (0x6DFA) - DSP2 PM 1530
5018  */
5019 #define WM5100_DSP2_PM_510_2_MASK               0x00FF  /* DSP2_PM_510 - [7:0] */
5020 #define WM5100_DSP2_PM_510_2_SHIFT                   0  /* DSP2_PM_510 - [7:0] */
5021 #define WM5100_DSP2_PM_510_2_WIDTH                   8  /* DSP2_PM_510 - [7:0] */
5022 
5023 /*
5024  * R28155 (0x6DFB) - DSP2 PM 1531
5025  */
5026 #define WM5100_DSP2_PM_510_1_MASK               0xFFFF  /* DSP2_PM_510 - [15:0] */
5027 #define WM5100_DSP2_PM_510_1_SHIFT                   0  /* DSP2_PM_510 - [15:0] */
5028 #define WM5100_DSP2_PM_510_1_WIDTH                  16  /* DSP2_PM_510 - [15:0] */
5029 
5030 /*
5031  * R28156 (0x6DFC) - DSP2 PM 1532
5032  */
5033 #define WM5100_DSP2_PM_510_MASK                 0xFFFF  /* DSP2_PM_510 - [15:0] */
5034 #define WM5100_DSP2_PM_510_SHIFT                     0  /* DSP2_PM_510 - [15:0] */
5035 #define WM5100_DSP2_PM_510_WIDTH                    16  /* DSP2_PM_510 - [15:0] */
5036 
5037 /*
5038  * R28157 (0x6DFD) - DSP2 PM 1533
5039  */
5040 #define WM5100_DSP2_PM_END_2_MASK               0x00FF  /* DSP2_PM_END - [7:0] */
5041 #define WM5100_DSP2_PM_END_2_SHIFT                   0  /* DSP2_PM_END - [7:0] */
5042 #define WM5100_DSP2_PM_END_2_WIDTH                   8  /* DSP2_PM_END - [7:0] */
5043 
5044 /*
5045  * R28158 (0x6DFE) - DSP2 PM 1534
5046  */
5047 #define WM5100_DSP2_PM_END_1_MASK               0xFFFF  /* DSP2_PM_END - [15:0] */
5048 #define WM5100_DSP2_PM_END_1_SHIFT                   0  /* DSP2_PM_END - [15:0] */
5049 #define WM5100_DSP2_PM_END_1_WIDTH                  16  /* DSP2_PM_END - [15:0] */
5050 
5051 /*
5052  * R28159 (0x6DFF) - DSP2 PM 1535
5053  */
5054 #define WM5100_DSP2_PM_END_MASK                 0xFFFF  /* DSP2_PM_END - [15:0] */
5055 #define WM5100_DSP2_PM_END_SHIFT                     0  /* DSP2_PM_END - [15:0] */
5056 #define WM5100_DSP2_PM_END_WIDTH                    16  /* DSP2_PM_END - [15:0] */
5057 
5058 /*
5059  * R28672 (0x7000) - DSP2 ZM 0
5060  */
5061 #define WM5100_DSP2_ZM_START_1_MASK             0x00FF  /* DSP2_ZM_START - [7:0] */
5062 #define WM5100_DSP2_ZM_START_1_SHIFT                 0  /* DSP2_ZM_START - [7:0] */
5063 #define WM5100_DSP2_ZM_START_1_WIDTH                 8  /* DSP2_ZM_START - [7:0] */
5064 
5065 /*
5066  * R28673 (0x7001) - DSP2 ZM 1
5067  */
5068 #define WM5100_DSP2_ZM_START_MASK               0xFFFF  /* DSP2_ZM_START - [15:0] */
5069 #define WM5100_DSP2_ZM_START_SHIFT                   0  /* DSP2_ZM_START - [15:0] */
5070 #define WM5100_DSP2_ZM_START_WIDTH                  16  /* DSP2_ZM_START - [15:0] */
5071 
5072 /*
5073  * R28674 (0x7002) - DSP2 ZM 2
5074  */
5075 #define WM5100_DSP2_ZM_1_1_MASK                 0x00FF  /* DSP2_ZM_1 - [7:0] */
5076 #define WM5100_DSP2_ZM_1_1_SHIFT                     0  /* DSP2_ZM_1 - [7:0] */
5077 #define WM5100_DSP2_ZM_1_1_WIDTH                     8  /* DSP2_ZM_1 - [7:0] */
5078 
5079 /*
5080  * R28675 (0x7003) - DSP2 ZM 3
5081  */
5082 #define WM5100_DSP2_ZM_1_MASK                   0xFFFF  /* DSP2_ZM_1 - [15:0] */
5083 #define WM5100_DSP2_ZM_1_SHIFT                       0  /* DSP2_ZM_1 - [15:0] */
5084 #define WM5100_DSP2_ZM_1_WIDTH                      16  /* DSP2_ZM_1 - [15:0] */
5085 
5086 /*
5087  * R30716 (0x77FC) - DSP2 ZM 2044
5088  */
5089 #define WM5100_DSP2_ZM_1022_1_MASK              0x00FF  /* DSP2_ZM_1022 - [7:0] */
5090 #define WM5100_DSP2_ZM_1022_1_SHIFT                  0  /* DSP2_ZM_1022 - [7:0] */
5091 #define WM5100_DSP2_ZM_1022_1_WIDTH                  8  /* DSP2_ZM_1022 - [7:0] */
5092 
5093 /*
5094  * R30717 (0x77FD) - DSP2 ZM 2045
5095  */
5096 #define WM5100_DSP2_ZM_1022_MASK                0xFFFF  /* DSP2_ZM_1022 - [15:0] */
5097 #define WM5100_DSP2_ZM_1022_SHIFT                    0  /* DSP2_ZM_1022 - [15:0] */
5098 #define WM5100_DSP2_ZM_1022_WIDTH                   16  /* DSP2_ZM_1022 - [15:0] */
5099 
5100 /*
5101  * R30718 (0x77FE) - DSP2 ZM 2046
5102  */
5103 #define WM5100_DSP2_ZM_END_1_MASK               0x00FF  /* DSP2_ZM_END - [7:0] */
5104 #define WM5100_DSP2_ZM_END_1_SHIFT                   0  /* DSP2_ZM_END - [7:0] */
5105 #define WM5100_DSP2_ZM_END_1_WIDTH                   8  /* DSP2_ZM_END - [7:0] */
5106 
5107 /*
5108  * R30719 (0x77FF) - DSP2 ZM 2047
5109  */
5110 #define WM5100_DSP2_ZM_END_MASK                 0xFFFF  /* DSP2_ZM_END - [15:0] */
5111 #define WM5100_DSP2_ZM_END_SHIFT                     0  /* DSP2_ZM_END - [15:0] */
5112 #define WM5100_DSP2_ZM_END_WIDTH                    16  /* DSP2_ZM_END - [15:0] */
5113 
5114 /*
5115  * R32768 (0x8000) - DSP3 DM 0
5116  */
5117 #define WM5100_DSP3_DM_START_1_MASK             0x00FF  /* DSP3_DM_START - [7:0] */
5118 #define WM5100_DSP3_DM_START_1_SHIFT                 0  /* DSP3_DM_START - [7:0] */
5119 #define WM5100_DSP3_DM_START_1_WIDTH                 8  /* DSP3_DM_START - [7:0] */
5120 
5121 /*
5122  * R32769 (0x8001) - DSP3 DM 1
5123  */
5124 #define WM5100_DSP3_DM_START_MASK               0xFFFF  /* DSP3_DM_START - [15:0] */
5125 #define WM5100_DSP3_DM_START_SHIFT                   0  /* DSP3_DM_START - [15:0] */
5126 #define WM5100_DSP3_DM_START_WIDTH                  16  /* DSP3_DM_START - [15:0] */
5127 
5128 /*
5129  * R32770 (0x8002) - DSP3 DM 2
5130  */
5131 #define WM5100_DSP3_DM_1_1_MASK                 0x00FF  /* DSP3_DM_1 - [7:0] */
5132 #define WM5100_DSP3_DM_1_1_SHIFT                     0  /* DSP3_DM_1 - [7:0] */
5133 #define WM5100_DSP3_DM_1_1_WIDTH                     8  /* DSP3_DM_1 - [7:0] */
5134 
5135 /*
5136  * R32771 (0x8003) - DSP3 DM 3
5137  */
5138 #define WM5100_DSP3_DM_1_MASK                   0xFFFF  /* DSP3_DM_1 - [15:0] */
5139 #define WM5100_DSP3_DM_1_SHIFT                       0  /* DSP3_DM_1 - [15:0] */
5140 #define WM5100_DSP3_DM_1_WIDTH                      16  /* DSP3_DM_1 - [15:0] */
5141 
5142 /*
5143  * R33276 (0x81FC) - DSP3 DM 508
5144  */
5145 #define WM5100_DSP3_DM_254_1_MASK               0x00FF  /* DSP3_DM_254 - [7:0] */
5146 #define WM5100_DSP3_DM_254_1_SHIFT                   0  /* DSP3_DM_254 - [7:0] */
5147 #define WM5100_DSP3_DM_254_1_WIDTH                   8  /* DSP3_DM_254 - [7:0] */
5148 
5149 /*
5150  * R33277 (0x81FD) - DSP3 DM 509
5151  */
5152 #define WM5100_DSP3_DM_254_MASK                 0xFFFF  /* DSP3_DM_254 - [15:0] */
5153 #define WM5100_DSP3_DM_254_SHIFT                     0  /* DSP3_DM_254 - [15:0] */
5154 #define WM5100_DSP3_DM_254_WIDTH                    16  /* DSP3_DM_254 - [15:0] */
5155 
5156 /*
5157  * R33278 (0x81FE) - DSP3 DM 510
5158  */
5159 #define WM5100_DSP3_DM_END_1_MASK               0x00FF  /* DSP3_DM_END - [7:0] */
5160 #define WM5100_DSP3_DM_END_1_SHIFT                   0  /* DSP3_DM_END - [7:0] */
5161 #define WM5100_DSP3_DM_END_1_WIDTH                   8  /* DSP3_DM_END - [7:0] */
5162 
5163 /*
5164  * R33279 (0x81FF) - DSP3 DM 511
5165  */
5166 #define WM5100_DSP3_DM_END_MASK                 0xFFFF  /* DSP3_DM_END - [15:0] */
5167 #define WM5100_DSP3_DM_END_SHIFT                     0  /* DSP3_DM_END - [15:0] */
5168 #define WM5100_DSP3_DM_END_WIDTH                    16  /* DSP3_DM_END - [15:0] */
5169 
5170 /*
5171  * R34816 (0x8800) - DSP3 PM 0
5172  */
5173 #define WM5100_DSP3_PM_START_2_MASK             0x00FF  /* DSP3_PM_START - [7:0] */
5174 #define WM5100_DSP3_PM_START_2_SHIFT                 0  /* DSP3_PM_START - [7:0] */
5175 #define WM5100_DSP3_PM_START_2_WIDTH                 8  /* DSP3_PM_START - [7:0] */
5176 
5177 /*
5178  * R34817 (0x8801) - DSP3 PM 1
5179  */
5180 #define WM5100_DSP3_PM_START_1_MASK             0xFFFF  /* DSP3_PM_START - [15:0] */
5181 #define WM5100_DSP3_PM_START_1_SHIFT                 0  /* DSP3_PM_START - [15:0] */
5182 #define WM5100_DSP3_PM_START_1_WIDTH                16  /* DSP3_PM_START - [15:0] */
5183 
5184 /*
5185  * R34818 (0x8802) - DSP3 PM 2
5186  */
5187 #define WM5100_DSP3_PM_START_MASK               0xFFFF  /* DSP3_PM_START - [15:0] */
5188 #define WM5100_DSP3_PM_START_SHIFT                   0  /* DSP3_PM_START - [15:0] */
5189 #define WM5100_DSP3_PM_START_WIDTH                  16  /* DSP3_PM_START - [15:0] */
5190 
5191 /*
5192  * R34819 (0x8803) - DSP3 PM 3
5193  */
5194 #define WM5100_DSP3_PM_1_2_MASK                 0x00FF  /* DSP3_PM_1 - [7:0] */
5195 #define WM5100_DSP3_PM_1_2_SHIFT                     0  /* DSP3_PM_1 - [7:0] */
5196 #define WM5100_DSP3_PM_1_2_WIDTH                     8  /* DSP3_PM_1 - [7:0] */
5197 
5198 /*
5199  * R34820 (0x8804) - DSP3 PM 4
5200  */
5201 #define WM5100_DSP3_PM_1_1_MASK                 0xFFFF  /* DSP3_PM_1 - [15:0] */
5202 #define WM5100_DSP3_PM_1_1_SHIFT                     0  /* DSP3_PM_1 - [15:0] */
5203 #define WM5100_DSP3_PM_1_1_WIDTH                    16  /* DSP3_PM_1 - [15:0] */
5204 
5205 /*
5206  * R34821 (0x8805) - DSP3 PM 5
5207  */
5208 #define WM5100_DSP3_PM_1_MASK                   0xFFFF  /* DSP3_PM_1 - [15:0] */
5209 #define WM5100_DSP3_PM_1_SHIFT                       0  /* DSP3_PM_1 - [15:0] */
5210 #define WM5100_DSP3_PM_1_WIDTH                      16  /* DSP3_PM_1 - [15:0] */
5211 
5212 /*
5213  * R36346 (0x8DFA) - DSP3 PM 1530
5214  */
5215 #define WM5100_DSP3_PM_510_2_MASK               0x00FF  /* DSP3_PM_510 - [7:0] */
5216 #define WM5100_DSP3_PM_510_2_SHIFT                   0  /* DSP3_PM_510 - [7:0] */
5217 #define WM5100_DSP3_PM_510_2_WIDTH                   8  /* DSP3_PM_510 - [7:0] */
5218 
5219 /*
5220  * R36347 (0x8DFB) - DSP3 PM 1531
5221  */
5222 #define WM5100_DSP3_PM_510_1_MASK               0xFFFF  /* DSP3_PM_510 - [15:0] */
5223 #define WM5100_DSP3_PM_510_1_SHIFT                   0  /* DSP3_PM_510 - [15:0] */
5224 #define WM5100_DSP3_PM_510_1_WIDTH                  16  /* DSP3_PM_510 - [15:0] */
5225 
5226 /*
5227  * R36348 (0x8DFC) - DSP3 PM 1532
5228  */
5229 #define WM5100_DSP3_PM_510_MASK                 0xFFFF  /* DSP3_PM_510 - [15:0] */
5230 #define WM5100_DSP3_PM_510_SHIFT                     0  /* DSP3_PM_510 - [15:0] */
5231 #define WM5100_DSP3_PM_510_WIDTH                    16  /* DSP3_PM_510 - [15:0] */
5232 
5233 /*
5234  * R36349 (0x8DFD) - DSP3 PM 1533
5235  */
5236 #define WM5100_DSP3_PM_END_2_MASK               0x00FF  /* DSP3_PM_END - [7:0] */
5237 #define WM5100_DSP3_PM_END_2_SHIFT                   0  /* DSP3_PM_END - [7:0] */
5238 #define WM5100_DSP3_PM_END_2_WIDTH                   8  /* DSP3_PM_END - [7:0] */
5239 
5240 /*
5241  * R36350 (0x8DFE) - DSP3 PM 1534
5242  */
5243 #define WM5100_DSP3_PM_END_1_MASK               0xFFFF  /* DSP3_PM_END - [15:0] */
5244 #define WM5100_DSP3_PM_END_1_SHIFT                   0  /* DSP3_PM_END - [15:0] */
5245 #define WM5100_DSP3_PM_END_1_WIDTH                  16  /* DSP3_PM_END - [15:0] */
5246 
5247 /*
5248  * R36351 (0x8DFF) - DSP3 PM 1535
5249  */
5250 #define WM5100_DSP3_PM_END_MASK                 0xFFFF  /* DSP3_PM_END - [15:0] */
5251 #define WM5100_DSP3_PM_END_SHIFT                     0  /* DSP3_PM_END - [15:0] */
5252 #define WM5100_DSP3_PM_END_WIDTH                    16  /* DSP3_PM_END - [15:0] */
5253 
5254 /*
5255  * R36864 (0x9000) - DSP3 ZM 0
5256  */
5257 #define WM5100_DSP3_ZM_START_1_MASK             0x00FF  /* DSP3_ZM_START - [7:0] */
5258 #define WM5100_DSP3_ZM_START_1_SHIFT                 0  /* DSP3_ZM_START - [7:0] */
5259 #define WM5100_DSP3_ZM_START_1_WIDTH                 8  /* DSP3_ZM_START - [7:0] */
5260 
5261 /*
5262  * R36865 (0x9001) - DSP3 ZM 1
5263  */
5264 #define WM5100_DSP3_ZM_START_MASK               0xFFFF  /* DSP3_ZM_START - [15:0] */
5265 #define WM5100_DSP3_ZM_START_SHIFT                   0  /* DSP3_ZM_START - [15:0] */
5266 #define WM5100_DSP3_ZM_START_WIDTH                  16  /* DSP3_ZM_START - [15:0] */
5267 
5268 /*
5269  * R36866 (0x9002) - DSP3 ZM 2
5270  */
5271 #define WM5100_DSP3_ZM_1_1_MASK                 0x00FF  /* DSP3_ZM_1 - [7:0] */
5272 #define WM5100_DSP3_ZM_1_1_SHIFT                     0  /* DSP3_ZM_1 - [7:0] */
5273 #define WM5100_DSP3_ZM_1_1_WIDTH                     8  /* DSP3_ZM_1 - [7:0] */
5274 
5275 /*
5276  * R36867 (0x9003) - DSP3 ZM 3
5277  */
5278 #define WM5100_DSP3_ZM_1_MASK                   0xFFFF  /* DSP3_ZM_1 - [15:0] */
5279 #define WM5100_DSP3_ZM_1_SHIFT                       0  /* DSP3_ZM_1 - [15:0] */
5280 #define WM5100_DSP3_ZM_1_WIDTH                      16  /* DSP3_ZM_1 - [15:0] */
5281 
5282 /*
5283  * R38908 (0x97FC) - DSP3 ZM 2044
5284  */
5285 #define WM5100_DSP3_ZM_1022_1_MASK              0x00FF  /* DSP3_ZM_1022 - [7:0] */
5286 #define WM5100_DSP3_ZM_1022_1_SHIFT                  0  /* DSP3_ZM_1022 - [7:0] */
5287 #define WM5100_DSP3_ZM_1022_1_WIDTH                  8  /* DSP3_ZM_1022 - [7:0] */
5288 
5289 /*
5290  * R38909 (0x97FD) - DSP3 ZM 2045
5291  */
5292 #define WM5100_DSP3_ZM_1022_MASK                0xFFFF  /* DSP3_ZM_1022 - [15:0] */
5293 #define WM5100_DSP3_ZM_1022_SHIFT                    0  /* DSP3_ZM_1022 - [15:0] */
5294 #define WM5100_DSP3_ZM_1022_WIDTH                   16  /* DSP3_ZM_1022 - [15:0] */
5295 
5296 /*
5297  * R38910 (0x97FE) - DSP3 ZM 2046
5298  */
5299 #define WM5100_DSP3_ZM_END_1_MASK               0x00FF  /* DSP3_ZM_END - [7:0] */
5300 #define WM5100_DSP3_ZM_END_1_SHIFT                   0  /* DSP3_ZM_END - [7:0] */
5301 #define WM5100_DSP3_ZM_END_1_WIDTH                   8  /* DSP3_ZM_END - [7:0] */
5302 
5303 /*
5304  * R38911 (0x97FF) - DSP3 ZM 2047
5305  */
5306 #define WM5100_DSP3_ZM_END_MASK                 0xFFFF  /* DSP3_ZM_END - [15:0] */
5307 #define WM5100_DSP3_ZM_END_SHIFT                     0  /* DSP3_ZM_END - [15:0] */
5308 #define WM5100_DSP3_ZM_END_WIDTH                    16  /* DSP3_ZM_END - [15:0] */
5309 
5310 bool wm5100_readable_register(struct device *dev, unsigned int reg);
5311 bool wm5100_volatile_register(struct device *dev, unsigned int reg);
5312 
5313 extern struct reg_default