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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm8400.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * wm8400.c  --  WM8400 ALSA Soc Audio driver
  3  *
  4  * Copyright 2008-11 Wolfson Microelectronics PLC.
  5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  6  *
  7  *  This program is free software; you can redistribute  it and/or modify it
  8  *  under  the terms of  the GNU General  Public License as published by the
  9  *  Free Software Foundation;  either version 2 of the  License, or (at your
 10  *  option) any later version.
 11  *
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/pm.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/regulator/consumer.h>
 23 #include <linux/mfd/wm8400-audio.h>
 24 #include <linux/mfd/wm8400-private.h>
 25 #include <linux/mfd/core.h>
 26 #include <sound/core.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/initval.h>
 31 #include <sound/tlv.h>
 32 
 33 #include "wm8400.h"
 34 
 35 static struct regulator_bulk_data power[] = {
 36         {
 37                 .supply = "I2S1VDD",
 38         },
 39         {
 40                 .supply = "I2S2VDD",
 41         },
 42         {
 43                 .supply = "DCVDD",
 44         },
 45         {
 46                 .supply = "AVDD",
 47         },
 48         {
 49                 .supply = "FLLVDD",
 50         },
 51         {
 52                 .supply = "HPVDD",
 53         },
 54         {
 55                 .supply = "SPKVDD",
 56         },
 57 };
 58 
 59 /* codec private data */
 60 struct wm8400_priv {
 61         struct snd_soc_codec *codec;
 62         struct wm8400 *wm8400;
 63         u16 fake_register;
 64         unsigned int sysclk;
 65         unsigned int pcmclk;
 66         struct work_struct work;
 67         int fll_in, fll_out;
 68 };
 69 
 70 static void wm8400_codec_reset(struct snd_soc_codec *codec)
 71 {
 72         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
 73 
 74         wm8400_reset_codec_reg_cache(wm8400->wm8400);
 75 }
 76 
 77 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
 78 
 79 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
 80 
 81 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
 82 
 83 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
 84 
 85 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
 86 
 87 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
 88 
 89 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
 90 
 91 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
 92 
 93 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 94         struct snd_ctl_elem_value *ucontrol)
 95 {
 96         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 97         struct soc_mixer_control *mc =
 98                 (struct soc_mixer_control *)kcontrol->private_value;
 99         int reg = mc->reg;
100         int ret;
101         u16 val;
102 
103         ret = snd_soc_put_volsw(kcontrol, ucontrol);
104         if (ret < 0)
105                 return ret;
106 
107         /* now hit the volume update bits (always bit 8) */
108         val = snd_soc_read(codec, reg);
109         return snd_soc_write(codec, reg, val | 0x0100);
110 }
111 
112 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
113         SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
114                 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
115 
116 
117 static const char *wm8400_digital_sidetone[] =
118         {"None", "Left ADC", "Right ADC", "Reserved"};
119 
120 static const struct soc_enum wm8400_left_digital_sidetone_enum =
121 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
122                 WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone);
123 
124 static const struct soc_enum wm8400_right_digital_sidetone_enum =
125 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
126                 WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone);
127 
128 static const char *wm8400_adcmode[] =
129         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
130 
131 static const struct soc_enum wm8400_right_adcmode_enum =
132 SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode);
133 
134 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
135 /* INMIXL */
136 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
137            1, 0),
138 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
139            1, 0),
140 /* INMIXR */
141 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
142            1, 0),
143 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
144            1, 0),
145 
146 /* LOMIX */
147 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
148         WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
149 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
150         WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
151 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
152         WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
153 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
154         WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
155 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
156         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
157 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
158         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
159 
160 /* ROMIX */
161 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
162         WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
163 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
164         WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
165 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
166         WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
167 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
168         WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
169 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
170         WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
171 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
172         WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
173 
174 /* LOUT */
175 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
176         WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
177 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
178 
179 /* ROUT */
180 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
181         WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
182 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
183 
184 /* LOPGA */
185 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
186         WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
187 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
188         WM8400_LOPGAZC_SHIFT, 1, 0),
189 
190 /* ROPGA */
191 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
192         WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
193 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
194         WM8400_ROPGAZC_SHIFT, 1, 0),
195 
196 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
197         WM8400_LONMUTE_SHIFT, 1, 0),
198 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
199         WM8400_LOPMUTE_SHIFT, 1, 0),
200 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
201         WM8400_LOATTN_SHIFT, 1, 0),
202 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
203         WM8400_RONMUTE_SHIFT, 1, 0),
204 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
205         WM8400_ROPMUTE_SHIFT, 1, 0),
206 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
207         WM8400_ROATTN_SHIFT, 1, 0),
208 
209 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
210         WM8400_OUT3MUTE_SHIFT, 1, 0),
211 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
212         WM8400_OUT3ATTN_SHIFT, 1, 0),
213 
214 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
215         WM8400_OUT4MUTE_SHIFT, 1, 0),
216 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
217         WM8400_OUT4ATTN_SHIFT, 1, 0),
218 
219 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
220         WM8400_CDMODE_SHIFT, 1, 0),
221 
222 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
223         WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
224 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
225         WM8400_DCGAIN_SHIFT, 6, 0),
226 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
227         WM8400_ACGAIN_SHIFT, 6, 0),
228 
229 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
230         WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
231         127, 0, out_dac_tlv),
232 
233 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
234         WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
235         127, 0, out_dac_tlv),
236 
237 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
238 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
239 
240 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
241         WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
242 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
243         WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
244 
245 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
246         WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
247 
248 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
249 
250 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
251         WM8400_LEFT_ADC_DIGITAL_VOLUME,
252         WM8400_ADCL_VOL_SHIFT,
253         WM8400_ADCL_VOL_MASK,
254         0,
255         in_adc_tlv),
256 
257 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
258         WM8400_RIGHT_ADC_DIGITAL_VOLUME,
259         WM8400_ADCR_VOL_SHIFT,
260         WM8400_ADCR_VOL_MASK,
261         0,
262         in_adc_tlv),
263 
264 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
265         WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
266         WM8400_LIN12VOL_SHIFT,
267         WM8400_LIN12VOL_MASK,
268         0,
269         in_pga_tlv),
270 
271 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
272         WM8400_LI12ZC_SHIFT, 1, 0),
273 
274 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
275         WM8400_LI12MUTE_SHIFT, 1, 0),
276 
277 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
278         WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
279         WM8400_LIN34VOL_SHIFT,
280         WM8400_LIN34VOL_MASK,
281         0,
282         in_pga_tlv),
283 
284 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
285         WM8400_LI34ZC_SHIFT, 1, 0),
286 
287 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
288         WM8400_LI34MUTE_SHIFT, 1, 0),
289 
290 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
291         WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
292         WM8400_RIN12VOL_SHIFT,
293         WM8400_RIN12VOL_MASK,
294         0,
295         in_pga_tlv),
296 
297 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
298         WM8400_RI12ZC_SHIFT, 1, 0),
299 
300 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
301         WM8400_RI12MUTE_SHIFT, 1, 0),
302 
303 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
304         WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
305         WM8400_RIN34VOL_SHIFT,
306         WM8400_RIN34VOL_MASK,
307         0,
308         in_pga_tlv),
309 
310 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
311         WM8400_RI34ZC_SHIFT, 1, 0),
312 
313 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
314         WM8400_RI34MUTE_SHIFT, 1, 0),
315 
316 };
317 
318 /*
319  * _DAPM_ Controls
320  */
321 
322 static int outmixer_event (struct snd_soc_dapm_widget *w,
323         struct snd_kcontrol * kcontrol, int event)
324 {
325         struct soc_mixer_control *mc =
326                 (struct soc_mixer_control *)kcontrol->private_value;
327         u32 reg_shift = mc->shift;
328         int ret = 0;
329         u16 reg;
330 
331         switch (reg_shift) {
332         case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
333                 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1);
334                 if (reg & WM8400_LDLO) {
335                         printk(KERN_WARNING
336                         "Cannot set as Output Mixer 1 LDLO Set\n");
337                         ret = -1;
338                 }
339                 break;
340         case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
341                 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2);
342                 if (reg & WM8400_RDRO) {
343                         printk(KERN_WARNING
344                         "Cannot set as Output Mixer 2 RDRO Set\n");
345                         ret = -1;
346                 }
347                 break;
348         case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
349                 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
350                 if (reg & WM8400_LDSPK) {
351                         printk(KERN_WARNING
352                         "Cannot set as Speaker Mixer LDSPK Set\n");
353                         ret = -1;
354                 }
355                 break;
356         case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
357                 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
358                 if (reg & WM8400_RDSPK) {
359                         printk(KERN_WARNING
360                         "Cannot set as Speaker Mixer RDSPK Set\n");
361                         ret = -1;
362                 }
363                 break;
364         }
365 
366         return ret;
367 }
368 
369 /* INMIX dB values */
370 static const unsigned int in_mix_tlv[] = {
371         TLV_DB_RANGE_HEAD(1),
372         0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
373 };
374 
375 /* Left In PGA Connections */
376 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
377 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
378 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
379 };
380 
381 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
382 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
383 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
384 };
385 
386 /* Right In PGA Connections */
387 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
388 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
389 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
390 };
391 
392 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
393 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
394 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
395 };
396 
397 /* INMIXL */
398 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
399 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
400         WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
401 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
402         7, 0, in_mix_tlv),
403 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
404                 1, 0),
405 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
406                 1, 0),
407 };
408 
409 /* INMIXR */
410 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
411 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
412         WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
413 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
414         7, 0, in_mix_tlv),
415 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
416         1, 0),
417 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
418         1, 0),
419 };
420 
421 /* AINLMUX */
422 static const char *wm8400_ainlmux[] =
423         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
424 
425 static const struct soc_enum wm8400_ainlmux_enum =
426 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT,
427         ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux);
428 
429 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
430 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
431 
432 /* DIFFINL */
433 
434 /* AINRMUX */
435 static const char *wm8400_ainrmux[] =
436         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
437 
438 static const struct soc_enum wm8400_ainrmux_enum =
439 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT,
440         ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux);
441 
442 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
443 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
444 
445 /* RXVOICE */
446 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
447 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
448                         WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
449 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
450                         WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
451 };
452 
453 /* LOMIX */
454 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
455 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
456         WM8400_LRBLO_SHIFT, 1, 0),
457 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
458         WM8400_LLBLO_SHIFT, 1, 0),
459 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
460         WM8400_LRI3LO_SHIFT, 1, 0),
461 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
462         WM8400_LLI3LO_SHIFT, 1, 0),
463 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
464         WM8400_LR12LO_SHIFT, 1, 0),
465 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
466         WM8400_LL12LO_SHIFT, 1, 0),
467 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
468         WM8400_LDLO_SHIFT, 1, 0),
469 };
470 
471 /* ROMIX */
472 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
473 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
474         WM8400_RLBRO_SHIFT, 1, 0),
475 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
476         WM8400_RRBRO_SHIFT, 1, 0),
477 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
478         WM8400_RLI3RO_SHIFT, 1, 0),
479 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
480         WM8400_RRI3RO_SHIFT, 1, 0),
481 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
482         WM8400_RL12RO_SHIFT, 1, 0),
483 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
484         WM8400_RR12RO_SHIFT, 1, 0),
485 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
486         WM8400_RDRO_SHIFT, 1, 0),
487 };
488 
489 /* LONMIX */
490 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
491 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
492         WM8400_LLOPGALON_SHIFT, 1, 0),
493 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
494         WM8400_LROPGALON_SHIFT, 1, 0),
495 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
496         WM8400_LOPLON_SHIFT, 1, 0),
497 };
498 
499 /* LOPMIX */
500 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
501 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
502         WM8400_LR12LOP_SHIFT, 1, 0),
503 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
504         WM8400_LL12LOP_SHIFT, 1, 0),
505 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
506         WM8400_LLOPGALOP_SHIFT, 1, 0),
507 };
508 
509 /* RONMIX */
510 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
511 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
512         WM8400_RROPGARON_SHIFT, 1, 0),
513 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
514         WM8400_RLOPGARON_SHIFT, 1, 0),
515 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
516         WM8400_ROPRON_SHIFT, 1, 0),
517 };
518 
519 /* ROPMIX */
520 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
521 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
522         WM8400_RL12ROP_SHIFT, 1, 0),
523 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
524         WM8400_RR12ROP_SHIFT, 1, 0),
525 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
526         WM8400_RROPGAROP_SHIFT, 1, 0),
527 };
528 
529 /* OUT3MIX */
530 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
531 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
532         WM8400_LI4O3_SHIFT, 1, 0),
533 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
534         WM8400_LPGAO3_SHIFT, 1, 0),
535 };
536 
537 /* OUT4MIX */
538 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
539 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
540         WM8400_RPGAO4_SHIFT, 1, 0),
541 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
542         WM8400_RI4O4_SHIFT, 1, 0),
543 };
544 
545 /* SPKMIX */
546 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
547 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
548         WM8400_LI2SPK_SHIFT, 1, 0),
549 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
550         WM8400_LB2SPK_SHIFT, 1, 0),
551 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
552         WM8400_LOPGASPK_SHIFT, 1, 0),
553 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
554         WM8400_LDSPK_SHIFT, 1, 0),
555 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
556         WM8400_RDSPK_SHIFT, 1, 0),
557 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
558         WM8400_ROPGASPK_SHIFT, 1, 0),
559 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
560         WM8400_RL12ROP_SHIFT, 1, 0),
561 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
562         WM8400_RI2SPK_SHIFT, 1, 0),
563 };
564 
565 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
566 /* Input Side */
567 /* Input Lines */
568 SND_SOC_DAPM_INPUT("LIN1"),
569 SND_SOC_DAPM_INPUT("LIN2"),
570 SND_SOC_DAPM_INPUT("LIN3"),
571 SND_SOC_DAPM_INPUT("LIN4/RXN"),
572 SND_SOC_DAPM_INPUT("RIN3"),
573 SND_SOC_DAPM_INPUT("RIN4/RXP"),
574 SND_SOC_DAPM_INPUT("RIN1"),
575 SND_SOC_DAPM_INPUT("RIN2"),
576 SND_SOC_DAPM_INPUT("Internal ADC Source"),
577 
578 /* DACs */
579 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
580         WM8400_ADCL_ENA_SHIFT, 0),
581 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
582         WM8400_ADCR_ENA_SHIFT, 0),
583 
584 /* Input PGAs */
585 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
586                    WM8400_LIN12_ENA_SHIFT,
587                    0, &wm8400_dapm_lin12_pga_controls[0],
588                    ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
589 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
590                    WM8400_LIN34_ENA_SHIFT,
591                    0, &wm8400_dapm_lin34_pga_controls[0],
592                    ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
593 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
594                    WM8400_RIN12_ENA_SHIFT,
595                    0, &wm8400_dapm_rin12_pga_controls[0],
596                    ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
597 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
598                    WM8400_RIN34_ENA_SHIFT,
599                    0, &wm8400_dapm_rin34_pga_controls[0],
600                    ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
601 
602 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
603                     0, NULL, 0),
604 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
605                     0, NULL, 0),
606 
607 /* INMIXL */
608 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
609         &wm8400_dapm_inmixl_controls[0],
610         ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
611 
612 /* AINLMUX */
613 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
614 
615 /* INMIXR */
616 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
617         &wm8400_dapm_inmixr_controls[0],
618         ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
619 
620 /* AINRMUX */
621 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
622 
623 /* Output Side */
624 /* DACs */
625 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
626         WM8400_DACL_ENA_SHIFT, 0),
627 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
628         WM8400_DACR_ENA_SHIFT, 0),
629 
630 /* LOMIX */
631 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
632                      WM8400_LOMIX_ENA_SHIFT,
633                      0, &wm8400_dapm_lomix_controls[0],
634                      ARRAY_SIZE(wm8400_dapm_lomix_controls),
635                      outmixer_event, SND_SOC_DAPM_PRE_REG),
636 
637 /* LONMIX */
638 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
639                    0, &wm8400_dapm_lonmix_controls[0],
640                    ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
641 
642 /* LOPMIX */
643 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
644                    0, &wm8400_dapm_lopmix_controls[0],
645                    ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
646 
647 /* OUT3MIX */
648 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
649                    0, &wm8400_dapm_out3mix_controls[0],
650                    ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
651 
652 /* SPKMIX */
653 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
654                      0, &wm8400_dapm_spkmix_controls[0],
655                      ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
656                      SND_SOC_DAPM_PRE_REG),
657 
658 /* OUT4MIX */
659 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
660         0, &wm8400_dapm_out4mix_controls[0],
661         ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
662 
663 /* ROPMIX */
664 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
665                    0, &wm8400_dapm_ropmix_controls[0],
666                    ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
667 
668 /* RONMIX */
669 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
670                    0, &wm8400_dapm_ronmix_controls[0],
671                    ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
672 
673 /* ROMIX */
674 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
675                      WM8400_ROMIX_ENA_SHIFT,
676                      0, &wm8400_dapm_romix_controls[0],
677                      ARRAY_SIZE(wm8400_dapm_romix_controls),
678                      outmixer_event, SND_SOC_DAPM_PRE_REG),
679 
680 /* LOUT PGA */
681 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
682                  0, NULL, 0),
683 
684 /* ROUT PGA */
685 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
686                  0, NULL, 0),
687 
688 /* LOPGA */
689 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
690         NULL, 0),
691 
692 /* ROPGA */
693 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
694         NULL, 0),
695 
696 /* MICBIAS */
697 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
698                     WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
699 
700 SND_SOC_DAPM_OUTPUT("LON"),
701 SND_SOC_DAPM_OUTPUT("LOP"),
702 SND_SOC_DAPM_OUTPUT("OUT3"),
703 SND_SOC_DAPM_OUTPUT("LOUT"),
704 SND_SOC_DAPM_OUTPUT("SPKN"),
705 SND_SOC_DAPM_OUTPUT("SPKP"),
706 SND_SOC_DAPM_OUTPUT("ROUT"),
707 SND_SOC_DAPM_OUTPUT("OUT4"),
708 SND_SOC_DAPM_OUTPUT("ROP"),
709 SND_SOC_DAPM_OUTPUT("RON"),
710 
711 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
712 };
713 
714 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
715         /* Make DACs turn on when playing even if not mixed into any outputs */
716         {"Internal DAC Sink", NULL, "Left DAC"},
717         {"Internal DAC Sink", NULL, "Right DAC"},
718 
719         /* Make ADCs turn on when recording
720          * even if not mixed from any inputs */
721         {"Left ADC", NULL, "Internal ADC Source"},
722         {"Right ADC", NULL, "Internal ADC Source"},
723 
724         /* Input Side */
725         /* LIN12 PGA */
726         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
727         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
728         /* LIN34 PGA */
729         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
730         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
731         /* INMIXL */
732         {"INMIXL", NULL, "INL"},
733         {"INMIXL", "Record Left Volume", "LOMIX"},
734         {"INMIXL", "LIN2 Volume", "LIN2"},
735         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
736         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
737         /* AILNMUX */
738         {"AILNMUX", NULL, "INL"},
739         {"AILNMUX", "INMIXL Mix", "INMIXL"},
740         {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
741         {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
742         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
743         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
744         /* ADC */
745         {"Left ADC", NULL, "AILNMUX"},
746 
747         /* RIN12 PGA */
748         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
749         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
750         /* RIN34 PGA */
751         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
752         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
753         /* INMIXR */
754         {"INMIXR", NULL, "INR"},
755         {"INMIXR", "Record Right Volume", "ROMIX"},
756         {"INMIXR", "RIN2 Volume", "RIN2"},
757         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
758         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
759         /* AIRNMUX */
760         {"AIRNMUX", NULL, "INR"},
761         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
762         {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
763         {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
764         {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
765         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
766         /* ADC */
767         {"Right ADC", NULL, "AIRNMUX"},
768 
769         /* LOMIX */
770         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
771         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
772         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
773         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
774         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
775         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
776         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
777 
778         /* ROMIX */
779         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
780         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
781         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
782         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
783         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
784         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
785         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
786 
787         /* SPKMIX */
788         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
789         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
790         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
791         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
792         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
793         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
794         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
795         {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
796 
797         /* LONMIX */
798         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
799         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
800         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
801 
802         /* LOPMIX */
803         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
804         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
805         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
806 
807         /* OUT3MIX */
808         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
809         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
810 
811         /* OUT4MIX */
812         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
813         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
814 
815         /* RONMIX */
816         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
817         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
818         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
819 
820         /* ROPMIX */
821         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
822         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
823         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
824 
825         /* Out Mixer PGAs */
826         {"LOPGA", NULL, "LOMIX"},
827         {"ROPGA", NULL, "ROMIX"},
828 
829         {"LOUT PGA", NULL, "LOMIX"},
830         {"ROUT PGA", NULL, "ROMIX"},
831 
832         /* Output Pins */
833         {"LON", NULL, "LONMIX"},
834         {"LOP", NULL, "LOPMIX"},
835         {"OUT3", NULL, "OUT3MIX"},
836         {"LOUT", NULL, "LOUT PGA"},
837         {"SPKN", NULL, "SPKMIX"},
838         {"ROUT", NULL, "ROUT PGA"},
839         {"OUT4", NULL, "OUT4MIX"},
840         {"ROP", NULL, "ROPMIX"},
841         {"RON", NULL, "RONMIX"},
842 };
843 
844 /*
845  * Clock after FLL and dividers
846  */
847 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
848                 int clk_id, unsigned int freq, int dir)
849 {
850         struct snd_soc_codec *codec = codec_dai->codec;
851         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
852 
853         wm8400->sysclk = freq;
854         return 0;
855 }
856 
857 struct fll_factors {
858         u16 n;
859         u16 k;
860         u16 outdiv;
861         u16 fratio;
862         u16 freq_ref;
863 };
864 
865 #define FIXED_FLL_SIZE ((1 << 16) * 10)
866 
867 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
868                        unsigned int Fref, unsigned int Fout)
869 {
870         u64 Kpart;
871         unsigned int K, Nmod, target;
872 
873         factors->outdiv = 2;
874         while (Fout * factors->outdiv <  90000000 ||
875                Fout * factors->outdiv > 100000000) {
876                 factors->outdiv *= 2;
877                 if (factors->outdiv > 32) {
878                         dev_err(wm8400->wm8400->dev,
879                                 "Unsupported FLL output frequency %uHz\n",
880                                 Fout);
881                         return -EINVAL;
882                 }
883         }
884         target = Fout * factors->outdiv;
885         factors->outdiv = factors->outdiv >> 2;
886 
887         if (Fref < 48000)
888                 factors->freq_ref = 1;
889         else
890                 factors->freq_ref = 0;
891 
892         if (Fref < 1000000)
893                 factors->fratio = 9;
894         else
895                 factors->fratio = 0;
896 
897         /* Ensure we have a fractional part */
898         do {
899                 if (Fref < 1000000)
900                         factors->fratio--;
901                 else
902                         factors->fratio++;
903 
904                 if (factors->fratio < 1 || factors->fratio > 8) {
905                         dev_err(wm8400->wm8400->dev,
906                                 "Unable to calculate FRATIO\n");
907                         return -EINVAL;
908                 }
909 
910                 factors->n = target / (Fref * factors->fratio);
911                 Nmod = target % (Fref * factors->fratio);
912         } while (Nmod == 0);
913 
914         /* Calculate fractional part - scale up so we can round. */
915         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
916 
917         do_div(Kpart, (Fref * factors->fratio));
918 
919         K = Kpart & 0xFFFFFFFF;
920 
921         if ((K % 10) >= 5)
922                 K += 5;
923 
924         /* Move down to proper range now rounding is done */
925         factors->k = K / 10;
926 
927         dev_dbg(wm8400->wm8400->dev,
928                 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
929                 Fref, Fout,
930                 factors->n, factors->k, factors->fratio, factors->outdiv);
931 
932         return 0;
933 }
934 
935 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
936                               int source, unsigned int freq_in,
937                               unsigned int freq_out)
938 {
939         struct snd_soc_codec *codec = codec_dai->codec;
940         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
941         struct fll_factors factors;
942         int ret;
943         u16 reg;
944 
945         if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
946                 return 0;
947 
948         if (freq_out) {
949                 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
950                 if (ret != 0)
951                         return ret;
952         } else {
953                 /* Bodge GCC 4.4.0 uninitialised variable warning - it
954                  * doesn't seem capable of working out that we exit if
955                  * freq_out is 0 before any of the uses. */
956                 memset(&factors, 0, sizeof(factors));
957         }
958 
959         wm8400->fll_out = freq_out;
960         wm8400->fll_in = freq_in;
961 
962         /* We *must* disable the FLL before any changes */
963         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
964         reg &= ~WM8400_FLL_ENA;
965         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
966 
967         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
968         reg &= ~WM8400_FLL_OSC_ENA;
969         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
970 
971         if (!freq_out)
972                 return 0;
973 
974         reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
975         reg |= WM8400_FLL_FRAC | factors.fratio;
976         reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
977         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
978 
979         snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
980         snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
981 
982         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
983         reg &= ~WM8400_FLL_OUTDIV_MASK;
984         reg |= factors.outdiv;
985         snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
986 
987         return 0;
988 }
989 
990 /*
991  * Sets ADC and Voice DAC format.
992  */
993 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
994                 unsigned int fmt)
995 {
996         struct snd_soc_codec *codec = codec_dai->codec;
997         u16 audio1, audio3;
998 
999         audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1000         audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
1001 
1002         /* set master/slave audio interface */
1003         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1004         case SND_SOC_DAIFMT_CBS_CFS:
1005                 audio3 &= ~WM8400_AIF_MSTR1;
1006                 break;
1007         case SND_SOC_DAIFMT_CBM_CFM:
1008                 audio3 |= WM8400_AIF_MSTR1;
1009                 break;
1010         default:
1011                 return -EINVAL;
1012         }
1013 
1014         audio1 &= ~WM8400_AIF_FMT_MASK;
1015 
1016         /* interface format */
1017         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1018         case SND_SOC_DAIFMT_I2S:
1019                 audio1 |= WM8400_AIF_FMT_I2S;
1020                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1021                 break;
1022         case SND_SOC_DAIFMT_RIGHT_J:
1023                 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1024                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1025                 break;
1026         case SND_SOC_DAIFMT_LEFT_J:
1027                 audio1 |= WM8400_AIF_FMT_LEFTJ;
1028                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1029                 break;
1030         case SND_SOC_DAIFMT_DSP_A:
1031                 audio1 |= WM8400_AIF_FMT_DSP;
1032                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1033                 break;
1034         case SND_SOC_DAIFMT_DSP_B:
1035                 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1036                 break;
1037         default:
1038                 return -EINVAL;
1039         }
1040 
1041         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1042         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1043         return 0;
1044 }
1045 
1046 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1047                 int div_id, int div)
1048 {
1049         struct snd_soc_codec *codec = codec_dai->codec;
1050         u16 reg;
1051 
1052         switch (div_id) {
1053         case WM8400_MCLK_DIV:
1054                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1055                         ~WM8400_MCLK_DIV_MASK;
1056                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1057                 break;
1058         case WM8400_DACCLK_DIV:
1059                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1060                         ~WM8400_DAC_CLKDIV_MASK;
1061                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1062                 break;
1063         case WM8400_ADCCLK_DIV:
1064                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1065                         ~WM8400_ADC_CLKDIV_MASK;
1066                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1067                 break;
1068         case WM8400_BCLK_DIV:
1069                 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
1070                         ~WM8400_BCLK_DIV_MASK;
1071                 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
1072                 break;
1073         default:
1074                 return -EINVAL;
1075         }
1076 
1077         return 0;
1078 }
1079 
1080 /*
1081  * Set PCM DAI bit size and sample rate.
1082  */
1083 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1084         struct snd_pcm_hw_params *params,
1085         struct snd_soc_dai *dai)
1086 {
1087         struct snd_soc_codec *codec = dai->codec;
1088         u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1089 
1090         audio1 &= ~WM8400_AIF_WL_MASK;
1091         /* bit size */
1092         switch (params_format(params)) {
1093         case SNDRV_PCM_FORMAT_S16_LE:
1094                 break;
1095         case SNDRV_PCM_FORMAT_S20_3LE:
1096                 audio1 |= WM8400_AIF_WL_20BITS;
1097                 break;
1098         case SNDRV_PCM_FORMAT_S24_LE:
1099                 audio1 |= WM8400_AIF_WL_24BITS;
1100                 break;
1101         case SNDRV_PCM_FORMAT_S32_LE:
1102                 audio1 |= WM8400_AIF_WL_32BITS;
1103                 break;
1104         }
1105 
1106         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1107         return 0;
1108 }
1109 
1110 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1111 {
1112         struct snd_soc_codec *codec = dai->codec;
1113         u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1114 
1115         if (mute)
1116                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1117         else
1118                 snd_soc_write(codec, WM8400_DAC_CTRL, val);
1119 
1120         return 0;
1121 }
1122 
1123 /* TODO: set bias for best performance at standby */
1124 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1125                                  enum snd_soc_bias_level level)
1126 {
1127         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1128         u16 val;
1129         int ret;
1130 
1131         switch (level) {
1132         case SND_SOC_BIAS_ON:
1133                 break;
1134 
1135         case SND_SOC_BIAS_PREPARE:
1136                 /* VMID=2*50k */
1137                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1138                         ~WM8400_VMID_MODE_MASK;
1139                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1140                 break;
1141 
1142         case SND_SOC_BIAS_STANDBY:
1143                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1144                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
1145                                                     &power[0]);
1146                         if (ret != 0) {
1147                                 dev_err(wm8400->wm8400->dev,
1148                                         "Failed to enable regulators: %d\n",
1149                                         ret);
1150                                 return ret;
1151                         }
1152 
1153                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1154                                      WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1155 
1156                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1157                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1158                                      WM8400_BUFDCOPEN | WM8400_POBCTRL);
1159 
1160                         msleep(50);
1161 
1162                         /* Enable VREF & VMID at 2x50k */
1163                         val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1164                         val |= 0x2 | WM8400_VREF_ENA;
1165                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1166 
1167                         /* Enable BUFIOEN */
1168                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1169                                      WM8400_BUFDCOPEN | WM8400_POBCTRL |
1170                                      WM8400_BUFIOEN);
1171 
1172                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1173                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1174                 }
1175 
1176                 /* VMID=2*300k */
1177                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1178                         ~WM8400_VMID_MODE_MASK;
1179                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1180                 break;
1181 
1182         case SND_SOC_BIAS_OFF:
1183                 /* Enable POBCTRL and SOFT_ST */
1184                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1185                         WM8400_POBCTRL | WM8400_BUFIOEN);
1186 
1187                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1188                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1189                         WM8400_BUFDCOPEN | WM8400_POBCTRL |
1190                         WM8400_BUFIOEN);
1191 
1192                 /* mute DAC */
1193                 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1194                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1195 
1196                 /* Enable any disabled outputs */
1197                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1198                 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1199                         WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1200                         WM8400_ROUT_ENA;
1201                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1202 
1203                 /* Disable VMID */
1204                 val &= ~WM8400_VMID_MODE_MASK;
1205                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1206 
1207                 msleep(300);
1208 
1209                 /* Enable all output discharge bits */
1210                 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1211                         WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1212                         WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1213                         WM8400_DIS_ROUT);
1214 
1215                 /* Disable VREF */
1216                 val &= ~WM8400_VREF_ENA;
1217                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1218 
1219                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1220                 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
1221 
1222                 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1223                                              &power[0]);
1224                 if (ret != 0)
1225                         return ret;
1226 
1227                 break;
1228         }
1229 
1230         codec->dapm.bias_level = level;
1231         return 0;
1232 }
1233 
1234 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1235 
1236 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1237         SNDRV_PCM_FMTBIT_S24_LE)
1238 
1239 static const struct snd_soc_dai_ops wm8400_dai_ops = {
1240         .hw_params = wm8400_hw_params,
1241         .digital_mute = wm8400_mute,
1242         .set_fmt = wm8400_set_dai_fmt,
1243         .set_clkdiv = wm8400_set_dai_clkdiv,
1244         .set_sysclk = wm8400_set_dai_sysclk,
1245         .set_pll = wm8400_set_dai_pll,
1246 };
1247 
1248 /*
1249  * The WM8400 supports 2 different and mutually exclusive DAI
1250  * configurations.
1251  *
1252  * 1. ADC/DAC on Primary Interface
1253  * 2. ADC on Primary Interface/DAC on secondary
1254  */
1255 static struct snd_soc_dai_driver wm8400_dai = {
1256 /* ADC/DAC on primary */
1257         .name = "wm8400-hifi",
1258         .playback = {
1259                 .stream_name = "Playback",
1260                 .channels_min = 1,
1261                 .channels_max = 2,
1262                 .rates = WM8400_RATES,
1263                 .formats = WM8400_FORMATS,
1264         },
1265         .capture = {
1266                 .stream_name = "Capture",
1267                 .channels_min = 1,
1268                 .channels_max = 2,
1269                 .rates = WM8400_RATES,
1270                 .formats = WM8400_FORMATS,
1271         },
1272         .ops = &wm8400_dai_ops,
1273 };
1274 
1275 static int wm8400_suspend(struct snd_soc_codec *codec)
1276 {
1277         wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
1278 
1279         return 0;
1280 }
1281 
1282 static int wm8400_resume(struct snd_soc_codec *codec)
1283 {
1284         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1285 
1286         return 0;
1287 }
1288 
1289 static void wm8400_probe_deferred(struct work_struct *work)
1290 {
1291         struct wm8400_priv *priv = container_of(work, struct wm8400_priv,
1292                                                 work);
1293         struct snd_soc_codec *codec = priv->codec;
1294 
1295         /* charge output caps */
1296         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1297 }
1298 
1299 static int wm8400_codec_probe(struct snd_soc_codec *codec)
1300 {
1301         struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
1302         struct wm8400_priv *priv;
1303         int ret;
1304         u16 reg;
1305 
1306         priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv),
1307                             GFP_KERNEL);
1308         if (priv == NULL)
1309                 return -ENOMEM;
1310 
1311         snd_soc_codec_set_drvdata(codec, priv);
1312         priv->wm8400 = wm8400;
1313         codec->control_data = wm8400->regmap;
1314         priv->codec = codec;
1315 
1316         snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1317 
1318         ret = devm_regulator_bulk_get(wm8400->dev,
1319                                  ARRAY_SIZE(power), &power[0]);
1320         if (ret != 0) {
1321                 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
1322                 return ret;
1323         }
1324 
1325         INIT_WORK(&priv->work, wm8400_probe_deferred);
1326 
1327         wm8400_codec_reset(codec);
1328 
1329         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1330         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1331 
1332         /* Latch volume update bits */
1333         reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1334         snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1335                      reg & WM8400_IPVU);
1336         reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1337         snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1338                      reg & WM8400_IPVU);
1339 
1340         snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1341         snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1342 
1343         if (!schedule_work(&priv->work))
1344                 return -EINVAL;
1345         return 0;
1346 }
1347 
1348 static int  wm8400_codec_remove(struct snd_soc_codec *codec)
1349 {
1350         u16 reg;
1351 
1352         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1353         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1354                      reg & (~WM8400_CODEC_ENA));
1355 
1356         return 0;
1357 }
1358 
1359 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1360         .probe =        wm8400_codec_probe,
1361         .remove =       wm8400_codec_remove,
1362         .suspend =      wm8400_suspend,
1363         .resume =       wm8400_resume,
1364         .set_bias_level = wm8400_set_bias_level,
1365 
1366         .controls = wm8400_snd_controls,
1367         .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1368         .dapm_widgets = wm8400_dapm_widgets,
1369         .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1370         .dapm_routes = wm8400_dapm_routes,
1371         .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1372 };
1373 
1374 static int wm8400_probe(struct platform_device *pdev)
1375 {
1376         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1377                         &wm8400_dai, 1);
1378 }
1379 
1380 static int wm8400_remove(struct platform_device *pdev)
1381 {
1382         snd_soc_unregister_codec(&pdev->dev);
1383         return 0;
1384 }
1385 
1386 static struct platform_driver wm8400_codec_driver = {
1387         .driver = {
1388                    .name = "wm8400-codec",
1389                    .owner = THIS_MODULE,
1390                    },
1391         .probe = wm8400_probe,
1392         .remove = wm8400_remove,
1393 };
1394 
1395 module_platform_driver(wm8400_codec_driver);
1396 
1397 MODULE_DESCRIPTION("ASoC WM8400 driver");
1398 MODULE_AUTHOR("Mark Brown");
1399 MODULE_LICENSE("GPL");
1400 MODULE_ALIAS("platform:wm8400-codec");
1401 

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