~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm8900.c

Version: ~ [ linux-5.2-rc5 ] ~ [ linux-5.1.12 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.53 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.128 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.182 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.182 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.68 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * wm8900.c  --  WM8900 ALSA Soc Audio driver
  3  *
  4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  *
 12  * TODO:
 13  *  - Tristating.
 14  *  - TDM.
 15  *  - Jack detect.
 16  *  - FLL source configuration, currently only MCLK is supported.
 17  */
 18 
 19 #include <linux/module.h>
 20 #include <linux/moduleparam.h>
 21 #include <linux/kernel.h>
 22 #include <linux/init.h>
 23 #include <linux/delay.h>
 24 #include <linux/pm.h>
 25 #include <linux/i2c.h>
 26 #include <linux/regmap.h>
 27 #include <linux/spi/spi.h>
 28 #include <linux/slab.h>
 29 #include <sound/core.h>
 30 #include <sound/pcm.h>
 31 #include <sound/pcm_params.h>
 32 #include <sound/soc.h>
 33 #include <sound/initval.h>
 34 #include <sound/tlv.h>
 35 
 36 #include "wm8900.h"
 37 
 38 /* WM8900 register space */
 39 #define WM8900_REG_RESET        0x0
 40 #define WM8900_REG_ID           0x0
 41 #define WM8900_REG_POWER1       0x1
 42 #define WM8900_REG_POWER2       0x2
 43 #define WM8900_REG_POWER3       0x3
 44 #define WM8900_REG_AUDIO1       0x4
 45 #define WM8900_REG_AUDIO2       0x5
 46 #define WM8900_REG_CLOCKING1    0x6
 47 #define WM8900_REG_CLOCKING2    0x7
 48 #define WM8900_REG_AUDIO3       0x8
 49 #define WM8900_REG_AUDIO4       0x9
 50 #define WM8900_REG_DACCTRL      0xa
 51 #define WM8900_REG_LDAC_DV      0xb
 52 #define WM8900_REG_RDAC_DV      0xc
 53 #define WM8900_REG_SIDETONE     0xd
 54 #define WM8900_REG_ADCCTRL      0xe
 55 #define WM8900_REG_LADC_DV      0xf
 56 #define WM8900_REG_RADC_DV      0x10
 57 #define WM8900_REG_GPIO         0x12
 58 #define WM8900_REG_INCTL        0x15
 59 #define WM8900_REG_LINVOL       0x16
 60 #define WM8900_REG_RINVOL       0x17
 61 #define WM8900_REG_INBOOSTMIX1  0x18
 62 #define WM8900_REG_INBOOSTMIX2  0x19
 63 #define WM8900_REG_ADCPATH      0x1a
 64 #define WM8900_REG_AUXBOOST     0x1b
 65 #define WM8900_REG_ADDCTL       0x1e
 66 #define WM8900_REG_FLLCTL1      0x24
 67 #define WM8900_REG_FLLCTL2      0x25
 68 #define WM8900_REG_FLLCTL3      0x26
 69 #define WM8900_REG_FLLCTL4      0x27
 70 #define WM8900_REG_FLLCTL5      0x28
 71 #define WM8900_REG_FLLCTL6      0x29
 72 #define WM8900_REG_LOUTMIXCTL1  0x2c
 73 #define WM8900_REG_ROUTMIXCTL1  0x2d
 74 #define WM8900_REG_BYPASS1      0x2e
 75 #define WM8900_REG_BYPASS2      0x2f
 76 #define WM8900_REG_AUXOUT_CTL   0x30
 77 #define WM8900_REG_LOUT1CTL     0x33
 78 #define WM8900_REG_ROUT1CTL     0x34
 79 #define WM8900_REG_LOUT2CTL     0x35
 80 #define WM8900_REG_ROUT2CTL     0x36
 81 #define WM8900_REG_HPCTL1       0x3a
 82 #define WM8900_REG_OUTBIASCTL   0x73
 83 
 84 #define WM8900_MAXREG           0x80
 85 
 86 #define WM8900_REG_ADDCTL_OUT1_DIS    0x80
 87 #define WM8900_REG_ADDCTL_OUT2_DIS    0x40
 88 #define WM8900_REG_ADDCTL_VMID_DIS    0x20
 89 #define WM8900_REG_ADDCTL_BIAS_SRC    0x10
 90 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
 91 #define WM8900_REG_ADDCTL_TEMP_SD     0x02
 92 
 93 #define WM8900_REG_GPIO_TEMP_ENA   0x2
 94 
 95 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
 96 #define WM8900_REG_POWER1_BIAS_ENA         0x0008
 97 #define WM8900_REG_POWER1_VMID_BUF_ENA     0x0004
 98 #define WM8900_REG_POWER1_FLL_ENA          0x0040
 99 
100 #define WM8900_REG_POWER2_SYSCLK_ENA  0x8000
101 #define WM8900_REG_POWER2_ADCL_ENA    0x0002
102 #define WM8900_REG_POWER2_ADCR_ENA    0x0001
103 
104 #define WM8900_REG_POWER3_DACL_ENA    0x0002
105 #define WM8900_REG_POWER3_DACR_ENA    0x0001
106 
107 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108 #define WM8900_REG_AUDIO1_LRCLK_INV    0x0080
109 #define WM8900_REG_AUDIO1_BCLK_INV     0x0100
110 
111 #define WM8900_REG_CLOCKING1_BCLK_DIR   0x1
112 #define WM8900_REG_CLOCKING1_MCLK_SRC   0x100
113 #define WM8900_REG_CLOCKING1_BCLK_MASK  0x01e
114 #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
115 
116 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118 
119 #define WM8900_REG_DACCTRL_MUTE          0x004
120 #define WM8900_REG_DACCTRL_DAC_SB_FILT   0x100
121 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
122 
123 #define WM8900_REG_AUDIO3_ADCLRC_DIR    0x0800
124 
125 #define WM8900_REG_AUDIO4_DACLRC_DIR    0x0800
126 
127 #define WM8900_REG_FLLCTL1_OSC_ENA    0x100
128 
129 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
130 
131 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133 #define WM8900_REG_HPCTL1_HP_CLAMP_IP    0x20
134 #define WM8900_REG_HPCTL1_HP_CLAMP_OP    0x10
135 #define WM8900_REG_HPCTL1_HP_SHORT       0x08
136 #define WM8900_REG_HPCTL1_HP_SHORT2      0x04
137 
138 #define WM8900_LRC_MASK 0x03ff
139 
140 struct wm8900_priv {
141         struct regmap *regmap;
142 
143         u32 fll_in; /* FLL input frequency */
144         u32 fll_out; /* FLL output frequency */
145 };
146 
147 /*
148  * wm8900 register cache.  We can't read the entire register space and we
149  * have slow control buses so we cache the registers.
150  */
151 static const struct reg_default wm8900_reg_defaults[] = {
152         {  1, 0x0000 },
153         {  2, 0xc000 },
154         {  3, 0x0000 },
155         {  4, 0x4050 },
156         {  5, 0x4000 },
157         {  6, 0x0008 },
158         {  7, 0x0000 },
159         {  8, 0x0040 },
160         {  9, 0x0040 },
161         { 10, 0x1004 },
162         { 11, 0x00c0 },
163         { 12, 0x00c0 },
164         { 13, 0x0000 },
165         { 14, 0x0100 },
166         { 15, 0x00c0 },
167         { 16, 0x00c0 },
168         { 17, 0x0000 },
169         { 18, 0xb001 },
170         { 19, 0x0000 },
171         { 20, 0x0000 },
172         { 21, 0x0044 },
173         { 22, 0x004c },
174         { 23, 0x004c },
175         { 24, 0x0044 },
176         { 25, 0x0044 },
177         { 26, 0x0000 },
178         { 27, 0x0044 },
179         { 28, 0x0000 },
180         { 29, 0x0000 },
181         { 30, 0x0002 },
182         { 31, 0x0000 },
183         { 32, 0x0000 },
184         { 33, 0x0000 },
185         { 34, 0x0000 },
186         { 35, 0x0000 },
187         { 36, 0x0008 },
188         { 37, 0x0000 },
189         { 38, 0x0000 },
190         { 39, 0x0008 },
191         { 40, 0x0097 },
192         { 41, 0x0100 },
193         { 42, 0x0000 },
194         { 43, 0x0000 },
195         { 44, 0x0050 },
196         { 45, 0x0050 },
197         { 46, 0x0055 },
198         { 47, 0x0055 },
199         { 48, 0x0055 },
200         { 49, 0x0000 },
201         { 50, 0x0000 },
202         { 51, 0x0079 },
203         { 52, 0x0079 },
204         { 53, 0x0079 },
205         { 54, 0x0079 },
206         { 55, 0x0000 },
207 };
208 
209 static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
210 {
211         switch (reg) {
212         case WM8900_REG_ID:
213                 return true;
214         default:
215                 return false;
216         }
217 }
218 
219 static void wm8900_reset(struct snd_soc_codec *codec)
220 {
221         snd_soc_write(codec, WM8900_REG_RESET, 0);
222 }
223 
224 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
225                            struct snd_kcontrol *kcontrol, int event)
226 {
227         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
228         u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
229 
230         switch (event) {
231         case SND_SOC_DAPM_PRE_PMU:
232                 /* Clamp headphone outputs */
233                 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
234                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
235                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
236                 break;
237 
238         case SND_SOC_DAPM_POST_PMU:
239                 /* Enable the input stage */
240                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
241                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
242                         WM8900_REG_HPCTL1_HP_SHORT2 |
243                         WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
244                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
245 
246                 msleep(400);
247 
248                 /* Enable the output stage */
249                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
250                 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
251                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
252 
253                 /* Remove the shorts */
254                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
255                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
256                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
257                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
258                 break;
259 
260         case SND_SOC_DAPM_PRE_PMD:
261                 /* Short the output */
262                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
263                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
264 
265                 /* Disable the output stage */
266                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
267                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
268 
269                 /* Clamp the outputs and power down input */
270                 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
271                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
272                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
273                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
274                 break;
275 
276         case SND_SOC_DAPM_POST_PMD:
277                 /* Disable everything */
278                 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
279                 break;
280 
281         default:
282                 WARN(1, "Invalid event %d\n", event);
283                 break;
284         }
285 
286         return 0;
287 }
288 
289 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
290 
291 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
292 
293 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
294 
295 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
296 
297 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
298 
299 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
300 
301 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
302 
303 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
304 
305 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
306 
307 static SOC_ENUM_SINGLE_DECL(mic_bias_level,
308                             WM8900_REG_INCTL, 8, mic_bias_level_txt);
309 
310 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
311 
312 static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
313                             WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
314 
315 static const char *dac_deemphasis_txt[] = {
316         "Disabled", "32kHz", "44.1kHz", "48kHz"
317 };
318 
319 static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
320                             WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
321 
322 static const char *adc_hpf_cut_txt[] = {
323         "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
324 };
325 
326 static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
327                             WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
328 
329 static const char *lr_txt[] = {
330         "Left", "Right"
331 };
332 
333 static SOC_ENUM_SINGLE_DECL(aifl_src,
334                             WM8900_REG_AUDIO1, 15, lr_txt);
335 
336 static SOC_ENUM_SINGLE_DECL(aifr_src,
337                             WM8900_REG_AUDIO1, 14, lr_txt);
338 
339 static SOC_ENUM_SINGLE_DECL(dacl_src,
340                             WM8900_REG_AUDIO2, 15, lr_txt);
341 
342 static SOC_ENUM_SINGLE_DECL(dacr_src,
343                             WM8900_REG_AUDIO2, 14, lr_txt);
344 
345 static const char *sidetone_txt[] = {
346         "Disabled", "Left ADC", "Right ADC"
347 };
348 
349 static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
350                             WM8900_REG_SIDETONE, 2, sidetone_txt);
351 
352 static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
353                             WM8900_REG_SIDETONE, 0, sidetone_txt);
354 
355 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
356 SOC_ENUM("Mic Bias Level", mic_bias_level),
357 
358 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
359                in_pga_tlv),
360 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
361 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
362 
363 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
364                in_pga_tlv),
365 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
366 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
367 
368 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
369 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
370 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
371 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
372 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
373            12, 1, 0),
374 
375 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
376 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
377 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
378 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
379                adc_svol_tlv),
380 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
381                adc_svol_tlv),
382 SOC_ENUM("Left Digital Audio Source", aifl_src),
383 SOC_ENUM("Right Digital Audio Source", aifr_src),
384 
385 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
386                dac_boost_tlv),
387 SOC_ENUM("Left DAC Source", dacl_src),
388 SOC_ENUM("Right DAC Source", dacr_src),
389 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
390 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
391 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
392 
393 SOC_DOUBLE_R_TLV("Digital Playback Volume",
394                  WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
395                  1, 96, 0, dac_tlv),
396 SOC_DOUBLE_R_TLV("Digital Capture Volume",
397                  WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
398 
399 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
400                out_mix_tlv),
401 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
402                out_mix_tlv),
403 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
404                out_mix_tlv),
405 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
406                out_mix_tlv),
407 
408 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
409                out_mix_tlv),
410 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
411                out_mix_tlv),
412 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
413                out_mix_tlv),
414 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
415                out_mix_tlv),
416 
417 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
418                in_boost_tlv),
419 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
420                in_boost_tlv),
421 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
422                in_boost_tlv),
423 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
424                in_boost_tlv),
425 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
426                in_boost_tlv),
427 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
428                in_boost_tlv),
429 
430 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
431                0, 63, 0, out_pga_tlv),
432 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
433              6, 1, 1),
434 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
435              7, 1, 0),
436 
437 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
438                  WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
439                  0, 63, 0, out_pga_tlv),
440 SOC_DOUBLE_R("LINEOUT2 Switch",
441              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
442 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
443              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
444 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
445            0, 1, 1),
446 
447 };
448 
449 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
450 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
451 
452 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
453 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
454 
455 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
456 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
457 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
458 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
459 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
460 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
461 };
462 
463 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
464 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
465 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
466 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
467 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
469 };
470 
471 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
472 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
473 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
474 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
475 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
476 };
477 
478 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
479 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
480 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
481 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
482 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
483 };
484 
485 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
486 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
487 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
488 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
489 };
490 
491 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
492 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
493 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
494 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
495 };
496 
497 static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
498 
499 static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
500                             WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
501 
502 static const struct snd_kcontrol_new wm8900_lineout2_lp =
503 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
504 
505 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
506 
507 /* Externally visible pins */
508 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
509 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
510 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
511 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
512 SND_SOC_DAPM_OUTPUT("HP_L"),
513 SND_SOC_DAPM_OUTPUT("HP_R"),
514 
515 SND_SOC_DAPM_INPUT("RINPUT1"),
516 SND_SOC_DAPM_INPUT("LINPUT1"),
517 SND_SOC_DAPM_INPUT("RINPUT2"),
518 SND_SOC_DAPM_INPUT("LINPUT2"),
519 SND_SOC_DAPM_INPUT("RINPUT3"),
520 SND_SOC_DAPM_INPUT("LINPUT3"),
521 SND_SOC_DAPM_INPUT("AUX"),
522 
523 SND_SOC_DAPM_VMID("VMID"),
524 
525 /* Input */
526 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
527                    wm8900_linpga_controls,
528                    ARRAY_SIZE(wm8900_linpga_controls)),
529 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
530                    wm8900_rinpga_controls,
531                    ARRAY_SIZE(wm8900_rinpga_controls)),
532 
533 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
534                    wm8900_linmix_controls,
535                    ARRAY_SIZE(wm8900_linmix_controls)),
536 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
537                    wm8900_rinmix_controls,
538                    ARRAY_SIZE(wm8900_rinmix_controls)),
539 
540 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
541 
542 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
543 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
544 
545 /* Output */
546 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
547 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
548 
549 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
550                    wm8900_hp_event,
551                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
552                    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
553 
554 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
555 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
556 
557 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
558 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
559 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
560 
561 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
562                    wm8900_loutmix_controls,
563                    ARRAY_SIZE(wm8900_loutmix_controls)),
564 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
565                    wm8900_routmix_controls,
566                    ARRAY_SIZE(wm8900_routmix_controls)),
567 };
568 
569 /* Target, Path, Source */
570 static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
571 /* Inputs */
572 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
573 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
574 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
575 
576 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
577 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
578 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
579 
580 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
581 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
582 {"Left Input Mixer", "AUX Switch", "AUX"},
583 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
584 
585 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
586 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
587 {"Right Input Mixer", "AUX Switch", "AUX"},
588 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
589 
590 {"ADCL", NULL, "Left Input Mixer"},
591 {"ADCR", NULL, "Right Input Mixer"},
592 
593 /* Outputs */
594 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
595 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
596 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
597 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
598 
599 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
600 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
601 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
602 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
603 
604 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
605 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
606 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
607 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
608 
609 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
610 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
611 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
612 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
613 {"Left Output Mixer", "DACL Switch", "DACL"},
614 
615 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
616 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
617 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
618 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
619 {"Right Output Mixer", "DACR Switch", "DACR"},
620 
621 /* Note that the headphone output stage needs to be connected
622  * externally to LINEOUT2 via DC blocking capacitors.  Other
623  * configurations are not supported.
624  *
625  * Note also that left and right headphone paths are treated as a
626  * mono path.
627  */
628 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
629 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
630 {"HP_L", NULL, "Headphone Amplifier"},
631 {"HP_R", NULL, "Headphone Amplifier"},
632 };
633 
634 static int wm8900_hw_params(struct snd_pcm_substream *substream,
635         struct snd_pcm_hw_params *params,
636         struct snd_soc_dai *dai)
637 {
638         struct snd_soc_codec *codec = dai->codec;
639         u16 reg;
640 
641         reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
642 
643         switch (params_width(params)) {
644         case 16:
645                 break;
646         case 20:
647                 reg |= 0x20;
648                 break;
649         case 24:
650                 reg |= 0x40;
651                 break;
652         case 32:
653                 reg |= 0x60;
654                 break;
655         default:
656                 return -EINVAL;
657         }
658 
659         snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
660 
661         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
662                 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
663 
664                 if (params_rate(params) <= 24000)
665                         reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
666                 else
667                         reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
668 
669                 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
670         }
671 
672         return 0;
673 }
674 
675 /* FLL divisors */
676 struct _fll_div {
677         u16 fll_ratio;
678         u16 fllclk_div;
679         u16 fll_slow_lock_ref;
680         u16 n;
681         u16 k;
682 };
683 
684 /* The size in bits of the FLL divide multiplied by 10
685  * to allow rounding later */
686 #define FIXED_FLL_SIZE ((1 << 16) * 10)
687 
688 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
689                        unsigned int Fout)
690 {
691         u64 Kpart;
692         unsigned int K, Ndiv, Nmod, target;
693         unsigned int div;
694 
695         if (WARN_ON(!Fout))
696                 return -EINVAL;
697 
698         /* The FLL must run at 90-100MHz which is then scaled down to
699          * the output value by FLLCLK_DIV. */
700         target = Fout;
701         div = 1;
702         while (target < 90000000) {
703                 div *= 2;
704                 target *= 2;
705         }
706 
707         if (target > 100000000)
708                 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
709                        " Fout=%u\n", target, Fref, Fout);
710         if (div > 32) {
711                 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
712                        "Fref=%u, Fout=%u, target=%u\n",
713                        div, Fref, Fout, target);
714                 return -EINVAL;
715         }
716 
717         fll_div->fllclk_div = div >> 2;
718 
719         if (Fref < 48000)
720                 fll_div->fll_slow_lock_ref = 1;
721         else
722                 fll_div->fll_slow_lock_ref = 0;
723 
724         Ndiv = target / Fref;
725 
726         if (Fref < 1000000)
727                 fll_div->fll_ratio = 8;
728         else
729                 fll_div->fll_ratio = 1;
730 
731         fll_div->n = Ndiv / fll_div->fll_ratio;
732         Nmod = (target / fll_div->fll_ratio) % Fref;
733 
734         /* Calculate fractional part - scale up so we can round. */
735         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
736 
737         do_div(Kpart, Fref);
738 
739         K = Kpart & 0xFFFFFFFF;
740 
741         if ((K % 10) >= 5)
742                 K += 5;
743 
744         /* Move down to proper range now rounding is done */
745         fll_div->k = K / 10;
746 
747         if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
748             WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
749                 return -EINVAL;
750 
751         return 0;
752 }
753 
754 static int wm8900_set_fll(struct snd_soc_codec *codec,
755         int fll_id, unsigned int freq_in, unsigned int freq_out)
756 {
757         struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
758         struct _fll_div fll_div;
759 
760         if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
761                 return 0;
762 
763         /* The digital side should be disabled during any change. */
764         snd_soc_update_bits(codec, WM8900_REG_POWER1,
765                             WM8900_REG_POWER1_FLL_ENA, 0);
766 
767         /* Disable the FLL? */
768         if (!freq_in || !freq_out) {
769                 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
770                                     WM8900_REG_CLOCKING1_MCLK_SRC, 0);
771                 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
772                                     WM8900_REG_FLLCTL1_OSC_ENA, 0);
773                 wm8900->fll_in = freq_in;
774                 wm8900->fll_out = freq_out;
775 
776                 return 0;
777         }
778 
779         if (fll_factors(&fll_div, freq_in, freq_out) != 0)
780                 goto reenable;
781 
782         wm8900->fll_in = freq_in;
783         wm8900->fll_out = freq_out;
784 
785         /* The osclilator *MUST* be enabled before we enable the
786          * digital circuit. */
787         snd_soc_write(codec, WM8900_REG_FLLCTL1,
788                      fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
789 
790         snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
791         snd_soc_write(codec, WM8900_REG_FLLCTL5,
792                      (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
793 
794         if (fll_div.k) {
795                 snd_soc_write(codec, WM8900_REG_FLLCTL2,
796                              (fll_div.k >> 8) | 0x100);
797                 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
798         } else
799                 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
800 
801         if (fll_div.fll_slow_lock_ref)
802                 snd_soc_write(codec, WM8900_REG_FLLCTL6,
803                              WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
804         else
805                 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
806 
807         snd_soc_update_bits(codec, WM8900_REG_POWER1,
808                             WM8900_REG_POWER1_FLL_ENA,
809                             WM8900_REG_POWER1_FLL_ENA);
810 
811 reenable:
812         snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
813                             WM8900_REG_CLOCKING1_MCLK_SRC,
814                             WM8900_REG_CLOCKING1_MCLK_SRC);
815         return 0;
816 }
817 
818 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
819                 int source, unsigned int freq_in, unsigned int freq_out)
820 {
821         return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
822 }
823 
824 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
825                                  int div_id, int div)
826 {
827         struct snd_soc_codec *codec = codec_dai->codec;
828 
829         switch (div_id) {
830         case WM8900_BCLK_DIV:
831                 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
832                                     WM8900_REG_CLOCKING1_BCLK_MASK, div);
833                 break;
834         case WM8900_OPCLK_DIV:
835                 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
836                                     WM8900_REG_CLOCKING1_OPCLK_MASK, div);
837                 break;
838         case WM8900_DAC_LRCLK:
839                 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
840                                     WM8900_LRC_MASK, div);
841                 break;
842         case WM8900_ADC_LRCLK:
843                 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
844                                     WM8900_LRC_MASK, div);
845                 break;
846         case WM8900_DAC_CLKDIV:
847                 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
848                                     WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
849                 break;
850         case WM8900_ADC_CLKDIV:
851                 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
852                                     WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
853                 break;
854         case WM8900_LRCLK_MODE:
855                 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
856                                     WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
857                 break;
858         default:
859                 return -EINVAL;
860         }
861 
862         return 0;
863 }
864 
865 
866 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
867                               unsigned int fmt)
868 {
869         struct snd_soc_codec *codec = codec_dai->codec;
870         unsigned int clocking1, aif1, aif3, aif4;
871 
872         clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
873         aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
874         aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
875         aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
876 
877         /* set master/slave audio interface */
878         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
879         case SND_SOC_DAIFMT_CBS_CFS:
880                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
881                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
882                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
883                 break;
884         case SND_SOC_DAIFMT_CBS_CFM:
885                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
886                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
887                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
888                 break;
889         case SND_SOC_DAIFMT_CBM_CFM:
890                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
891                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
892                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
893                 break;
894         case SND_SOC_DAIFMT_CBM_CFS:
895                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
896                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
897                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
898                 break;
899         default:
900                 return -EINVAL;
901         }
902 
903         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
904         case SND_SOC_DAIFMT_DSP_A:
905                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
906                 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
907                 break;
908         case SND_SOC_DAIFMT_DSP_B:
909                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
910                 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
911                 break;
912         case SND_SOC_DAIFMT_I2S:
913                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
914                 aif1 |= 0x10;
915                 break;
916         case SND_SOC_DAIFMT_RIGHT_J:
917                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
918                 break;
919         case SND_SOC_DAIFMT_LEFT_J:
920                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
921                 aif1 |= 0x8;
922                 break;
923         default:
924                 return -EINVAL;
925         }
926 
927         /* Clock inversion */
928         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
929         case SND_SOC_DAIFMT_DSP_A:
930         case SND_SOC_DAIFMT_DSP_B:
931                 /* frame inversion not valid for DSP modes */
932                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
933                 case SND_SOC_DAIFMT_NB_NF:
934                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
935                         break;
936                 case SND_SOC_DAIFMT_IB_NF:
937                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
938                         break;
939                 default:
940                         return -EINVAL;
941                 }
942                 break;
943         case SND_SOC_DAIFMT_I2S:
944         case SND_SOC_DAIFMT_RIGHT_J:
945         case SND_SOC_DAIFMT_LEFT_J:
946                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
947                 case SND_SOC_DAIFMT_NB_NF:
948                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
949                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
950                         break;
951                 case SND_SOC_DAIFMT_IB_IF:
952                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
953                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
954                         break;
955                 case SND_SOC_DAIFMT_IB_NF:
956                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
957                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
958                         break;
959                 case SND_SOC_DAIFMT_NB_IF:
960                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
961                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
962                         break;
963                 default:
964                         return -EINVAL;
965                 }
966                 break;
967         default:
968                 return -EINVAL;
969         }
970 
971         snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
972         snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
973         snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
974         snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
975 
976         return 0;
977 }
978 
979 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
980 {
981         struct snd_soc_codec *codec = codec_dai->codec;
982         u16 reg;
983 
984         reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
985 
986         if (mute)
987                 reg |= WM8900_REG_DACCTRL_MUTE;
988         else
989                 reg &= ~WM8900_REG_DACCTRL_MUTE;
990 
991         snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
992 
993         return 0;
994 }
995 
996 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
997                       SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
998                       SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
999 
1000 #define WM8900_PCM_FORMATS \
1001         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1002          SNDRV_PCM_FMTBIT_S24_LE)
1003 
1004 static const struct snd_soc_dai_ops wm8900_dai_ops = {
1005         .hw_params      = wm8900_hw_params,
1006         .set_clkdiv     = wm8900_set_dai_clkdiv,
1007         .set_pll        = wm8900_set_dai_pll,
1008         .set_fmt        = wm8900_set_dai_fmt,
1009         .digital_mute   = wm8900_digital_mute,
1010 };
1011 
1012 static struct snd_soc_dai_driver wm8900_dai = {
1013         .name = "wm8900-hifi",
1014         .playback = {
1015                 .stream_name = "HiFi Playback",
1016                 .channels_min = 1,
1017                 .channels_max = 2,
1018                 .rates = WM8900_RATES,
1019                 .formats = WM8900_PCM_FORMATS,
1020         },
1021         .capture = {
1022                 .stream_name = "HiFi Capture",
1023                 .channels_min = 1,
1024                 .channels_max = 2,
1025                 .rates = WM8900_RATES,
1026                 .formats = WM8900_PCM_FORMATS,
1027          },
1028         .ops = &wm8900_dai_ops,
1029 };
1030 
1031 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1032                                  enum snd_soc_bias_level level)
1033 {
1034         u16 reg;
1035 
1036         switch (level) {
1037         case SND_SOC_BIAS_ON:
1038                 /* Enable thermal shutdown */
1039                 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1040                                     WM8900_REG_GPIO_TEMP_ENA,
1041                                     WM8900_REG_GPIO_TEMP_ENA);
1042                 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1043                                     WM8900_REG_ADDCTL_TEMP_SD,
1044                                     WM8900_REG_ADDCTL_TEMP_SD);
1045                 break;
1046 
1047         case SND_SOC_BIAS_PREPARE:
1048                 break;
1049 
1050         case SND_SOC_BIAS_STANDBY:
1051                 /* Charge capacitors if initial power up */
1052                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1053                         /* STARTUP_BIAS_ENA on */
1054                         snd_soc_write(codec, WM8900_REG_POWER1,
1055                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1056 
1057                         /* Startup bias mode */
1058                         snd_soc_write(codec, WM8900_REG_ADDCTL,
1059                                      WM8900_REG_ADDCTL_BIAS_SRC |
1060                                      WM8900_REG_ADDCTL_VMID_SOFTST);
1061 
1062                         /* VMID 2x50k */
1063                         snd_soc_write(codec, WM8900_REG_POWER1,
1064                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1065 
1066                         /* Allow capacitors to charge */
1067                         schedule_timeout_interruptible(msecs_to_jiffies(400));
1068 
1069                         /* Enable bias */
1070                         snd_soc_write(codec, WM8900_REG_POWER1,
1071                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1072                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1073 
1074                         snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1075 
1076                         snd_soc_write(codec, WM8900_REG_POWER1,
1077                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1078                 }
1079 
1080                 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1081                 snd_soc_write(codec, WM8900_REG_POWER1,
1082                              (reg & WM8900_REG_POWER1_FLL_ENA) |
1083                              WM8900_REG_POWER1_BIAS_ENA | 0x1);
1084                 snd_soc_write(codec, WM8900_REG_POWER2,
1085                              WM8900_REG_POWER2_SYSCLK_ENA);
1086                 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1087                 break;
1088 
1089         case SND_SOC_BIAS_OFF:
1090                 /* Startup bias enable */
1091                 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1092                 snd_soc_write(codec, WM8900_REG_POWER1,
1093                              reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1094                 snd_soc_write(codec, WM8900_REG_ADDCTL,
1095                              WM8900_REG_ADDCTL_BIAS_SRC |
1096                              WM8900_REG_ADDCTL_VMID_SOFTST);
1097 
1098                 /* Discharge caps */
1099                 snd_soc_write(codec, WM8900_REG_POWER1,
1100                              WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1101                 schedule_timeout_interruptible(msecs_to_jiffies(500));
1102 
1103                 /* Remove clamp */
1104                 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1105 
1106                 /* Power down */
1107                 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1108                 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1109                 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1110                 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1111 
1112                 /* Need to let things settle before stopping the clock
1113                  * to ensure that restart works, see "Stopping the
1114                  * master clock" in the datasheet. */
1115                 schedule_timeout_interruptible(msecs_to_jiffies(1));
1116                 snd_soc_write(codec, WM8900_REG_POWER2,
1117                              WM8900_REG_POWER2_SYSCLK_ENA);
1118                 break;
1119         }
1120         return 0;
1121 }
1122 
1123 static int wm8900_suspend(struct snd_soc_codec *codec)
1124 {
1125         struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1126         int fll_out = wm8900->fll_out;
1127         int fll_in  = wm8900->fll_in;
1128         int ret;
1129 
1130         /* Stop the FLL in an orderly fashion */
1131         ret = wm8900_set_fll(codec, 0, 0, 0);
1132         if (ret != 0) {
1133                 dev_err(codec->dev, "Failed to stop FLL\n");
1134                 return ret;
1135         }
1136 
1137         wm8900->fll_out = fll_out;
1138         wm8900->fll_in = fll_in;
1139 
1140         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1141 
1142         return 0;
1143 }
1144 
1145 static int wm8900_resume(struct snd_soc_codec *codec)
1146 {
1147         struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1148         int ret;
1149 
1150         wm8900_reset(codec);
1151 
1152         ret = regcache_sync(wm8900->regmap);
1153         if (ret != 0) {
1154                 dev_err(codec->dev, "Failed to restore cache: %d\n", ret);
1155                 return ret;
1156         }
1157 
1158         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1159 
1160         /* Restart the FLL? */
1161         if (wm8900->fll_out) {
1162                 int fll_out = wm8900->fll_out;
1163                 int fll_in  = wm8900->fll_in;
1164 
1165                 wm8900->fll_in = 0;
1166                 wm8900->fll_out = 0;
1167 
1168                 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1169                 if (ret != 0) {
1170                         dev_err(codec->dev, "Failed to restart FLL\n");
1171                         return ret;
1172                 }
1173         }
1174 
1175         return 0;
1176 }
1177 
1178 static int wm8900_probe(struct snd_soc_codec *codec)
1179 {
1180         int reg;
1181 
1182         reg = snd_soc_read(codec, WM8900_REG_ID);
1183         if (reg != 0x8900) {
1184                 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1185                 return -ENODEV;
1186         }
1187 
1188         wm8900_reset(codec);
1189 
1190         /* Turn the chip on */
1191         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1192 
1193         /* Latch the volume update bits */
1194         snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1195         snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1196         snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1197         snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1198         snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1199         snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1200         snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1201         snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1202         snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1203         snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
1204 
1205         /* Set the DAC and mixer output bias */
1206         snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1207 
1208         return 0;
1209 }
1210 
1211 static const struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1212         .probe =        wm8900_probe,
1213         .suspend =      wm8900_suspend,
1214         .resume =       wm8900_resume,
1215         .set_bias_level = wm8900_set_bias_level,
1216 
1217         .component_driver = {
1218                 .controls               = wm8900_snd_controls,
1219                 .num_controls           = ARRAY_SIZE(wm8900_snd_controls),
1220                 .dapm_widgets           = wm8900_dapm_widgets,
1221                 .num_dapm_widgets       = ARRAY_SIZE(wm8900_dapm_widgets),
1222                 .dapm_routes            = wm8900_dapm_routes,
1223                 .num_dapm_routes        = ARRAY_SIZE(wm8900_dapm_routes),
1224         },
1225 };
1226 
1227 static const struct regmap_config wm8900_regmap = {
1228         .reg_bits = 8,
1229         .val_bits = 16,
1230         .max_register = WM8900_MAXREG,
1231 
1232         .reg_defaults = wm8900_reg_defaults,
1233         .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1234         .cache_type = REGCACHE_RBTREE,
1235 
1236         .volatile_reg = wm8900_volatile_register,
1237 };
1238 
1239 #if defined(CONFIG_SPI_MASTER)
1240 static int wm8900_spi_probe(struct spi_device *spi)
1241 {
1242         struct wm8900_priv *wm8900;
1243         int ret;
1244 
1245         wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1246                               GFP_KERNEL);
1247         if (wm8900 == NULL)
1248                 return -ENOMEM;
1249 
1250         wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1251         if (IS_ERR(wm8900->regmap))
1252                 return PTR_ERR(wm8900->regmap);
1253 
1254         spi_set_drvdata(spi, wm8900);
1255 
1256         ret = snd_soc_register_codec(&spi->dev,
1257                         &soc_codec_dev_wm8900, &wm8900_dai, 1);
1258 
1259         return ret;
1260 }
1261 
1262 static int wm8900_spi_remove(struct spi_device *spi)
1263 {
1264         snd_soc_unregister_codec(&spi->dev);
1265         return 0;
1266 }
1267 
1268 static struct spi_driver wm8900_spi_driver = {
1269         .driver = {
1270                 .name   = "wm8900",
1271         },
1272         .probe          = wm8900_spi_probe,
1273         .remove         = wm8900_spi_remove,
1274 };
1275 #endif /* CONFIG_SPI_MASTER */
1276 
1277 #if IS_ENABLED(CONFIG_I2C)
1278 static int wm8900_i2c_probe(struct i2c_client *i2c,
1279                             const struct i2c_device_id *id)
1280 {
1281         struct wm8900_priv *wm8900;
1282         int ret;
1283 
1284         wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1285                               GFP_KERNEL);
1286         if (wm8900 == NULL)
1287                 return -ENOMEM;
1288 
1289         wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1290         if (IS_ERR(wm8900->regmap))
1291                 return PTR_ERR(wm8900->regmap);
1292 
1293         i2c_set_clientdata(i2c, wm8900);
1294 
1295         ret =  snd_soc_register_codec(&i2c->dev,
1296                         &soc_codec_dev_wm8900, &wm8900_dai, 1);
1297 
1298         return ret;
1299 }
1300 
1301 static int wm8900_i2c_remove(struct i2c_client *client)
1302 {
1303         snd_soc_unregister_codec(&client->dev);
1304         return 0;
1305 }
1306 
1307 static const struct i2c_device_id wm8900_i2c_id[] = {
1308         { "wm8900", 0 },
1309         { }
1310 };
1311 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1312 
1313 static struct i2c_driver wm8900_i2c_driver = {
1314         .driver = {
1315                 .name = "wm8900",
1316         },
1317         .probe =    wm8900_i2c_probe,
1318         .remove =   wm8900_i2c_remove,
1319         .id_table = wm8900_i2c_id,
1320 };
1321 #endif
1322 
1323 static int __init wm8900_modinit(void)
1324 {
1325         int ret = 0;
1326 #if IS_ENABLED(CONFIG_I2C)
1327         ret = i2c_add_driver(&wm8900_i2c_driver);
1328         if (ret != 0) {
1329                 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1330                        ret);
1331         }
1332 #endif
1333 #if defined(CONFIG_SPI_MASTER)
1334         ret = spi_register_driver(&wm8900_spi_driver);
1335         if (ret != 0) {
1336                 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1337                        ret);
1338         }
1339 #endif
1340         return ret;
1341 }
1342 module_init(wm8900_modinit);
1343 
1344 static void __exit wm8900_exit(void)
1345 {
1346 #if IS_ENABLED(CONFIG_I2C)
1347         i2c_del_driver(&wm8900_i2c_driver);
1348 #endif
1349 #if defined(CONFIG_SPI_MASTER)
1350         spi_unregister_driver(&wm8900_spi_driver);
1351 #endif
1352 }
1353 module_exit(wm8900_exit);
1354 
1355 MODULE_DESCRIPTION("ASoC WM8900 driver");
1356 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1357 MODULE_LICENSE("GPL");
1358 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp