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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/wm8990.c

Version: ~ [ linux-5.4-rc7 ] ~ [ linux-5.3.10 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.83 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.153 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.200 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.200 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.76 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * wm8990.c  --  WM8990 ALSA Soc Audio driver
  3  *
  4  * Copyright 2008 Wolfson Microelectronics PLC.
  5  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
  6  *
  7  *  This program is free software; you can redistribute  it and/or modify it
  8  *  under  the terms of  the GNU General  Public License as published by the
  9  *  Free Software Foundation;  either version 2 of the  License, or (at your
 10  *  option) any later version.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/kernel.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/i2c.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/slab.h>
 22 #include <sound/core.h>
 23 #include <sound/pcm.h>
 24 #include <sound/pcm_params.h>
 25 #include <sound/soc.h>
 26 #include <sound/initval.h>
 27 #include <sound/tlv.h>
 28 #include <asm/div64.h>
 29 
 30 #include "wm8990.h"
 31 
 32 /* codec private data */
 33 struct wm8990_priv {
 34         enum snd_soc_control_type control_type;
 35         unsigned int sysclk;
 36         unsigned int pcmclk;
 37 };
 38 
 39 static int wm8990_volatile_register(struct snd_soc_codec *codec,
 40                                     unsigned int reg)
 41 {
 42         switch (reg) {
 43         case WM8990_RESET:
 44                 return 1;
 45         default:
 46                 return 0;
 47         }
 48 }
 49 
 50 static const u16 wm8990_reg[] = {
 51         0x8990,     /* R0  - Reset */
 52         0x0000,     /* R1  - Power Management (1) */
 53         0x6000,     /* R2  - Power Management (2) */
 54         0x0000,     /* R3  - Power Management (3) */
 55         0x4050,     /* R4  - Audio Interface (1) */
 56         0x4000,     /* R5  - Audio Interface (2) */
 57         0x01C8,     /* R6  - Clocking (1) */
 58         0x0000,     /* R7  - Clocking (2) */
 59         0x0040,     /* R8  - Audio Interface (3) */
 60         0x0040,     /* R9  - Audio Interface (4) */
 61         0x0004,     /* R10 - DAC CTRL */
 62         0x00C0,     /* R11 - Left DAC Digital Volume */
 63         0x00C0,     /* R12 - Right DAC Digital Volume */
 64         0x0000,     /* R13 - Digital Side Tone */
 65         0x0100,     /* R14 - ADC CTRL */
 66         0x00C0,     /* R15 - Left ADC Digital Volume */
 67         0x00C0,     /* R16 - Right ADC Digital Volume */
 68         0x0000,     /* R17 */
 69         0x0000,     /* R18 - GPIO CTRL 1 */
 70         0x1000,     /* R19 - GPIO1 & GPIO2 */
 71         0x1010,     /* R20 - GPIO3 & GPIO4 */
 72         0x1010,     /* R21 - GPIO5 & GPIO6 */
 73         0x8000,     /* R22 - GPIOCTRL 2 */
 74         0x0800,     /* R23 - GPIO_POL */
 75         0x008B,     /* R24 - Left Line Input 1&2 Volume */
 76         0x008B,     /* R25 - Left Line Input 3&4 Volume */
 77         0x008B,     /* R26 - Right Line Input 1&2 Volume */
 78         0x008B,     /* R27 - Right Line Input 3&4 Volume */
 79         0x0000,     /* R28 - Left Output Volume */
 80         0x0000,     /* R29 - Right Output Volume */
 81         0x0066,     /* R30 - Line Outputs Volume */
 82         0x0022,     /* R31 - Out3/4 Volume */
 83         0x0079,     /* R32 - Left OPGA Volume */
 84         0x0079,     /* R33 - Right OPGA Volume */
 85         0x0003,     /* R34 - Speaker Volume */
 86         0x0003,     /* R35 - ClassD1 */
 87         0x0000,     /* R36 */
 88         0x0100,     /* R37 - ClassD3 */
 89         0x0079,     /* R38 - ClassD4 */
 90         0x0000,     /* R39 - Input Mixer1 */
 91         0x0000,     /* R40 - Input Mixer2 */
 92         0x0000,     /* R41 - Input Mixer3 */
 93         0x0000,     /* R42 - Input Mixer4 */
 94         0x0000,     /* R43 - Input Mixer5 */
 95         0x0000,     /* R44 - Input Mixer6 */
 96         0x0000,     /* R45 - Output Mixer1 */
 97         0x0000,     /* R46 - Output Mixer2 */
 98         0x0000,     /* R47 - Output Mixer3 */
 99         0x0000,     /* R48 - Output Mixer4 */
100         0x0000,     /* R49 - Output Mixer5 */
101         0x0000,     /* R50 - Output Mixer6 */
102         0x0180,     /* R51 - Out3/4 Mixer */
103         0x0000,     /* R52 - Line Mixer1 */
104         0x0000,     /* R53 - Line Mixer2 */
105         0x0000,     /* R54 - Speaker Mixer */
106         0x0000,     /* R55 - Additional Control */
107         0x0000,     /* R56 - AntiPOP1 */
108         0x0000,     /* R57 - AntiPOP2 */
109         0x0000,     /* R58 - MICBIAS */
110         0x0000,     /* R59 */
111         0x0008,     /* R60 - PLL1 */
112         0x0031,     /* R61 - PLL2 */
113         0x0026,     /* R62 - PLL3 */
114         0x0000,     /* R63 - Driver internal */
115 };
116 
117 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
118 
119 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
120 
121 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
122 
123 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
124 
125 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
126 
127 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
128 
129 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
130 
131 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
132 
133 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
134 
135 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
136         struct snd_ctl_elem_value *ucontrol)
137 {
138         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
139         struct soc_mixer_control *mc =
140                 (struct soc_mixer_control *)kcontrol->private_value;
141         int reg = mc->reg;
142         int ret;
143         u16 val;
144 
145         ret = snd_soc_put_volsw(kcontrol, ucontrol);
146         if (ret < 0)
147                 return ret;
148 
149         /* now hit the volume update bits (always bit 8) */
150         val = snd_soc_read(codec, reg);
151         return snd_soc_write(codec, reg, val | 0x0100);
152 }
153 
154 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
155          tlv_array) {\
156         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
157         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
158                   SNDRV_CTL_ELEM_ACCESS_READWRITE,\
159         .tlv.p = (tlv_array), \
160         .info = snd_soc_info_volsw, \
161         .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
162         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
163 
164 
165 static const char *wm8990_digital_sidetone[] =
166         {"None", "Left ADC", "Right ADC", "Reserved"};
167 
168 static const struct soc_enum wm8990_left_digital_sidetone_enum =
169 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
170         WM8990_ADC_TO_DACL_SHIFT,
171         WM8990_ADC_TO_DACL_MASK,
172         wm8990_digital_sidetone);
173 
174 static const struct soc_enum wm8990_right_digital_sidetone_enum =
175 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
176         WM8990_ADC_TO_DACR_SHIFT,
177         WM8990_ADC_TO_DACR_MASK,
178         wm8990_digital_sidetone);
179 
180 static const char *wm8990_adcmode[] =
181         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
182 
183 static const struct soc_enum wm8990_right_adcmode_enum =
184 SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
185         WM8990_ADC_HPF_CUT_SHIFT,
186         WM8990_ADC_HPF_CUT_MASK,
187         wm8990_adcmode);
188 
189 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
190 /* INMIXL */
191 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
192 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
193 /* INMIXR */
194 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
195 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
196 
197 /* LOMIX */
198 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
199         WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
200 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
201         WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
202 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
203         WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
204 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
205         WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
206 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
207         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
208 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
209         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
210 
211 /* ROMIX */
212 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
213         WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
214 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
215         WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
216 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
217         WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
218 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
219         WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
220 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
221         WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
222 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
223         WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
224 
225 /* LOUT */
226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
227         WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
228 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
229 
230 /* ROUT */
231 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
232         WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
233 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
234 
235 /* LOPGA */
236 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
237         WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
238 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
239         WM8990_LOPGAZC_BIT, 1, 0),
240 
241 /* ROPGA */
242 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
243         WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
244 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
245         WM8990_ROPGAZC_BIT, 1, 0),
246 
247 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
248         WM8990_LONMUTE_BIT, 1, 0),
249 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
250         WM8990_LOPMUTE_BIT, 1, 0),
251 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
252         WM8990_LOATTN_BIT, 1, 0),
253 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
254         WM8990_RONMUTE_BIT, 1, 0),
255 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
256         WM8990_ROPMUTE_BIT, 1, 0),
257 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
258         WM8990_ROATTN_BIT, 1, 0),
259 
260 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
261         WM8990_OUT3MUTE_BIT, 1, 0),
262 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
263         WM8990_OUT3ATTN_BIT, 1, 0),
264 
265 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
266         WM8990_OUT4MUTE_BIT, 1, 0),
267 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
268         WM8990_OUT4ATTN_BIT, 1, 0),
269 
270 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
271         WM8990_CDMODE_BIT, 1, 0),
272 
273 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
274         WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
275 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
276         WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
277 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
278         WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
279 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
280         WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
281 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
282         WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
283 
284 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
285         WM8990_LEFT_DAC_DIGITAL_VOLUME,
286         WM8990_DACL_VOL_SHIFT,
287         WM8990_DACL_VOL_MASK,
288         0,
289         out_dac_tlv),
290 
291 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
292         WM8990_RIGHT_DAC_DIGITAL_VOLUME,
293         WM8990_DACR_VOL_SHIFT,
294         WM8990_DACR_VOL_MASK,
295         0,
296         out_dac_tlv),
297 
298 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
299 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
300 
301 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
302         WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
303         out_sidetone_tlv),
304 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
305         WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
306         out_sidetone_tlv),
307 
308 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
309         WM8990_ADC_HPF_ENA_BIT, 1, 0),
310 
311 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
312 
313 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
314         WM8990_LEFT_ADC_DIGITAL_VOLUME,
315         WM8990_ADCL_VOL_SHIFT,
316         WM8990_ADCL_VOL_MASK,
317         0,
318         in_adc_tlv),
319 
320 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
321         WM8990_RIGHT_ADC_DIGITAL_VOLUME,
322         WM8990_ADCR_VOL_SHIFT,
323         WM8990_ADCR_VOL_MASK,
324         0,
325         in_adc_tlv),
326 
327 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
328         WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
329         WM8990_LIN12VOL_SHIFT,
330         WM8990_LIN12VOL_MASK,
331         0,
332         in_pga_tlv),
333 
334 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
335         WM8990_LI12ZC_BIT, 1, 0),
336 
337 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
338         WM8990_LI12MUTE_BIT, 1, 0),
339 
340 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
341         WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
342         WM8990_LIN34VOL_SHIFT,
343         WM8990_LIN34VOL_MASK,
344         0,
345         in_pga_tlv),
346 
347 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
348         WM8990_LI34ZC_BIT, 1, 0),
349 
350 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
351         WM8990_LI34MUTE_BIT, 1, 0),
352 
353 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
354         WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
355         WM8990_RIN12VOL_SHIFT,
356         WM8990_RIN12VOL_MASK,
357         0,
358         in_pga_tlv),
359 
360 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
361         WM8990_RI12ZC_BIT, 1, 0),
362 
363 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
364         WM8990_RI12MUTE_BIT, 1, 0),
365 
366 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
367         WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
368         WM8990_RIN34VOL_SHIFT,
369         WM8990_RIN34VOL_MASK,
370         0,
371         in_pga_tlv),
372 
373 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
374         WM8990_RI34ZC_BIT, 1, 0),
375 
376 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
377         WM8990_RI34MUTE_BIT, 1, 0),
378 
379 };
380 
381 /*
382  * _DAPM_ Controls
383  */
384 
385 static int inmixer_event(struct snd_soc_dapm_widget *w,
386         struct snd_kcontrol *kcontrol, int event)
387 {
388         u16 reg, fakepower;
389 
390         reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
391         fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
392 
393         if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
394                 (1 << WM8990_AINLMUX_PWR_BIT))) {
395                 reg |= WM8990_AINL_ENA;
396         } else {
397                 reg &= ~WM8990_AINL_ENA;
398         }
399 
400         if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
401                 (1 << WM8990_AINRMUX_PWR_BIT))) {
402                 reg |= WM8990_AINR_ENA;
403         } else {
404                 reg &= ~WM8990_AINR_ENA;
405         }
406         snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
407 
408         return 0;
409 }
410 
411 static int outmixer_event(struct snd_soc_dapm_widget *w,
412         struct snd_kcontrol *kcontrol, int event)
413 {
414         u32 reg_shift = kcontrol->private_value & 0xfff;
415         int ret = 0;
416         u16 reg;
417 
418         switch (reg_shift) {
419         case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
420                 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
421                 if (reg & WM8990_LDLO) {
422                         printk(KERN_WARNING
423                         "Cannot set as Output Mixer 1 LDLO Set\n");
424                         ret = -1;
425                 }
426                 break;
427         case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
428                 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
429                 if (reg & WM8990_RDRO) {
430                         printk(KERN_WARNING
431                         "Cannot set as Output Mixer 2 RDRO Set\n");
432                         ret = -1;
433                 }
434                 break;
435         case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
436                 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
437                 if (reg & WM8990_LDSPK) {
438                         printk(KERN_WARNING
439                         "Cannot set as Speaker Mixer LDSPK Set\n");
440                         ret = -1;
441                 }
442                 break;
443         case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
444                 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
445                 if (reg & WM8990_RDSPK) {
446                         printk(KERN_WARNING
447                         "Cannot set as Speaker Mixer RDSPK Set\n");
448                         ret = -1;
449                 }
450                 break;
451         }
452 
453         return ret;
454 }
455 
456 /* INMIX dB values */
457 static const unsigned int in_mix_tlv[] = {
458         TLV_DB_RANGE_HEAD(1),
459         0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
460 };
461 
462 /* Left In PGA Connections */
463 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
464 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
465 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
466 };
467 
468 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
469 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
470 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
471 };
472 
473 /* Right In PGA Connections */
474 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
475 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
476 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
477 };
478 
479 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
480 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
481 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
482 };
483 
484 /* INMIXL */
485 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
486 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
487         WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
488 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
489         7, 0, in_mix_tlv),
490 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
491         1, 0),
492 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
493         1, 0),
494 };
495 
496 /* INMIXR */
497 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
498 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
499         WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
500 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
501         7, 0, in_mix_tlv),
502 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
503         1, 0),
504 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
505         1, 0),
506 };
507 
508 /* AINLMUX */
509 static const char *wm8990_ainlmux[] =
510         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
511 
512 static const struct soc_enum wm8990_ainlmux_enum =
513 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
514         ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
515 
516 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
517 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
518 
519 /* DIFFINL */
520 
521 /* AINRMUX */
522 static const char *wm8990_ainrmux[] =
523         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
524 
525 static const struct soc_enum wm8990_ainrmux_enum =
526 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
527         ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
528 
529 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
530 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
531 
532 /* RXVOICE */
533 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
534 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
535                         WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
536 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
537                         WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
538 };
539 
540 /* LOMIX */
541 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
542 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
543         WM8990_LRBLO_BIT, 1, 0),
544 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
545         WM8990_LLBLO_BIT, 1, 0),
546 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
547         WM8990_LRI3LO_BIT, 1, 0),
548 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
549         WM8990_LLI3LO_BIT, 1, 0),
550 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
551         WM8990_LR12LO_BIT, 1, 0),
552 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
553         WM8990_LL12LO_BIT, 1, 0),
554 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
555         WM8990_LDLO_BIT, 1, 0),
556 };
557 
558 /* ROMIX */
559 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
560 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
561         WM8990_RLBRO_BIT, 1, 0),
562 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
563         WM8990_RRBRO_BIT, 1, 0),
564 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
565         WM8990_RLI3RO_BIT, 1, 0),
566 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
567         WM8990_RRI3RO_BIT, 1, 0),
568 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
569         WM8990_RL12RO_BIT, 1, 0),
570 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
571         WM8990_RR12RO_BIT, 1, 0),
572 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
573         WM8990_RDRO_BIT, 1, 0),
574 };
575 
576 /* LONMIX */
577 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
578 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
579         WM8990_LLOPGALON_BIT, 1, 0),
580 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
581         WM8990_LROPGALON_BIT, 1, 0),
582 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
583         WM8990_LOPLON_BIT, 1, 0),
584 };
585 
586 /* LOPMIX */
587 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
588 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
589         WM8990_LR12LOP_BIT, 1, 0),
590 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
591         WM8990_LL12LOP_BIT, 1, 0),
592 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
593         WM8990_LLOPGALOP_BIT, 1, 0),
594 };
595 
596 /* RONMIX */
597 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
598 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
599         WM8990_RROPGARON_BIT, 1, 0),
600 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
601         WM8990_RLOPGARON_BIT, 1, 0),
602 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
603         WM8990_ROPRON_BIT, 1, 0),
604 };
605 
606 /* ROPMIX */
607 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
608 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
609         WM8990_RL12ROP_BIT, 1, 0),
610 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
611         WM8990_RR12ROP_BIT, 1, 0),
612 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
613         WM8990_RROPGAROP_BIT, 1, 0),
614 };
615 
616 /* OUT3MIX */
617 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
618 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
619         WM8990_LI4O3_BIT, 1, 0),
620 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
621         WM8990_LPGAO3_BIT, 1, 0),
622 };
623 
624 /* OUT4MIX */
625 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
626 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
627         WM8990_RPGAO4_BIT, 1, 0),
628 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
629         WM8990_RI4O4_BIT, 1, 0),
630 };
631 
632 /* SPKMIX */
633 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
634 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
635         WM8990_LI2SPK_BIT, 1, 0),
636 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
637         WM8990_LB2SPK_BIT, 1, 0),
638 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
639         WM8990_LOPGASPK_BIT, 1, 0),
640 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
641         WM8990_LDSPK_BIT, 1, 0),
642 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
643         WM8990_RDSPK_BIT, 1, 0),
644 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
645         WM8990_ROPGASPK_BIT, 1, 0),
646 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
647         WM8990_RL12ROP_BIT, 1, 0),
648 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
649         WM8990_RI2SPK_BIT, 1, 0),
650 };
651 
652 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
653 /* Input Side */
654 /* Input Lines */
655 SND_SOC_DAPM_INPUT("LIN1"),
656 SND_SOC_DAPM_INPUT("LIN2"),
657 SND_SOC_DAPM_INPUT("LIN3"),
658 SND_SOC_DAPM_INPUT("LIN4/RXN"),
659 SND_SOC_DAPM_INPUT("RIN3"),
660 SND_SOC_DAPM_INPUT("RIN4/RXP"),
661 SND_SOC_DAPM_INPUT("RIN1"),
662 SND_SOC_DAPM_INPUT("RIN2"),
663 SND_SOC_DAPM_INPUT("Internal ADC Source"),
664 
665 /* DACs */
666 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
667         WM8990_ADCL_ENA_BIT, 0),
668 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
669         WM8990_ADCR_ENA_BIT, 0),
670 
671 /* Input PGAs */
672 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
673         0, &wm8990_dapm_lin12_pga_controls[0],
674         ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
675 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
676         0, &wm8990_dapm_lin34_pga_controls[0],
677         ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
678 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
679         0, &wm8990_dapm_rin12_pga_controls[0],
680         ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
681 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
682         0, &wm8990_dapm_rin34_pga_controls[0],
683         ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
684 
685 /* INMIXL */
686 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
687         &wm8990_dapm_inmixl_controls[0],
688         ARRAY_SIZE(wm8990_dapm_inmixl_controls),
689         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
690 
691 /* AINLMUX */
692 SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
693         &wm8990_dapm_ainlmux_controls, inmixer_event,
694         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
695 
696 /* INMIXR */
697 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
698         &wm8990_dapm_inmixr_controls[0],
699         ARRAY_SIZE(wm8990_dapm_inmixr_controls),
700         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
701 
702 /* AINRMUX */
703 SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
704         &wm8990_dapm_ainrmux_controls, inmixer_event,
705         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
706 
707 /* Output Side */
708 /* DACs */
709 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
710         WM8990_DACL_ENA_BIT, 0),
711 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
712         WM8990_DACR_ENA_BIT, 0),
713 
714 /* LOMIX */
715 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
716         0, &wm8990_dapm_lomix_controls[0],
717         ARRAY_SIZE(wm8990_dapm_lomix_controls),
718         outmixer_event, SND_SOC_DAPM_PRE_REG),
719 
720 /* LONMIX */
721 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
722         &wm8990_dapm_lonmix_controls[0],
723         ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
724 
725 /* LOPMIX */
726 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
727         &wm8990_dapm_lopmix_controls[0],
728         ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
729 
730 /* OUT3MIX */
731 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
732         &wm8990_dapm_out3mix_controls[0],
733         ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
734 
735 /* SPKMIX */
736 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
737         &wm8990_dapm_spkmix_controls[0],
738         ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
739         SND_SOC_DAPM_PRE_REG),
740 
741 /* OUT4MIX */
742 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
743         &wm8990_dapm_out4mix_controls[0],
744         ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
745 
746 /* ROPMIX */
747 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
748         &wm8990_dapm_ropmix_controls[0],
749         ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
750 
751 /* RONMIX */
752 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
753         &wm8990_dapm_ronmix_controls[0],
754         ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
755 
756 /* ROMIX */
757 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
758         0, &wm8990_dapm_romix_controls[0],
759         ARRAY_SIZE(wm8990_dapm_romix_controls),
760         outmixer_event, SND_SOC_DAPM_PRE_REG),
761 
762 /* LOUT PGA */
763 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
764         NULL, 0),
765 
766 /* ROUT PGA */
767 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
768         NULL, 0),
769 
770 /* LOPGA */
771 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
772         NULL, 0),
773 
774 /* ROPGA */
775 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
776         NULL, 0),
777 
778 /* MICBIAS */
779 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
780         WM8990_MICBIAS_ENA_BIT, 0),
781 
782 SND_SOC_DAPM_OUTPUT("LON"),
783 SND_SOC_DAPM_OUTPUT("LOP"),
784 SND_SOC_DAPM_OUTPUT("OUT3"),
785 SND_SOC_DAPM_OUTPUT("LOUT"),
786 SND_SOC_DAPM_OUTPUT("SPKN"),
787 SND_SOC_DAPM_OUTPUT("SPKP"),
788 SND_SOC_DAPM_OUTPUT("ROUT"),
789 SND_SOC_DAPM_OUTPUT("OUT4"),
790 SND_SOC_DAPM_OUTPUT("ROP"),
791 SND_SOC_DAPM_OUTPUT("RON"),
792 
793 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
794 };
795 
796 static const struct snd_soc_dapm_route audio_map[] = {
797         /* Make DACs turn on when playing even if not mixed into any outputs */
798         {"Internal DAC Sink", NULL, "Left DAC"},
799         {"Internal DAC Sink", NULL, "Right DAC"},
800 
801         /* Make ADCs turn on when recording even if not mixed from any inputs */
802         {"Left ADC", NULL, "Internal ADC Source"},
803         {"Right ADC", NULL, "Internal ADC Source"},
804 
805         /* Input Side */
806         /* LIN12 PGA */
807         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
808         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
809         /* LIN34 PGA */
810         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
811         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
812         /* INMIXL */
813         {"INMIXL", "Record Left Volume", "LOMIX"},
814         {"INMIXL", "LIN2 Volume", "LIN2"},
815         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
816         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
817         /* AINLMUX */
818         {"AINLMUX", "INMIXL Mix", "INMIXL"},
819         {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
820         {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
821         {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
822         {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
823         /* ADC */
824         {"Left ADC", NULL, "AINLMUX"},
825 
826         /* RIN12 PGA */
827         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
828         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
829         /* RIN34 PGA */
830         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
831         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
832         /* INMIXL */
833         {"INMIXR", "Record Right Volume", "ROMIX"},
834         {"INMIXR", "RIN2 Volume", "RIN2"},
835         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
836         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
837         /* AINRMUX */
838         {"AINRMUX", "INMIXR Mix", "INMIXR"},
839         {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
840         {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
841         {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
842         {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
843         /* ADC */
844         {"Right ADC", NULL, "AINRMUX"},
845 
846         /* LOMIX */
847         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
848         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
849         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
850         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
851         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
852         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
853         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
854 
855         /* ROMIX */
856         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
857         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
858         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
859         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
860         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
861         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
862         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
863 
864         /* SPKMIX */
865         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
866         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
867         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
868         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
869         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
870         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
871         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
872         {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
873 
874         /* LONMIX */
875         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
876         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
877         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
878 
879         /* LOPMIX */
880         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
881         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
882         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
883 
884         /* OUT3MIX */
885         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
886         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
887 
888         /* OUT4MIX */
889         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
890         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
891 
892         /* RONMIX */
893         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
894         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
895         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
896 
897         /* ROPMIX */
898         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
899         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
900         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
901 
902         /* Out Mixer PGAs */
903         {"LOPGA", NULL, "LOMIX"},
904         {"ROPGA", NULL, "ROMIX"},
905 
906         {"LOUT PGA", NULL, "LOMIX"},
907         {"ROUT PGA", NULL, "ROMIX"},
908 
909         /* Output Pins */
910         {"LON", NULL, "LONMIX"},
911         {"LOP", NULL, "LOPMIX"},
912         {"OUT3", NULL, "OUT3MIX"},
913         {"LOUT", NULL, "LOUT PGA"},
914         {"SPKN", NULL, "SPKMIX"},
915         {"ROUT", NULL, "ROUT PGA"},
916         {"OUT4", NULL, "OUT4MIX"},
917         {"ROP", NULL, "ROPMIX"},
918         {"RON", NULL, "RONMIX"},
919 };
920 
921 static int wm8990_add_widgets(struct snd_soc_codec *codec)
922 {
923         struct snd_soc_dapm_context *dapm = &codec->dapm;
924 
925         snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets,
926                                   ARRAY_SIZE(wm8990_dapm_widgets));
927         /* set up the WM8990 audio map */
928         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
929 
930         return 0;
931 }
932 
933 /* PLL divisors */
934 struct _pll_div {
935         u32 div2;
936         u32 n;
937         u32 k;
938 };
939 
940 /* The size in bits of the pll divide multiplied by 10
941  * to allow rounding later */
942 #define FIXED_PLL_SIZE ((1 << 16) * 10)
943 
944 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
945         unsigned int source)
946 {
947         u64 Kpart;
948         unsigned int K, Ndiv, Nmod;
949 
950 
951         Ndiv = target / source;
952         if (Ndiv < 6) {
953                 source >>= 1;
954                 pll_div->div2 = 1;
955                 Ndiv = target / source;
956         } else
957                 pll_div->div2 = 0;
958 
959         if ((Ndiv < 6) || (Ndiv > 12))
960                 printk(KERN_WARNING
961                 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
962 
963         pll_div->n = Ndiv;
964         Nmod = target % source;
965         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
966 
967         do_div(Kpart, source);
968 
969         K = Kpart & 0xFFFFFFFF;
970 
971         /* Check if we need to round */
972         if ((K % 10) >= 5)
973                 K += 5;
974 
975         /* Move down to proper range now rounding is done */
976         K /= 10;
977 
978         pll_div->k = K;
979 }
980 
981 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
982                 int source, unsigned int freq_in, unsigned int freq_out)
983 {
984         struct snd_soc_codec *codec = codec_dai->codec;
985         struct _pll_div pll_div;
986 
987         if (freq_in && freq_out) {
988                 pll_factors(&pll_div, freq_out * 4, freq_in);
989 
990                 /* Turn on PLL */
991                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
992                                     WM8990_PLL_ENA, WM8990_PLL_ENA);
993 
994                 /* sysclk comes from PLL */
995                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
996                                     WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
997 
998                 /* set up N , fractional mode and pre-divisor if necessary */
999                 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1000                         (pll_div.div2?WM8990_PRESCALE:0));
1001                 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1002                 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1003         } else {
1004                 /* Turn off PLL */
1005                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1006                                     WM8990_PLL_ENA, 0);
1007         }
1008         return 0;
1009 }
1010 
1011 /*
1012  * Clock after PLL and dividers
1013  */
1014 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1015                 int clk_id, unsigned int freq, int dir)
1016 {
1017         struct snd_soc_codec *codec = codec_dai->codec;
1018         struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1019 
1020         wm8990->sysclk = freq;
1021         return 0;
1022 }
1023 
1024 /*
1025  * Set's ADC and Voice DAC format.
1026  */
1027 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1028                 unsigned int fmt)
1029 {
1030         struct snd_soc_codec *codec = codec_dai->codec;
1031         u16 audio1, audio3;
1032 
1033         audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1034         audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
1035 
1036         /* set master/slave audio interface */
1037         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1038         case SND_SOC_DAIFMT_CBS_CFS:
1039                 audio3 &= ~WM8990_AIF_MSTR1;
1040                 break;
1041         case SND_SOC_DAIFMT_CBM_CFM:
1042                 audio3 |= WM8990_AIF_MSTR1;
1043                 break;
1044         default:
1045                 return -EINVAL;
1046         }
1047 
1048         audio1 &= ~WM8990_AIF_FMT_MASK;
1049 
1050         /* interface format */
1051         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1052         case SND_SOC_DAIFMT_I2S:
1053                 audio1 |= WM8990_AIF_TMF_I2S;
1054                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1055                 break;
1056         case SND_SOC_DAIFMT_RIGHT_J:
1057                 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1058                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1059                 break;
1060         case SND_SOC_DAIFMT_LEFT_J:
1061                 audio1 |= WM8990_AIF_TMF_LEFTJ;
1062                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1063                 break;
1064         case SND_SOC_DAIFMT_DSP_A:
1065                 audio1 |= WM8990_AIF_TMF_DSP;
1066                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1067                 break;
1068         case SND_SOC_DAIFMT_DSP_B:
1069                 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1070                 break;
1071         default:
1072                 return -EINVAL;
1073         }
1074 
1075         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1076         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1077         return 0;
1078 }
1079 
1080 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1081                 int div_id, int div)
1082 {
1083         struct snd_soc_codec *codec = codec_dai->codec;
1084 
1085         switch (div_id) {
1086         case WM8990_MCLK_DIV:
1087                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1088                                     WM8990_MCLK_DIV_MASK, div);
1089                 break;
1090         case WM8990_DACCLK_DIV:
1091                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1092                                     WM8990_DAC_CLKDIV_MASK, div);
1093                 break;
1094         case WM8990_ADCCLK_DIV:
1095                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1096                                     WM8990_ADC_CLKDIV_MASK, div);
1097                 break;
1098         case WM8990_BCLK_DIV:
1099                 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
1100                                     WM8990_BCLK_DIV_MASK, div);
1101                 break;
1102         default:
1103                 return -EINVAL;
1104         }
1105 
1106         return 0;
1107 }
1108 
1109 /*
1110  * Set PCM DAI bit size and sample rate.
1111  */
1112 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1113                             struct snd_pcm_hw_params *params,
1114                             struct snd_soc_dai *dai)
1115 {
1116         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1117         struct snd_soc_codec *codec = rtd->codec;
1118         u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1119 
1120         audio1 &= ~WM8990_AIF_WL_MASK;
1121         /* bit size */
1122         switch (params_format(params)) {
1123         case SNDRV_PCM_FORMAT_S16_LE:
1124                 break;
1125         case SNDRV_PCM_FORMAT_S20_3LE:
1126                 audio1 |= WM8990_AIF_WL_20BITS;
1127                 break;
1128         case SNDRV_PCM_FORMAT_S24_LE:
1129                 audio1 |= WM8990_AIF_WL_24BITS;
1130                 break;
1131         case SNDRV_PCM_FORMAT_S32_LE:
1132                 audio1 |= WM8990_AIF_WL_32BITS;
1133                 break;
1134         }
1135 
1136         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1137         return 0;
1138 }
1139 
1140 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1141 {
1142         struct snd_soc_codec *codec = dai->codec;
1143         u16 val;
1144 
1145         val  = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1146 
1147         if (mute)
1148                 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1149         else
1150                 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1151 
1152         return 0;
1153 }
1154 
1155 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1156         enum snd_soc_bias_level level)
1157 {
1158         int ret;
1159 
1160         switch (level) {
1161         case SND_SOC_BIAS_ON:
1162                 break;
1163 
1164         case SND_SOC_BIAS_PREPARE:
1165                 /* VMID=2*50k */
1166                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1167                                     WM8990_VMID_MODE_MASK, 0x2);
1168                 break;
1169 
1170         case SND_SOC_BIAS_STANDBY:
1171                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1172                         ret = snd_soc_cache_sync(codec);
1173                         if (ret < 0) {
1174                                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1175                                 return ret;
1176                         }
1177 
1178                         /* Enable all output discharge bits */
1179                         snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1180                                 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1181                                 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1182                                 WM8990_DIS_ROUT);
1183 
1184                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1185                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1186                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1187                                      WM8990_VMIDTOG);
1188 
1189                         /* Delay to allow output caps to discharge */
1190                         msleep(300);
1191 
1192                         /* Disable VMIDTOG */
1193                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1194                                      WM8990_BUFDCOPEN | WM8990_POBCTRL);
1195 
1196                         /* disable all output discharge bits */
1197                         snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1198 
1199                         /* Enable outputs */
1200                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1201 
1202                         msleep(50);
1203 
1204                         /* Enable VMID at 2x50k */
1205                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1206 
1207                         msleep(100);
1208 
1209                         /* Enable VREF */
1210                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1211 
1212                         msleep(600);
1213 
1214                         /* Enable BUFIOEN */
1215                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1216                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1217                                      WM8990_BUFIOEN);
1218 
1219                         /* Disable outputs */
1220                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1221 
1222                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1223                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1224 
1225                         /* Enable workaround for ADC clocking issue. */
1226                         snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1227                         snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1228                         snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1229                 }
1230 
1231                 /* VMID=2*250k */
1232                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1233                                     WM8990_VMID_MODE_MASK, 0x4);
1234                 break;
1235 
1236         case SND_SOC_BIAS_OFF:
1237                 /* Enable POBCTRL and SOFT_ST */
1238                 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1239                         WM8990_POBCTRL | WM8990_BUFIOEN);
1240 
1241                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1242                 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1243                         WM8990_BUFDCOPEN | WM8990_POBCTRL |
1244                         WM8990_BUFIOEN);
1245 
1246                 /* mute DAC */
1247                 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1248                                     WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1249 
1250                 /* Enable any disabled outputs */
1251                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1252 
1253                 /* Disable VMID */
1254                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1255 
1256                 msleep(300);
1257 
1258                 /* Enable all output discharge bits */
1259                 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1260                         WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1261                         WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1262                         WM8990_DIS_ROUT);
1263 
1264                 /* Disable VREF */
1265                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1266 
1267                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1268                 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1269 
1270                 codec->cache_sync = 1;
1271                 break;
1272         }
1273 
1274         codec->dapm.bias_level = level;
1275         return 0;
1276 }
1277 
1278 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1279         SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1280         SNDRV_PCM_RATE_48000)
1281 
1282 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1283         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1284 
1285 /*
1286  * The WM8990 supports 2 different and mutually exclusive DAI
1287  * configurations.
1288  *
1289  * 1. ADC/DAC on Primary Interface
1290  * 2. ADC on Primary Interface/DAC on secondary
1291  */
1292 static struct snd_soc_dai_ops wm8990_dai_ops = {
1293         .hw_params      = wm8990_hw_params,
1294         .digital_mute   = wm8990_mute,
1295         .set_fmt        = wm8990_set_dai_fmt,
1296         .set_clkdiv     = wm8990_set_dai_clkdiv,
1297         .set_pll        = wm8990_set_dai_pll,
1298         .set_sysclk     = wm8990_set_dai_sysclk,
1299 };
1300 
1301 static struct snd_soc_dai_driver wm8990_dai = {
1302 /* ADC/DAC on primary */
1303         .name = "wm8990-hifi",
1304         .playback = {
1305                 .stream_name = "Playback",
1306                 .channels_min = 1,
1307                 .channels_max = 2,
1308                 .rates = WM8990_RATES,
1309                 .formats = WM8990_FORMATS,},
1310         .capture = {
1311                 .stream_name = "Capture",
1312                 .channels_min = 1,
1313                 .channels_max = 2,
1314                 .rates = WM8990_RATES,
1315                 .formats = WM8990_FORMATS,},
1316         .ops = &wm8990_dai_ops,
1317 };
1318 
1319 static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state)
1320 {
1321         wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1322         return 0;
1323 }
1324 
1325 static int wm8990_resume(struct snd_soc_codec *codec)
1326 {
1327         wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1328         return 0;
1329 }
1330 
1331 /*
1332  * initialise the WM8990 driver
1333  * register the mixer and dsp interfaces with the kernel
1334  */
1335 static int wm8990_probe(struct snd_soc_codec *codec)
1336 {
1337         int ret;
1338 
1339         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1340         if (ret < 0) {
1341                 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1342                 return ret;
1343         }
1344 
1345         wm8990_reset(codec);
1346 
1347         /* charge output caps */
1348         wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1349 
1350         snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1351                             WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1352 
1353         snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1354                             WM8990_GPIO1_SEL_MASK, 1);
1355 
1356         snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1357                             WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1358 
1359         snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1360         snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1361 
1362         snd_soc_add_controls(codec, wm8990_snd_controls,
1363                                 ARRAY_SIZE(wm8990_snd_controls));
1364         wm8990_add_widgets(codec);
1365 
1366         return 0;
1367 }
1368 
1369 /* power down chip */
1370 static int wm8990_remove(struct snd_soc_codec *codec)
1371 {
1372         wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1373         return 0;
1374 }
1375 
1376 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1377         .probe =        wm8990_probe,
1378         .remove =       wm8990_remove,
1379         .suspend =      wm8990_suspend,
1380         .resume =       wm8990_resume,
1381         .set_bias_level = wm8990_set_bias_level,
1382         .reg_cache_size = ARRAY_SIZE(wm8990_reg),
1383         .reg_word_size = sizeof(u16),
1384         .reg_cache_default = wm8990_reg,
1385         .volatile_register = wm8990_volatile_register,
1386 };
1387 
1388 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1389 static __devinit int wm8990_i2c_probe(struct i2c_client *i2c,
1390                                       const struct i2c_device_id *id)
1391 {
1392         struct wm8990_priv *wm8990;
1393         int ret;
1394 
1395         wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1396         if (wm8990 == NULL)
1397                 return -ENOMEM;
1398 
1399         i2c_set_clientdata(i2c, wm8990);
1400 
1401         ret = snd_soc_register_codec(&i2c->dev,
1402                         &soc_codec_dev_wm8990, &wm8990_dai, 1);
1403         if (ret < 0)
1404                 kfree(wm8990);
1405         return ret;
1406 }
1407 
1408 static __devexit int wm8990_i2c_remove(struct i2c_client *client)
1409 {
1410         snd_soc_unregister_codec(&client->dev);
1411         kfree(i2c_get_clientdata(client));
1412         return 0;
1413 }
1414 
1415 static const struct i2c_device_id wm8990_i2c_id[] = {
1416         { "wm8990", 0 },
1417         { }
1418 };
1419 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1420 
1421 static struct i2c_driver wm8990_i2c_driver = {
1422         .driver = {
1423                 .name = "wm8990-codec",
1424                 .owner = THIS_MODULE,
1425         },
1426         .probe =    wm8990_i2c_probe,
1427         .remove =   __devexit_p(wm8990_i2c_remove),
1428         .id_table = wm8990_i2c_id,
1429 };
1430 #endif
1431 
1432 static int __init wm8990_modinit(void)
1433 {
1434         int ret = 0;
1435 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1436         ret = i2c_add_driver(&wm8990_i2c_driver);
1437         if (ret != 0) {
1438                 printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n",
1439                        ret);
1440         }
1441 #endif
1442         return ret;
1443 }
1444 module_init(wm8990_modinit);
1445 
1446 static void __exit wm8990_exit(void)
1447 {
1448 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1449         i2c_del_driver(&wm8990_i2c_driver);
1450 #endif
1451 }
1452 module_exit(wm8990_exit);
1453 
1454 MODULE_DESCRIPTION("ASoC WM8990 driver");
1455 MODULE_AUTHOR("Liam Girdwood");
1456 MODULE_LICENSE("GPL");
1457 

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