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Linux/sound/soc/codecs/wm8994.c

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  1 /*
  2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
  3  *
  4  * Copyright 2009-12 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/gcd.h>
 20 #include <linux/i2c.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/pm_runtime.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/slab.h>
 25 #include <sound/core.h>
 26 #include <sound/jack.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/initval.h>
 31 #include <sound/tlv.h>
 32 #include <trace/events/asoc.h>
 33 
 34 #include <linux/mfd/wm8994/core.h>
 35 #include <linux/mfd/wm8994/registers.h>
 36 #include <linux/mfd/wm8994/pdata.h>
 37 #include <linux/mfd/wm8994/gpio.h>
 38 
 39 #include "wm8994.h"
 40 #include "wm_hubs.h"
 41 
 42 #define WM1811_JACKDET_MODE_NONE  0x0000
 43 #define WM1811_JACKDET_MODE_JACK  0x0100
 44 #define WM1811_JACKDET_MODE_MIC   0x0080
 45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
 46 
 47 #define WM8994_NUM_DRC 3
 48 #define WM8994_NUM_EQ  3
 49 
 50 static struct {
 51         unsigned int reg;
 52         unsigned int mask;
 53 } wm8994_vu_bits[] = {
 54         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
 55         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
 56         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
 57         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
 58         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
 59         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
 60         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
 61         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
 62         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
 63         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
 64 
 65         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
 66         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
 67         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
 68         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
 69         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
 70         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
 71         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
 72         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
 73         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
 74         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
 75         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
 76         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
 77         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
 78         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
 79         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
 80         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
 81 };
 82 
 83 static int wm8994_drc_base[] = {
 84         WM8994_AIF1_DRC1_1,
 85         WM8994_AIF1_DRC2_1,
 86         WM8994_AIF2_DRC_1,
 87 };
 88 
 89 static int wm8994_retune_mobile_base[] = {
 90         WM8994_AIF1_DAC1_EQ_GAINS_1,
 91         WM8994_AIF1_DAC2_EQ_GAINS_1,
 92         WM8994_AIF2_EQ_GAINS_1,
 93 };
 94 
 95 static const struct wm8958_micd_rate micdet_rates[] = {
 96         { 32768,       true,  1, 4 },
 97         { 32768,       false, 1, 1 },
 98         { 44100 * 256, true,  7, 10 },
 99         { 44100 * 256, false, 7, 10 },
100 };
101 
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103         { 32768,       true,  0, 1 },
104         { 32768,       false, 0, 1 },
105         { 44100 * 256, true,  10, 10 },
106         { 44100 * 256, false, 7, 8 },
107 };
108 
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 {
111         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112         struct wm8994 *control = wm8994->wm8994;
113         int best, i, sysclk, val;
114         bool idle;
115         const struct wm8958_micd_rate *rates;
116         int num_rates;
117 
118         idle = !wm8994->jack_mic;
119 
120         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121         if (sysclk & WM8994_SYSCLK_SRC)
122                 sysclk = wm8994->aifclk[1];
123         else
124                 sysclk = wm8994->aifclk[0];
125 
126         if (control->pdata.micd_rates) {
127                 rates = control->pdata.micd_rates;
128                 num_rates = control->pdata.num_micd_rates;
129         } else if (wm8994->jackdet) {
130                 rates = jackdet_rates;
131                 num_rates = ARRAY_SIZE(jackdet_rates);
132         } else {
133                 rates = micdet_rates;
134                 num_rates = ARRAY_SIZE(micdet_rates);
135         }
136 
137         best = 0;
138         for (i = 0; i < num_rates; i++) {
139                 if (rates[i].idle != idle)
140                         continue;
141                 if (abs(rates[i].sysclk - sysclk) <
142                     abs(rates[best].sysclk - sysclk))
143                         best = i;
144                 else if (rates[best].idle != idle)
145                         best = i;
146         }
147 
148         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150 
151         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152                 rates[best].start, rates[best].rate, sysclk,
153                 idle ? "idle" : "active");
154 
155         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156                             WM8958_MICD_BIAS_STARTTIME_MASK |
157                             WM8958_MICD_RATE_MASK, val);
158 }
159 
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 {
162         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163         int rate;
164         int reg1 = 0;
165         int offset;
166 
167         if (aif)
168                 offset = 4;
169         else
170                 offset = 0;
171 
172         switch (wm8994->sysclk[aif]) {
173         case WM8994_SYSCLK_MCLK1:
174                 rate = wm8994->mclk[0];
175                 break;
176 
177         case WM8994_SYSCLK_MCLK2:
178                 reg1 |= 0x8;
179                 rate = wm8994->mclk[1];
180                 break;
181 
182         case WM8994_SYSCLK_FLL1:
183                 reg1 |= 0x10;
184                 rate = wm8994->fll[0].out;
185                 break;
186 
187         case WM8994_SYSCLK_FLL2:
188                 reg1 |= 0x18;
189                 rate = wm8994->fll[1].out;
190                 break;
191 
192         default:
193                 return -EINVAL;
194         }
195 
196         if (rate >= 13500000) {
197                 rate /= 2;
198                 reg1 |= WM8994_AIF1CLK_DIV;
199 
200                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201                         aif + 1, rate);
202         }
203 
204         wm8994->aifclk[aif] = rate;
205 
206         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208                             reg1);
209 
210         return 0;
211 }
212 
213 static int configure_clock(struct snd_soc_codec *codec)
214 {
215         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216         int change, new;
217 
218         /* Bring up the AIF clocks first */
219         configure_aif_clock(codec, 0);
220         configure_aif_clock(codec, 1);
221 
222         /* Then switch CLK_SYS over to the higher of them; a change
223          * can only happen as a result of a clocking change which can
224          * only be made outside of DAPM so we can safely redo the
225          * clocking.
226          */
227 
228         /* If they're equal it doesn't matter which is used */
229         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230                 wm8958_micd_set_rate(codec);
231                 return 0;
232         }
233 
234         if (wm8994->aifclk[0] < wm8994->aifclk[1])
235                 new = WM8994_SYSCLK_SRC;
236         else
237                 new = 0;
238 
239         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240                                      WM8994_SYSCLK_SRC, new);
241         if (change)
242                 snd_soc_dapm_sync(&codec->dapm);
243 
244         wm8958_micd_set_rate(codec);
245 
246         return 0;
247 }
248 
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250                          struct snd_soc_dapm_widget *sink)
251 {
252         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253         const char *clk;
254 
255         /* Check what we're currently using for CLK_SYS */
256         if (reg & WM8994_SYSCLK_SRC)
257                 clk = "AIF2CLK";
258         else
259                 clk = "AIF1CLK";
260 
261         return strcmp(source->name, clk) == 0;
262 }
263 
264 static const char *sidetone_hpf_text[] = {
265         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266 };
267 
268 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
269                             WM8994_SIDETONE, 7, sidetone_hpf_text);
270 
271 static const char *adc_hpf_text[] = {
272         "HiFi", "Voice 1", "Voice 2", "Voice 3"
273 };
274 
275 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
276                             WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
277 
278 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
279                             WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
280 
281 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
282                             WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
283 
284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291 
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293         SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294                 snd_soc_get_volsw, wm8994_put_drc_sw)
295 
296 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297                              struct snd_ctl_elem_value *ucontrol)
298 {
299         struct soc_mixer_control *mc =
300                 (struct soc_mixer_control *)kcontrol->private_value;
301         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
302         int mask, ret;
303 
304         /* Can't enable both ADC and DAC paths simultaneously */
305         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
308         else
309                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310 
311         ret = snd_soc_read(codec, mc->reg);
312         if (ret < 0)
313                 return ret;
314         if (ret & mask)
315                 return -EINVAL;
316 
317         return snd_soc_put_volsw(kcontrol, ucontrol);
318 }
319 
320 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321 {
322         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
323         struct wm8994 *control = wm8994->wm8994;
324         struct wm8994_pdata *pdata = &control->pdata;
325         int base = wm8994_drc_base[drc];
326         int cfg = wm8994->drc_cfg[drc];
327         int save, i;
328 
329         /* Save any enables; the configuration should clear them. */
330         save = snd_soc_read(codec, base);
331         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332                 WM8994_AIF1ADC1R_DRC_ENA;
333 
334         for (i = 0; i < WM8994_DRC_REGS; i++)
335                 snd_soc_update_bits(codec, base + i, 0xffff,
336                                     pdata->drc_cfgs[cfg].regs[i]);
337 
338         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339                              WM8994_AIF1ADC1L_DRC_ENA |
340                              WM8994_AIF1ADC1R_DRC_ENA, save);
341 }
342 
343 /* Icky as hell but saves code duplication */
344 static int wm8994_get_drc(const char *name)
345 {
346         if (strcmp(name, "AIF1DRC1 Mode") == 0)
347                 return 0;
348         if (strcmp(name, "AIF1DRC2 Mode") == 0)
349                 return 1;
350         if (strcmp(name, "AIF2DRC Mode") == 0)
351                 return 2;
352         return -EINVAL;
353 }
354 
355 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356                                struct snd_ctl_elem_value *ucontrol)
357 {
358         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
359         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360         struct wm8994 *control = wm8994->wm8994;
361         struct wm8994_pdata *pdata = &control->pdata;
362         int drc = wm8994_get_drc(kcontrol->id.name);
363         int value = ucontrol->value.enumerated.item[0];
364 
365         if (drc < 0)
366                 return drc;
367 
368         if (value >= pdata->num_drc_cfgs)
369                 return -EINVAL;
370 
371         wm8994->drc_cfg[drc] = value;
372 
373         wm8994_set_drc(codec, drc);
374 
375         return 0;
376 }
377 
378 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379                                struct snd_ctl_elem_value *ucontrol)
380 {
381         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
382         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
383         int drc = wm8994_get_drc(kcontrol->id.name);
384 
385         if (drc < 0)
386                 return drc;
387         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388 
389         return 0;
390 }
391 
392 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393 {
394         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
395         struct wm8994 *control = wm8994->wm8994;
396         struct wm8994_pdata *pdata = &control->pdata;
397         int base = wm8994_retune_mobile_base[block];
398         int iface, best, best_val, save, i, cfg;
399 
400         if (!pdata || !wm8994->num_retune_mobile_texts)
401                 return;
402 
403         switch (block) {
404         case 0:
405         case 1:
406                 iface = 0;
407                 break;
408         case 2:
409                 iface = 1;
410                 break;
411         default:
412                 return;
413         }
414 
415         /* Find the version of the currently selected configuration
416          * with the nearest sample rate. */
417         cfg = wm8994->retune_mobile_cfg[block];
418         best = 0;
419         best_val = INT_MAX;
420         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422                            wm8994->retune_mobile_texts[cfg]) == 0 &&
423                     abs(pdata->retune_mobile_cfgs[i].rate
424                         - wm8994->dac_rates[iface]) < best_val) {
425                         best = i;
426                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
427                                        - wm8994->dac_rates[iface]);
428                 }
429         }
430 
431         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432                 block,
433                 pdata->retune_mobile_cfgs[best].name,
434                 pdata->retune_mobile_cfgs[best].rate,
435                 wm8994->dac_rates[iface]);
436 
437         /* The EQ will be disabled while reconfiguring it, remember the
438          * current configuration.
439          */
440         save = snd_soc_read(codec, base);
441         save &= WM8994_AIF1DAC1_EQ_ENA;
442 
443         for (i = 0; i < WM8994_EQ_REGS; i++)
444                 snd_soc_update_bits(codec, base + i, 0xffff,
445                                 pdata->retune_mobile_cfgs[best].regs[i]);
446 
447         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448 }
449 
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name)
452 {
453         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454                 return 0;
455         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456                 return 1;
457         if (strcmp(name, "AIF2 EQ Mode") == 0)
458                 return 2;
459         return -EINVAL;
460 }
461 
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463                                          struct snd_ctl_elem_value *ucontrol)
464 {
465         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
466         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467         struct wm8994 *control = wm8994->wm8994;
468         struct wm8994_pdata *pdata = &control->pdata;
469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470         int value = ucontrol->value.enumerated.item[0];
471 
472         if (block < 0)
473                 return block;
474 
475         if (value >= pdata->num_retune_mobile_cfgs)
476                 return -EINVAL;
477 
478         wm8994->retune_mobile_cfg[block] = value;
479 
480         wm8994_set_retune_mobile(codec, block);
481 
482         return 0;
483 }
484 
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486                                          struct snd_ctl_elem_value *ucontrol)
487 {
488         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491 
492         if (block < 0)
493                 return block;
494 
495         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496 
497         return 0;
498 }
499 
500 static const char *aif_chan_src_text[] = {
501         "Left", "Right"
502 };
503 
504 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
505                             WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
506 
507 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
508                             WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
509 
510 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
511                             WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
512 
513 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
514                             WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
515 
516 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
517                             WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
518 
519 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
520                             WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
521 
522 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
523                             WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
524 
525 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
526                             WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
527 
528 static const char *osr_text[] = {
529         "Low Power", "High Performance",
530 };
531 
532 static SOC_ENUM_SINGLE_DECL(dac_osr,
533                             WM8994_OVERSAMPLING, 0, osr_text);
534 
535 static SOC_ENUM_SINGLE_DECL(adc_osr,
536                             WM8994_OVERSAMPLING, 1, osr_text);
537 
538 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
541                  1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
544                  1, 119, 0, digital_tlv),
545 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546                  WM8994_AIF2_ADC_RIGHT_VOLUME,
547                  1, 119, 0, digital_tlv),
548 
549 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
551 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
553 
554 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
556 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
558 
559 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565 
566 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568 
569 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572 
573 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576 
577 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580 
581 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584 
585 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586                5, 12, 0, st_tlv),
587 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588                0, 12, 0, st_tlv),
589 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590                5, 12, 0, st_tlv),
591 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592                0, 12, 0, st_tlv),
593 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595 
596 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598 
599 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601 
602 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604 
605 SOC_ENUM("ADC OSR", adc_osr),
606 SOC_ENUM("DAC OSR", dac_osr),
607 
608 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612 
613 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617 
618 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619                6, 1, 1, wm_hubs_spkmix_tlv),
620 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621                2, 1, 1, wm_hubs_spkmix_tlv),
622 
623 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624                6, 1, 1, wm_hubs_spkmix_tlv),
625 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626                2, 1, 1, wm_hubs_spkmix_tlv),
627 
628 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629                10, 15, 0, wm8994_3d_tlv),
630 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
631            8, 1, 0),
632 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633                10, 15, 0, wm8994_3d_tlv),
634 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635            8, 1, 0),
636 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
637                10, 15, 0, wm8994_3d_tlv),
638 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
639            8, 1, 0),
640 };
641 
642 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644                eq_tlv),
645 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646                eq_tlv),
647 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648                eq_tlv),
649 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650                eq_tlv),
651 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652                eq_tlv),
653 
654 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655                eq_tlv),
656 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657                eq_tlv),
658 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659                eq_tlv),
660 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661                eq_tlv),
662 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663                eq_tlv),
664 
665 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666                eq_tlv),
667 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668                eq_tlv),
669 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670                eq_tlv),
671 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672                eq_tlv),
673 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674                eq_tlv),
675 };
676 
677 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680                    WM8994_AIF1ADC1R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683                    WM8994_AIF1ADC2R_DRC_ENA),
684 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686                    WM8994_AIF2ADCR_DRC_ENA),
687 };
688 
689 static const char *wm8958_ng_text[] = {
690         "30ms", "125ms", "250ms", "500ms",
691 };
692 
693 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
694                             WM8958_AIF1_DAC1_NOISE_GATE,
695                             WM8958_AIF1DAC1_NG_THR_SHIFT,
696                             wm8958_ng_text);
697 
698 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
699                             WM8958_AIF1_DAC2_NOISE_GATE,
700                             WM8958_AIF1DAC2_NG_THR_SHIFT,
701                             wm8958_ng_text);
702 
703 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
704                             WM8958_AIF2_DAC_NOISE_GATE,
705                             WM8958_AIF2DAC_NG_THR_SHIFT,
706                             wm8958_ng_text);
707 
708 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
709 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
710 
711 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
712            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
713 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
714 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
715                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
716                7, 1, ng_tlv),
717 
718 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
719            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
720 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
721 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
722                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
723                7, 1, ng_tlv),
724 
725 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
726            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
727 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
728 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
729                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
730                7, 1, ng_tlv),
731 };
732 
733 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
734 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
735                mixin_boost_tlv),
736 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
737                mixin_boost_tlv),
738 };
739 
740 /* We run all mode setting through a function to enforce audio mode */
741 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
742 {
743         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744 
745         if (!wm8994->jackdet || !wm8994->micdet[0].jack)
746                 return;
747 
748         if (wm8994->active_refcount)
749                 mode = WM1811_JACKDET_MODE_AUDIO;
750 
751         if (mode == wm8994->jackdet_mode)
752                 return;
753 
754         wm8994->jackdet_mode = mode;
755 
756         /* Always use audio mode to detect while the system is active */
757         if (mode != WM1811_JACKDET_MODE_NONE)
758                 mode = WM1811_JACKDET_MODE_AUDIO;
759 
760         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
761                             WM1811_JACKDET_MODE_MASK, mode);
762 }
763 
764 static void active_reference(struct snd_soc_codec *codec)
765 {
766         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
767 
768         mutex_lock(&wm8994->accdet_lock);
769 
770         wm8994->active_refcount++;
771 
772         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
773                 wm8994->active_refcount);
774 
775         /* If we're using jack detection go into audio mode */
776         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
777 
778         mutex_unlock(&wm8994->accdet_lock);
779 }
780 
781 static void active_dereference(struct snd_soc_codec *codec)
782 {
783         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784         u16 mode;
785 
786         mutex_lock(&wm8994->accdet_lock);
787 
788         wm8994->active_refcount--;
789 
790         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
791                 wm8994->active_refcount);
792 
793         if (wm8994->active_refcount == 0) {
794                 /* Go into appropriate detection only mode */
795                 if (wm8994->jack_mic || wm8994->mic_detecting)
796                         mode = WM1811_JACKDET_MODE_MIC;
797                 else
798                         mode = WM1811_JACKDET_MODE_JACK;
799 
800                 wm1811_jackdet_set_mode(codec, mode);
801         }
802 
803         mutex_unlock(&wm8994->accdet_lock);
804 }
805 
806 static int clk_sys_event(struct snd_soc_dapm_widget *w,
807                          struct snd_kcontrol *kcontrol, int event)
808 {
809         struct snd_soc_codec *codec = w->codec;
810         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
811 
812         switch (event) {
813         case SND_SOC_DAPM_PRE_PMU:
814                 return configure_clock(codec);
815 
816         case SND_SOC_DAPM_POST_PMU:
817                 /*
818                  * JACKDET won't run until we start the clock and it
819                  * only reports deltas, make sure we notify the state
820                  * up the stack on startup.  Use a *very* generous
821                  * timeout for paranoia, there's no urgency and we
822                  * don't want false reports.
823                  */
824                 if (wm8994->jackdet && !wm8994->clk_has_run) {
825                         queue_delayed_work(system_power_efficient_wq,
826                                            &wm8994->jackdet_bootstrap,
827                                            msecs_to_jiffies(1000));
828                         wm8994->clk_has_run = true;
829                 }
830                 break;
831 
832         case SND_SOC_DAPM_POST_PMD:
833                 configure_clock(codec);
834                 break;
835         }
836 
837         return 0;
838 }
839 
840 static void vmid_reference(struct snd_soc_codec *codec)
841 {
842         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
843 
844         pm_runtime_get_sync(codec->dev);
845 
846         wm8994->vmid_refcount++;
847 
848         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
849                 wm8994->vmid_refcount);
850 
851         if (wm8994->vmid_refcount == 1) {
852                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
853                                     WM8994_LINEOUT1_DISCH |
854                                     WM8994_LINEOUT2_DISCH, 0);
855 
856                 wm_hubs_vmid_ena(codec);
857 
858                 switch (wm8994->vmid_mode) {
859                 default:
860                         WARN_ON(NULL == "Invalid VMID mode");
861                 case WM8994_VMID_NORMAL:
862                         /* Startup bias, VMID ramp & buffer */
863                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
864                                             WM8994_BIAS_SRC |
865                                             WM8994_VMID_DISCH |
866                                             WM8994_STARTUP_BIAS_ENA |
867                                             WM8994_VMID_BUF_ENA |
868                                             WM8994_VMID_RAMP_MASK,
869                                             WM8994_BIAS_SRC |
870                                             WM8994_STARTUP_BIAS_ENA |
871                                             WM8994_VMID_BUF_ENA |
872                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
873 
874                         /* Main bias enable, VMID=2x40k */
875                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
876                                             WM8994_BIAS_ENA |
877                                             WM8994_VMID_SEL_MASK,
878                                             WM8994_BIAS_ENA | 0x2);
879 
880                         msleep(300);
881 
882                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883                                             WM8994_VMID_RAMP_MASK |
884                                             WM8994_BIAS_SRC,
885                                             0);
886                         break;
887 
888                 case WM8994_VMID_FORCE:
889                         /* Startup bias, slow VMID ramp & buffer */
890                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
891                                             WM8994_BIAS_SRC |
892                                             WM8994_VMID_DISCH |
893                                             WM8994_STARTUP_BIAS_ENA |
894                                             WM8994_VMID_BUF_ENA |
895                                             WM8994_VMID_RAMP_MASK,
896                                             WM8994_BIAS_SRC |
897                                             WM8994_STARTUP_BIAS_ENA |
898                                             WM8994_VMID_BUF_ENA |
899                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
900 
901                         /* Main bias enable, VMID=2x40k */
902                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
903                                             WM8994_BIAS_ENA |
904                                             WM8994_VMID_SEL_MASK,
905                                             WM8994_BIAS_ENA | 0x2);
906 
907                         msleep(400);
908 
909                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910                                             WM8994_VMID_RAMP_MASK |
911                                             WM8994_BIAS_SRC,
912                                             0);
913                         break;
914                 }
915         }
916 }
917 
918 static void vmid_dereference(struct snd_soc_codec *codec)
919 {
920         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
921 
922         wm8994->vmid_refcount--;
923 
924         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
925                 wm8994->vmid_refcount);
926 
927         if (wm8994->vmid_refcount == 0) {
928                 if (wm8994->hubs.lineout1_se)
929                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930                                             WM8994_LINEOUT1N_ENA |
931                                             WM8994_LINEOUT1P_ENA,
932                                             WM8994_LINEOUT1N_ENA |
933                                             WM8994_LINEOUT1P_ENA);
934 
935                 if (wm8994->hubs.lineout2_se)
936                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
937                                             WM8994_LINEOUT2N_ENA |
938                                             WM8994_LINEOUT2P_ENA,
939                                             WM8994_LINEOUT2N_ENA |
940                                             WM8994_LINEOUT2P_ENA);
941 
942                 /* Start discharging VMID */
943                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
944                                     WM8994_BIAS_SRC |
945                                     WM8994_VMID_DISCH,
946                                     WM8994_BIAS_SRC |
947                                     WM8994_VMID_DISCH);
948 
949                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
950                                     WM8994_VMID_SEL_MASK, 0);
951 
952                 msleep(400);
953 
954                 /* Active discharge */
955                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
956                                     WM8994_LINEOUT1_DISCH |
957                                     WM8994_LINEOUT2_DISCH,
958                                     WM8994_LINEOUT1_DISCH |
959                                     WM8994_LINEOUT2_DISCH);
960 
961                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
962                                     WM8994_LINEOUT1N_ENA |
963                                     WM8994_LINEOUT1P_ENA |
964                                     WM8994_LINEOUT2N_ENA |
965                                     WM8994_LINEOUT2P_ENA, 0);
966 
967                 /* Switch off startup biases */
968                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
969                                     WM8994_BIAS_SRC |
970                                     WM8994_STARTUP_BIAS_ENA |
971                                     WM8994_VMID_BUF_ENA |
972                                     WM8994_VMID_RAMP_MASK, 0);
973 
974                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
975                                     WM8994_VMID_SEL_MASK, 0);
976         }
977 
978         pm_runtime_put(codec->dev);
979 }
980 
981 static int vmid_event(struct snd_soc_dapm_widget *w,
982                       struct snd_kcontrol *kcontrol, int event)
983 {
984         struct snd_soc_codec *codec = w->codec;
985 
986         switch (event) {
987         case SND_SOC_DAPM_PRE_PMU:
988                 vmid_reference(codec);
989                 break;
990 
991         case SND_SOC_DAPM_POST_PMD:
992                 vmid_dereference(codec);
993                 break;
994         }
995 
996         return 0;
997 }
998 
999 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1000 {
1001         int source = 0;  /* GCC flow analysis can't track enable */
1002         int reg, reg_r;
1003 
1004         /* We also need the same AIF source for L/R and only one path */
1005         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1006         switch (reg) {
1007         case WM8994_AIF2DACL_TO_DAC1L:
1008                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1009                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010                 break;
1011         case WM8994_AIF1DAC2L_TO_DAC1L:
1012                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1013                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014                 break;
1015         case WM8994_AIF1DAC1L_TO_DAC1L:
1016                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1017                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018                 break;
1019         default:
1020                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1021                 return false;
1022         }
1023 
1024         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1025         if (reg_r != reg) {
1026                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1027                 return false;
1028         }
1029 
1030         /* Set the source up */
1031         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1032                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1033 
1034         return true;
1035 }
1036 
1037 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1038                       struct snd_kcontrol *kcontrol, int event)
1039 {
1040         struct snd_soc_codec *codec = w->codec;
1041         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1042         struct wm8994 *control = wm8994->wm8994;
1043         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1044         int i;
1045         int dac;
1046         int adc;
1047         int val;
1048 
1049         switch (control->type) {
1050         case WM8994:
1051         case WM8958:
1052                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1053                 break;
1054         default:
1055                 break;
1056         }
1057 
1058         switch (event) {
1059         case SND_SOC_DAPM_PRE_PMU:
1060                 /* Don't enable timeslot 2 if not in use */
1061                 if (wm8994->channels[0] <= 2)
1062                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1063 
1064                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1065                 if ((val & WM8994_AIF1ADCL_SRC) &&
1066                     (val & WM8994_AIF1ADCR_SRC))
1067                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1068                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1069                          !(val & WM8994_AIF1ADCR_SRC))
1070                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071                 else
1072                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1073                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1074 
1075                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1076                 if ((val & WM8994_AIF1DACL_SRC) &&
1077                     (val & WM8994_AIF1DACR_SRC))
1078                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1079                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1080                          !(val & WM8994_AIF1DACR_SRC))
1081                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082                 else
1083                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1084                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1085 
1086                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1087                                     mask, adc);
1088                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1089                                     mask, dac);
1090                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1091                                     WM8994_AIF1DSPCLK_ENA |
1092                                     WM8994_SYSDSPCLK_ENA,
1093                                     WM8994_AIF1DSPCLK_ENA |
1094                                     WM8994_SYSDSPCLK_ENA);
1095                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1096                                     WM8994_AIF1ADC1R_ENA |
1097                                     WM8994_AIF1ADC1L_ENA |
1098                                     WM8994_AIF1ADC2R_ENA |
1099                                     WM8994_AIF1ADC2L_ENA);
1100                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1101                                     WM8994_AIF1DAC1R_ENA |
1102                                     WM8994_AIF1DAC1L_ENA |
1103                                     WM8994_AIF1DAC2R_ENA |
1104                                     WM8994_AIF1DAC2L_ENA);
1105                 break;
1106 
1107         case SND_SOC_DAPM_POST_PMU:
1108                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1109                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1110                                       snd_soc_read(codec,
1111                                                    wm8994_vu_bits[i].reg));
1112                 break;
1113 
1114         case SND_SOC_DAPM_PRE_PMD:
1115         case SND_SOC_DAPM_POST_PMD:
1116                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1117                                     mask, 0);
1118                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1119                                     mask, 0);
1120 
1121                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1122                 if (val & WM8994_AIF2DSPCLK_ENA)
1123                         val = WM8994_SYSDSPCLK_ENA;
1124                 else
1125                         val = 0;
1126                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1127                                     WM8994_SYSDSPCLK_ENA |
1128                                     WM8994_AIF1DSPCLK_ENA, val);
1129                 break;
1130         }
1131 
1132         return 0;
1133 }
1134 
1135 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1136                       struct snd_kcontrol *kcontrol, int event)
1137 {
1138         struct snd_soc_codec *codec = w->codec;
1139         int i;
1140         int dac;
1141         int adc;
1142         int val;
1143 
1144         switch (event) {
1145         case SND_SOC_DAPM_PRE_PMU:
1146                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1147                 if ((val & WM8994_AIF2ADCL_SRC) &&
1148                     (val & WM8994_AIF2ADCR_SRC))
1149                         adc = WM8994_AIF2ADCR_ENA;
1150                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1151                          !(val & WM8994_AIF2ADCR_SRC))
1152                         adc = WM8994_AIF2ADCL_ENA;
1153                 else
1154                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1155 
1156 
1157                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1158                 if ((val & WM8994_AIF2DACL_SRC) &&
1159                     (val & WM8994_AIF2DACR_SRC))
1160                         dac = WM8994_AIF2DACR_ENA;
1161                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1162                          !(val & WM8994_AIF2DACR_SRC))
1163                         dac = WM8994_AIF2DACL_ENA;
1164                 else
1165                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1166 
1167                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1168                                     WM8994_AIF2ADCL_ENA |
1169                                     WM8994_AIF2ADCR_ENA, adc);
1170                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1171                                     WM8994_AIF2DACL_ENA |
1172                                     WM8994_AIF2DACR_ENA, dac);
1173                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1174                                     WM8994_AIF2DSPCLK_ENA |
1175                                     WM8994_SYSDSPCLK_ENA,
1176                                     WM8994_AIF2DSPCLK_ENA |
1177                                     WM8994_SYSDSPCLK_ENA);
1178                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1179                                     WM8994_AIF2ADCL_ENA |
1180                                     WM8994_AIF2ADCR_ENA,
1181                                     WM8994_AIF2ADCL_ENA |
1182                                     WM8994_AIF2ADCR_ENA);
1183                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1184                                     WM8994_AIF2DACL_ENA |
1185                                     WM8994_AIF2DACR_ENA,
1186                                     WM8994_AIF2DACL_ENA |
1187                                     WM8994_AIF2DACR_ENA);
1188                 break;
1189 
1190         case SND_SOC_DAPM_POST_PMU:
1191                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1192                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1193                                       snd_soc_read(codec,
1194                                                    wm8994_vu_bits[i].reg));
1195                 break;
1196 
1197         case SND_SOC_DAPM_PRE_PMD:
1198         case SND_SOC_DAPM_POST_PMD:
1199                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1200                                     WM8994_AIF2DACL_ENA |
1201                                     WM8994_AIF2DACR_ENA, 0);
1202                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1203                                     WM8994_AIF2ADCL_ENA |
1204                                     WM8994_AIF2ADCR_ENA, 0);
1205 
1206                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1207                 if (val & WM8994_AIF1DSPCLK_ENA)
1208                         val = WM8994_SYSDSPCLK_ENA;
1209                 else
1210                         val = 0;
1211                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1212                                     WM8994_SYSDSPCLK_ENA |
1213                                     WM8994_AIF2DSPCLK_ENA, val);
1214                 break;
1215         }
1216 
1217         return 0;
1218 }
1219 
1220 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1221                            struct snd_kcontrol *kcontrol, int event)
1222 {
1223         struct snd_soc_codec *codec = w->codec;
1224         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1225 
1226         switch (event) {
1227         case SND_SOC_DAPM_PRE_PMU:
1228                 wm8994->aif1clk_enable = 1;
1229                 break;
1230         case SND_SOC_DAPM_POST_PMD:
1231                 wm8994->aif1clk_disable = 1;
1232                 break;
1233         }
1234 
1235         return 0;
1236 }
1237 
1238 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1239                            struct snd_kcontrol *kcontrol, int event)
1240 {
1241         struct snd_soc_codec *codec = w->codec;
1242         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1243 
1244         switch (event) {
1245         case SND_SOC_DAPM_PRE_PMU:
1246                 wm8994->aif2clk_enable = 1;
1247                 break;
1248         case SND_SOC_DAPM_POST_PMD:
1249                 wm8994->aif2clk_disable = 1;
1250                 break;
1251         }
1252 
1253         return 0;
1254 }
1255 
1256 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1257                           struct snd_kcontrol *kcontrol, int event)
1258 {
1259         struct snd_soc_codec *codec = w->codec;
1260         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1261 
1262         switch (event) {
1263         case SND_SOC_DAPM_PRE_PMU:
1264                 if (wm8994->aif1clk_enable) {
1265                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1266                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1267                                             WM8994_AIF1CLK_ENA_MASK,
1268                                             WM8994_AIF1CLK_ENA);
1269                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1270                         wm8994->aif1clk_enable = 0;
1271                 }
1272                 if (wm8994->aif2clk_enable) {
1273                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1274                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1275                                             WM8994_AIF2CLK_ENA_MASK,
1276                                             WM8994_AIF2CLK_ENA);
1277                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1278                         wm8994->aif2clk_enable = 0;
1279                 }
1280                 break;
1281         }
1282 
1283         /* We may also have postponed startup of DSP, handle that. */
1284         wm8958_aif_ev(w, kcontrol, event);
1285 
1286         return 0;
1287 }
1288 
1289 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1290                            struct snd_kcontrol *kcontrol, int event)
1291 {
1292         struct snd_soc_codec *codec = w->codec;
1293         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1294 
1295         switch (event) {
1296         case SND_SOC_DAPM_POST_PMD:
1297                 if (wm8994->aif1clk_disable) {
1298                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1299                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1300                                             WM8994_AIF1CLK_ENA_MASK, 0);
1301                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1302                         wm8994->aif1clk_disable = 0;
1303                 }
1304                 if (wm8994->aif2clk_disable) {
1305                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1306                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1307                                             WM8994_AIF2CLK_ENA_MASK, 0);
1308                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1309                         wm8994->aif2clk_disable = 0;
1310                 }
1311                 break;
1312         }
1313 
1314         return 0;
1315 }
1316 
1317 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1318                       struct snd_kcontrol *kcontrol, int event)
1319 {
1320         late_enable_ev(w, kcontrol, event);
1321         return 0;
1322 }
1323 
1324 static int micbias_ev(struct snd_soc_dapm_widget *w,
1325                       struct snd_kcontrol *kcontrol, int event)
1326 {
1327         late_enable_ev(w, kcontrol, event);
1328         return 0;
1329 }
1330 
1331 static int dac_ev(struct snd_soc_dapm_widget *w,
1332                   struct snd_kcontrol *kcontrol, int event)
1333 {
1334         struct snd_soc_codec *codec = w->codec;
1335         unsigned int mask = 1 << w->shift;
1336 
1337         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1338                             mask, mask);
1339         return 0;
1340 }
1341 
1342 static const char *adc_mux_text[] = {
1343         "ADC",
1344         "DMIC",
1345 };
1346 
1347 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1348 
1349 static const struct snd_kcontrol_new adcl_mux =
1350         SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1351 
1352 static const struct snd_kcontrol_new adcr_mux =
1353         SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1354 
1355 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1356 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1357 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1358 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1359 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1360 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1361 };
1362 
1363 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1364 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1365 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1366 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1367 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1368 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1369 };
1370 
1371 /* Debugging; dump chip status after DAPM transitions */
1372 static int post_ev(struct snd_soc_dapm_widget *w,
1373             struct snd_kcontrol *kcontrol, int event)
1374 {
1375         struct snd_soc_codec *codec = w->codec;
1376         dev_dbg(codec->dev, "SRC status: %x\n",
1377                 snd_soc_read(codec,
1378                              WM8994_RATE_STATUS));
1379         return 0;
1380 }
1381 
1382 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1383 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384                 1, 1, 0),
1385 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1386                 0, 1, 0),
1387 };
1388 
1389 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1390 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391                 1, 1, 0),
1392 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1393                 0, 1, 0),
1394 };
1395 
1396 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1397 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398                 1, 1, 0),
1399 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1400                 0, 1, 0),
1401 };
1402 
1403 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1404 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405                 1, 1, 0),
1406 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1407                 0, 1, 0),
1408 };
1409 
1410 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1411 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412                 5, 1, 0),
1413 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414                 4, 1, 0),
1415 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416                 2, 1, 0),
1417 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418                 1, 1, 0),
1419 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420                 0, 1, 0),
1421 };
1422 
1423 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1424 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425                 5, 1, 0),
1426 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427                 4, 1, 0),
1428 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429                 2, 1, 0),
1430 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431                 1, 1, 0),
1432 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433                 0, 1, 0),
1434 };
1435 
1436 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1437         SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1438                 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1439 
1440 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1441                               struct snd_ctl_elem_value *ucontrol)
1442 {
1443         struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1444         int ret;
1445 
1446         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1447 
1448         wm_hubs_update_class_w(codec);
1449 
1450         return ret;
1451 }
1452 
1453 static const struct snd_kcontrol_new dac1l_mix[] = {
1454 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455                       5, 1, 0),
1456 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457                       4, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459                       2, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461                       1, 1, 0),
1462 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463                       0, 1, 0),
1464 };
1465 
1466 static const struct snd_kcontrol_new dac1r_mix[] = {
1467 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468                       5, 1, 0),
1469 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470                       4, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472                       2, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474                       1, 1, 0),
1475 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476                       0, 1, 0),
1477 };
1478 
1479 static const char *sidetone_text[] = {
1480         "ADC/DMIC1", "DMIC2",
1481 };
1482 
1483 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1484                             WM8994_SIDETONE, 0, sidetone_text);
1485 
1486 static const struct snd_kcontrol_new sidetone1_mux =
1487         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1488 
1489 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1490                             WM8994_SIDETONE, 1, sidetone_text);
1491 
1492 static const struct snd_kcontrol_new sidetone2_mux =
1493         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1494 
1495 static const char *aif1dac_text[] = {
1496         "AIF1DACDAT", "AIF3DACDAT",
1497 };
1498 
1499 static const char *loopback_text[] = {
1500         "None", "ADCDAT",
1501 };
1502 
1503 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1504                             WM8994_AIF1_CONTROL_2,
1505                             WM8994_AIF1_LOOPBACK_SHIFT,
1506                             loopback_text);
1507 
1508 static const struct snd_kcontrol_new aif1_loopback =
1509         SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1510 
1511 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1512                             WM8994_AIF2_CONTROL_2,
1513                             WM8994_AIF2_LOOPBACK_SHIFT,
1514                             loopback_text);
1515 
1516 static const struct snd_kcontrol_new aif2_loopback =
1517         SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1518 
1519 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1520                             WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1521 
1522 static const struct snd_kcontrol_new aif1dac_mux =
1523         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1524 
1525 static const char *aif2dac_text[] = {
1526         "AIF2DACDAT", "AIF3DACDAT",
1527 };
1528 
1529 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1530                             WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1531 
1532 static const struct snd_kcontrol_new aif2dac_mux =
1533         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1534 
1535 static const char *aif2adc_text[] = {
1536         "AIF2ADCDAT", "AIF3DACDAT",
1537 };
1538 
1539 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1540                             WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1541 
1542 static const struct snd_kcontrol_new aif2adc_mux =
1543         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1544 
1545 static const char *aif3adc_text[] = {
1546         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1547 };
1548 
1549 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1550                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1551 
1552 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1553         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1554 
1555 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1556                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1557 
1558 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1559         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1560 
1561 static const char *mono_pcm_out_text[] = {
1562         "None", "AIF2ADCL", "AIF2ADCR",
1563 };
1564 
1565 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1566                             WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1567 
1568 static const struct snd_kcontrol_new mono_pcm_out_mux =
1569         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1570 
1571 static const char *aif2dac_src_text[] = {
1572         "AIF2", "AIF3",
1573 };
1574 
1575 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1576 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1577                             WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1578 
1579 static const struct snd_kcontrol_new aif2dacl_src_mux =
1580         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1581 
1582 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1583                             WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1584 
1585 static const struct snd_kcontrol_new aif2dacr_src_mux =
1586         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1587 
1588 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1589 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1590         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1591 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1592         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1593 
1594 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1598 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1599         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1601         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1602 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1603         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604 
1605 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1607                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1608 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1609                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1610                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1611 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1612                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1614                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1615 
1616 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1617 };
1618 
1619 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1620 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1621                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1622                     SND_SOC_DAPM_PRE_PMD),
1623 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1624                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1625                     SND_SOC_DAPM_PRE_PMD),
1626 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1627 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1628                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1629 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1630                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1631 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1632 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1633 };
1634 
1635 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1636 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1637         dac_ev, SND_SOC_DAPM_PRE_PMU),
1638 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1639         dac_ev, SND_SOC_DAPM_PRE_PMU),
1640 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1641         dac_ev, SND_SOC_DAPM_PRE_PMU),
1642 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1643         dac_ev, SND_SOC_DAPM_PRE_PMU),
1644 };
1645 
1646 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1647 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1648 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1649 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1650 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1651 };
1652 
1653 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1654 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1655                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1656 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1657                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1658 };
1659 
1660 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1661 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1662 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1663 };
1664 
1665 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1666 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1667 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1668 SND_SOC_DAPM_INPUT("Clock"),
1669 
1670 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1671                       SND_SOC_DAPM_PRE_PMU),
1672 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1673                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1674 
1675 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1676                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677                     SND_SOC_DAPM_PRE_PMD),
1678 
1679 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1680 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1681 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1682 
1683 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1684                      0, SND_SOC_NOPM, 9, 0),
1685 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1686                      0, SND_SOC_NOPM, 8, 0),
1687 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1688                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1689                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1690 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1691                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1692                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1693 
1694 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1695                      0, SND_SOC_NOPM, 11, 0),
1696 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1697                      0, SND_SOC_NOPM, 10, 0),
1698 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1699                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1700                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1701 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1702                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1703                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1704 
1705 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1706                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1707 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1708                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1709 
1710 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1711                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1712 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1713                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1714 
1715 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1716                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1717 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1718                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1719 
1720 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1721 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1722 
1723 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1724                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1725 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1726                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1727 
1728 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1729                      SND_SOC_NOPM, 13, 0),
1730 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1731                      SND_SOC_NOPM, 12, 0),
1732 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1733                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1734                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1735 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1736                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1737                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1738 
1739 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1740 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1743 
1744 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1745 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1746 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1747 
1748 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1749 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750 
1751 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1752 
1753 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1754 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1755 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1756 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1757 
1758 /* Power is done with the muxes since the ADC power also controls the
1759  * downsampling chain, the chip will automatically manage the analogue
1760  * specific portions.
1761  */
1762 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1763 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1764 
1765 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1766 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1767 
1768 SND_SOC_DAPM_POST("Debug log", post_ev),
1769 };
1770 
1771 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1772 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1773 };
1774 
1775 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1776 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1777 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1778 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1779 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1780 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1781 };
1782 
1783 static const struct snd_soc_dapm_route intercon[] = {
1784         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1785         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1786 
1787         { "DSP1CLK", NULL, "CLK_SYS" },
1788         { "DSP2CLK", NULL, "CLK_SYS" },
1789         { "DSPINTCLK", NULL, "CLK_SYS" },
1790 
1791         { "AIF1ADC1L", NULL, "AIF1CLK" },
1792         { "AIF1ADC1L", NULL, "DSP1CLK" },
1793         { "AIF1ADC1R", NULL, "AIF1CLK" },
1794         { "AIF1ADC1R", NULL, "DSP1CLK" },
1795         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1796 
1797         { "AIF1DAC1L", NULL, "AIF1CLK" },
1798         { "AIF1DAC1L", NULL, "DSP1CLK" },
1799         { "AIF1DAC1R", NULL, "AIF1CLK" },
1800         { "AIF1DAC1R", NULL, "DSP1CLK" },
1801         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1802 
1803         { "AIF1ADC2L", NULL, "AIF1CLK" },
1804         { "AIF1ADC2L", NULL, "DSP1CLK" },
1805         { "AIF1ADC2R", NULL, "AIF1CLK" },
1806         { "AIF1ADC2R", NULL, "DSP1CLK" },
1807         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1808 
1809         { "AIF1DAC2L", NULL, "AIF1CLK" },
1810         { "AIF1DAC2L", NULL, "DSP1CLK" },
1811         { "AIF1DAC2R", NULL, "AIF1CLK" },
1812         { "AIF1DAC2R", NULL, "DSP1CLK" },
1813         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1814 
1815         { "AIF2ADCL", NULL, "AIF2CLK" },
1816         { "AIF2ADCL", NULL, "DSP2CLK" },
1817         { "AIF2ADCR", NULL, "AIF2CLK" },
1818         { "AIF2ADCR", NULL, "DSP2CLK" },
1819         { "AIF2ADCR", NULL, "DSPINTCLK" },
1820 
1821         { "AIF2DACL", NULL, "AIF2CLK" },
1822         { "AIF2DACL", NULL, "DSP2CLK" },
1823         { "AIF2DACR", NULL, "AIF2CLK" },
1824         { "AIF2DACR", NULL, "DSP2CLK" },
1825         { "AIF2DACR", NULL, "DSPINTCLK" },
1826 
1827         { "DMIC1L", NULL, "DMIC1DAT" },
1828         { "DMIC1L", NULL, "CLK_SYS" },
1829         { "DMIC1R", NULL, "DMIC1DAT" },
1830         { "DMIC1R", NULL, "CLK_SYS" },
1831         { "DMIC2L", NULL, "DMIC2DAT" },
1832         { "DMIC2L", NULL, "CLK_SYS" },
1833         { "DMIC2R", NULL, "DMIC2DAT" },
1834         { "DMIC2R", NULL, "CLK_SYS" },
1835 
1836         { "ADCL", NULL, "AIF1CLK" },
1837         { "ADCL", NULL, "DSP1CLK" },
1838         { "ADCL", NULL, "DSPINTCLK" },
1839 
1840         { "ADCR", NULL, "AIF1CLK" },
1841         { "ADCR", NULL, "DSP1CLK" },
1842         { "ADCR", NULL, "DSPINTCLK" },
1843 
1844         { "ADCL Mux", "ADC", "ADCL" },
1845         { "ADCL Mux", "DMIC", "DMIC1L" },
1846         { "ADCR Mux", "ADC", "ADCR" },
1847         { "ADCR Mux", "DMIC", "DMIC1R" },
1848 
1849         { "DAC1L", NULL, "AIF1CLK" },
1850         { "DAC1L", NULL, "DSP1CLK" },
1851         { "DAC1L", NULL, "DSPINTCLK" },
1852 
1853         { "DAC1R", NULL, "AIF1CLK" },
1854         { "DAC1R", NULL, "DSP1CLK" },
1855         { "DAC1R", NULL, "DSPINTCLK" },
1856 
1857         { "DAC2L", NULL, "AIF2CLK" },
1858         { "DAC2L", NULL, "DSP2CLK" },
1859         { "DAC2L", NULL, "DSPINTCLK" },
1860 
1861         { "DAC2R", NULL, "AIF2DACR" },
1862         { "DAC2R", NULL, "AIF2CLK" },
1863         { "DAC2R", NULL, "DSP2CLK" },
1864         { "DAC2R", NULL, "DSPINTCLK" },
1865 
1866         { "TOCLK", NULL, "CLK_SYS" },
1867 
1868         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1869         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1870         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1871 
1872         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1873         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1874         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1875 
1876         /* AIF1 outputs */
1877         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1878         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1879         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1880 
1881         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1882         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1883         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1884 
1885         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1886         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1887         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1888 
1889         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1890         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1891         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1892 
1893         /* Pin level routing for AIF3 */
1894         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1895         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1896         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1897         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1898 
1899         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1900         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1901         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1902         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1903         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1904         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1905         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1906 
1907         /* DAC1 inputs */
1908         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1909         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1910         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1911         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1912         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1913 
1914         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1915         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1916         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1917         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1918         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1919 
1920         /* DAC2/AIF2 outputs  */
1921         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1922         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1923         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1924         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1925         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1926         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1927 
1928         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1929         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1930         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1931         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1932         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1933         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1934 
1935         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1936         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1937         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1938         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1939 
1940         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1941 
1942         /* AIF3 output */
1943         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1944         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1945         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1946         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1947         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1948         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1949         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1950         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1951 
1952         /* Loopback */
1953         { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1954         { "AIF1 Loopback", "None", "AIF1DACDAT" },
1955         { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1956         { "AIF2 Loopback", "None", "AIF2DACDAT" },
1957 
1958         /* Sidetone */
1959         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1960         { "Left Sidetone", "DMIC2", "DMIC2L" },
1961         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1962         { "Right Sidetone", "DMIC2", "DMIC2R" },
1963 
1964         /* Output stages */
1965         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1966         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1967 
1968         { "SPKL", "DAC1 Switch", "DAC1L" },
1969         { "SPKL", "DAC2 Switch", "DAC2L" },
1970 
1971         { "SPKR", "DAC1 Switch", "DAC1R" },
1972         { "SPKR", "DAC2 Switch", "DAC2R" },
1973 
1974         { "Left Headphone Mux", "DAC", "DAC1L" },
1975         { "Right Headphone Mux", "DAC", "DAC1R" },
1976 };
1977 
1978 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1979         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1980         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1981         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1982         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1983         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1984         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1985         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1986         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1987 };
1988 
1989 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1990         { "DAC1L", NULL, "DAC1L Mixer" },
1991         { "DAC1R", NULL, "DAC1R Mixer" },
1992         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1993         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1994 };
1995 
1996 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1997         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1998         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1999         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2000         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2001         { "MICBIAS1", NULL, "CLK_SYS" },
2002         { "MICBIAS1", NULL, "MICBIAS Supply" },
2003         { "MICBIAS2", NULL, "CLK_SYS" },
2004         { "MICBIAS2", NULL, "MICBIAS Supply" },
2005 };
2006 
2007 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2008         { "AIF2DACL", NULL, "AIF2DAC Mux" },
2009         { "AIF2DACR", NULL, "AIF2DAC Mux" },
2010         { "MICBIAS1", NULL, "VMID" },
2011         { "MICBIAS2", NULL, "VMID" },
2012 };
2013 
2014 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2015         { "AIF2DACL", NULL, "AIF2DACL Mux" },
2016         { "AIF2DACR", NULL, "AIF2DACR Mux" },
2017 
2018         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2019         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2020         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2021         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2022 
2023         { "AIF3DACDAT", NULL, "AIF3" },
2024         { "AIF3ADCDAT", NULL, "AIF3" },
2025 
2026         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2027         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2028 
2029         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2030 };
2031 
2032 /* The size in bits of the FLL divide multiplied by 10
2033  * to allow rounding later */
2034 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2035 
2036 struct fll_div {
2037         u16 outdiv;
2038         u16 n;
2039         u16 k;
2040         u16 lambda;
2041         u16 clk_ref_div;
2042         u16 fll_fratio;
2043 };
2044 
2045 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2046                                  int freq_in, int freq_out)
2047 {
2048         u64 Kpart;
2049         unsigned int K, Ndiv, Nmod, gcd_fll;
2050 
2051         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2052 
2053         /* Scale the input frequency down to <= 13.5MHz */
2054         fll->clk_ref_div = 0;
2055         while (freq_in > 13500000) {
2056                 fll->clk_ref_div++;
2057                 freq_in /= 2;
2058 
2059                 if (fll->clk_ref_div > 3)
2060                         return -EINVAL;
2061         }
2062         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2063 
2064         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2065         fll->outdiv = 3;
2066         while (freq_out * (fll->outdiv + 1) < 90000000) {
2067                 fll->outdiv++;
2068                 if (fll->outdiv > 63)
2069                         return -EINVAL;
2070         }
2071         freq_out *= fll->outdiv + 1;
2072         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2073 
2074         if (freq_in > 1000000) {
2075                 fll->fll_fratio = 0;
2076         } else if (freq_in > 256000) {
2077                 fll->fll_fratio = 1;
2078                 freq_in *= 2;
2079         } else if (freq_in > 128000) {
2080                 fll->fll_fratio = 2;
2081                 freq_in *= 4;
2082         } else if (freq_in > 64000) {
2083                 fll->fll_fratio = 3;
2084                 freq_in *= 8;
2085         } else {
2086                 fll->fll_fratio = 4;
2087                 freq_in *= 16;
2088         }
2089         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2090 
2091         /* Now, calculate N.K */
2092         Ndiv = freq_out / freq_in;
2093 
2094         fll->n = Ndiv;
2095         Nmod = freq_out % freq_in;
2096         pr_debug("Nmod=%d\n", Nmod);
2097 
2098         switch (control->type) {
2099         case WM8994:
2100                 /* Calculate fractional part - scale up so we can round. */
2101                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2102 
2103                 do_div(Kpart, freq_in);
2104 
2105                 K = Kpart & 0xFFFFFFFF;
2106 
2107                 if ((K % 10) >= 5)
2108                         K += 5;
2109 
2110                 /* Move down to proper range now rounding is done */
2111                 fll->k = K / 10;
2112                 fll->lambda = 0;
2113 
2114                 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2115                 break;
2116 
2117         default:
2118                 gcd_fll = gcd(freq_out, freq_in);
2119 
2120                 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2121                 fll->lambda = freq_in / gcd_fll;
2122                 
2123         }
2124 
2125         return 0;
2126 }
2127 
2128 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2129                           unsigned int freq_in, unsigned int freq_out)
2130 {
2131         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2132         struct wm8994 *control = wm8994->wm8994;
2133         int reg_offset, ret;
2134         struct fll_div fll;
2135         u16 reg, clk1, aif_reg, aif_src;
2136         unsigned long timeout;
2137         bool was_enabled;
2138 
2139         switch (id) {
2140         case WM8994_FLL1:
2141                 reg_offset = 0;
2142                 id = 0;
2143                 aif_src = 0x10;
2144                 break;
2145         case WM8994_FLL2:
2146                 reg_offset = 0x20;
2147                 id = 1;
2148                 aif_src = 0x18;
2149                 break;
2150         default:
2151                 return -EINVAL;
2152         }
2153 
2154         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2155         was_enabled = reg & WM8994_FLL1_ENA;
2156 
2157         switch (src) {
2158         case 0:
2159                 /* Allow no source specification when stopping */
2160                 if (freq_out)
2161                         return -EINVAL;
2162                 src = wm8994->fll[id].src;
2163                 break;
2164         case WM8994_FLL_SRC_MCLK1:
2165         case WM8994_FLL_SRC_MCLK2:
2166         case WM8994_FLL_SRC_LRCLK:
2167         case WM8994_FLL_SRC_BCLK:
2168                 break;
2169         case WM8994_FLL_SRC_INTERNAL:
2170                 freq_in = 12000000;
2171                 freq_out = 12000000;
2172                 break;
2173         default:
2174                 return -EINVAL;
2175         }
2176 
2177         /* Are we changing anything? */
2178         if (wm8994->fll[id].src == src &&
2179             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2180                 return 0;
2181 
2182         /* If we're stopping the FLL redo the old config - no
2183          * registers will actually be written but we avoid GCC flow
2184          * analysis bugs spewing warnings.
2185          */
2186         if (freq_out)
2187                 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2188         else
2189                 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2190                                             wm8994->fll[id].out);
2191         if (ret < 0)
2192                 return ret;
2193 
2194         /* Make sure that we're not providing SYSCLK right now */
2195         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2196         if (clk1 & WM8994_SYSCLK_SRC)
2197                 aif_reg = WM8994_AIF2_CLOCKING_1;
2198         else
2199                 aif_reg = WM8994_AIF1_CLOCKING_1;
2200         reg = snd_soc_read(codec, aif_reg);
2201 
2202         if ((reg & WM8994_AIF1CLK_ENA) &&
2203             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2204                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2205                         id + 1);
2206                 return -EBUSY;
2207         }
2208 
2209         /* We always need to disable the FLL while reconfiguring */
2210         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2211                             WM8994_FLL1_ENA, 0);
2212 
2213         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2214             freq_in == freq_out && freq_out) {
2215                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2216                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2217                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2218                 goto out;
2219         }
2220 
2221         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2222                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2223         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2224                             WM8994_FLL1_OUTDIV_MASK |
2225                             WM8994_FLL1_FRATIO_MASK, reg);
2226 
2227         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2228                             WM8994_FLL1_K_MASK, fll.k);
2229 
2230         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2231                             WM8994_FLL1_N_MASK,
2232                             fll.n << WM8994_FLL1_N_SHIFT);
2233 
2234         if (fll.lambda) {
2235                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2236                                     WM8958_FLL1_LAMBDA_MASK,
2237                                     fll.lambda);
2238                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2239                                     WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2240         } else {
2241                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2242                                     WM8958_FLL1_EFS_ENA, 0);
2243         }
2244 
2245         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2246                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2247                             WM8994_FLL1_REFCLK_DIV_MASK |
2248                             WM8994_FLL1_REFCLK_SRC_MASK,
2249                             ((src == WM8994_FLL_SRC_INTERNAL)
2250                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2251                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2252                             (src - 1));
2253 
2254         /* Clear any pending completion from a previous failure */
2255         try_wait_for_completion(&wm8994->fll_locked[id]);
2256 
2257         /* Enable (with fractional mode if required) */
2258         if (freq_out) {
2259                 /* Enable VMID if we need it */
2260                 if (!was_enabled) {
2261                         active_reference(codec);
2262 
2263                         switch (control->type) {
2264                         case WM8994:
2265                                 vmid_reference(codec);
2266                                 break;
2267                         case WM8958:
2268                                 if (control->revision < 1)
2269                                         vmid_reference(codec);
2270                                 break;
2271                         default:
2272                                 break;
2273                         }
2274                 }
2275 
2276                 reg = WM8994_FLL1_ENA;
2277 
2278                 if (fll.k)
2279                         reg |= WM8994_FLL1_FRAC;
2280                 if (src == WM8994_FLL_SRC_INTERNAL)
2281                         reg |= WM8994_FLL1_OSC_ENA;
2282 
2283                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2284                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2285                                     WM8994_FLL1_FRAC, reg);
2286 
2287                 if (wm8994->fll_locked_irq) {
2288                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2289                                                               msecs_to_jiffies(10));
2290                         if (timeout == 0)
2291                                 dev_warn(codec->dev,
2292                                          "Timed out waiting for FLL lock\n");
2293                 } else {
2294                         msleep(5);
2295                 }
2296         } else {
2297                 if (was_enabled) {
2298                         switch (control->type) {
2299                         case WM8994:
2300                                 vmid_dereference(codec);
2301                                 break;
2302                         case WM8958:
2303                                 if (control->revision < 1)
2304                                         vmid_dereference(codec);
2305                                 break;
2306                         default:
2307                                 break;
2308                         }
2309 
2310                         active_dereference(codec);
2311                 }
2312         }
2313 
2314 out:
2315         wm8994->fll[id].in = freq_in;
2316         wm8994->fll[id].out = freq_out;
2317         wm8994->fll[id].src = src;
2318 
2319         configure_clock(codec);
2320 
2321         /*
2322          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2323          * for detection.
2324          */
2325         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2326                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2327 
2328                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2329                         & WM8994_AIF1CLK_RATE_MASK;
2330                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2331                         & WM8994_AIF1CLK_RATE_MASK;
2332 
2333                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2334                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2335                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2336                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2337         } else if (wm8994->aifdiv[0]) {
2338                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2339                                     WM8994_AIF1CLK_RATE_MASK,
2340                                     wm8994->aifdiv[0]);
2341                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2342                                     WM8994_AIF2CLK_RATE_MASK,
2343                                     wm8994->aifdiv[1]);
2344 
2345                 wm8994->aifdiv[0] = 0;
2346                 wm8994->aifdiv[1] = 0;
2347         }
2348 
2349         return 0;
2350 }
2351 
2352 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2353 {
2354         struct completion *completion = data;
2355 
2356         complete(completion);
2357 
2358         return IRQ_HANDLED;
2359 }
2360 
2361 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2362 
2363 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2364                           unsigned int freq_in, unsigned int freq_out)
2365 {
2366         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2367 }
2368 
2369 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2370                 int clk_id, unsigned int freq, int dir)
2371 {
2372         struct snd_soc_codec *codec = dai->codec;
2373         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2374         int i;
2375 
2376         switch (dai->id) {
2377         case 1:
2378         case 2:
2379                 break;
2380 
2381         default:
2382                 /* AIF3 shares clocking with AIF1/2 */
2383                 return -EINVAL;
2384         }
2385 
2386         switch (clk_id) {
2387         case WM8994_SYSCLK_MCLK1:
2388                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2389                 wm8994->mclk[0] = freq;
2390                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2391                         dai->id, freq);
2392                 break;
2393 
2394         case WM8994_SYSCLK_MCLK2:
2395                 /* TODO: Set GPIO AF */
2396                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2397                 wm8994->mclk[1] = freq;
2398                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2399                         dai->id, freq);
2400                 break;
2401 
2402         case WM8994_SYSCLK_FLL1:
2403                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2404                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2405                 break;
2406 
2407         case WM8994_SYSCLK_FLL2:
2408                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2409                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2410                 break;
2411 
2412         case WM8994_SYSCLK_OPCLK:
2413                 /* Special case - a division (times 10) is given and
2414                  * no effect on main clocking.
2415                  */
2416                 if (freq) {
2417                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2418                                 if (opclk_divs[i] == freq)
2419                                         break;
2420                         if (i == ARRAY_SIZE(opclk_divs))
2421                                 return -EINVAL;
2422                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2423                                             WM8994_OPCLK_DIV_MASK, i);
2424                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2425                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2426                 } else {
2427                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2428                                             WM8994_OPCLK_ENA, 0);
2429                 }
2430                 break;
2431 
2432         default:
2433                 return -EINVAL;
2434         }
2435 
2436         configure_clock(codec);
2437 
2438         /*
2439          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2440          * for detection.
2441          */
2442         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2443                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2444 
2445                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2446                         & WM8994_AIF1CLK_RATE_MASK;
2447                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2448                         & WM8994_AIF1CLK_RATE_MASK;
2449 
2450                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2452                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2453                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2454         } else if (wm8994->aifdiv[0]) {
2455                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2456                                     WM8994_AIF1CLK_RATE_MASK,
2457                                     wm8994->aifdiv[0]);
2458                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2459                                     WM8994_AIF2CLK_RATE_MASK,
2460                                     wm8994->aifdiv[1]);
2461 
2462                 wm8994->aifdiv[0] = 0;
2463                 wm8994->aifdiv[1] = 0;
2464         }
2465 
2466         return 0;
2467 }
2468 
2469 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2470                                  enum snd_soc_bias_level level)
2471 {
2472         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2473         struct wm8994 *control = wm8994->wm8994;
2474 
2475         wm_hubs_set_bias_level(codec, level);
2476 
2477         switch (level) {
2478         case SND_SOC_BIAS_ON:
2479                 break;
2480 
2481         case SND_SOC_BIAS_PREPARE:
2482                 /* MICBIAS into regulating mode */
2483                 switch (control->type) {
2484                 case WM8958:
2485                 case WM1811:
2486                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2487                                             WM8958_MICB1_MODE, 0);
2488                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2489                                             WM8958_MICB2_MODE, 0);
2490                         break;
2491                 default:
2492                         break;
2493                 }
2494 
2495                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2496                         active_reference(codec);
2497                 break;
2498 
2499         case SND_SOC_BIAS_STANDBY:
2500                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2501                         switch (control->type) {
2502                         case WM8958:
2503                                 if (control->revision == 0) {
2504                                         /* Optimise performance for rev A */
2505                                         snd_soc_update_bits(codec,
2506                                                             WM8958_CHARGE_PUMP_2,
2507                                                             WM8958_CP_DISCH,
2508                                                             WM8958_CP_DISCH);
2509                                 }
2510                                 break;
2511 
2512                         default:
2513                                 break;
2514                         }
2515 
2516                         /* Discharge LINEOUT1 & 2 */
2517                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2518                                             WM8994_LINEOUT1_DISCH |
2519                                             WM8994_LINEOUT2_DISCH,
2520                                             WM8994_LINEOUT1_DISCH |
2521                                             WM8994_LINEOUT2_DISCH);
2522                 }
2523 
2524                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2525                         active_dereference(codec);
2526 
2527                 /* MICBIAS into bypass mode on newer devices */
2528                 switch (control->type) {
2529                 case WM8958:
2530                 case WM1811:
2531                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2532                                             WM8958_MICB1_MODE,
2533                                             WM8958_MICB1_MODE);
2534                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2535                                             WM8958_MICB2_MODE,
2536                                             WM8958_MICB2_MODE);
2537                         break;
2538                 default:
2539                         break;
2540                 }
2541                 break;
2542 
2543         case SND_SOC_BIAS_OFF:
2544                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2545                         wm8994->cur_fw = NULL;
2546                 break;
2547         }
2548 
2549         codec->dapm.bias_level = level;
2550 
2551         return 0;
2552 }
2553 
2554 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2555 {
2556         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2557         struct snd_soc_dapm_context *dapm = &codec->dapm;
2558 
2559         switch (mode) {
2560         case WM8994_VMID_NORMAL:
2561                 snd_soc_dapm_mutex_lock(dapm);
2562 
2563                 if (wm8994->hubs.lineout1_se) {
2564                         snd_soc_dapm_disable_pin_unlocked(dapm,
2565                                                           "LINEOUT1N Driver");
2566                         snd_soc_dapm_disable_pin_unlocked(dapm,
2567                                                           "LINEOUT1P Driver");
2568                 }
2569                 if (wm8994->hubs.lineout2_se) {
2570                         snd_soc_dapm_disable_pin_unlocked(dapm,
2571                                                           "LINEOUT2N Driver");
2572                         snd_soc_dapm_disable_pin_unlocked(dapm,
2573                                                           "LINEOUT2P Driver");
2574                 }
2575 
2576                 /* Do the sync with the old mode to allow it to clean up */
2577                 snd_soc_dapm_sync_unlocked(dapm);
2578                 wm8994->vmid_mode = mode;
2579 
2580                 snd_soc_dapm_mutex_unlock(dapm);
2581                 break;
2582 
2583         case WM8994_VMID_FORCE:
2584                 snd_soc_dapm_mutex_lock(dapm);
2585 
2586                 if (wm8994->hubs.lineout1_se) {
2587                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2588                                                                "LINEOUT1N Driver");
2589                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2590                                                                "LINEOUT1P Driver");
2591                 }
2592                 if (wm8994->hubs.lineout2_se) {
2593                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2594                                                                "LINEOUT2N Driver");
2595                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2596                                                                "LINEOUT2P Driver");
2597                 }
2598 
2599                 wm8994->vmid_mode = mode;
2600                 snd_soc_dapm_sync_unlocked(dapm);
2601 
2602                 snd_soc_dapm_mutex_unlock(dapm);
2603                 break;
2604 
2605         default:
2606                 return -EINVAL;
2607         }
2608 
2609         return 0;
2610 }
2611 
2612 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2613 {
2614         struct snd_soc_codec *codec = dai->codec;
2615         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2616         struct wm8994 *control = wm8994->wm8994;
2617         int ms_reg;
2618         int aif1_reg;
2619         int dac_reg;
2620         int adc_reg;
2621         int ms = 0;
2622         int aif1 = 0;
2623         int lrclk = 0;
2624 
2625         switch (dai->id) {
2626         case 1:
2627                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2628                 aif1_reg = WM8994_AIF1_CONTROL_1;
2629                 dac_reg = WM8994_AIF1DAC_LRCLK;
2630                 adc_reg = WM8994_AIF1ADC_LRCLK;
2631                 break;
2632         case 2:
2633                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2634                 aif1_reg = WM8994_AIF2_CONTROL_1;
2635                 dac_reg = WM8994_AIF1DAC_LRCLK;
2636                 adc_reg = WM8994_AIF1ADC_LRCLK;
2637                 break;
2638         default:
2639                 return -EINVAL;
2640         }
2641 
2642         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2643         case SND_SOC_DAIFMT_CBS_CFS:
2644                 break;
2645         case SND_SOC_DAIFMT_CBM_CFM:
2646                 ms = WM8994_AIF1_MSTR;
2647                 break;
2648         default:
2649                 return -EINVAL;
2650         }
2651 
2652         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2653         case SND_SOC_DAIFMT_DSP_B:
2654                 aif1 |= WM8994_AIF1_LRCLK_INV;
2655                 lrclk |= WM8958_AIF1_LRCLK_INV;
2656         case SND_SOC_DAIFMT_DSP_A:
2657                 aif1 |= 0x18;
2658                 break;
2659         case SND_SOC_DAIFMT_I2S:
2660                 aif1 |= 0x10;
2661                 break;
2662         case SND_SOC_DAIFMT_RIGHT_J:
2663                 break;
2664         case SND_SOC_DAIFMT_LEFT_J:
2665                 aif1 |= 0x8;
2666                 break;
2667         default:
2668                 return -EINVAL;
2669         }
2670 
2671         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2672         case SND_SOC_DAIFMT_DSP_A:
2673         case SND_SOC_DAIFMT_DSP_B:
2674                 /* frame inversion not valid for DSP modes */
2675                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2676                 case SND_SOC_DAIFMT_NB_NF:
2677                         break;
2678                 case SND_SOC_DAIFMT_IB_NF:
2679                         aif1 |= WM8994_AIF1_BCLK_INV;
2680                         break;
2681                 default:
2682                         return -EINVAL;
2683                 }
2684                 break;
2685 
2686         case SND_SOC_DAIFMT_I2S:
2687         case SND_SOC_DAIFMT_RIGHT_J:
2688         case SND_SOC_DAIFMT_LEFT_J:
2689                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2690                 case SND_SOC_DAIFMT_NB_NF:
2691                         break;
2692                 case SND_SOC_DAIFMT_IB_IF:
2693                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2694                         lrclk |= WM8958_AIF1_LRCLK_INV;
2695                         break;
2696                 case SND_SOC_DAIFMT_IB_NF:
2697                         aif1 |= WM8994_AIF1_BCLK_INV;
2698                         break;
2699                 case SND_SOC_DAIFMT_NB_IF:
2700                         aif1 |= WM8994_AIF1_LRCLK_INV;
2701                         lrclk |= WM8958_AIF1_LRCLK_INV;
2702                         break;
2703                 default:
2704                         return -EINVAL;
2705                 }
2706                 break;
2707         default:
2708                 return -EINVAL;
2709         }
2710 
2711         /* The AIF2 format configuration needs to be mirrored to AIF3
2712          * on WM8958 if it's in use so just do it all the time. */
2713         switch (control->type) {
2714         case WM1811:
2715         case WM8958:
2716                 if (dai->id == 2)
2717                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2718                                             WM8994_AIF1_LRCLK_INV |
2719                                             WM8958_AIF3_FMT_MASK, aif1);
2720                 break;
2721 
2722         default:
2723                 break;
2724         }
2725 
2726         snd_soc_update_bits(codec, aif1_reg,
2727                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2728                             WM8994_AIF1_FMT_MASK,
2729                             aif1);
2730         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2731                             ms);
2732         snd_soc_update_bits(codec, dac_reg,
2733                             WM8958_AIF1_LRCLK_INV, lrclk);
2734         snd_soc_update_bits(codec, adc_reg,
2735                             WM8958_AIF1_LRCLK_INV, lrclk);
2736 
2737         return 0;
2738 }
2739 
2740 static struct {
2741         int val, rate;
2742 } srs[] = {
2743         { 0,   8000 },
2744         { 1,  11025 },
2745         { 2,  12000 },
2746         { 3,  16000 },
2747         { 4,  22050 },
2748         { 5,  24000 },
2749         { 6,  32000 },
2750         { 7,  44100 },
2751         { 8,  48000 },
2752         { 9,  88200 },
2753         { 10, 96000 },
2754 };
2755 
2756 static int fs_ratios[] = {
2757         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2758 };
2759 
2760 static int bclk_divs[] = {
2761         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2762         640, 880, 960, 1280, 1760, 1920
2763 };
2764 
2765 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2766                             struct snd_pcm_hw_params *params,
2767                             struct snd_soc_dai *dai)
2768 {
2769         struct snd_soc_codec *codec = dai->codec;
2770         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2771         struct wm8994 *control = wm8994->wm8994;
2772         struct wm8994_pdata *pdata = &control->pdata;
2773         int aif1_reg;
2774         int aif2_reg;
2775         int bclk_reg;
2776         int lrclk_reg;
2777         int rate_reg;
2778         int aif1 = 0;
2779         int aif2 = 0;
2780         int bclk = 0;
2781         int lrclk = 0;
2782         int rate_val = 0;
2783         int id = dai->id - 1;
2784 
2785         int i, cur_val, best_val, bclk_rate, best;
2786 
2787         switch (dai->id) {
2788         case 1:
2789                 aif1_reg = WM8994_AIF1_CONTROL_1;
2790                 aif2_reg = WM8994_AIF1_CONTROL_2;
2791                 bclk_reg = WM8994_AIF1_BCLK;
2792                 rate_reg = WM8994_AIF1_RATE;
2793                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2794                     wm8994->lrclk_shared[0]) {
2795                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2796                 } else {
2797                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2798                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2799                 }
2800                 break;
2801         case 2:
2802                 aif1_reg = WM8994_AIF2_CONTROL_1;
2803                 aif2_reg = WM8994_AIF2_CONTROL_2;
2804                 bclk_reg = WM8994_AIF2_BCLK;
2805                 rate_reg = WM8994_AIF2_RATE;
2806                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2807                     wm8994->lrclk_shared[1]) {
2808                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2809                 } else {
2810                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2811                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2812                 }
2813                 break;
2814         default:
2815                 return -EINVAL;
2816         }
2817 
2818         bclk_rate = params_rate(params);
2819         switch (params_format(params)) {
2820         case SNDRV_PCM_FORMAT_S16_LE:
2821                 bclk_rate *= 16;
2822                 break;
2823         case SNDRV_PCM_FORMAT_S20_3LE:
2824                 bclk_rate *= 20;
2825                 aif1 |= 0x20;
2826                 break;
2827         case SNDRV_PCM_FORMAT_S24_LE:
2828                 bclk_rate *= 24;
2829                 aif1 |= 0x40;
2830                 break;
2831         case SNDRV_PCM_FORMAT_S32_LE:
2832                 bclk_rate *= 32;
2833                 aif1 |= 0x60;
2834                 break;
2835         default:
2836                 return -EINVAL;
2837         }
2838 
2839         wm8994->channels[id] = params_channels(params);
2840         if (pdata->max_channels_clocked[id] &&
2841             wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2842                 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2843                         pdata->max_channels_clocked[id], wm8994->channels[id]);
2844                 wm8994->channels[id] = pdata->max_channels_clocked[id];
2845         }
2846 
2847         switch (wm8994->channels[id]) {
2848         case 1:
2849         case 2:
2850                 bclk_rate *= 2;
2851                 break;
2852         default:
2853                 bclk_rate *= 4;
2854                 break;
2855         }
2856 
2857         /* Try to find an appropriate sample rate; look for an exact match. */
2858         for (i = 0; i < ARRAY_SIZE(srs); i++)
2859                 if (srs[i].rate == params_rate(params))
2860                         break;
2861         if (i == ARRAY_SIZE(srs))
2862                 return -EINVAL;
2863         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2864 
2865         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2866         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2867                 dai->id, wm8994->aifclk[id], bclk_rate);
2868 
2869         if (wm8994->channels[id] == 1 &&
2870             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2871                 aif2 |= WM8994_AIF1_MONO;
2872 
2873         if (wm8994->aifclk[id] == 0) {
2874                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2875                 return -EINVAL;
2876         }
2877 
2878         /* AIFCLK/fs ratio; look for a close match in either direction */
2879         best = 0;
2880         best_val = abs((fs_ratios[0] * params_rate(params))
2881                        - wm8994->aifclk[id]);
2882         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2883                 cur_val = abs((fs_ratios[i] * params_rate(params))
2884                               - wm8994->aifclk[id]);
2885                 if (cur_val >= best_val)
2886                         continue;
2887                 best = i;
2888                 best_val = cur_val;
2889         }
2890         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2891                 dai->id, fs_ratios[best]);
2892         rate_val |= best;
2893 
2894         /* We may not get quite the right frequency if using
2895          * approximate clocks so look for the closest match that is
2896          * higher than the target (we need to ensure that there enough
2897          * BCLKs to clock out the samples).
2898          */
2899         best = 0;
2900         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2901                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2902                 if (cur_val < 0) /* BCLK table is sorted */
2903                         break;
2904                 best = i;
2905         }
2906         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2907         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2908                 bclk_divs[best], bclk_rate);
2909         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2910 
2911         lrclk = bclk_rate / params_rate(params);
2912         if (!lrclk) {
2913                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2914                         bclk_rate);
2915                 return -EINVAL;
2916         }
2917         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2918                 lrclk, bclk_rate / lrclk);
2919 
2920         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2921         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2922         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2923         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2924                             lrclk);
2925         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2926                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2927 
2928         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2929                 switch (dai->id) {
2930                 case 1:
2931                         wm8994->dac_rates[0] = params_rate(params);
2932                         wm8994_set_retune_mobile(codec, 0);
2933                         wm8994_set_retune_mobile(codec, 1);
2934                         break;
2935                 case 2:
2936                         wm8994->dac_rates[1] = params_rate(params);
2937                         wm8994_set_retune_mobile(codec, 2);
2938                         break;
2939                 }
2940         }
2941 
2942         return 0;
2943 }
2944 
2945 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2946                                  struct snd_pcm_hw_params *params,
2947                                  struct snd_soc_dai *dai)
2948 {
2949         struct snd_soc_codec *codec = dai->codec;
2950         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2951         struct wm8994 *control = wm8994->wm8994;
2952         int aif1_reg;
2953         int aif1 = 0;
2954 
2955         switch (dai->id) {
2956         case 3:
2957                 switch (control->type) {
2958                 case WM1811:
2959                 case WM8958:
2960                         aif1_reg = WM8958_AIF3_CONTROL_1;
2961                         break;
2962                 default:
2963                         return 0;
2964                 }
2965                 break;
2966         default:
2967                 return 0;
2968         }
2969 
2970         switch (params_format(params)) {
2971         case SNDRV_PCM_FORMAT_S16_LE:
2972                 break;
2973         case SNDRV_PCM_FORMAT_S20_3LE:
2974                 aif1 |= 0x20;
2975                 break;
2976         case SNDRV_PCM_FORMAT_S24_LE:
2977                 aif1 |= 0x40;
2978                 break;
2979         case SNDRV_PCM_FORMAT_S32_LE:
2980                 aif1 |= 0x60;
2981                 break;
2982         default:
2983                 return -EINVAL;
2984         }
2985 
2986         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2987 }
2988 
2989 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2990 {
2991         struct snd_soc_codec *codec = codec_dai->codec;
2992         int mute_reg;
2993         int reg;
2994 
2995         switch (codec_dai->id) {
2996         case 1:
2997                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2998                 break;
2999         case 2:
3000                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3001                 break;
3002         default:
3003                 return -EINVAL;
3004         }
3005 
3006         if (mute)
3007                 reg = WM8994_AIF1DAC1_MUTE;
3008         else
3009                 reg = 0;
3010 
3011         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3012 
3013         return 0;
3014 }
3015 
3016 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3017 {
3018         struct snd_soc_codec *codec = codec_dai->codec;
3019         int reg, val, mask;
3020 
3021         switch (codec_dai->id) {
3022         case 1:
3023                 reg = WM8994_AIF1_MASTER_SLAVE;
3024                 mask = WM8994_AIF1_TRI;
3025                 break;
3026         case 2:
3027                 reg = WM8994_AIF2_MASTER_SLAVE;
3028                 mask = WM8994_AIF2_TRI;
3029                 break;
3030         default:
3031                 return -EINVAL;
3032         }
3033 
3034         if (tristate)
3035                 val = mask;
3036         else
3037                 val = 0;
3038 
3039         return snd_soc_update_bits(codec, reg, mask, val);
3040 }
3041 
3042 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3043 {
3044         struct snd_soc_codec *codec = dai->codec;
3045 
3046         /* Disable the pulls on the AIF if we're using it to save power. */
3047         snd_soc_update_bits(codec, WM8994_GPIO_3,
3048                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3049         snd_soc_update_bits(codec, WM8994_GPIO_4,
3050                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3051         snd_soc_update_bits(codec, WM8994_GPIO_5,
3052                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3053 
3054         return 0;
3055 }
3056 
3057 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3058 
3059 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3060                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3061 
3062 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3063         .set_sysclk     = wm8994_set_dai_sysclk,
3064         .set_fmt        = wm8994_set_dai_fmt,
3065         .hw_params      = wm8994_hw_params,
3066         .digital_mute   = wm8994_aif_mute,
3067         .set_pll        = wm8994_set_fll,
3068         .set_tristate   = wm8994_set_tristate,
3069 };
3070 
3071 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3072         .set_sysclk     = wm8994_set_dai_sysclk,
3073         .set_fmt        = wm8994_set_dai_fmt,
3074         .hw_params      = wm8994_hw_params,
3075         .digital_mute   = wm8994_aif_mute,
3076         .set_pll        = wm8994_set_fll,
3077         .set_tristate   = wm8994_set_tristate,
3078 };
3079 
3080 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3081         .hw_params      = wm8994_aif3_hw_params,
3082 };
3083 
3084 static struct snd_soc_dai_driver wm8994_dai[] = {
3085         {
3086                 .name = "wm8994-aif1",
3087                 .id = 1,
3088                 .playback = {
3089                         .stream_name = "AIF1 Playback",
3090                         .channels_min = 1,
3091                         .channels_max = 2,
3092                         .rates = WM8994_RATES,
3093                         .formats = WM8994_FORMATS,
3094                         .sig_bits = 24,
3095                 },
3096                 .capture = {
3097                         .stream_name = "AIF1 Capture",
3098                         .channels_min = 1,
3099                         .channels_max = 2,
3100                         .rates = WM8994_RATES,
3101                         .formats = WM8994_FORMATS,
3102                         .sig_bits = 24,
3103                  },
3104                 .ops = &wm8994_aif1_dai_ops,
3105         },
3106         {
3107                 .name = "wm8994-aif2",
3108                 .id = 2,
3109                 .playback = {
3110                         .stream_name = "AIF2 Playback",
3111                         .channels_min = 1,
3112                         .channels_max = 2,
3113                         .rates = WM8994_RATES,
3114                         .formats = WM8994_FORMATS,
3115                         .sig_bits = 24,
3116                 },
3117                 .capture = {
3118                         .stream_name = "AIF2 Capture",
3119                         .channels_min = 1,
3120                         .channels_max = 2,
3121                         .rates = WM8994_RATES,
3122                         .formats = WM8994_FORMATS,
3123                         .sig_bits = 24,
3124                 },
3125                 .probe = wm8994_aif2_probe,
3126                 .ops = &wm8994_aif2_dai_ops,
3127         },
3128         {
3129                 .name = "wm8994-aif3",
3130                 .id = 3,
3131                 .playback = {
3132                         .stream_name = "AIF3 Playback",
3133                         .channels_min = 1,
3134                         .channels_max = 2,
3135                         .rates = WM8994_RATES,
3136                         .formats = WM8994_FORMATS,
3137                         .sig_bits = 24,
3138                 },
3139                 .capture = {
3140                         .stream_name = "AIF3 Capture",
3141                         .channels_min = 1,
3142                         .channels_max = 2,
3143                         .rates = WM8994_RATES,
3144                         .formats = WM8994_FORMATS,
3145                         .sig_bits = 24,
3146                  },
3147                 .ops = &wm8994_aif3_dai_ops,
3148         }
3149 };
3150 
3151 #ifdef CONFIG_PM
3152 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3153 {
3154         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3155         int i, ret;
3156 
3157         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3158                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3159                        sizeof(struct wm8994_fll_config));
3160                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3161                 if (ret < 0)
3162                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3163                                  i + 1, ret);
3164         }
3165 
3166         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3167 
3168         return 0;
3169 }
3170 
3171 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3172 {
3173         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3174         int i, ret;
3175 
3176         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3177                 if (!wm8994->fll_suspend[i].out)
3178                         continue;
3179 
3180                 ret = _wm8994_set_fll(codec, i + 1,
3181                                      wm8994->fll_suspend[i].src,
3182                                      wm8994->fll_suspend[i].in,
3183                                      wm8994->fll_suspend[i].out);
3184                 if (ret < 0)
3185                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3186                                  i + 1, ret);
3187         }
3188 
3189         return 0;
3190 }
3191 #else
3192 #define wm8994_codec_suspend NULL
3193 #define wm8994_codec_resume NULL
3194 #endif
3195 
3196 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3197 {
3198         struct snd_soc_codec *codec = wm8994->hubs.codec;
3199         struct wm8994 *control = wm8994->wm8994;
3200         struct wm8994_pdata *pdata = &control->pdata;
3201         struct snd_kcontrol_new controls[] = {
3202                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3203                              wm8994->retune_mobile_enum,
3204                              wm8994_get_retune_mobile_enum,
3205                              wm8994_put_retune_mobile_enum),
3206                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3207                              wm8994->retune_mobile_enum,
3208                              wm8994_get_retune_mobile_enum,
3209                              wm8994_put_retune_mobile_enum),
3210                 SOC_ENUM_EXT("AIF2 EQ Mode",
3211                              wm8994->retune_mobile_enum,
3212                              wm8994_get_retune_mobile_enum,
3213                              wm8994_put_retune_mobile_enum),
3214         };
3215         int ret, i, j;
3216         const char **t;
3217 
3218         /* We need an array of texts for the enum API but the number
3219          * of texts is likely to be less than the number of
3220          * configurations due to the sample rate dependency of the
3221          * configurations. */
3222         wm8994->num_retune_mobile_texts = 0;
3223         wm8994->retune_mobile_texts = NULL;
3224         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3225                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3226                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3227                                    wm8994->retune_mobile_texts[j]) == 0)
3228                                 break;
3229                 }
3230 
3231                 if (j != wm8994->num_retune_mobile_texts)
3232                         continue;
3233 
3234                 /* Expand the array... */
3235                 t = krealloc(wm8994->retune_mobile_texts,
3236                              sizeof(char *) *
3237                              (wm8994->num_retune_mobile_texts + 1),
3238                              GFP_KERNEL);
3239                 if (t == NULL)
3240                         continue;
3241 
3242                 /* ...store the new entry... */
3243                 t[wm8994->num_retune_mobile_texts] =
3244                         pdata->retune_mobile_cfgs[i].name;
3245 
3246                 /* ...and remember the new version. */
3247                 wm8994->num_retune_mobile_texts++;
3248                 wm8994->retune_mobile_texts = t;
3249         }
3250 
3251         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3252                 wm8994->num_retune_mobile_texts);
3253 
3254         wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3255         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3256 
3257         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3258                                    ARRAY_SIZE(controls));
3259         if (ret != 0)
3260                 dev_err(wm8994->hubs.codec->dev,
3261                         "Failed to add ReTune Mobile controls: %d\n", ret);
3262 }
3263 
3264 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3265 {
3266         struct snd_soc_codec *codec = wm8994->hubs.codec;
3267         struct wm8994 *control = wm8994->wm8994;
3268         struct wm8994_pdata *pdata = &control->pdata;
3269         int ret, i;
3270 
3271         if (!pdata)
3272                 return;
3273 
3274         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3275                                       pdata->lineout2_diff,
3276                                       pdata->lineout1fb,
3277                                       pdata->lineout2fb,
3278                                       pdata->jd_scthr,
3279                                       pdata->jd_thr,
3280                                       pdata->micb1_delay,
3281                                       pdata->micb2_delay,
3282                                       pdata->micbias1_lvl,
3283                                       pdata->micbias2_lvl);
3284 
3285         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3286 
3287         if (pdata->num_drc_cfgs) {
3288                 struct snd_kcontrol_new controls[] = {
3289                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3290                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3291                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3292                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3293                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3294                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3295                 };
3296 
3297                 /* We need an array of texts for the enum API */
3298                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3299                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3300                 if (!wm8994->drc_texts) {
3301                         dev_err(wm8994->hubs.codec->dev,
3302                                 "Failed to allocate %d DRC config texts\n",
3303                                 pdata->num_drc_cfgs);
3304                         return;
3305                 }
3306 
3307                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3308                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3309 
3310                 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3311                 wm8994->drc_enum.texts = wm8994->drc_texts;
3312 
3313                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3314                                            ARRAY_SIZE(controls));
3315                 for (i = 0; i < WM8994_NUM_DRC; i++)
3316                         wm8994_set_drc(codec, i);
3317         } else {
3318                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3319                                                  wm8994_drc_controls,
3320                                                  ARRAY_SIZE(wm8994_drc_controls));
3321         }
3322 
3323         if (ret != 0)
3324                 dev_err(wm8994->hubs.codec->dev,
3325                         "Failed to add DRC mode controls: %d\n", ret);
3326 
3327 
3328         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3329                 pdata->num_retune_mobile_cfgs);
3330 
3331         if (pdata->num_retune_mobile_cfgs)
3332                 wm8994_handle_retune_mobile_pdata(wm8994);
3333         else
3334                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3335                                      ARRAY_SIZE(wm8994_eq_controls));
3336 
3337         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3338                 if (pdata->micbias[i]) {
3339                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3340                                 pdata->micbias[i] & 0xffff);
3341                 }
3342         }
3343 }
3344 
3345 /**
3346  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3347  *
3348  * @codec:   WM8994 codec
3349  * @jack:    jack to report detection events on
3350  * @micbias: microphone bias to detect on
3351  *
3352  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3353  * being used to bring out signals to the processor then only platform
3354  * data configuration is needed for WM8994 and processor GPIOs should
3355  * be configured using snd_soc_jack_add_gpios() instead.
3356  *
3357  * Configuration of detection levels is available via the micbias1_lvl
3358  * and micbias2_lvl platform data members.
3359  */
3360 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3361                       int micbias)
3362 {
3363         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3364         struct wm8994_micdet *micdet;
3365         struct wm8994 *control = wm8994->wm8994;
3366         int reg, ret;
3367 
3368         if (control->type != WM8994) {
3369                 dev_warn(codec->dev, "Not a WM8994\n");
3370                 return -EINVAL;
3371         }
3372 
3373         switch (micbias) {
3374         case 1:
3375                 micdet = &wm8994->micdet[0];
3376                 if (jack)
3377                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3378                                                             "MICBIAS1");
3379                 else
3380                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3381                                                        "MICBIAS1");
3382                 break;
3383         case 2:
3384                 micdet = &wm8994->micdet[1];
3385                 if (jack)
3386                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3387                                                             "MICBIAS1");
3388                 else
3389                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3390                                                        "MICBIAS1");
3391                 break;
3392         default:
3393                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3394                 return -EINVAL;
3395         }
3396 
3397         if (ret != 0)
3398                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3399                          micbias, ret);
3400 
3401         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3402                 micbias, jack);
3403 
3404         /* Store the configuration */
3405         micdet->jack = jack;
3406         micdet->detecting = true;
3407 
3408         /* If either of the jacks is set up then enable detection */
3409         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3410                 reg = WM8994_MICD_ENA;
3411         else
3412                 reg = 0;
3413 
3414         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3415 
3416         /* enable MICDET and MICSHRT deboune */
3417         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3418                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3419                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3420                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3421 
3422         snd_soc_dapm_sync(&codec->dapm);
3423 
3424         return 0;
3425 }
3426 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3427 
3428 static void wm8994_mic_work(struct work_struct *work)
3429 {
3430         struct wm8994_priv *priv = container_of(work,
3431                                                 struct wm8994_priv,
3432                                                 mic_work.work);
3433         struct regmap *regmap = priv->wm8994->regmap;
3434         struct device *dev = priv->wm8994->dev;
3435         unsigned int reg;
3436         int ret;
3437         int report;
3438 
3439         pm_runtime_get_sync(dev);
3440 
3441         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3442         if (ret < 0) {
3443                 dev_err(dev, "Failed to read microphone status: %d\n",
3444                         ret);
3445                 pm_runtime_put(dev);
3446                 return;
3447         }
3448 
3449         dev_dbg(dev, "Microphone status: %x\n", reg);
3450 
3451         report = 0;
3452         if (reg & WM8994_MIC1_DET_STS) {
3453                 if (priv->micdet[0].detecting)
3454                         report = SND_JACK_HEADSET;
3455         }
3456         if (reg & WM8994_MIC1_SHRT_STS) {
3457                 if (priv->micdet[0].detecting)
3458                         report = SND_JACK_HEADPHONE;
3459                 else
3460                         report |= SND_JACK_BTN_0;
3461         }
3462         if (report)
3463                 priv->micdet[0].detecting = false;
3464         else
3465                 priv->micdet[0].detecting = true;
3466 
3467         snd_soc_jack_report(priv->micdet[0].jack, report,
3468                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3469 
3470         report = 0;
3471         if (reg & WM8994_MIC2_DET_STS) {
3472                 if (priv->micdet[1].detecting)
3473                         report = SND_JACK_HEADSET;
3474         }
3475         if (reg & WM8994_MIC2_SHRT_STS) {
3476                 if (priv->micdet[1].detecting)
3477                         report = SND_JACK_HEADPHONE;
3478                 else
3479                         report |= SND_JACK_BTN_0;
3480         }
3481         if (report)
3482                 priv->micdet[1].detecting = false;
3483         else
3484                 priv->micdet[1].detecting = true;
3485 
3486         snd_soc_jack_report(priv->micdet[1].jack, report,
3487                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3488 
3489         pm_runtime_put(dev);
3490 }
3491 
3492 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3493 {
3494         struct wm8994_priv *priv = data;
3495         struct snd_soc_codec *codec = priv->hubs.codec;
3496 
3497 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3498         trace_snd_soc_jack_irq(dev_name(codec->dev));
3499 #endif
3500 
3501         pm_wakeup_event(codec->dev, 300);
3502 
3503         queue_delayed_work(system_power_efficient_wq,
3504                            &priv->mic_work, msecs_to_jiffies(250));
3505 
3506         return IRQ_HANDLED;
3507 }
3508 
3509 /* Should be called with accdet_lock held */
3510 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3511 {
3512         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3513 
3514         if (!wm8994->jackdet)
3515                 return;
3516 
3517         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3518 
3519         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3520 
3521         if (wm8994->wm8994->pdata.jd_ext_cap)
3522                 snd_soc_dapm_disable_pin(&codec->dapm,
3523                                          "MICBIAS2");
3524 }
3525 
3526 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3527 {
3528         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3529         int report;
3530 
3531         report = 0;
3532         if (status & 0x4)
3533                 report |= SND_JACK_BTN_0;
3534 
3535         if (status & 0x8)
3536                 report |= SND_JACK_BTN_1;
3537 
3538         if (status & 0x10)
3539                 report |= SND_JACK_BTN_2;
3540 
3541         if (status & 0x20)
3542                 report |= SND_JACK_BTN_3;
3543 
3544         if (status & 0x40)
3545                 report |= SND_JACK_BTN_4;
3546 
3547         if (status & 0x80)
3548                 report |= SND_JACK_BTN_5;
3549 
3550         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3551                             wm8994->btn_mask);
3552 }
3553 
3554 static void wm8958_open_circuit_work(struct work_struct *work)
3555 {
3556         struct wm8994_priv *wm8994 = container_of(work,
3557                                                   struct wm8994_priv,
3558                                                   open_circuit_work.work);
3559         struct device *dev = wm8994->wm8994->dev;
3560 
3561         mutex_lock(&wm8994->accdet_lock);
3562 
3563         wm1811_micd_stop(wm8994->hubs.codec);
3564 
3565         dev_dbg(dev, "Reporting open circuit\n");
3566 
3567         wm8994->jack_mic = false;
3568         wm8994->mic_detecting = true;
3569 
3570         wm8958_micd_set_rate(wm8994->hubs.codec);
3571 
3572         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3573                             wm8994->btn_mask |
3574                             SND_JACK_HEADSET);
3575 
3576         mutex_unlock(&wm8994->accdet_lock);
3577 }
3578 
3579 static void wm8958_mic_id(void *data, u16 status)
3580 {
3581         struct snd_soc_codec *codec = data;
3582         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3583 
3584         /* Either nothing present or just starting detection */
3585         if (!(status & WM8958_MICD_STS)) {
3586                 /* If nothing present then clear our statuses */
3587                 dev_dbg(codec->dev, "Detected open circuit\n");
3588 
3589                 queue_delayed_work(system_power_efficient_wq,
3590                                    &wm8994->open_circuit_work,
3591                                    msecs_to_jiffies(2500));
3592                 return;
3593         }
3594 
3595         /* If the measurement is showing a high impedence we've got a
3596          * microphone.
3597          */
3598         if (status & 0x600) {
3599                 dev_dbg(codec->dev, "Detected microphone\n");
3600 
3601                 wm8994->mic_detecting = false;
3602                 wm8994->jack_mic = true;
3603 
3604                 wm8958_micd_set_rate(codec);
3605 
3606                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3607                                     SND_JACK_HEADSET);
3608         }
3609 
3610 
3611         if (status & 0xfc) {
3612                 dev_dbg(codec->dev, "Detected headphone\n");
3613                 wm8994->mic_detecting = false;
3614 
3615                 wm8958_micd_set_rate(codec);
3616 
3617                 /* If we have jackdet that will detect removal */
3618                 wm1811_micd_stop(codec);
3619 
3620                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3621                                     SND_JACK_HEADSET);
3622         }
3623 }
3624 
3625 /* Deferred mic detection to allow for extra settling time */
3626 static void wm1811_mic_work(struct work_struct *work)
3627 {
3628         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3629                                                   mic_work.work);
3630         struct wm8994 *control = wm8994->wm8994;
3631         struct snd_soc_codec *codec = wm8994->hubs.codec;
3632 
3633         pm_runtime_get_sync(codec->dev);
3634 
3635         /* If required for an external cap force MICBIAS on */
3636         if (control->pdata.jd_ext_cap) {
3637                 snd_soc_dapm_force_enable_pin(&codec->dapm,
3638                                               "MICBIAS2");
3639                 snd_soc_dapm_sync(&codec->dapm);
3640         }
3641 
3642         mutex_lock(&wm8994->accdet_lock);
3643 
3644         dev_dbg(codec->dev, "Starting mic detection\n");
3645 
3646         /* Use a user-supplied callback if we have one */
3647         if (wm8994->micd_cb) {
3648                 wm8994->micd_cb(wm8994->micd_cb_data);
3649         } else {
3650                 /*
3651                  * Start off measument of microphone impedence to find out
3652                  * what's actually there.
3653                  */
3654                 wm8994->mic_detecting = true;
3655                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3656 
3657                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3658                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3659         }
3660 
3661         mutex_unlock(&wm8994->accdet_lock);
3662 
3663         pm_runtime_put(codec->dev);
3664 }
3665 
3666 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3667 {
3668         struct wm8994_priv *wm8994 = data;
3669         struct wm8994 *control = wm8994->wm8994;
3670         struct snd_soc_codec *codec = wm8994->hubs.codec;
3671         int reg, delay;
3672         bool present;
3673 
3674         pm_runtime_get_sync(codec->dev);
3675 
3676         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3677 
3678         mutex_lock(&wm8994->accdet_lock);
3679 
3680         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3681         if (reg < 0) {
3682                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3683                 mutex_unlock(&wm8994->accdet_lock);
3684                 pm_runtime_put(codec->dev);
3685                 return IRQ_NONE;
3686         }
3687 
3688         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3689 
3690         present = reg & WM1811_JACKDET_LVL;
3691 
3692         if (present) {
3693                 dev_dbg(codec->dev, "Jack detected\n");
3694 
3695                 wm8958_micd_set_rate(codec);
3696 
3697                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3698                                     WM8958_MICB2_DISCH, 0);
3699 
3700                 /* Disable debounce while inserted */
3701                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3702                                     WM1811_JACKDET_DB, 0);
3703 
3704                 delay = control->pdata.micdet_delay;
3705                 queue_delayed_work(system_power_efficient_wq,
3706                                    &wm8994->mic_work,
3707                                    msecs_to_jiffies(delay));
3708         } else {
3709                 dev_dbg(codec->dev, "Jack not detected\n");
3710 
3711                 cancel_delayed_work_sync(&wm8994->mic_work);
3712 
3713                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3714                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3715 
3716                 /* Enable debounce while removed */
3717                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3718                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3719 
3720                 wm8994->mic_detecting = false;
3721                 wm8994->jack_mic = false;
3722                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3723                                     WM8958_MICD_ENA, 0);
3724                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3725         }
3726 
3727         mutex_unlock(&wm8994->accdet_lock);
3728 
3729         /* Turn off MICBIAS if it was on for an external cap */
3730         if (control->pdata.jd_ext_cap && !present)
3731                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3732 
3733         if (present)
3734                 snd_soc_jack_report(wm8994->micdet[0].jack,
3735                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3736         else
3737                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3738                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3739                                     wm8994->btn_mask);
3740 
3741         /* Since we only report deltas force an update, ensures we
3742          * avoid bootstrapping issues with the core. */
3743         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3744 
3745         pm_runtime_put(codec->dev);
3746         return IRQ_HANDLED;
3747 }
3748 
3749 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3750 {
3751         struct wm8994_priv *wm8994 = container_of(work,
3752                                                 struct wm8994_priv,
3753                                                 jackdet_bootstrap.work);
3754         wm1811_jackdet_irq(0, wm8994);
3755 }
3756 
3757 /**
3758  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3759  *
3760  * @codec:   WM8958 codec
3761  * @jack:    jack to report detection events on
3762  *
3763  * Enable microphone detection functionality for the WM8958.  By
3764  * default simple detection which supports the detection of up to 6
3765  * buttons plus video and microphone functionality is supported.
3766  *
3767  * The WM8958 has an advanced jack detection facility which is able to
3768  * support complex accessory detection, especially when used in
3769  * conjunction with external circuitry.  In order to provide maximum
3770  * flexiblity a callback is provided which allows a completely custom
3771  * detection algorithm.
3772  */
3773 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3774                       wm1811_micdet_cb det_cb, void *det_cb_data,
3775                       wm1811_mic_id_cb id_cb, void *id_cb_data)
3776 {
3777         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3778         struct wm8994 *control = wm8994->wm8994;
3779         u16 micd_lvl_sel;
3780 
3781         switch (control->type) {
3782         case WM1811:
3783         case WM8958:
3784                 break;
3785         default:
3786                 return -EINVAL;
3787         }
3788 
3789         if (jack) {
3790                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3791                 snd_soc_dapm_sync(&codec->dapm);
3792 
3793                 wm8994->micdet[0].jack = jack;
3794 
3795                 if (det_cb) {
3796                         wm8994->micd_cb = det_cb;
3797                         wm8994->micd_cb_data = det_cb_data;
3798                 } else {
3799                         wm8994->mic_detecting = true;
3800                         wm8994->jack_mic = false;
3801                 }
3802 
3803                 if (id_cb) {
3804                         wm8994->mic_id_cb = id_cb;
3805                         wm8994->mic_id_cb_data = id_cb_data;
3806                 } else {
3807                         wm8994->mic_id_cb = wm8958_mic_id;
3808                         wm8994->mic_id_cb_data = codec;
3809                 }
3810 
3811                 wm8958_micd_set_rate(codec);
3812 
3813                 /* Detect microphones and short circuits by default */
3814                 if (control->pdata.micd_lvl_sel)
3815                         micd_lvl_sel = control->pdata.micd_lvl_sel;
3816                 else
3817                         micd_lvl_sel = 0x41;
3818 
3819                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3820                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3821                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3822 
3823                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3824                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3825 
3826                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3827 
3828                 /*
3829                  * If we can use jack detection start off with that,
3830                  * otherwise jump straight to microphone detection.
3831                  */
3832                 if (wm8994->jackdet) {
3833                         /* Disable debounce for the initial detect */
3834                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3835                                             WM1811_JACKDET_DB, 0);
3836 
3837                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3838                                             WM8958_MICB2_DISCH,
3839                                             WM8958_MICB2_DISCH);
3840                         snd_soc_update_bits(codec, WM8994_LDO_1,
3841                                             WM8994_LDO1_DISCH, 0);
3842                         wm1811_jackdet_set_mode(codec,
3843                                                 WM1811_JACKDET_MODE_JACK);
3844                 } else {
3845                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3846                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3847                 }
3848 
3849         } else {
3850                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3851                                     WM8958_MICD_ENA, 0);
3852                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3853                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3854                 snd_soc_dapm_sync(&codec->dapm);
3855         }
3856 
3857         return 0;
3858 }
3859 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3860 
3861 static void wm8958_mic_work(struct work_struct *work)
3862 {
3863         struct wm8994_priv *wm8994 = container_of(work,
3864                                                   struct wm8994_priv,
3865                                                   mic_complete_work.work);
3866         struct snd_soc_codec *codec = wm8994->hubs.codec;
3867 
3868         pm_runtime_get_sync(codec->dev);
3869 
3870         mutex_lock(&wm8994->accdet_lock);
3871 
3872         wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3873 
3874         mutex_unlock(&wm8994->accdet_lock);
3875 
3876         pm_runtime_put(codec->dev);
3877 }
3878 
3879 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3880 {
3881         struct wm8994_priv *wm8994 = data;
3882         struct snd_soc_codec *codec = wm8994->hubs.codec;
3883         int reg, count, ret, id_delay;
3884 
3885         /*
3886          * Jack detection may have detected a removal simulataneously
3887          * with an update of the MICDET status; if so it will have
3888          * stopped detection and we can ignore this interrupt.
3889          */
3890         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3891                 return IRQ_HANDLED;
3892 
3893         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3894         cancel_delayed_work_sync(&wm8994->open_circuit_work);
3895 
3896         pm_runtime_get_sync(codec->dev);
3897 
3898         /* We may occasionally read a detection without an impedence
3899          * range being provided - if that happens loop again.
3900          */
3901         count = 10;
3902         do {
3903                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3904                 if (reg < 0) {
3905                         dev_err(codec->dev,
3906                                 "Failed to read mic detect status: %d\n",
3907                                 reg);
3908                         pm_runtime_put(codec->dev);
3909                         return IRQ_NONE;
3910                 }
3911 
3912                 if (!(reg & WM8958_MICD_VALID)) {
3913                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3914                         goto out;
3915                 }
3916 
3917                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3918                         break;
3919 
3920                 msleep(1);
3921         } while (count--);
3922 
3923         if (count == 0)
3924                 dev_warn(codec->dev, "No impedance range reported for jack\n");
3925 
3926 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3927         trace_snd_soc_jack_irq(dev_name(codec->dev));
3928 #endif
3929 
3930         /* Avoid a transient report when the accessory is being removed */
3931         if (wm8994->jackdet) {
3932                 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3933                 if (ret < 0) {
3934                         dev_err(codec->dev, "Failed to read jack status: %d\n",
3935                                 ret);
3936                 } else if (!(ret & WM1811_JACKDET_LVL)) {
3937                         dev_dbg(codec->dev, "Ignoring removed jack\n");
3938                         goto out;
3939                 }
3940         } else if (!(reg & WM8958_MICD_STS)) {
3941                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3942                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3943                                     wm8994->btn_mask);
3944                 wm8994->mic_detecting = true;
3945                 goto out;
3946         }
3947 
3948         wm8994->mic_status = reg;
3949         id_delay = wm8994->wm8994->pdata.mic_id_delay;
3950 
3951         if (wm8994->mic_detecting)
3952                 queue_delayed_work(system_power_efficient_wq,
3953                                    &wm8994->mic_complete_work,
3954                                    msecs_to_jiffies(id_delay));
3955         else
3956                 wm8958_button_det(codec, reg);
3957 
3958 out:
3959         pm_runtime_put(codec->dev);
3960         return IRQ_HANDLED;
3961 }
3962 
3963 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3964 {
3965         struct snd_soc_codec *codec = data;
3966 
3967         dev_err(codec->dev, "FIFO error\n");
3968 
3969         return IRQ_HANDLED;
3970 }
3971 
3972 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3973 {
3974         struct snd_soc_codec *codec = data;
3975 
3976         dev_err(codec->dev, "Thermal warning\n");
3977 
3978         return IRQ_HANDLED;
3979 }
3980 
3981 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3982 {
3983         struct snd_soc_codec *codec = data;
3984 
3985         dev_crit(codec->dev, "Thermal shutdown\n");
3986 
3987         return IRQ_HANDLED;
3988 }
3989 
3990 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3991 {
3992         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3993         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3994         struct snd_soc_dapm_context *dapm = &codec->dapm;
3995         unsigned int reg;
3996         int ret, i;
3997 
3998         wm8994->hubs.codec = codec;
3999 
4000         mutex_init(&wm8994->accdet_lock);
4001         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4002                           wm1811_jackdet_bootstrap);
4003         INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4004                           wm8958_open_circuit_work);
4005 
4006         switch (control->type) {
4007         case WM8994:
4008                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4009                 break;
4010         case WM1811:
4011                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4012                 break;
4013         default:
4014                 break;
4015         }
4016 
4017         INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4018 
4019         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4020                 init_completion(&wm8994->fll_locked[i]);
4021 
4022         wm8994->micdet_irq = control->pdata.micdet_irq;
4023 
4024         /* By default use idle_bias_off, will override for WM8994 */
4025         codec->dapm.idle_bias_off = 1;
4026 
4027         /* Set revision-specific configuration */
4028         switch (control->type) {
4029         case WM8994:
4030                 /* Single ended line outputs should have VMID on. */
4031                 if (!control->pdata.lineout1_diff ||
4032                     !control->pdata.lineout2_diff)
4033                         codec->dapm.idle_bias_off = 0;
4034 
4035                 switch (control->revision) {
4036                 case 2:
4037                 case 3:
4038                         wm8994->hubs.dcs_codes_l = -5;
4039                         wm8994->hubs.dcs_codes_r = -5;
4040                         wm8994->hubs.hp_startup_mode = 1;
4041                         wm8994->hubs.dcs_readback_mode = 1;
4042                         wm8994->hubs.series_startup = 1;
4043                         break;
4044                 default:
4045                         wm8994->hubs.dcs_readback_mode = 2;
4046                         break;
4047                 }
4048                 break;
4049 
4050         case WM8958:
4051                 wm8994->hubs.dcs_readback_mode = 1;
4052                 wm8994->hubs.hp_startup_mode = 1;
4053 
4054                 switch (control->revision) {
4055                 case 0:
4056                         break;
4057                 default:
4058                         wm8994->fll_byp = true;
4059                         break;
4060                 }
4061                 break;
4062 
4063         case WM1811:
4064                 wm8994->hubs.dcs_readback_mode = 2;
4065                 wm8994->hubs.no_series_update = 1;
4066                 wm8994->hubs.hp_startup_mode = 1;
4067                 wm8994->hubs.no_cache_dac_hp_direct = true;
4068                 wm8994->fll_byp = true;
4069 
4070                 wm8994->hubs.dcs_codes_l = -9;
4071                 wm8994->hubs.dcs_codes_r = -7;
4072 
4073                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4074                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4075                 break;
4076 
4077         default:
4078                 break;
4079         }
4080 
4081         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4082                            wm8994_fifo_error, "FIFO error", codec);
4083         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4084                            wm8994_temp_warn, "Thermal warning", codec);
4085         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4086                            wm8994_temp_shut, "Thermal shutdown", codec);
4087 
4088         switch (control->type) {
4089         case WM8994:
4090                 if (wm8994->micdet_irq) {
4091                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4092                                                    wm8994_mic_irq,
4093                                                    IRQF_TRIGGER_RISING,
4094                                                    "Mic1 detect",
4095                                                    wm8994);
4096                         if (ret != 0)
4097                                 dev_warn(codec->dev,
4098                                          "Failed to request Mic1 detect IRQ: %d\n",
4099                                          ret);
4100                 }
4101 
4102                 ret = wm8994_request_irq(wm8994->wm8994,
4103                                          WM8994_IRQ_MIC1_SHRT,
4104                                          wm8994_mic_irq, "Mic 1 short",
4105                                          wm8994);
4106                 if (ret != 0)
4107                         dev_warn(codec->dev,
4108                                  "Failed to request Mic1 short IRQ: %d\n",
4109                                  ret);
4110 
4111                 ret = wm8994_request_irq(wm8994->wm8994,
4112                                          WM8994_IRQ_MIC2_DET,
4113                                          wm8994_mic_irq, "Mic 2 detect",
4114                                          wm8994);
4115                 if (ret != 0)
4116                         dev_warn(codec->dev,
4117                                  "Failed to request Mic2 detect IRQ: %d\n",
4118                                  ret);
4119 
4120                 ret = wm8994_request_irq(wm8994->wm8994,
4121                                          WM8994_IRQ_MIC2_SHRT,
4122                                          wm8994_mic_irq, "Mic 2 short",
4123                                          wm8994);
4124                 if (ret != 0)
4125                         dev_warn(codec->dev,
4126                                  "Failed to request Mic2 short IRQ: %d\n",
4127                                  ret);
4128                 break;
4129 
4130         case WM8958:
4131         case WM1811:
4132                 if (wm8994->micdet_irq) {
4133                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4134                                                    wm8958_mic_irq,
4135                                                    IRQF_TRIGGER_RISING,
4136                                                    "Mic detect",
4137                                                    wm8994);
4138                         if (ret != 0)
4139                                 dev_warn(codec->dev,
4140                                          "Failed to request Mic detect IRQ: %d\n",
4141                                          ret);
4142                 } else {
4143                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4144                                            wm8958_mic_irq, "Mic detect",
4145                                            wm8994);
4146                 }
4147         }
4148 
4149         switch (control->type) {
4150         case WM1811:
4151                 if (control->cust_id > 1 || control->revision > 1) {
4152                         ret = wm8994_request_irq(wm8994->wm8994,
4153                                                  WM8994_IRQ_GPIO(6),
4154                                                  wm1811_jackdet_irq, "JACKDET",
4155                                                  wm8994);
4156                         if (ret == 0)
4157                                 wm8994->jackdet = true;
4158                 }
4159                 break;
4160         default:
4161                 break;
4162         }
4163 
4164         wm8994->fll_locked_irq = true;
4165         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4166                 ret = wm8994_request_irq(wm8994->wm8994,
4167                                          WM8994_IRQ_FLL1_LOCK + i,
4168                                          wm8994_fll_locked_irq, "FLL lock",
4169                                          &wm8994->fll_locked[i]);
4170                 if (ret != 0)
4171                         wm8994->fll_locked_irq = false;
4172         }
4173 
4174         /* Make sure we can read from the GPIOs if they're inputs */
4175         pm_runtime_get_sync(codec->dev);
4176 
4177         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
4178          * configured on init - if a system wants to do this dynamically
4179          * at runtime we can deal with that then.
4180          */
4181         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4182         if (ret < 0) {
4183                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4184                 goto err_irq;
4185         }
4186         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4187                 wm8994->lrclk_shared[0] = 1;
4188                 wm8994_dai[0].symmetric_rates = 1;
4189         } else {
4190                 wm8994->lrclk_shared[0] = 0;
4191         }
4192 
4193         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4194         if (ret < 0) {
4195                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4196                 goto err_irq;
4197         }
4198         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4199                 wm8994->lrclk_shared[1] = 1;
4200                 wm8994_dai[1].symmetric_rates = 1;
4201         } else {
4202                 wm8994->lrclk_shared[1] = 0;
4203         }
4204 
4205         pm_runtime_put(codec->dev);
4206 
4207         /* Latch volume update bits */
4208         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4209                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4210                                     wm8994_vu_bits[i].mask,
4211                                     wm8994_vu_bits[i].mask);
4212 
4213         /* Set the low bit of the 3D stereo depth so TLV matches */
4214         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4215                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4216                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4217         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4218                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4219                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4220         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4221                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4222                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4223 
4224         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4225          * use this; it only affects behaviour on idle TDM clock
4226          * cycles. */
4227         switch (control->type) {
4228         case WM8994:
4229         case WM8958:
4230                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4231                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4232                 break;
4233         default:
4234                 break;
4235         }
4236 
4237         /* Put MICBIAS into bypass mode by default on newer devices */
4238         switch (control->type) {
4239         case WM8958:
4240         case WM1811:
4241                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4242                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4243                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4244                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4245                 break;
4246         default:
4247                 break;
4248         }
4249 
4250         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4251         wm_hubs_update_class_w(codec);
4252 
4253         wm8994_handle_pdata(wm8994);
4254 
4255         wm_hubs_add_analogue_controls(codec);
4256         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4257                              ARRAY_SIZE(wm8994_snd_controls));
4258         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4259                                   ARRAY_SIZE(wm8994_dapm_widgets));
4260 
4261         switch (control->type) {
4262         case WM8994:
4263                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4264                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4265                 if (control->revision < 4) {
4266                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4267                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4268                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4269                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4270                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4271                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4272                 } else {
4273                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4274                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4275                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4276                                                   ARRAY_SIZE(wm8994_adc_widgets));
4277                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4278                                                   ARRAY_SIZE(wm8994_dac_widgets));
4279                 }
4280                 break;
4281         case WM8958:
4282                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4283                                      ARRAY_SIZE(wm8958_snd_controls));
4284                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4285                                           ARRAY_SIZE(wm8958_dapm_widgets));
4286                 if (control->revision < 1) {
4287                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4288                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4289                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4290                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4291                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4292                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4293                 } else {
4294                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4295                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4296                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4297                                                   ARRAY_SIZE(wm8994_adc_widgets));
4298                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4299                                                   ARRAY_SIZE(wm8994_dac_widgets));
4300                 }
4301                 break;
4302 
4303         case WM1811:
4304                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4305                                      ARRAY_SIZE(wm8958_snd_controls));
4306                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4307                                           ARRAY_SIZE(wm8958_dapm_widgets));
4308                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4309                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4310                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4311                                           ARRAY_SIZE(wm8994_adc_widgets));
4312                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4313                                           ARRAY_SIZE(wm8994_dac_widgets));
4314                 break;
4315         }
4316 
4317         wm_hubs_add_analogue_routes(codec, 0, 0);
4318         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4319                                  wm_hubs_dcs_done, "DC servo done",
4320                                  &wm8994->hubs);
4321         if (ret == 0)
4322                 wm8994->hubs.dcs_done_irq = true;
4323         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4324 
4325         switch (control->type) {
4326         case WM8994:
4327                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4328                                         ARRAY_SIZE(wm8994_intercon));
4329 
4330                 if (control->revision < 4) {
4331                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4332                                                 ARRAY_SIZE(wm8994_revd_intercon));
4333                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4334                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4335                 } else {
4336                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4337                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4338                 }
4339                 break;
4340         case WM8958:
4341                 if (control->revision < 1) {
4342                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4343                                                 ARRAY_SIZE(wm8994_intercon));
4344                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4345                                                 ARRAY_SIZE(wm8994_revd_intercon));
4346                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4347                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4348                 } else {
4349                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4350                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4351                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4352                                                 ARRAY_SIZE(wm8958_intercon));
4353                 }
4354 
4355                 wm8958_dsp2_init(codec);
4356                 break;
4357         case WM1811:
4358                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4359                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4360                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4361                                         ARRAY_SIZE(wm8958_intercon));
4362                 break;
4363         }
4364 
4365         return 0;
4366 
4367 err_irq:
4368         if (wm8994->jackdet)
4369                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4370         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4371         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4372         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4373         if (wm8994->micdet_irq)
4374                 free_irq(wm8994->micdet_irq, wm8994);
4375         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4376                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4377                                 &wm8994->fll_locked[i]);
4378         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4379                         &wm8994->hubs);
4380         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4381         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4382         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4383 
4384         return ret;
4385 }
4386 
4387 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4388 {
4389         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4390         struct wm8994 *control = wm8994->wm8994;
4391         int i;
4392 
4393         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4394 
4395         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4396                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4397                                 &wm8994->fll_locked[i]);
4398 
4399         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4400                         &wm8994->hubs);
4401         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4402         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4403         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4404 
4405         if (wm8994->jackdet)
4406                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4407 
4408         switch (control->type) {
4409         case WM8994:
4410                 if (wm8994->micdet_irq)
4411                         free_irq(wm8994->micdet_irq, wm8994);
4412                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4413                                 wm8994);
4414                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4415                                 wm8994);
4416                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4417                                 wm8994);
4418                 break;
4419 
4420         case WM1811:
4421         case WM8958:
4422                 if (wm8994->micdet_irq)
4423                         free_irq(wm8994->micdet_irq, wm8994);
4424                 break;
4425         }
4426         release_firmware(wm8994->mbc);
4427         release_firmware(wm8994->mbc_vss);
4428         release_firmware(wm8994->enh_eq);
4429         kfree(wm8994->retune_mobile_texts);
4430         return 0;
4431 }
4432 
4433 static struct regmap *wm8994_get_regmap(struct device *dev)
4434 {
4435         struct wm8994 *control = dev_get_drvdata(dev->parent);
4436 
4437         return control->regmap;
4438 }
4439 
4440 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4441         .probe =        wm8994_codec_probe,
4442         .remove =       wm8994_codec_remove,
4443         .suspend =      wm8994_codec_suspend,
4444         .resume =       wm8994_codec_resume,
4445         .get_regmap =   wm8994_get_regmap,
4446         .set_bias_level = wm8994_set_bias_level,
4447 };
4448 
4449 static int wm8994_probe(struct platform_device *pdev)
4450 {
4451         struct wm8994_priv *wm8994;
4452 
4453         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4454                               GFP_KERNEL);
4455         if (wm8994 == NULL)
4456                 return -ENOMEM;
4457         platform_set_drvdata(pdev, wm8994);
4458 
4459         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4460 
4461         pm_runtime_enable(&pdev->dev);
4462         pm_runtime_idle(&pdev->dev);
4463 
4464         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4465                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4466 }
4467 
4468 static int wm8994_remove(struct platform_device *pdev)
4469 {
4470         snd_soc_unregister_codec(&pdev->dev);
4471         pm_runtime_disable(&pdev->dev);
4472 
4473         return 0;
4474 }
4475 
4476 #ifdef CONFIG_PM_SLEEP
4477 static int wm8994_suspend(struct device *dev)
4478 {
4479         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4480 
4481         /* Drop down to power saving mode when system is suspended */
4482         if (wm8994->jackdet && !wm8994->active_refcount)
4483                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4484                                    WM1811_JACKDET_MODE_MASK,
4485                                    wm8994->jackdet_mode);
4486 
4487         return 0;
4488 }
4489 
4490 static int wm8994_resume(struct device *dev)
4491 {
4492         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4493 
4494         if (wm8994->jackdet && wm8994->jackdet_mode)
4495                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4496                                    WM1811_JACKDET_MODE_MASK,
4497                                    WM1811_JACKDET_MODE_AUDIO);
4498 
4499         return 0;
4500 }
4501 #endif
4502 
4503 static const struct dev_pm_ops wm8994_pm_ops = {
4504         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4505 };
4506 
4507 static struct platform_driver wm8994_codec_driver = {
4508         .driver = {
4509                 .name = "wm8994-codec",
4510                 .owner = THIS_MODULE,
4511                 .pm = &wm8994_pm_ops,
4512         },
4513         .probe = wm8994_probe,
4514         .remove = wm8994_remove,
4515 };
4516 
4517 module_platform_driver(wm8994_codec_driver);
4518 
4519 MODULE_DESCRIPTION("ASoC WM8994 driver");
4520 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4521 MODULE_LICENSE("GPL");
4522 MODULE_ALIAS("platform:wm8994-codec");
4523 

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