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TOMOYO Linux Cross Reference
Linux/sound/soc/davinci/davinci-mcasp.c

Version: ~ [ linux-5.10-rc5 ] ~ [ linux-5.9.10 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.79 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.159 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.208 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.245 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.245 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/pm_runtime.h>
 25 #include <linux/of.h>
 26 #include <linux/of_platform.h>
 27 #include <linux/of_device.h>
 28 
 29 #include <sound/core.h>
 30 #include <sound/pcm.h>
 31 #include <sound/pcm_params.h>
 32 #include <sound/initval.h>
 33 #include <sound/soc.h>
 34 
 35 #include "davinci-pcm.h"
 36 #include "davinci-mcasp.h"
 37 
 38 /*
 39  * McASP register definitions
 40  */
 41 #define DAVINCI_MCASP_PID_REG           0x00
 42 #define DAVINCI_MCASP_PWREMUMGT_REG     0x04
 43 
 44 #define DAVINCI_MCASP_PFUNC_REG         0x10
 45 #define DAVINCI_MCASP_PDIR_REG          0x14
 46 #define DAVINCI_MCASP_PDOUT_REG         0x18
 47 #define DAVINCI_MCASP_PDSET_REG         0x1c
 48 
 49 #define DAVINCI_MCASP_PDCLR_REG         0x20
 50 
 51 #define DAVINCI_MCASP_TLGC_REG          0x30
 52 #define DAVINCI_MCASP_TLMR_REG          0x34
 53 
 54 #define DAVINCI_MCASP_GBLCTL_REG        0x44
 55 #define DAVINCI_MCASP_AMUTE_REG         0x48
 56 #define DAVINCI_MCASP_LBCTL_REG         0x4c
 57 
 58 #define DAVINCI_MCASP_TXDITCTL_REG      0x50
 59 
 60 #define DAVINCI_MCASP_GBLCTLR_REG       0x60
 61 #define DAVINCI_MCASP_RXMASK_REG        0x64
 62 #define DAVINCI_MCASP_RXFMT_REG         0x68
 63 #define DAVINCI_MCASP_RXFMCTL_REG       0x6c
 64 
 65 #define DAVINCI_MCASP_ACLKRCTL_REG      0x70
 66 #define DAVINCI_MCASP_AHCLKRCTL_REG     0x74
 67 #define DAVINCI_MCASP_RXTDM_REG         0x78
 68 #define DAVINCI_MCASP_EVTCTLR_REG       0x7c
 69 
 70 #define DAVINCI_MCASP_RXSTAT_REG        0x80
 71 #define DAVINCI_MCASP_RXTDMSLOT_REG     0x84
 72 #define DAVINCI_MCASP_RXCLKCHK_REG      0x88
 73 #define DAVINCI_MCASP_REVTCTL_REG       0x8c
 74 
 75 #define DAVINCI_MCASP_GBLCTLX_REG       0xa0
 76 #define DAVINCI_MCASP_TXMASK_REG        0xa4
 77 #define DAVINCI_MCASP_TXFMT_REG         0xa8
 78 #define DAVINCI_MCASP_TXFMCTL_REG       0xac
 79 
 80 #define DAVINCI_MCASP_ACLKXCTL_REG      0xb0
 81 #define DAVINCI_MCASP_AHCLKXCTL_REG     0xb4
 82 #define DAVINCI_MCASP_TXTDM_REG         0xb8
 83 #define DAVINCI_MCASP_EVTCTLX_REG       0xbc
 84 
 85 #define DAVINCI_MCASP_TXSTAT_REG        0xc0
 86 #define DAVINCI_MCASP_TXTDMSLOT_REG     0xc4
 87 #define DAVINCI_MCASP_TXCLKCHK_REG      0xc8
 88 #define DAVINCI_MCASP_XEVTCTL_REG       0xcc
 89 
 90 /* Left(even TDM Slot) Channel Status Register File */
 91 #define DAVINCI_MCASP_DITCSRA_REG       0x100
 92 /* Right(odd TDM slot) Channel Status Register File */
 93 #define DAVINCI_MCASP_DITCSRB_REG       0x118
 94 /* Left(even TDM slot) User Data Register File */
 95 #define DAVINCI_MCASP_DITUDRA_REG       0x130
 96 /* Right(odd TDM Slot) User Data Register File */
 97 #define DAVINCI_MCASP_DITUDRB_REG       0x148
 98 
 99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG  0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n)    (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102                                                 (n << 2))
103 
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG         0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG         0x280
108 
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL          (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS          (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL          (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS          (0x101C)
114 #define MCASP_VER3_WFIFOCTL             (0x1000)
115 #define MCASP_VER3_WFIFOSTS             (0x1004)
116 #define MCASP_VER3_RFIFOCTL             (0x1008)
117 #define MCASP_VER3_RFIFOSTS             (0x100C)
118 
119 /*
120  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121  *     Register Bits
122  */
123 #define MCASP_FREE      BIT(0)
124 #define MCASP_SOFT      BIT(1)
125 
126 /*
127  * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128  */
129 #define AXR(n)          (1<<n)
130 #define PFUNC_AMUTE     BIT(25)
131 #define ACLKX           BIT(26)
132 #define AHCLKX          BIT(27)
133 #define AFSX            BIT(28)
134 #define ACLKR           BIT(29)
135 #define AHCLKR          BIT(30)
136 #define AFSR            BIT(31)
137 
138 /*
139  * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140  */
141 #define AXR(n)          (1<<n)
142 #define PDIR_AMUTE      BIT(25)
143 #define ACLKX           BIT(26)
144 #define AHCLKX          BIT(27)
145 #define AFSX            BIT(28)
146 #define ACLKR           BIT(29)
147 #define AHCLKR          BIT(30)
148 #define AFSR            BIT(31)
149 
150 /*
151  * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152  */
153 #define DITEN   BIT(0)  /* Transmit DIT mode enable/disable */
154 #define VA      BIT(2)
155 #define VB      BIT(3)
156 
157 /*
158  * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159  */
160 #define TXROT(val)      (val)
161 #define TXSEL           BIT(3)
162 #define TXSSZ(val)      (val<<4)
163 #define TXPBIT(val)     (val<<8)
164 #define TXPAD(val)      (val<<13)
165 #define TXORD           BIT(15)
166 #define FSXDLY(val)     (val<<16)
167 
168 /*
169  * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170  */
171 #define RXROT(val)      (val)
172 #define RXSEL           BIT(3)
173 #define RXSSZ(val)      (val<<4)
174 #define RXPBIT(val)     (val<<8)
175 #define RXPAD(val)      (val<<13)
176 #define RXORD           BIT(15)
177 #define FSRDLY(val)     (val<<16)
178 
179 /*
180  * DAVINCI_MCASP_TXFMCTL_REG -  Transmit Frame Control Register Bits
181  */
182 #define FSXPOL          BIT(0)
183 #define AFSXE           BIT(1)
184 #define FSXDUR          BIT(4)
185 #define FSXMOD(val)     (val<<7)
186 
187 /*
188  * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189  */
190 #define FSRPOL          BIT(0)
191 #define AFSRE           BIT(1)
192 #define FSRDUR          BIT(4)
193 #define FSRMOD(val)     (val<<7)
194 
195 /*
196  * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197  */
198 #define ACLKXDIV(val)   (val)
199 #define ACLKXE          BIT(5)
200 #define TX_ASYNC        BIT(6)
201 #define ACLKXPOL        BIT(7)
202 #define ACLKXDIV_MASK   0x1f
203 
204 /*
205  * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206  */
207 #define ACLKRDIV(val)   (val)
208 #define ACLKRE          BIT(5)
209 #define RX_ASYNC        BIT(6)
210 #define ACLKRPOL        BIT(7)
211 #define ACLKRDIV_MASK   0x1f
212 
213 /*
214  * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215  *     Register Bits
216  */
217 #define AHCLKXDIV(val)  (val)
218 #define AHCLKXPOL       BIT(14)
219 #define AHCLKXE         BIT(15)
220 #define AHCLKXDIV_MASK  0xfff
221 
222 /*
223  * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224  *     Register Bits
225  */
226 #define AHCLKRDIV(val)  (val)
227 #define AHCLKRPOL       BIT(14)
228 #define AHCLKRE         BIT(15)
229 #define AHCLKRDIV_MASK  0xfff
230 
231 /*
232  * DAVINCI_MCASP_XRSRCTL_BASE_REG -  Serializer Control Register Bits
233  */
234 #define MODE(val)       (val)
235 #define DISMOD          (val)(val<<2)
236 #define TXSTATE         BIT(4)
237 #define RXSTATE         BIT(5)
238 #define SRMOD_MASK      3
239 #define SRMOD_INACTIVE  0
240 
241 /*
242  * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
243  */
244 #define LBEN            BIT(0)
245 #define LBORD           BIT(1)
246 #define LBGENMODE(val)  (val<<2)
247 
248 /*
249  * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
250  */
251 #define TXTDMS(n)       (1<<n)
252 
253 /*
254  * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
255  */
256 #define RXTDMS(n)       (1<<n)
257 
258 /*
259  * DAVINCI_MCASP_GBLCTL_REG -  Global Control Register Bits
260  */
261 #define RXCLKRST        BIT(0)  /* Receiver Clock Divider Reset */
262 #define RXHCLKRST       BIT(1)  /* Receiver High Frequency Clock Divider */
263 #define RXSERCLR        BIT(2)  /* Receiver Serializer Clear */
264 #define RXSMRST         BIT(3)  /* Receiver State Machine Reset */
265 #define RXFSRST         BIT(4)  /* Frame Sync Generator Reset */
266 #define TXCLKRST        BIT(8)  /* Transmitter Clock Divider Reset */
267 #define TXHCLKRST       BIT(9)  /* Transmitter High Frequency Clock Divider*/
268 #define TXSERCLR        BIT(10) /* Transmit Serializer Clear */
269 #define TXSMRST         BIT(11) /* Transmitter State Machine Reset */
270 #define TXFSRST         BIT(12) /* Frame Sync Generator Reset */
271 
272 /*
273  * DAVINCI_MCASP_AMUTE_REG -  Mute Control Register Bits
274  */
275 #define MUTENA(val)     (val)
276 #define MUTEINPOL       BIT(2)
277 #define MUTEINENA       BIT(3)
278 #define MUTEIN          BIT(4)
279 #define MUTER           BIT(5)
280 #define MUTEX           BIT(6)
281 #define MUTEFSR         BIT(7)
282 #define MUTEFSX         BIT(8)
283 #define MUTEBADCLKR     BIT(9)
284 #define MUTEBADCLKX     BIT(10)
285 #define MUTERXDMAERR    BIT(11)
286 #define MUTETXDMAERR    BIT(12)
287 
288 /*
289  * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
290  */
291 #define RXDATADMADIS    BIT(0)
292 
293 /*
294  * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
295  */
296 #define TXDATADMADIS    BIT(0)
297 
298 /*
299  * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
300  */
301 #define FIFO_ENABLE     BIT(16)
302 #define NUMEVT_MASK     (0xFF << 8)
303 #define NUMDMA_MASK     (0xFF)
304 
305 #define DAVINCI_MCASP_NUM_SERIALIZER    16
306 
307 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
308 {
309         __raw_writel(__raw_readl(reg) | val, reg);
310 }
311 
312 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
313 {
314         __raw_writel((__raw_readl(reg) & ~(val)), reg);
315 }
316 
317 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
318 {
319         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
320 }
321 
322 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
323 {
324         __raw_writel(val, reg);
325 }
326 
327 static inline u32 mcasp_get_reg(void __iomem *reg)
328 {
329         return (unsigned int)__raw_readl(reg);
330 }
331 
332 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
333 {
334         int i = 0;
335 
336         mcasp_set_bits(regs, val);
337 
338         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
339         /* loop count is to avoid the lock-up */
340         for (i = 0; i < 1000; i++) {
341                 if ((mcasp_get_reg(regs) & val) == val)
342                         break;
343         }
344 
345         if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
346                 printk(KERN_ERR "GBLCTL write error\n");
347 }
348 
349 static void mcasp_start_rx(struct davinci_audio_dev *dev)
350 {
351         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
352         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
353         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
354         mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
355 
356         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
357         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
358         mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
359 
360         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
361         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
362 }
363 
364 static void mcasp_start_tx(struct davinci_audio_dev *dev)
365 {
366         u8 offset = 0, i;
367         u32 cnt;
368 
369         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
370         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
371         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
372         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
373 
374         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
375         mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
376         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
377         for (i = 0; i < dev->num_serializer; i++) {
378                 if (dev->serial_dir[i] == TX_MODE) {
379                         offset = i;
380                         break;
381                 }
382         }
383 
384         /* wait for TX ready */
385         cnt = 0;
386         while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
387                  TXSTATE) && (cnt < 100000))
388                 cnt++;
389 
390         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
391 }
392 
393 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
394 {
395         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
396                 if (dev->txnumevt) {    /* enable FIFO */
397                         switch (dev->version) {
398                         case MCASP_VERSION_3:
399                                 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
400                                                                 FIFO_ENABLE);
401                                 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
402                                                                 FIFO_ENABLE);
403                                 break;
404                         default:
405                                 mcasp_clr_bits(dev->base +
406                                         DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407                                 mcasp_set_bits(dev->base +
408                                         DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
409                         }
410                 }
411                 mcasp_start_tx(dev);
412         } else {
413                 if (dev->rxnumevt) {    /* enable FIFO */
414                         switch (dev->version) {
415                         case MCASP_VERSION_3:
416                                 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
417                                                                 FIFO_ENABLE);
418                                 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
419                                                                 FIFO_ENABLE);
420                                 break;
421                         default:
422                                 mcasp_clr_bits(dev->base +
423                                         DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424                                 mcasp_set_bits(dev->base +
425                                         DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
426                         }
427                 }
428                 mcasp_start_rx(dev);
429         }
430 }
431 
432 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
433 {
434         mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
435         mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
436 }
437 
438 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
439 {
440         mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
441         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
442 }
443 
444 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
445 {
446         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
447                 if (dev->txnumevt) {    /* disable FIFO */
448                         switch (dev->version) {
449                         case MCASP_VERSION_3:
450                                 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
451                                                                 FIFO_ENABLE);
452                                 break;
453                         default:
454                                 mcasp_clr_bits(dev->base +
455                                         DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
456                         }
457                 }
458                 mcasp_stop_tx(dev);
459         } else {
460                 if (dev->rxnumevt) {    /* disable FIFO */
461                         switch (dev->version) {
462                         case MCASP_VERSION_3:
463                                 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
464                                                                 FIFO_ENABLE);
465                         break;
466 
467                         default:
468                                 mcasp_clr_bits(dev->base +
469                                         DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
470                         }
471                 }
472                 mcasp_stop_rx(dev);
473         }
474 }
475 
476 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
477                                          unsigned int fmt)
478 {
479         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
480         void __iomem *base = dev->base;
481 
482         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483         case SND_SOC_DAIFMT_DSP_B:
484         case SND_SOC_DAIFMT_AC97:
485                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
486                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
487                 break;
488         default:
489                 /* configure a full-word SYNC pulse (LRCLK) */
490                 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
491                 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
492 
493                 /* make 1st data bit occur one ACLK cycle after the frame sync */
494                 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
495                 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
496                 break;
497         }
498 
499         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
500         case SND_SOC_DAIFMT_CBS_CFS:
501                 /* codec is clock and frame slave */
502                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
503                 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
504 
505                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
506                 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
507 
508                 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
509                                 ACLKX | ACLKR);
510                 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
511                                 AFSX | AFSR);
512                 break;
513         case SND_SOC_DAIFMT_CBM_CFS:
514                 /* codec is clock master and frame slave */
515                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516                 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517 
518                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519                 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520 
521                 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
522                                 ACLKX | ACLKR);
523                 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
524                                 AFSX | AFSR);
525                 break;
526         case SND_SOC_DAIFMT_CBM_CFM:
527                 /* codec is clock and frame master */
528                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
529                 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530 
531                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
532                 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
533 
534                 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
535                                 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
536                 break;
537 
538         default:
539                 return -EINVAL;
540         }
541 
542         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543         case SND_SOC_DAIFMT_IB_NF:
544                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
545                 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
546 
547                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
548                 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
549                 break;
550 
551         case SND_SOC_DAIFMT_NB_IF:
552                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
553                 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
554 
555                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
556                 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
557                 break;
558 
559         case SND_SOC_DAIFMT_IB_IF:
560                 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561                 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
562 
563                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564                 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
565                 break;
566 
567         case SND_SOC_DAIFMT_NB_NF:
568                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
569                 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
570 
571                 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572                 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
573                 break;
574 
575         default:
576                 return -EINVAL;
577         }
578 
579         return 0;
580 }
581 
582 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
583 {
584         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
585 
586         switch (div_id) {
587         case 0:         /* MCLK divider */
588                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
589                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
590                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
591                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
592                 break;
593 
594         case 1:         /* BCLK divider */
595                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
596                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
597                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
598                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
599                 break;
600 
601         case 2:         /* BCLK/LRCLK ratio */
602                 dev->bclk_lrclk_ratio = div;
603                 break;
604 
605         default:
606                 return -EINVAL;
607         }
608 
609         return 0;
610 }
611 
612 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
613                                     unsigned int freq, int dir)
614 {
615         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
616 
617         if (dir == SND_SOC_CLOCK_OUT) {
618                 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
619                 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
620                 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
621         } else {
622                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
623                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
624                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
625         }
626 
627         return 0;
628 }
629 
630 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
631                                        int word_length)
632 {
633         u32 fmt;
634         u32 tx_rotate = (word_length / 4) & 0x7;
635         u32 mask = (1ULL << word_length) - 1;
636         /*
637          * For captured data we should not rotate, inversion and masking is
638          * enoguh to get the data to the right position:
639          * Format         data from bus         after reverse (XRBUF)
640          * S16_LE:      |LSB|MSB|xxx|xxx|       |xxx|xxx|MSB|LSB|
641          * S24_3LE:     |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
642          * S24_LE:      |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
643          * S32_LE:      |LSB|DAT|DAT|MSB|       |MSB|DAT|DAT|LSB|
644          */
645         u32 rx_rotate = 0;
646 
647         /*
648          * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
649          * callback, take it into account here. That allows us to for example
650          * send 32 bits per channel to the codec, while only 16 of them carry
651          * audio payload.
652          * The clock ratio is given for a full period of data (for I2S format
653          * both left and right channels), so it has to be divided by number of
654          * tdm-slots (for I2S - divided by 2).
655          */
656         if (dev->bclk_lrclk_ratio)
657                 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
658 
659         /* mapping of the XSSZ bit-field as described in the datasheet */
660         fmt = (word_length >> 1) - 1;
661 
662         if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
663                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
664                                 RXSSZ(fmt), RXSSZ(0x0F));
665                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
666                                 TXSSZ(fmt), TXSSZ(0x0F));
667                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
668                                 TXROT(tx_rotate), TXROT(7));
669                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
670                                 RXROT(rx_rotate), RXROT(7));
671                 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
672                                 mask);
673         }
674 
675         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
676 
677         return 0;
678 }
679 
680 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
681                                     int channels)
682 {
683         int i;
684         u8 tx_ser = 0;
685         u8 rx_ser = 0;
686         u8 ser;
687         u8 slots = dev->tdm_slots;
688         u8 max_active_serializers = (channels + slots - 1) / slots;
689         /* Default configuration */
690         mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
691 
692         /* All PINS as McASP */
693         mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
694 
695         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
696                 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
697                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
698                                 TXDATADMADIS);
699         } else {
700                 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
701                 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
702                                 RXDATADMADIS);
703         }
704 
705         for (i = 0; i < dev->num_serializer; i++) {
706                 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
707                                         dev->serial_dir[i]);
708                 if (dev->serial_dir[i] == TX_MODE &&
709                                         tx_ser < max_active_serializers) {
710                         mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
711                                         AXR(i));
712                         tx_ser++;
713                 } else if (dev->serial_dir[i] == RX_MODE &&
714                                         rx_ser < max_active_serializers) {
715                         mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
716                                         AXR(i));
717                         rx_ser++;
718                 } else {
719                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
720                                         SRMOD_INACTIVE, SRMOD_MASK);
721                 }
722         }
723 
724         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
725                 ser = tx_ser;
726         else
727                 ser = rx_ser;
728 
729         if (ser < max_active_serializers) {
730                 dev_warn(dev->dev, "stream has more channels (%d) than are "
731                         "enabled in mcasp (%d)\n", channels, ser * slots);
732                 return -EINVAL;
733         }
734 
735         if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
736                 if (dev->txnumevt * tx_ser > 64)
737                         dev->txnumevt = 1;
738 
739                 switch (dev->version) {
740                 case MCASP_VERSION_3:
741                         mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
742                                                                 NUMDMA_MASK);
743                         mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
744                                 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
745                         break;
746                 default:
747                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
748                                                         tx_ser, NUMDMA_MASK);
749                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
750                                 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
751                 }
752         }
753 
754         if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
755                 if (dev->rxnumevt * rx_ser > 64)
756                         dev->rxnumevt = 1;
757                 switch (dev->version) {
758                 case MCASP_VERSION_3:
759                         mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
760                                                                 NUMDMA_MASK);
761                         mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
762                                 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
763                         break;
764                 default:
765                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
766                                                         rx_ser, NUMDMA_MASK);
767                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
768                                 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
769                 }
770         }
771 
772         return 0;
773 }
774 
775 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
776 {
777         int i, active_slots;
778         u32 mask = 0;
779 
780         active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
781         for (i = 0; i < active_slots; i++)
782                 mask |= (1 << i);
783 
784         mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
785 
786         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
787                 /* bit stream is MSB first  with no delay */
788                 /* DSP_B mode */
789                 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
790                 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
791 
792                 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
793                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
794                                         FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
795                 else
796                         printk(KERN_ERR "playback tdm slot %d not supported\n",
797                                 dev->tdm_slots);
798         } else {
799                 /* bit stream is MSB first with no delay */
800                 /* DSP_B mode */
801                 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
802                 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
803 
804                 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
805                         mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
806                                         FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
807                 else
808                         printk(KERN_ERR "capture tdm slot %d not supported\n",
809                                 dev->tdm_slots);
810         }
811 }
812 
813 /* S/PDIF */
814 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
815 {
816         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
817            and LSB first */
818         mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
819                                                 TXROT(6) | TXSSZ(15));
820 
821         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
822         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
823                                                 AFSXE | FSXMOD(0x180));
824 
825         /* Set the TX tdm : for all the slots */
826         mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
827 
828         /* Set the TX clock controls : div = 1 and internal */
829         mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
830                                                 ACLKXE | TX_ASYNC);
831 
832         mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
833 
834         /* Only 44100 and 48000 are valid, both have the same setting */
835         mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
836 
837         /* Enable the DIT */
838         mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
839 }
840 
841 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
842                                         struct snd_pcm_hw_params *params,
843                                         struct snd_soc_dai *cpu_dai)
844 {
845         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
846         struct davinci_pcm_dma_params *dma_params =
847                                         &dev->dma_params[substream->stream];
848         int word_length;
849         u8 fifo_level;
850         u8 slots = dev->tdm_slots;
851         u8 active_serializers;
852         int channels;
853         struct snd_interval *pcm_channels = hw_param_interval(params,
854                                         SNDRV_PCM_HW_PARAM_CHANNELS);
855         channels = pcm_channels->min;
856 
857         active_serializers = (channels + slots - 1) / slots;
858 
859         if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
860                 return -EINVAL;
861         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
862                 fifo_level = dev->txnumevt * active_serializers;
863         else
864                 fifo_level = dev->rxnumevt * active_serializers;
865 
866         if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
867                 davinci_hw_dit_param(dev);
868         else
869                 davinci_hw_param(dev, substream->stream);
870 
871         switch (params_format(params)) {
872         case SNDRV_PCM_FORMAT_U8:
873         case SNDRV_PCM_FORMAT_S8:
874                 dma_params->data_type = 1;
875                 word_length = 8;
876                 break;
877 
878         case SNDRV_PCM_FORMAT_U16_LE:
879         case SNDRV_PCM_FORMAT_S16_LE:
880                 dma_params->data_type = 2;
881                 word_length = 16;
882                 break;
883 
884         case SNDRV_PCM_FORMAT_U24_3LE:
885         case SNDRV_PCM_FORMAT_S24_3LE:
886                 dma_params->data_type = 3;
887                 word_length = 24;
888                 break;
889 
890         case SNDRV_PCM_FORMAT_U24_LE:
891         case SNDRV_PCM_FORMAT_S24_LE:
892         case SNDRV_PCM_FORMAT_U32_LE:
893         case SNDRV_PCM_FORMAT_S32_LE:
894                 dma_params->data_type = 4;
895                 word_length = 32;
896                 break;
897 
898         default:
899                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
900                 return -EINVAL;
901         }
902 
903         if (dev->version == MCASP_VERSION_2 && !fifo_level)
904                 dma_params->acnt = 4;
905         else
906                 dma_params->acnt = dma_params->data_type;
907 
908         dma_params->fifo_level = fifo_level;
909         davinci_config_channel_size(dev, word_length);
910 
911         return 0;
912 }
913 
914 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
915                                      int cmd, struct snd_soc_dai *cpu_dai)
916 {
917         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
918         int ret = 0;
919 
920         switch (cmd) {
921         case SNDRV_PCM_TRIGGER_RESUME:
922         case SNDRV_PCM_TRIGGER_START:
923         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
924                 ret = pm_runtime_get_sync(dev->dev);
925                 if (IS_ERR_VALUE(ret))
926                         dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
927                 davinci_mcasp_start(dev, substream->stream);
928                 break;
929 
930         case SNDRV_PCM_TRIGGER_SUSPEND:
931                 davinci_mcasp_stop(dev, substream->stream);
932                 ret = pm_runtime_put_sync(dev->dev);
933                 if (IS_ERR_VALUE(ret))
934                         dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
935                 break;
936 
937         case SNDRV_PCM_TRIGGER_STOP:
938         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
939                 davinci_mcasp_stop(dev, substream->stream);
940                 break;
941 
942         default:
943                 ret = -EINVAL;
944         }
945 
946         return ret;
947 }
948 
949 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
950                                  struct snd_soc_dai *dai)
951 {
952         struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
953 
954         snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
955         return 0;
956 }
957 
958 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
959         .startup        = davinci_mcasp_startup,
960         .trigger        = davinci_mcasp_trigger,
961         .hw_params      = davinci_mcasp_hw_params,
962         .set_fmt        = davinci_mcasp_set_dai_fmt,
963         .set_clkdiv     = davinci_mcasp_set_clkdiv,
964         .set_sysclk     = davinci_mcasp_set_sysclk,
965 };
966 
967 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
968                                 SNDRV_PCM_FMTBIT_U8 | \
969                                 SNDRV_PCM_FMTBIT_S16_LE | \
970                                 SNDRV_PCM_FMTBIT_U16_LE | \
971                                 SNDRV_PCM_FMTBIT_S24_LE | \
972                                 SNDRV_PCM_FMTBIT_U24_LE | \
973                                 SNDRV_PCM_FMTBIT_S24_3LE | \
974                                 SNDRV_PCM_FMTBIT_U24_3LE | \
975                                 SNDRV_PCM_FMTBIT_S32_LE | \
976                                 SNDRV_PCM_FMTBIT_U32_LE)
977 
978 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
979         {
980                 .name           = "davinci-mcasp.0",
981                 .playback       = {
982                         .channels_min   = 2,
983                         .channels_max   = 32 * 16,
984                         .rates          = DAVINCI_MCASP_RATES,
985                         .formats        = DAVINCI_MCASP_PCM_FMTS,
986                 },
987                 .capture        = {
988                         .channels_min   = 2,
989                         .channels_max   = 32 * 16,
990                         .rates          = DAVINCI_MCASP_RATES,
991                         .formats        = DAVINCI_MCASP_PCM_FMTS,
992                 },
993                 .ops            = &davinci_mcasp_dai_ops,
994 
995         },
996         {
997                 "davinci-mcasp.1",
998                 .playback       = {
999                         .channels_min   = 1,
1000                         .channels_max   = 384,
1001                         .rates          = DAVINCI_MCASP_RATES,
1002                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1003                 },
1004                 .ops            = &davinci_mcasp_dai_ops,
1005         },
1006 
1007 };
1008 
1009 static const struct snd_soc_component_driver davinci_mcasp_component = {
1010         .name           = "davinci-mcasp",
1011 };
1012 
1013 static const struct of_device_id mcasp_dt_ids[] = {
1014         {
1015                 .compatible = "ti,dm646x-mcasp-audio",
1016                 .data = (void *)MCASP_VERSION_1,
1017         },
1018         {
1019                 .compatible = "ti,da830-mcasp-audio",
1020                 .data = (void *)MCASP_VERSION_2,
1021         },
1022         {
1023                 .compatible = "ti,omap2-mcasp-audio",
1024                 .data = (void *)MCASP_VERSION_3,
1025         },
1026         { /* sentinel */ }
1027 };
1028 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1029 
1030 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1031                                                 struct platform_device *pdev)
1032 {
1033         struct device_node *np = pdev->dev.of_node;
1034         struct snd_platform_data *pdata = NULL;
1035         const struct of_device_id *match =
1036                         of_match_device(mcasp_dt_ids, &pdev->dev);
1037 
1038         const u32 *of_serial_dir32;
1039         u8 *of_serial_dir;
1040         u32 val;
1041         int i, ret = 0;
1042 
1043         if (pdev->dev.platform_data) {
1044                 pdata = pdev->dev.platform_data;
1045                 return pdata;
1046         } else if (match) {
1047                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1048                 if (!pdata) {
1049                         ret = -ENOMEM;
1050                         goto nodata;
1051                 }
1052         } else {
1053                 /* control shouldn't reach here. something is wrong */
1054                 ret = -EINVAL;
1055                 goto nodata;
1056         }
1057 
1058         if (match->data)
1059                 pdata->version = (u8)((int)match->data);
1060 
1061         ret = of_property_read_u32(np, "op-mode", &val);
1062         if (ret >= 0)
1063                 pdata->op_mode = val;
1064 
1065         ret = of_property_read_u32(np, "tdm-slots", &val);
1066         if (ret >= 0) {
1067                 if (val < 2 || val > 32) {
1068                         dev_err(&pdev->dev,
1069                                 "tdm-slots must be in rage [2-32]\n");
1070                         ret = -EINVAL;
1071                         goto nodata;
1072                 }
1073 
1074                 pdata->tdm_slots = val;
1075         }
1076 
1077         ret = of_property_read_u32(np, "num-serializer", &val);
1078         if (ret >= 0)
1079                 pdata->num_serializer = val;
1080 
1081         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1082         val /= sizeof(u32);
1083         if (val != pdata->num_serializer) {
1084                 dev_err(&pdev->dev,
1085                                 "num-serializer(%d) != serial-dir size(%d)\n",
1086                                 pdata->num_serializer, val);
1087                 ret = -EINVAL;
1088                 goto nodata;
1089         }
1090 
1091         if (of_serial_dir32) {
1092                 of_serial_dir = devm_kzalloc(&pdev->dev,
1093                                                 (sizeof(*of_serial_dir) * val),
1094                                                 GFP_KERNEL);
1095                 if (!of_serial_dir) {
1096                         ret = -ENOMEM;
1097                         goto nodata;
1098                 }
1099 
1100                 for (i = 0; i < pdata->num_serializer; i++)
1101                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1102 
1103                 pdata->serial_dir = of_serial_dir;
1104         }
1105 
1106         ret = of_property_read_u32(np, "tx-num-evt", &val);
1107         if (ret >= 0)
1108                 pdata->txnumevt = val;
1109 
1110         ret = of_property_read_u32(np, "rx-num-evt", &val);
1111         if (ret >= 0)
1112                 pdata->rxnumevt = val;
1113 
1114         ret = of_property_read_u32(np, "sram-size-playback", &val);
1115         if (ret >= 0)
1116                 pdata->sram_size_playback = val;
1117 
1118         ret = of_property_read_u32(np, "sram-size-capture", &val);
1119         if (ret >= 0)
1120                 pdata->sram_size_capture = val;
1121 
1122         return  pdata;
1123 
1124 nodata:
1125         if (ret < 0) {
1126                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1127                         ret);
1128                 pdata = NULL;
1129         }
1130         return  pdata;
1131 }
1132 
1133 static int davinci_mcasp_probe(struct platform_device *pdev)
1134 {
1135         struct davinci_pcm_dma_params *dma_data;
1136         struct resource *mem, *ioarea, *res;
1137         struct snd_platform_data *pdata;
1138         struct davinci_audio_dev *dev;
1139         int ret;
1140 
1141         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1142                 dev_err(&pdev->dev, "No platform data supplied\n");
1143                 return -EINVAL;
1144         }
1145 
1146         dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1147                            GFP_KERNEL);
1148         if (!dev)
1149                 return  -ENOMEM;
1150 
1151         pdata = davinci_mcasp_set_pdata_from_of(pdev);
1152         if (!pdata) {
1153                 dev_err(&pdev->dev, "no platform data\n");
1154                 return -EINVAL;
1155         }
1156 
1157         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158         if (!mem) {
1159                 dev_err(&pdev->dev, "no mem resource?\n");
1160                 return -ENODEV;
1161         }
1162 
1163         ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1164                         resource_size(mem), pdev->name);
1165         if (!ioarea) {
1166                 dev_err(&pdev->dev, "Audio region already claimed\n");
1167                 return -EBUSY;
1168         }
1169 
1170         pm_runtime_enable(&pdev->dev);
1171 
1172         ret = pm_runtime_get_sync(&pdev->dev);
1173         if (IS_ERR_VALUE(ret)) {
1174                 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1175                 return ret;
1176         }
1177 
1178         dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1179         if (!dev->base) {
1180                 dev_err(&pdev->dev, "ioremap failed\n");
1181                 ret = -ENOMEM;
1182                 goto err_release_clk;
1183         }
1184 
1185         dev->op_mode = pdata->op_mode;
1186         dev->tdm_slots = pdata->tdm_slots;
1187         dev->num_serializer = pdata->num_serializer;
1188         dev->serial_dir = pdata->serial_dir;
1189         dev->version = pdata->version;
1190         dev->txnumevt = pdata->txnumevt;
1191         dev->rxnumevt = pdata->rxnumevt;
1192         dev->dev = &pdev->dev;
1193 
1194         dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1195         dma_data->asp_chan_q = pdata->asp_chan_q;
1196         dma_data->ram_chan_q = pdata->ram_chan_q;
1197         dma_data->sram_pool = pdata->sram_pool;
1198         dma_data->sram_size = pdata->sram_size_playback;
1199         dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1200                                                         mem->start);
1201 
1202         /* first TX, then RX */
1203         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1204         if (!res) {
1205                 dev_err(&pdev->dev, "no DMA resource\n");
1206                 ret = -ENODEV;
1207                 goto err_release_clk;
1208         }
1209 
1210         dma_data->channel = res->start;
1211 
1212         dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1213         dma_data->asp_chan_q = pdata->asp_chan_q;
1214         dma_data->ram_chan_q = pdata->ram_chan_q;
1215         dma_data->sram_pool = pdata->sram_pool;
1216         dma_data->sram_size = pdata->sram_size_capture;
1217         dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1218                                                         mem->start);
1219 
1220         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1221         if (!res) {
1222                 dev_err(&pdev->dev, "no DMA resource\n");
1223                 ret = -ENODEV;
1224                 goto err_release_clk;
1225         }
1226 
1227         dma_data->channel = res->start;
1228         dev_set_drvdata(&pdev->dev, dev);
1229         ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1230                                          &davinci_mcasp_dai[pdata->op_mode], 1);
1231 
1232         if (ret != 0)
1233                 goto err_release_clk;
1234 
1235         ret = davinci_soc_platform_register(&pdev->dev);
1236         if (ret) {
1237                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1238                 goto err_unregister_component;
1239         }
1240 
1241         return 0;
1242 
1243 err_unregister_component:
1244         snd_soc_unregister_component(&pdev->dev);
1245 err_release_clk:
1246         pm_runtime_put_sync(&pdev->dev);
1247         pm_runtime_disable(&pdev->dev);
1248         return ret;
1249 }
1250 
1251 static int davinci_mcasp_remove(struct platform_device *pdev)
1252 {
1253 
1254         snd_soc_unregister_component(&pdev->dev);
1255         davinci_soc_platform_unregister(&pdev->dev);
1256 
1257         pm_runtime_put_sync(&pdev->dev);
1258         pm_runtime_disable(&pdev->dev);
1259 
1260         return 0;
1261 }
1262 
1263 static struct platform_driver davinci_mcasp_driver = {
1264         .probe          = davinci_mcasp_probe,
1265         .remove         = davinci_mcasp_remove,
1266         .driver         = {
1267                 .name   = "davinci-mcasp",
1268                 .owner  = THIS_MODULE,
1269                 .of_match_table = mcasp_dt_ids,
1270         },
1271 };
1272 
1273 module_platform_driver(davinci_mcasp_driver);
1274 
1275 MODULE_AUTHOR("Steve Chen");
1276 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1277 MODULE_LICENSE("GPL");
1278 
1279 

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