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Linux/sound/soc/fsl/fsl_asrc.c

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  1 /*
  2  * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  5  *
  6  * Author: Nicolin Chen <nicoleotsuka@gmail.com>
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2. This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  */
 12 
 13 #include <linux/clk.h>
 14 #include <linux/delay.h>
 15 #include <linux/dma-mapping.h>
 16 #include <linux/module.h>
 17 #include <linux/of_platform.h>
 18 #include <linux/platform_data/dma-imx.h>
 19 #include <linux/pm_runtime.h>
 20 #include <sound/dmaengine_pcm.h>
 21 #include <sound/pcm_params.h>
 22 
 23 #include "fsl_asrc.h"
 24 
 25 #define IDEAL_RATIO_DECIMAL_DEPTH 26
 26 
 27 #define pair_err(fmt, ...) \
 28         dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
 29 
 30 #define pair_dbg(fmt, ...) \
 31         dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
 32 
 33 /* Sample rates are aligned with that defined in pcm.h file */
 34 static const u8 process_option[][12][2] = {
 35         /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz   64kHz   88.2kHz 96kHz   176kHz  192kHz */
 36         {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},      /* 5512Hz */
 37         {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},      /* 8kHz */
 38         {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},      /* 11025Hz */
 39         {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},      /* 16kHz */
 40         {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},      /* 22050Hz */
 41         {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},},      /* 32kHz */
 42         {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},      /* 44.1kHz */
 43         {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},      /* 48kHz */
 44         {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},},      /* 64kHz */
 45         {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},      /* 88.2kHz */
 46         {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},      /* 96kHz */
 47         {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},      /* 176kHz */
 48         {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},      /* 192kHz */
 49 };
 50 
 51 /* Corresponding to process_option */
 52 static int supported_input_rate[] = {
 53         5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
 54         96000, 176400, 192000,
 55 };
 56 
 57 static int supported_asrc_rate[] = {
 58         8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
 59 };
 60 
 61 /**
 62  * The following tables map the relationship between asrc_inclk/asrc_outclk in
 63  * fsl_asrc.h and the registers of ASRCSR
 64  */
 65 static unsigned char input_clk_map_imx35[] = {
 66         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
 67 };
 68 
 69 static unsigned char output_clk_map_imx35[] = {
 70         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
 71 };
 72 
 73 /* i.MX53 uses the same map for input and output */
 74 static unsigned char input_clk_map_imx53[] = {
 75 /*      0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
 76         0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
 77 };
 78 
 79 static unsigned char output_clk_map_imx53[] = {
 80 /*      0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
 81         0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
 82 };
 83 
 84 static unsigned char *clk_map[2];
 85 
 86 /**
 87  * Request ASRC pair
 88  *
 89  * It assigns pair by the order of A->C->B because allocation of pair B,
 90  * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
 91  * while pair A and pair C are comparatively independent.
 92  */
 93 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
 94 {
 95         enum asrc_pair_index index = ASRC_INVALID_PAIR;
 96         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 97         struct device *dev = &asrc_priv->pdev->dev;
 98         unsigned long lock_flags;
 99         int i, ret = 0;
100 
101         spin_lock_irqsave(&asrc_priv->lock, lock_flags);
102 
103         for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
104                 if (asrc_priv->pair[i] != NULL)
105                         continue;
106 
107                 index = i;
108 
109                 if (i != ASRC_PAIR_B)
110                         break;
111         }
112 
113         if (index == ASRC_INVALID_PAIR) {
114                 dev_err(dev, "all pairs are busy now\n");
115                 ret = -EBUSY;
116         } else if (asrc_priv->channel_avail < channels) {
117                 dev_err(dev, "can't afford required channels: %d\n", channels);
118                 ret = -EINVAL;
119         } else {
120                 asrc_priv->channel_avail -= channels;
121                 asrc_priv->pair[index] = pair;
122                 pair->channels = channels;
123                 pair->index = index;
124         }
125 
126         spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
127 
128         return ret;
129 }
130 
131 /**
132  * Release ASRC pair
133  *
134  * It clears the resource from asrc_priv and releases the occupied channels.
135  */
136 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
137 {
138         struct fsl_asrc *asrc_priv = pair->asrc_priv;
139         enum asrc_pair_index index = pair->index;
140         unsigned long lock_flags;
141 
142         /* Make sure the pair is disabled */
143         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
144                            ASRCTR_ASRCEi_MASK(index), 0);
145 
146         spin_lock_irqsave(&asrc_priv->lock, lock_flags);
147 
148         asrc_priv->channel_avail += pair->channels;
149         asrc_priv->pair[index] = NULL;
150         pair->error = 0;
151 
152         spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
153 }
154 
155 /**
156  * Configure input and output thresholds
157  */
158 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
159 {
160         struct fsl_asrc *asrc_priv = pair->asrc_priv;
161         enum asrc_pair_index index = pair->index;
162 
163         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
164                            ASRMCRi_EXTTHRSHi_MASK |
165                            ASRMCRi_INFIFO_THRESHOLD_MASK |
166                            ASRMCRi_OUTFIFO_THRESHOLD_MASK,
167                            ASRMCRi_EXTTHRSHi |
168                            ASRMCRi_INFIFO_THRESHOLD(in) |
169                            ASRMCRi_OUTFIFO_THRESHOLD(out));
170 }
171 
172 /**
173  * Calculate the total divisor between asrck clock rate and sample rate
174  *
175  * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
176  */
177 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
178 {
179         u32 ps;
180 
181         /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
182         for (ps = 0; div > 8; ps++)
183                 div >>= 1;
184 
185         return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
186 }
187 
188 /**
189  * Calculate and set the ratio for Ideal Ratio mode only
190  *
191  * The ratio is a 32-bit fixed point value with 26 fractional bits.
192  */
193 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
194                                     int inrate, int outrate)
195 {
196         struct fsl_asrc *asrc_priv = pair->asrc_priv;
197         enum asrc_pair_index index = pair->index;
198         unsigned long ratio;
199         int i;
200 
201         if (!outrate) {
202                 pair_err("output rate should not be zero\n");
203                 return -EINVAL;
204         }
205 
206         /* Calculate the intergal part of the ratio */
207         ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
208 
209         /* ... and then the 26 depth decimal part */
210         inrate %= outrate;
211 
212         for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
213                 inrate <<= 1;
214 
215                 if (inrate < outrate)
216                         continue;
217 
218                 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
219                 inrate -= outrate;
220 
221                 if (!inrate)
222                         break;
223         }
224 
225         regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
226         regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
227 
228         return 0;
229 }
230 
231 /**
232  * Configure the assigned ASRC pair
233  *
234  * It configures those ASRC registers according to a configuration instance
235  * of struct asrc_config which includes in/output sample rate, width, channel
236  * and clock settings.
237  */
238 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
239 {
240         struct asrc_config *config = pair->config;
241         struct fsl_asrc *asrc_priv = pair->asrc_priv;
242         enum asrc_pair_index index = pair->index;
243         u32 inrate, outrate, indiv, outdiv;
244         u32 clk_index[2], div[2];
245         int in, out, channels;
246         struct clk *clk;
247         bool ideal;
248 
249         if (!config) {
250                 pair_err("invalid pair config\n");
251                 return -EINVAL;
252         }
253 
254         /* Validate channels */
255         if (config->channel_num < 1 || config->channel_num > 10) {
256                 pair_err("does not support %d channels\n", config->channel_num);
257                 return -EINVAL;
258         }
259 
260         /* Validate output width */
261         if (config->output_word_width == ASRC_WIDTH_8_BIT) {
262                 pair_err("does not support 8bit width output\n");
263                 return -EINVAL;
264         }
265 
266         inrate = config->input_sample_rate;
267         outrate = config->output_sample_rate;
268         ideal = config->inclk == INCLK_NONE;
269 
270         /* Validate input and output sample rates */
271         for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
272                 if (inrate == supported_input_rate[in])
273                         break;
274 
275         if (in == ARRAY_SIZE(supported_input_rate)) {
276                 pair_err("unsupported input sample rate: %dHz\n", inrate);
277                 return -EINVAL;
278         }
279 
280         for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
281                 if (outrate == supported_asrc_rate[out])
282                         break;
283 
284         if (out == ARRAY_SIZE(supported_asrc_rate)) {
285                 pair_err("unsupported output sample rate: %dHz\n", outrate);
286                 return -EINVAL;
287         }
288 
289         if ((outrate > 8000 && outrate < 30000) &&
290             (outrate/inrate > 24 || inrate/outrate > 8)) {
291                 pair_err("exceed supported ratio range [1/24, 8] for \
292                                 inrate/outrate: %d/%d\n", inrate, outrate);
293                 return -EINVAL;
294         }
295 
296         /* Validate input and output clock sources */
297         clk_index[IN] = clk_map[IN][config->inclk];
298         clk_index[OUT] = clk_map[OUT][config->outclk];
299 
300         /* We only have output clock for ideal ratio mode */
301         clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
302 
303         div[IN] = clk_get_rate(clk) / inrate;
304         if (div[IN] == 0) {
305                 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
306                                 inrate, clk_index[ideal ? OUT : IN]);
307                 return -EINVAL;
308         }
309 
310         clk = asrc_priv->asrck_clk[clk_index[OUT]];
311 
312         /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
313         if (ideal)
314                 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
315         else
316                 div[OUT] = clk_get_rate(clk) / outrate;
317 
318         if (div[OUT] == 0) {
319                 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
320                                 outrate, clk_index[OUT]);
321                 return -EINVAL;
322         }
323 
324         /* Set the channel number */
325         channels = config->channel_num;
326 
327         if (asrc_priv->channel_bits < 4)
328                 channels /= 2;
329 
330         /* Update channels for current pair */
331         regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
332                            ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
333                            ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
334 
335         /* Default setting: Automatic selection for processing mode */
336         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
337                            ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
338         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
339                            ASRCTR_USRi_MASK(index), 0);
340 
341         /* Set the input and output clock sources */
342         regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
343                            ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
344                            ASRCSR_AICS(index, clk_index[IN]) |
345                            ASRCSR_AOCS(index, clk_index[OUT]));
346 
347         /* Calculate the input clock divisors */
348         indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
349         outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
350 
351         /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
352         regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
353                            ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
354                            ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
355                            ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
356 
357         /* Implement word_width configurations */
358         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
359                            ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
360                            ASRMCR1i_OW16(config->output_word_width) |
361                            ASRMCR1i_IWD(config->input_word_width));
362 
363         /* Enable BUFFER STALL */
364         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
365                            ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
366 
367         /* Set default thresholds for input and output FIFO */
368         fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
369                                 ASRC_INPUTFIFO_THRESHOLD);
370 
371         /* Configure the followings only for Ideal Ratio mode */
372         if (!ideal)
373                 return 0;
374 
375         /* Clear ASTSx bit to use Ideal Ratio mode */
376         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
377                            ASRCTR_ATSi_MASK(index), 0);
378 
379         /* Enable Ideal Ratio mode */
380         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
381                            ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
382                            ASRCTR_IDR(index) | ASRCTR_USR(index));
383 
384         /* Apply configurations for pre- and post-processing */
385         regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
386                            ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
387                            ASRCFG_PREMOD(index, process_option[in][out][0]) |
388                            ASRCFG_POSTMOD(index, process_option[in][out][1]));
389 
390         return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
391 }
392 
393 /**
394  * Start the assigned ASRC pair
395  *
396  * It enables the assigned pair and makes it stopped at the stall level.
397  */
398 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
399 {
400         struct fsl_asrc *asrc_priv = pair->asrc_priv;
401         enum asrc_pair_index index = pair->index;
402         int reg, retry = 10, i;
403 
404         /* Enable the current pair */
405         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
406                            ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
407 
408         /* Wait for status of initialization */
409         do {
410                 udelay(5);
411                 regmap_read(asrc_priv->regmap, REG_ASRCFG, &reg);
412                 reg &= ASRCFG_INIRQi_MASK(index);
413         } while (!reg && --retry);
414 
415         /* Make the input fifo to ASRC STALL level */
416         regmap_read(asrc_priv->regmap, REG_ASRCNCR, &reg);
417         for (i = 0; i < pair->channels * 4; i++)
418                 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
419 
420         /* Enable overload interrupt */
421         regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
422 }
423 
424 /**
425  * Stop the assigned ASRC pair
426  */
427 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
428 {
429         struct fsl_asrc *asrc_priv = pair->asrc_priv;
430         enum asrc_pair_index index = pair->index;
431 
432         /* Stop the current pair */
433         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
434                            ASRCTR_ASRCEi_MASK(index), 0);
435 }
436 
437 /**
438  * Get DMA channel according to the pair and direction.
439  */
440 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
441 {
442         struct fsl_asrc *asrc_priv = pair->asrc_priv;
443         enum asrc_pair_index index = pair->index;
444         char name[4];
445 
446         sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
447 
448         return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
449 }
450 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
451 
452 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
453                                   struct snd_pcm_hw_params *params,
454                                   struct snd_soc_dai *dai)
455 {
456         struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
457         int width = params_width(params);
458         struct snd_pcm_runtime *runtime = substream->runtime;
459         struct fsl_asrc_pair *pair = runtime->private_data;
460         unsigned int channels = params_channels(params);
461         unsigned int rate = params_rate(params);
462         struct asrc_config config;
463         int word_width, ret;
464 
465         ret = fsl_asrc_request_pair(channels, pair);
466         if (ret) {
467                 dev_err(dai->dev, "fail to request asrc pair\n");
468                 return ret;
469         }
470 
471         pair->config = &config;
472 
473         if (width == 16)
474                 width = ASRC_WIDTH_16_BIT;
475         else
476                 width = ASRC_WIDTH_24_BIT;
477 
478         if (asrc_priv->asrc_width == 16)
479                 word_width = ASRC_WIDTH_16_BIT;
480         else
481                 word_width = ASRC_WIDTH_24_BIT;
482 
483         config.pair = pair->index;
484         config.channel_num = channels;
485         config.inclk = INCLK_NONE;
486         config.outclk = OUTCLK_ASRCK1_CLK;
487 
488         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
489                 config.input_word_width   = width;
490                 config.output_word_width  = word_width;
491                 config.input_sample_rate  = rate;
492                 config.output_sample_rate = asrc_priv->asrc_rate;
493         } else {
494                 config.input_word_width   = word_width;
495                 config.output_word_width  = width;
496                 config.input_sample_rate  = asrc_priv->asrc_rate;
497                 config.output_sample_rate = rate;
498         }
499 
500         ret = fsl_asrc_config_pair(pair);
501         if (ret) {
502                 dev_err(dai->dev, "fail to config asrc pair\n");
503                 return ret;
504         }
505 
506         return 0;
507 }
508 
509 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
510                                 struct snd_soc_dai *dai)
511 {
512         struct snd_pcm_runtime *runtime = substream->runtime;
513         struct fsl_asrc_pair *pair = runtime->private_data;
514 
515         if (pair)
516                 fsl_asrc_release_pair(pair);
517 
518         return 0;
519 }
520 
521 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
522                                 struct snd_soc_dai *dai)
523 {
524         struct snd_pcm_runtime *runtime = substream->runtime;
525         struct fsl_asrc_pair *pair = runtime->private_data;
526 
527         switch (cmd) {
528         case SNDRV_PCM_TRIGGER_START:
529         case SNDRV_PCM_TRIGGER_RESUME:
530         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
531                 fsl_asrc_start_pair(pair);
532                 break;
533         case SNDRV_PCM_TRIGGER_STOP:
534         case SNDRV_PCM_TRIGGER_SUSPEND:
535         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
536                 fsl_asrc_stop_pair(pair);
537                 break;
538         default:
539                 return -EINVAL;
540         }
541 
542         return 0;
543 }
544 
545 static struct snd_soc_dai_ops fsl_asrc_dai_ops = {
546         .hw_params    = fsl_asrc_dai_hw_params,
547         .hw_free      = fsl_asrc_dai_hw_free,
548         .trigger      = fsl_asrc_dai_trigger,
549 };
550 
551 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
552 {
553         struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
554 
555         snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
556                                   &asrc_priv->dma_params_rx);
557 
558         return 0;
559 }
560 
561 #define FSL_ASRC_RATES           SNDRV_PCM_RATE_8000_192000
562 #define FSL_ASRC_FORMATS        (SNDRV_PCM_FMTBIT_S24_LE | \
563                                  SNDRV_PCM_FMTBIT_S16_LE | \
564                                  SNDRV_PCM_FMTBIT_S20_3LE)
565 
566 static struct snd_soc_dai_driver fsl_asrc_dai = {
567         .probe = fsl_asrc_dai_probe,
568         .playback = {
569                 .stream_name = "ASRC-Playback",
570                 .channels_min = 1,
571                 .channels_max = 10,
572                 .rates = FSL_ASRC_RATES,
573                 .formats = FSL_ASRC_FORMATS,
574         },
575         .capture = {
576                 .stream_name = "ASRC-Capture",
577                 .channels_min = 1,
578                 .channels_max = 10,
579                 .rates = FSL_ASRC_RATES,
580                 .formats = FSL_ASRC_FORMATS,
581         },
582         .ops = &fsl_asrc_dai_ops,
583 };
584 
585 static const struct snd_soc_component_driver fsl_asrc_component = {
586         .name = "fsl-asrc-dai",
587 };
588 
589 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
590 {
591         switch (reg) {
592         case REG_ASRCTR:
593         case REG_ASRIER:
594         case REG_ASRCNCR:
595         case REG_ASRCFG:
596         case REG_ASRCSR:
597         case REG_ASRCDR1:
598         case REG_ASRCDR2:
599         case REG_ASRSTR:
600         case REG_ASRPM1:
601         case REG_ASRPM2:
602         case REG_ASRPM3:
603         case REG_ASRPM4:
604         case REG_ASRPM5:
605         case REG_ASRTFR1:
606         case REG_ASRCCR:
607         case REG_ASRDOA:
608         case REG_ASRDOB:
609         case REG_ASRDOC:
610         case REG_ASRIDRHA:
611         case REG_ASRIDRLA:
612         case REG_ASRIDRHB:
613         case REG_ASRIDRLB:
614         case REG_ASRIDRHC:
615         case REG_ASRIDRLC:
616         case REG_ASR76K:
617         case REG_ASR56K:
618         case REG_ASRMCRA:
619         case REG_ASRFSTA:
620         case REG_ASRMCRB:
621         case REG_ASRFSTB:
622         case REG_ASRMCRC:
623         case REG_ASRFSTC:
624         case REG_ASRMCR1A:
625         case REG_ASRMCR1B:
626         case REG_ASRMCR1C:
627                 return true;
628         default:
629                 return false;
630         }
631 }
632 
633 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
634 {
635         switch (reg) {
636         case REG_ASRSTR:
637         case REG_ASRDIA:
638         case REG_ASRDIB:
639         case REG_ASRDIC:
640         case REG_ASRDOA:
641         case REG_ASRDOB:
642         case REG_ASRDOC:
643         case REG_ASRFSTA:
644         case REG_ASRFSTB:
645         case REG_ASRFSTC:
646         case REG_ASRCFG:
647                 return true;
648         default:
649                 return false;
650         }
651 }
652 
653 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
654 {
655         switch (reg) {
656         case REG_ASRCTR:
657         case REG_ASRIER:
658         case REG_ASRCNCR:
659         case REG_ASRCFG:
660         case REG_ASRCSR:
661         case REG_ASRCDR1:
662         case REG_ASRCDR2:
663         case REG_ASRSTR:
664         case REG_ASRPM1:
665         case REG_ASRPM2:
666         case REG_ASRPM3:
667         case REG_ASRPM4:
668         case REG_ASRPM5:
669         case REG_ASRTFR1:
670         case REG_ASRCCR:
671         case REG_ASRDIA:
672         case REG_ASRDIB:
673         case REG_ASRDIC:
674         case REG_ASRIDRHA:
675         case REG_ASRIDRLA:
676         case REG_ASRIDRHB:
677         case REG_ASRIDRLB:
678         case REG_ASRIDRHC:
679         case REG_ASRIDRLC:
680         case REG_ASR76K:
681         case REG_ASR56K:
682         case REG_ASRMCRA:
683         case REG_ASRMCRB:
684         case REG_ASRMCRC:
685         case REG_ASRMCR1A:
686         case REG_ASRMCR1B:
687         case REG_ASRMCR1C:
688                 return true;
689         default:
690                 return false;
691         }
692 }
693 
694 static struct reg_default fsl_asrc_reg[] = {
695         { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
696         { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
697         { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
698         { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
699         { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
700         { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
701         { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
702         { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
703         { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
704         { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
705         { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
706         { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
707         { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
708         { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
709         { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
710         { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
711         { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
712         { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
713         { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
714         { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
715         { REG_ASRMCR1C, 0x0000 },
716 };
717 
718 static const struct regmap_config fsl_asrc_regmap_config = {
719         .reg_bits = 32,
720         .reg_stride = 4,
721         .val_bits = 32,
722 
723         .max_register = REG_ASRMCR1C,
724         .reg_defaults = fsl_asrc_reg,
725         .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
726         .readable_reg = fsl_asrc_readable_reg,
727         .volatile_reg = fsl_asrc_volatile_reg,
728         .writeable_reg = fsl_asrc_writeable_reg,
729         .cache_type = REGCACHE_RBTREE,
730 };
731 
732 /**
733  * Initialize ASRC registers with a default configurations
734  */
735 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
736 {
737         /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
738         regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
739 
740         /* Disable interrupt by default */
741         regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
742 
743         /* Apply recommended settings for parameters from Reference Manual */
744         regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
745         regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
746         regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
747         regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
748         regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
749 
750         /* Base address for task queue FIFO. Set to 0x7C */
751         regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
752                            ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
753 
754         /* Set the processing clock for 76KHz to 133M */
755         regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
756 
757         /* Set the processing clock for 56KHz to 133M */
758         return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
759 }
760 
761 /**
762  * Interrupt handler for ASRC
763  */
764 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
765 {
766         struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
767         struct device *dev = &asrc_priv->pdev->dev;
768         enum asrc_pair_index index;
769         u32 status;
770 
771         regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
772 
773         /* Clean overload error */
774         regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
775 
776         /*
777          * We here use dev_dbg() for all exceptions because ASRC itself does
778          * not care if FIFO overflowed or underrun while a warning in the
779          * interrupt would result a ridged conversion.
780          */
781         for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
782                 if (!asrc_priv->pair[index])
783                         continue;
784 
785                 if (status & ASRSTR_ATQOL) {
786                         asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
787                         dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
788                 }
789 
790                 if (status & ASRSTR_AOOL(index)) {
791                         asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
792                         pair_dbg("Output Task Overload\n");
793                 }
794 
795                 if (status & ASRSTR_AIOL(index)) {
796                         asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
797                         pair_dbg("Input Task Overload\n");
798                 }
799 
800                 if (status & ASRSTR_AODO(index)) {
801                         asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
802                         pair_dbg("Output Data Buffer has overflowed\n");
803                 }
804 
805                 if (status & ASRSTR_AIDU(index)) {
806                         asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
807                         pair_dbg("Input Data Buffer has underflowed\n");
808                 }
809         }
810 
811         return IRQ_HANDLED;
812 }
813 
814 static int fsl_asrc_probe(struct platform_device *pdev)
815 {
816         struct device_node *np = pdev->dev.of_node;
817         struct fsl_asrc *asrc_priv;
818         struct resource *res;
819         void __iomem *regs;
820         int irq, ret, i;
821         char tmp[16];
822 
823         asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
824         if (!asrc_priv)
825                 return -ENOMEM;
826 
827         asrc_priv->pdev = pdev;
828 
829         /* Get the addresses and IRQ */
830         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
831         regs = devm_ioremap_resource(&pdev->dev, res);
832         if (IS_ERR(regs))
833                 return PTR_ERR(regs);
834 
835         asrc_priv->paddr = res->start;
836 
837         asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
838                                                       &fsl_asrc_regmap_config);
839         if (IS_ERR(asrc_priv->regmap)) {
840                 dev_err(&pdev->dev, "failed to init regmap\n");
841                 return PTR_ERR(asrc_priv->regmap);
842         }
843 
844         irq = platform_get_irq(pdev, 0);
845         if (irq < 0) {
846                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
847                 return irq;
848         }
849 
850         ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
851                                dev_name(&pdev->dev), asrc_priv);
852         if (ret) {
853                 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
854                 return ret;
855         }
856 
857         asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
858         if (IS_ERR(asrc_priv->mem_clk)) {
859                 dev_err(&pdev->dev, "failed to get mem clock\n");
860                 return PTR_ERR(asrc_priv->mem_clk);
861         }
862 
863         asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
864         if (IS_ERR(asrc_priv->ipg_clk)) {
865                 dev_err(&pdev->dev, "failed to get ipg clock\n");
866                 return PTR_ERR(asrc_priv->ipg_clk);
867         }
868 
869         asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
870         if (IS_ERR(asrc_priv->spba_clk))
871                 dev_warn(&pdev->dev, "failed to get spba clock\n");
872 
873         for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
874                 sprintf(tmp, "asrck_%x", i);
875                 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
876                 if (IS_ERR(asrc_priv->asrck_clk[i])) {
877                         dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
878                         return PTR_ERR(asrc_priv->asrck_clk[i]);
879                 }
880         }
881 
882         if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-asrc")) {
883                 asrc_priv->channel_bits = 3;
884                 clk_map[IN] = input_clk_map_imx35;
885                 clk_map[OUT] = output_clk_map_imx35;
886         } else {
887                 asrc_priv->channel_bits = 4;
888                 clk_map[IN] = input_clk_map_imx53;
889                 clk_map[OUT] = output_clk_map_imx53;
890         }
891 
892         ret = fsl_asrc_init(asrc_priv);
893         if (ret) {
894                 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
895                 return -EINVAL;
896         }
897 
898         asrc_priv->channel_avail = 10;
899 
900         ret = of_property_read_u32(np, "fsl,asrc-rate",
901                                    &asrc_priv->asrc_rate);
902         if (ret) {
903                 dev_err(&pdev->dev, "failed to get output rate\n");
904                 return -EINVAL;
905         }
906 
907         ret = of_property_read_u32(np, "fsl,asrc-width",
908                                    &asrc_priv->asrc_width);
909         if (ret) {
910                 dev_err(&pdev->dev, "failed to get output width\n");
911                 return -EINVAL;
912         }
913 
914         if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
915                 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
916                 asrc_priv->asrc_width = 24;
917         }
918 
919         platform_set_drvdata(pdev, asrc_priv);
920         pm_runtime_enable(&pdev->dev);
921         spin_lock_init(&asrc_priv->lock);
922 
923         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
924                                               &fsl_asrc_dai, 1);
925         if (ret) {
926                 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
927                 return ret;
928         }
929 
930         ret = devm_snd_soc_register_platform(&pdev->dev, &fsl_asrc_platform);
931         if (ret) {
932                 dev_err(&pdev->dev, "failed to register ASoC platform\n");
933                 return ret;
934         }
935 
936         dev_info(&pdev->dev, "driver registered\n");
937 
938         return 0;
939 }
940 
941 #ifdef CONFIG_PM
942 static int fsl_asrc_runtime_resume(struct device *dev)
943 {
944         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
945         int i, ret;
946 
947         ret = clk_prepare_enable(asrc_priv->mem_clk);
948         if (ret)
949                 return ret;
950         ret = clk_prepare_enable(asrc_priv->ipg_clk);
951         if (ret)
952                 goto disable_mem_clk;
953         if (!IS_ERR(asrc_priv->spba_clk)) {
954                 ret = clk_prepare_enable(asrc_priv->spba_clk);
955                 if (ret)
956                         goto disable_ipg_clk;
957         }
958         for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
959                 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
960                 if (ret)
961                         goto disable_asrck_clk;
962         }
963 
964         return 0;
965 
966 disable_asrck_clk:
967         for (i--; i >= 0; i--)
968                 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
969         if (!IS_ERR(asrc_priv->spba_clk))
970                 clk_disable_unprepare(asrc_priv->spba_clk);
971 disable_ipg_clk:
972         clk_disable_unprepare(asrc_priv->ipg_clk);
973 disable_mem_clk:
974         clk_disable_unprepare(asrc_priv->mem_clk);
975         return ret;
976 }
977 
978 static int fsl_asrc_runtime_suspend(struct device *dev)
979 {
980         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
981         int i;
982 
983         for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
984                 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
985         if (!IS_ERR(asrc_priv->spba_clk))
986                 clk_disable_unprepare(asrc_priv->spba_clk);
987         clk_disable_unprepare(asrc_priv->ipg_clk);
988         clk_disable_unprepare(asrc_priv->mem_clk);
989 
990         return 0;
991 }
992 #endif /* CONFIG_PM */
993 
994 #ifdef CONFIG_PM_SLEEP
995 static int fsl_asrc_suspend(struct device *dev)
996 {
997         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
998 
999         regmap_read(asrc_priv->regmap, REG_ASRCFG,
1000                     &asrc_priv->regcache_cfg);
1001 
1002         regcache_cache_only(asrc_priv->regmap, true);
1003         regcache_mark_dirty(asrc_priv->regmap);
1004 
1005         return 0;
1006 }
1007 
1008 static int fsl_asrc_resume(struct device *dev)
1009 {
1010         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1011         u32 asrctr;
1012 
1013         /* Stop all pairs provisionally */
1014         regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
1015         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1016                            ASRCTR_ASRCEi_ALL_MASK, 0);
1017 
1018         /* Restore all registers */
1019         regcache_cache_only(asrc_priv->regmap, false);
1020         regcache_sync(asrc_priv->regmap);
1021 
1022         regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1023                            ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1024                            ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1025 
1026         /* Restart enabled pairs */
1027         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1028                            ASRCTR_ASRCEi_ALL_MASK, asrctr);
1029 
1030         return 0;
1031 }
1032 #endif /* CONFIG_PM_SLEEP */
1033 
1034 static const struct dev_pm_ops fsl_asrc_pm = {
1035         SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1036         SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1037 };
1038 
1039 static const struct of_device_id fsl_asrc_ids[] = {
1040         { .compatible = "fsl,imx35-asrc", },
1041         { .compatible = "fsl,imx53-asrc", },
1042         {}
1043 };
1044 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1045 
1046 static struct platform_driver fsl_asrc_driver = {
1047         .probe = fsl_asrc_probe,
1048         .driver = {
1049                 .name = "fsl-asrc",
1050                 .of_match_table = fsl_asrc_ids,
1051                 .pm = &fsl_asrc_pm,
1052         },
1053 };
1054 module_platform_driver(fsl_asrc_driver);
1055 
1056 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1057 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1058 MODULE_ALIAS("platform:fsl-asrc");
1059 MODULE_LICENSE("GPL v2");
1060 

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