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Linux/sound/soc/fsl/fsl_dma.c

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  1 /*
  2  * Freescale DMA ALSA SoC PCM driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  * This driver implements ASoC support for the Elo DMA controller, which is
 13  * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
 14  * the PCM driver is what handles the DMA buffer.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/init.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/dma-mapping.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/delay.h>
 23 #include <linux/gfp.h>
 24 #include <linux/of_platform.h>
 25 #include <linux/list.h>
 26 #include <linux/slab.h>
 27 
 28 #include <sound/core.h>
 29 #include <sound/pcm.h>
 30 #include <sound/pcm_params.h>
 31 #include <sound/soc.h>
 32 
 33 #include <asm/io.h>
 34 
 35 #include "fsl_dma.h"
 36 #include "fsl_ssi.h"    /* For the offset of stx0 and srx0 */
 37 
 38 /*
 39  * The formats that the DMA controller supports, which is anything
 40  * that is 8, 16, or 32 bits.
 41  */
 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8         | \
 43                             SNDRV_PCM_FMTBIT_U8         | \
 44                             SNDRV_PCM_FMTBIT_S16_LE     | \
 45                             SNDRV_PCM_FMTBIT_S16_BE     | \
 46                             SNDRV_PCM_FMTBIT_U16_LE     | \
 47                             SNDRV_PCM_FMTBIT_U16_BE     | \
 48                             SNDRV_PCM_FMTBIT_S24_LE     | \
 49                             SNDRV_PCM_FMTBIT_S24_BE     | \
 50                             SNDRV_PCM_FMTBIT_U24_LE     | \
 51                             SNDRV_PCM_FMTBIT_U24_BE     | \
 52                             SNDRV_PCM_FMTBIT_S32_LE     | \
 53                             SNDRV_PCM_FMTBIT_S32_BE     | \
 54                             SNDRV_PCM_FMTBIT_U32_LE     | \
 55                             SNDRV_PCM_FMTBIT_U32_BE)
 56 
 57 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
 58                           SNDRV_PCM_RATE_CONTINUOUS)
 59 
 60 struct dma_object {
 61         struct snd_soc_platform_driver dai;
 62         dma_addr_t ssi_stx_phys;
 63         dma_addr_t ssi_srx_phys;
 64         unsigned int ssi_fifo_depth;
 65         struct ccsr_dma_channel __iomem *channel;
 66         unsigned int irq;
 67         bool assigned;
 68         char path[1];
 69 };
 70 
 71 /*
 72  * The number of DMA links to use.  Two is the bare minimum, but if you
 73  * have really small links you might need more.
 74  */
 75 #define NUM_DMA_LINKS   2
 76 
 77 /** fsl_dma_private: p-substream DMA data
 78  *
 79  * Each substream has a 1-to-1 association with a DMA channel.
 80  *
 81  * The link[] array is first because it needs to be aligned on a 32-byte
 82  * boundary, so putting it first will ensure alignment without padding the
 83  * structure.
 84  *
 85  * @link[]: array of link descriptors
 86  * @dma_channel: pointer to the DMA channel's registers
 87  * @irq: IRQ for this DMA channel
 88  * @substream: pointer to the substream object, needed by the ISR
 89  * @ssi_sxx_phys: bus address of the STX or SRX register to use
 90  * @ld_buf_phys: physical address of the LD buffer
 91  * @current_link: index into link[] of the link currently being processed
 92  * @dma_buf_phys: physical address of the DMA buffer
 93  * @dma_buf_next: physical address of the next period to process
 94  * @dma_buf_end: physical address of the byte after the end of the DMA
 95  * @buffer period_size: the size of a single period
 96  * @num_periods: the number of periods in the DMA buffer
 97  */
 98 struct fsl_dma_private {
 99         struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
100         struct ccsr_dma_channel __iomem *dma_channel;
101         unsigned int irq;
102         struct snd_pcm_substream *substream;
103         dma_addr_t ssi_sxx_phys;
104         unsigned int ssi_fifo_depth;
105         dma_addr_t ld_buf_phys;
106         unsigned int current_link;
107         dma_addr_t dma_buf_phys;
108         dma_addr_t dma_buf_next;
109         dma_addr_t dma_buf_end;
110         size_t period_size;
111         unsigned int num_periods;
112 };
113 
114 /**
115  * fsl_dma_hardare: define characteristics of the PCM hardware.
116  *
117  * The PCM hardware is the Freescale DMA controller.  This structure defines
118  * the capabilities of that hardware.
119  *
120  * Since the sampling rate and data format are not controlled by the DMA
121  * controller, we specify no limits for those values.  The only exception is
122  * period_bytes_min, which is set to a reasonably low value to prevent the
123  * DMA controller from generating too many interrupts per second.
124  *
125  * Since each link descriptor has a 32-bit byte count field, we set
126  * period_bytes_max to the largest 32-bit number.  We also have no maximum
127  * number of periods.
128  *
129  * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
130  * limitation in the SSI driver requires the sample rates for playback and
131  * capture to be the same.
132  */
133 static const struct snd_pcm_hardware fsl_dma_hardware = {
134 
135         .info                   = SNDRV_PCM_INFO_INTERLEAVED |
136                                   SNDRV_PCM_INFO_MMAP |
137                                   SNDRV_PCM_INFO_MMAP_VALID |
138                                   SNDRV_PCM_INFO_JOINT_DUPLEX |
139                                   SNDRV_PCM_INFO_PAUSE,
140         .formats                = FSLDMA_PCM_FORMATS,
141         .rates                  = FSLDMA_PCM_RATES,
142         .rate_min               = 5512,
143         .rate_max               = 192000,
144         .period_bytes_min       = 512,          /* A reasonable limit */
145         .period_bytes_max       = (u32) -1,
146         .periods_min            = NUM_DMA_LINKS,
147         .periods_max            = (unsigned int) -1,
148         .buffer_bytes_max       = 128 * 1024,   /* A reasonable limit */
149 };
150 
151 /**
152  * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
153  *
154  * This function should be called by the ISR whenever the DMA controller
155  * halts data transfer.
156  */
157 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
158 {
159         unsigned long flags;
160 
161         snd_pcm_stream_lock_irqsave(substream, flags);
162 
163         if (snd_pcm_running(substream))
164                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
165 
166         snd_pcm_stream_unlock_irqrestore(substream, flags);
167 }
168 
169 /**
170  * fsl_dma_update_pointers - update LD pointers to point to the next period
171  *
172  * As each period is completed, this function changes the the link
173  * descriptor pointers for that period to point to the next period.
174  */
175 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
176 {
177         struct fsl_dma_link_descriptor *link =
178                 &dma_private->link[dma_private->current_link];
179 
180         /* Update our link descriptors to point to the next period. On a 36-bit
181          * system, we also need to update the ESAD bits.  We also set (keep) the
182          * snoop bits.  See the comments in fsl_dma_hw_params() about snooping.
183          */
184         if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
185                 link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
186 #ifdef CONFIG_PHYS_64BIT
187                 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
188                         upper_32_bits(dma_private->dma_buf_next));
189 #endif
190         } else {
191                 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
192 #ifdef CONFIG_PHYS_64BIT
193                 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
194                         upper_32_bits(dma_private->dma_buf_next));
195 #endif
196         }
197 
198         /* Update our variables for next time */
199         dma_private->dma_buf_next += dma_private->period_size;
200 
201         if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
202                 dma_private->dma_buf_next = dma_private->dma_buf_phys;
203 
204         if (++dma_private->current_link >= NUM_DMA_LINKS)
205                 dma_private->current_link = 0;
206 }
207 
208 /**
209  * fsl_dma_isr: interrupt handler for the DMA controller
210  *
211  * @irq: IRQ of the DMA channel
212  * @dev_id: pointer to the dma_private structure for this DMA channel
213  */
214 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
215 {
216         struct fsl_dma_private *dma_private = dev_id;
217         struct snd_pcm_substream *substream = dma_private->substream;
218         struct snd_soc_pcm_runtime *rtd = substream->private_data;
219         struct device *dev = rtd->platform->dev;
220         struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
221         irqreturn_t ret = IRQ_NONE;
222         u32 sr, sr2 = 0;
223 
224         /* We got an interrupt, so read the status register to see what we
225            were interrupted for.
226          */
227         sr = in_be32(&dma_channel->sr);
228 
229         if (sr & CCSR_DMA_SR_TE) {
230                 dev_err(dev, "dma transmit error\n");
231                 fsl_dma_abort_stream(substream);
232                 sr2 |= CCSR_DMA_SR_TE;
233                 ret = IRQ_HANDLED;
234         }
235 
236         if (sr & CCSR_DMA_SR_CH)
237                 ret = IRQ_HANDLED;
238 
239         if (sr & CCSR_DMA_SR_PE) {
240                 dev_err(dev, "dma programming error\n");
241                 fsl_dma_abort_stream(substream);
242                 sr2 |= CCSR_DMA_SR_PE;
243                 ret = IRQ_HANDLED;
244         }
245 
246         if (sr & CCSR_DMA_SR_EOLNI) {
247                 sr2 |= CCSR_DMA_SR_EOLNI;
248                 ret = IRQ_HANDLED;
249         }
250 
251         if (sr & CCSR_DMA_SR_CB)
252                 ret = IRQ_HANDLED;
253 
254         if (sr & CCSR_DMA_SR_EOSI) {
255                 /* Tell ALSA we completed a period. */
256                 snd_pcm_period_elapsed(substream);
257 
258                 /*
259                  * Update our link descriptors to point to the next period. We
260                  * only need to do this if the number of periods is not equal to
261                  * the number of links.
262                  */
263                 if (dma_private->num_periods != NUM_DMA_LINKS)
264                         fsl_dma_update_pointers(dma_private);
265 
266                 sr2 |= CCSR_DMA_SR_EOSI;
267                 ret = IRQ_HANDLED;
268         }
269 
270         if (sr & CCSR_DMA_SR_EOLSI) {
271                 sr2 |= CCSR_DMA_SR_EOLSI;
272                 ret = IRQ_HANDLED;
273         }
274 
275         /* Clear the bits that we set */
276         if (sr2)
277                 out_be32(&dma_channel->sr, sr2);
278 
279         return ret;
280 }
281 
282 /**
283  * fsl_dma_new: initialize this PCM driver.
284  *
285  * This function is called when the codec driver calls snd_soc_new_pcms(),
286  * once for each .dai_link in the machine driver's snd_soc_card
287  * structure.
288  *
289  * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
290  * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
291  * is specified. Therefore, any DMA buffers we allocate will always be in low
292  * memory, but we support for 36-bit physical addresses anyway.
293  *
294  * Regardless of where the memory is actually allocated, since the device can
295  * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
296  */
297 static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd)
298 {
299         struct snd_card *card = rtd->card->snd_card;
300         struct snd_pcm *pcm = rtd->pcm;
301         static u64 fsl_dma_dmamask = DMA_BIT_MASK(36);
302         int ret;
303 
304         if (!card->dev->dma_mask)
305                 card->dev->dma_mask = &fsl_dma_dmamask;
306 
307         if (!card->dev->coherent_dma_mask)
308                 card->dev->coherent_dma_mask = fsl_dma_dmamask;
309 
310         /* Some codecs have separate DAIs for playback and capture, so we
311          * should allocate a DMA buffer only for the streams that are valid.
312          */
313 
314         if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
315                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
316                         fsl_dma_hardware.buffer_bytes_max,
317                         &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
318                 if (ret) {
319                         dev_err(card->dev, "can't alloc playback dma buffer\n");
320                         return ret;
321                 }
322         }
323 
324         if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
325                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
326                         fsl_dma_hardware.buffer_bytes_max,
327                         &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
328                 if (ret) {
329                         dev_err(card->dev, "can't alloc capture dma buffer\n");
330                         snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
331                         return ret;
332                 }
333         }
334 
335         return 0;
336 }
337 
338 /**
339  * fsl_dma_open: open a new substream.
340  *
341  * Each substream has its own DMA buffer.
342  *
343  * ALSA divides the DMA buffer into N periods.  We create NUM_DMA_LINKS link
344  * descriptors that ping-pong from one period to the next.  For example, if
345  * there are six periods and two link descriptors, this is how they look
346  * before playback starts:
347  *
348  *                 The last link descriptor
349  *   ____________  points back to the first
350  *  |            |
351  *  V            |
352  *  ___    ___   |
353  * |   |->|   |->|
354  * |___|  |___|
355  *   |      |
356  *   |      |
357  *   V      V
358  *  _________________________________________
359  * |      |      |      |      |      |      |  The DMA buffer is
360  * |      |      |      |      |      |      |    divided into 6 parts
361  * |______|______|______|______|______|______|
362  *
363  * and here's how they look after the first period is finished playing:
364  *
365  *   ____________
366  *  |            |
367  *  V            |
368  *  ___    ___   |
369  * |   |->|   |->|
370  * |___|  |___|
371  *   |      |
372  *   |______________
373  *          |       |
374  *          V       V
375  *  _________________________________________
376  * |      |      |      |      |      |      |
377  * |      |      |      |      |      |      |
378  * |______|______|______|______|______|______|
379  *
380  * The first link descriptor now points to the third period.  The DMA
381  * controller is currently playing the second period.  When it finishes, it
382  * will jump back to the first descriptor and play the third period.
383  *
384  * There are four reasons we do this:
385  *
386  * 1. The only way to get the DMA controller to automatically restart the
387  *    transfer when it gets to the end of the buffer is to use chaining
388  *    mode.  Basic direct mode doesn't offer that feature.
389  * 2. We need to receive an interrupt at the end of every period.  The DMA
390  *    controller can generate an interrupt at the end of every link transfer
391  *    (aka segment).  Making each period into a DMA segment will give us the
392  *    interrupts we need.
393  * 3. By creating only two link descriptors, regardless of the number of
394  *    periods, we do not need to reallocate the link descriptors if the
395  *    number of periods changes.
396  * 4. All of the audio data is still stored in a single, contiguous DMA
397  *    buffer, which is what ALSA expects.  We're just dividing it into
398  *    contiguous parts, and creating a link descriptor for each one.
399  */
400 static int fsl_dma_open(struct snd_pcm_substream *substream)
401 {
402         struct snd_pcm_runtime *runtime = substream->runtime;
403         struct snd_soc_pcm_runtime *rtd = substream->private_data;
404         struct device *dev = rtd->platform->dev;
405         struct dma_object *dma =
406                 container_of(rtd->platform->driver, struct dma_object, dai);
407         struct fsl_dma_private *dma_private;
408         struct ccsr_dma_channel __iomem *dma_channel;
409         dma_addr_t ld_buf_phys;
410         u64 temp_link;          /* Pointer to next link descriptor */
411         u32 mr;
412         unsigned int channel;
413         int ret = 0;
414         unsigned int i;
415 
416         /*
417          * Reject any DMA buffer whose size is not a multiple of the period
418          * size.  We need to make sure that the DMA buffer can be evenly divided
419          * into periods.
420          */
421         ret = snd_pcm_hw_constraint_integer(runtime,
422                 SNDRV_PCM_HW_PARAM_PERIODS);
423         if (ret < 0) {
424                 dev_err(dev, "invalid buffer size\n");
425                 return ret;
426         }
427 
428         channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
429 
430         if (dma->assigned) {
431                 dev_err(dev, "dma channel already assigned\n");
432                 return -EBUSY;
433         }
434 
435         dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
436                                          &ld_buf_phys, GFP_KERNEL);
437         if (!dma_private) {
438                 dev_err(dev, "can't allocate dma private data\n");
439                 return -ENOMEM;
440         }
441         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
442                 dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
443         else
444                 dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
445 
446         dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
447         dma_private->dma_channel = dma->channel;
448         dma_private->irq = dma->irq;
449         dma_private->substream = substream;
450         dma_private->ld_buf_phys = ld_buf_phys;
451         dma_private->dma_buf_phys = substream->dma_buffer.addr;
452 
453         ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
454                           dma_private);
455         if (ret) {
456                 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
457                         dma_private->irq, ret);
458                 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
459                         dma_private, dma_private->ld_buf_phys);
460                 return ret;
461         }
462 
463         dma->assigned = 1;
464 
465         snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
466         snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
467         runtime->private_data = dma_private;
468 
469         /* Program the fixed DMA controller parameters */
470 
471         dma_channel = dma_private->dma_channel;
472 
473         temp_link = dma_private->ld_buf_phys +
474                 sizeof(struct fsl_dma_link_descriptor);
475 
476         for (i = 0; i < NUM_DMA_LINKS; i++) {
477                 dma_private->link[i].next = cpu_to_be64(temp_link);
478 
479                 temp_link += sizeof(struct fsl_dma_link_descriptor);
480         }
481         /* The last link descriptor points to the first */
482         dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
483 
484         /* Tell the DMA controller where the first link descriptor is */
485         out_be32(&dma_channel->clndar,
486                 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
487         out_be32(&dma_channel->eclndar,
488                 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
489 
490         /* The manual says the BCR must be clear before enabling EMP */
491         out_be32(&dma_channel->bcr, 0);
492 
493         /*
494          * Program the mode register for interrupts, external master control,
495          * and source/destination hold.  Also clear the Channel Abort bit.
496          */
497         mr = in_be32(&dma_channel->mr) &
498                 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
499 
500         /*
501          * We want External Master Start and External Master Pause enabled,
502          * because the SSI is controlling the DMA controller.  We want the DMA
503          * controller to be set up in advance, and then we signal only the SSI
504          * to start transferring.
505          *
506          * We want End-Of-Segment Interrupts enabled, because this will generate
507          * an interrupt at the end of each segment (each link descriptor
508          * represents one segment).  Each DMA segment is the same thing as an
509          * ALSA period, so this is how we get an interrupt at the end of every
510          * period.
511          *
512          * We want Error Interrupt enabled, so that we can get an error if
513          * the DMA controller is mis-programmed somehow.
514          */
515         mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
516                 CCSR_DMA_MR_EMS_EN;
517 
518         /* For playback, we want the destination address to be held.  For
519            capture, set the source address to be held. */
520         mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
521                 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
522 
523         out_be32(&dma_channel->mr, mr);
524 
525         return 0;
526 }
527 
528 /**
529  * fsl_dma_hw_params: continue initializing the DMA links
530  *
531  * This function obtains hardware parameters about the opened stream and
532  * programs the DMA controller accordingly.
533  *
534  * One drawback of big-endian is that when copying integers of different
535  * sizes to a fixed-sized register, the address to which the integer must be
536  * copied is dependent on the size of the integer.
537  *
538  * For example, if P is the address of a 32-bit register, and X is a 32-bit
539  * integer, then X should be copied to address P.  However, if X is a 16-bit
540  * integer, then it should be copied to P+2.  If X is an 8-bit register,
541  * then it should be copied to P+3.
542  *
543  * So for playback of 8-bit samples, the DMA controller must transfer single
544  * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
545  * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
546  *
547  * For 24-bit samples, the offset is 1 byte.  However, the DMA controller
548  * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
549  * and 8 bytes at a time).  So we do not support packed 24-bit samples.
550  * 24-bit data must be padded to 32 bits.
551  */
552 static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
553         struct snd_pcm_hw_params *hw_params)
554 {
555         struct snd_pcm_runtime *runtime = substream->runtime;
556         struct fsl_dma_private *dma_private = runtime->private_data;
557         struct snd_soc_pcm_runtime *rtd = substream->private_data;
558         struct device *dev = rtd->platform->dev;
559 
560         /* Number of bits per sample */
561         unsigned int sample_bits =
562                 snd_pcm_format_physical_width(params_format(hw_params));
563 
564         /* Number of bytes per frame */
565         unsigned int sample_bytes = sample_bits / 8;
566 
567         /* Bus address of SSI STX register */
568         dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
569 
570         /* Size of the DMA buffer, in bytes */
571         size_t buffer_size = params_buffer_bytes(hw_params);
572 
573         /* Number of bytes per period */
574         size_t period_size = params_period_bytes(hw_params);
575 
576         /* Pointer to next period */
577         dma_addr_t temp_addr = substream->dma_buffer.addr;
578 
579         /* Pointer to DMA controller */
580         struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
581 
582         u32 mr; /* DMA Mode Register */
583 
584         unsigned int i;
585 
586         /* Initialize our DMA tracking variables */
587         dma_private->period_size = period_size;
588         dma_private->num_periods = params_periods(hw_params);
589         dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
590         dma_private->dma_buf_next = dma_private->dma_buf_phys +
591                 (NUM_DMA_LINKS * period_size);
592 
593         if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
594                 /* This happens if the number of periods == NUM_DMA_LINKS */
595                 dma_private->dma_buf_next = dma_private->dma_buf_phys;
596 
597         mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
598                   CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
599 
600         /* Due to a quirk of the SSI's STX register, the target address
601          * for the DMA operations depends on the sample size.  So we calculate
602          * that offset here.  While we're at it, also tell the DMA controller
603          * how much data to transfer per sample.
604          */
605         switch (sample_bits) {
606         case 8:
607                 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
608                 ssi_sxx_phys += 3;
609                 break;
610         case 16:
611                 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
612                 ssi_sxx_phys += 2;
613                 break;
614         case 32:
615                 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
616                 break;
617         default:
618                 /* We should never get here */
619                 dev_err(dev, "unsupported sample size %u\n", sample_bits);
620                 return -EINVAL;
621         }
622 
623         /*
624          * BWC determines how many bytes are sent/received before the DMA
625          * controller checks the SSI to see if it needs to stop. BWC should
626          * always be a multiple of the frame size, so that we always transmit
627          * whole frames.  Each frame occupies two slots in the FIFO.  The
628          * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
629          * (MR[BWC] can only represent even powers of two).
630          *
631          * To simplify the process, we set BWC to the largest value that is
632          * less than or equal to the FIFO watermark.  For playback, this ensures
633          * that we transfer the maximum amount without overrunning the FIFO.
634          * For capture, this ensures that we transfer the maximum amount without
635          * underrunning the FIFO.
636          *
637          * f = SSI FIFO depth
638          * w = SSI watermark value (which equals f - 2)
639          * b = DMA bandwidth count (in bytes)
640          * s = sample size (in bytes, which equals frame_size * 2)
641          *
642          * For playback, we never transmit more than the transmit FIFO
643          * watermark, otherwise we might write more data than the FIFO can hold.
644          * The watermark is equal to the FIFO depth minus two.
645          *
646          * For capture, two equations must hold:
647          *      w > f - (b / s)
648          *      w >= b / s
649          *
650          * So, b > 2 * s, but b must also be <= s * w.  To simplify, we set
651          * b = s * w, which is equal to
652          *      (dma_private->ssi_fifo_depth - 2) * sample_bytes.
653          */
654         mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
655 
656         out_be32(&dma_channel->mr, mr);
657 
658         for (i = 0; i < NUM_DMA_LINKS; i++) {
659                 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
660 
661                 link->count = cpu_to_be32(period_size);
662 
663                 /* The snoop bit tells the DMA controller whether it should tell
664                  * the ECM to snoop during a read or write to an address. For
665                  * audio, we use DMA to transfer data between memory and an I/O
666                  * device (the SSI's STX0 or SRX0 register). Snooping is only
667                  * needed if there is a cache, so we need to snoop memory
668                  * addresses only.  For playback, that means we snoop the source
669                  * but not the destination.  For capture, we snoop the
670                  * destination but not the source.
671                  *
672                  * Note that failing to snoop properly is unlikely to cause
673                  * cache incoherency if the period size is larger than the
674                  * size of L1 cache.  This is because filling in one period will
675                  * flush out the data for the previous period.  So if you
676                  * increased period_bytes_min to a large enough size, you might
677                  * get more performance by not snooping, and you'll still be
678                  * okay.  You'll need to update fsl_dma_update_pointers() also.
679                  */
680                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
681                         link->source_addr = cpu_to_be32(temp_addr);
682                         link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
683                                 upper_32_bits(temp_addr));
684 
685                         link->dest_addr = cpu_to_be32(ssi_sxx_phys);
686                         link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
687                                 upper_32_bits(ssi_sxx_phys));
688                 } else {
689                         link->source_addr = cpu_to_be32(ssi_sxx_phys);
690                         link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
691                                 upper_32_bits(ssi_sxx_phys));
692 
693                         link->dest_addr = cpu_to_be32(temp_addr);
694                         link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
695                                 upper_32_bits(temp_addr));
696                 }
697 
698                 temp_addr += period_size;
699         }
700 
701         return 0;
702 }
703 
704 /**
705  * fsl_dma_pointer: determine the current position of the DMA transfer
706  *
707  * This function is called by ALSA when ALSA wants to know where in the
708  * stream buffer the hardware currently is.
709  *
710  * For playback, the SAR register contains the physical address of the most
711  * recent DMA transfer.  For capture, the value is in the DAR register.
712  *
713  * The base address of the buffer is stored in the source_addr field of the
714  * first link descriptor.
715  */
716 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
717 {
718         struct snd_pcm_runtime *runtime = substream->runtime;
719         struct fsl_dma_private *dma_private = runtime->private_data;
720         struct snd_soc_pcm_runtime *rtd = substream->private_data;
721         struct device *dev = rtd->platform->dev;
722         struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
723         dma_addr_t position;
724         snd_pcm_uframes_t frames;
725 
726         /* Obtain the current DMA pointer, but don't read the ESAD bits if we
727          * only have 32-bit DMA addresses.  This function is typically called
728          * in interrupt context, so we need to optimize it.
729          */
730         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
731                 position = in_be32(&dma_channel->sar);
732 #ifdef CONFIG_PHYS_64BIT
733                 position |= (u64)(in_be32(&dma_channel->satr) &
734                                   CCSR_DMA_ATR_ESAD_MASK) << 32;
735 #endif
736         } else {
737                 position = in_be32(&dma_channel->dar);
738 #ifdef CONFIG_PHYS_64BIT
739                 position |= (u64)(in_be32(&dma_channel->datr) &
740                                   CCSR_DMA_ATR_ESAD_MASK) << 32;
741 #endif
742         }
743 
744         /*
745          * When capture is started, the SSI immediately starts to fill its FIFO.
746          * This means that the DMA controller is not started until the FIFO is
747          * full.  However, ALSA calls this function before that happens, when
748          * MR.DAR is still zero.  In this case, just return zero to indicate
749          * that nothing has been received yet.
750          */
751         if (!position)
752                 return 0;
753 
754         if ((position < dma_private->dma_buf_phys) ||
755             (position > dma_private->dma_buf_end)) {
756                 dev_err(dev, "dma pointer is out of range, halting stream\n");
757                 return SNDRV_PCM_POS_XRUN;
758         }
759 
760         frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
761 
762         /*
763          * If the current address is just past the end of the buffer, wrap it
764          * around.
765          */
766         if (frames == runtime->buffer_size)
767                 frames = 0;
768 
769         return frames;
770 }
771 
772 /**
773  * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
774  *
775  * Release the resources allocated in fsl_dma_hw_params() and de-program the
776  * registers.
777  *
778  * This function can be called multiple times.
779  */
780 static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
781 {
782         struct snd_pcm_runtime *runtime = substream->runtime;
783         struct fsl_dma_private *dma_private = runtime->private_data;
784 
785         if (dma_private) {
786                 struct ccsr_dma_channel __iomem *dma_channel;
787 
788                 dma_channel = dma_private->dma_channel;
789 
790                 /* Stop the DMA */
791                 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
792                 out_be32(&dma_channel->mr, 0);
793 
794                 /* Reset all the other registers */
795                 out_be32(&dma_channel->sr, -1);
796                 out_be32(&dma_channel->clndar, 0);
797                 out_be32(&dma_channel->eclndar, 0);
798                 out_be32(&dma_channel->satr, 0);
799                 out_be32(&dma_channel->sar, 0);
800                 out_be32(&dma_channel->datr, 0);
801                 out_be32(&dma_channel->dar, 0);
802                 out_be32(&dma_channel->bcr, 0);
803                 out_be32(&dma_channel->nlndar, 0);
804                 out_be32(&dma_channel->enlndar, 0);
805         }
806 
807         return 0;
808 }
809 
810 /**
811  * fsl_dma_close: close the stream.
812  */
813 static int fsl_dma_close(struct snd_pcm_substream *substream)
814 {
815         struct snd_pcm_runtime *runtime = substream->runtime;
816         struct fsl_dma_private *dma_private = runtime->private_data;
817         struct snd_soc_pcm_runtime *rtd = substream->private_data;
818         struct device *dev = rtd->platform->dev;
819         struct dma_object *dma =
820                 container_of(rtd->platform->driver, struct dma_object, dai);
821 
822         if (dma_private) {
823                 if (dma_private->irq)
824                         free_irq(dma_private->irq, dma_private);
825 
826                 if (dma_private->ld_buf_phys) {
827                         dma_unmap_single(dev, dma_private->ld_buf_phys,
828                                          sizeof(dma_private->link),
829                                          DMA_TO_DEVICE);
830                 }
831 
832                 /* Deallocate the fsl_dma_private structure */
833                 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
834                                   dma_private, dma_private->ld_buf_phys);
835                 substream->runtime->private_data = NULL;
836         }
837 
838         dma->assigned = 0;
839 
840         return 0;
841 }
842 
843 /*
844  * Remove this PCM driver.
845  */
846 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
847 {
848         struct snd_pcm_substream *substream;
849         unsigned int i;
850 
851         for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
852                 substream = pcm->streams[i].substream;
853                 if (substream) {
854                         snd_dma_free_pages(&substream->dma_buffer);
855                         substream->dma_buffer.area = NULL;
856                         substream->dma_buffer.addr = 0;
857                 }
858         }
859 }
860 
861 /**
862  * find_ssi_node -- returns the SSI node that points to his DMA channel node
863  *
864  * Although this DMA driver attempts to operate independently of the other
865  * devices, it still needs to determine some information about the SSI device
866  * that it's working with.  Unfortunately, the device tree does not contain
867  * a pointer from the DMA channel node to the SSI node -- the pointer goes the
868  * other way.  So we need to scan the device tree for SSI nodes until we find
869  * the one that points to the given DMA channel node.  It's ugly, but at least
870  * it's contained in this one function.
871  */
872 static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
873 {
874         struct device_node *ssi_np, *np;
875 
876         for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
877                 /* Check each DMA phandle to see if it points to us.  We
878                  * assume that device_node pointers are a valid comparison.
879                  */
880                 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
881                 of_node_put(np);
882                 if (np == dma_channel_np)
883                         return ssi_np;
884 
885                 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
886                 of_node_put(np);
887                 if (np == dma_channel_np)
888                         return ssi_np;
889         }
890 
891         return NULL;
892 }
893 
894 static struct snd_pcm_ops fsl_dma_ops = {
895         .open           = fsl_dma_open,
896         .close          = fsl_dma_close,
897         .ioctl          = snd_pcm_lib_ioctl,
898         .hw_params      = fsl_dma_hw_params,
899         .hw_free        = fsl_dma_hw_free,
900         .pointer        = fsl_dma_pointer,
901 };
902 
903 static int __devinit fsl_soc_dma_probe(struct platform_device *pdev)
904  {
905         struct dma_object *dma;
906         struct device_node *np = pdev->dev.of_node;
907         struct device_node *ssi_np;
908         struct resource res;
909         const uint32_t *iprop;
910         int ret;
911 
912         /* Find the SSI node that points to us. */
913         ssi_np = find_ssi_node(np);
914         if (!ssi_np) {
915                 dev_err(&pdev->dev, "cannot find parent SSI node\n");
916                 return -ENODEV;
917         }
918 
919         ret = of_address_to_resource(ssi_np, 0, &res);
920         if (ret) {
921                 dev_err(&pdev->dev, "could not determine resources for %s\n",
922                         ssi_np->full_name);
923                 of_node_put(ssi_np);
924                 return ret;
925         }
926 
927         dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL);
928         if (!dma) {
929                 dev_err(&pdev->dev, "could not allocate dma object\n");
930                 of_node_put(ssi_np);
931                 return -ENOMEM;
932         }
933 
934         strcpy(dma->path, np->full_name);
935         dma->dai.ops = &fsl_dma_ops;
936         dma->dai.pcm_new = fsl_dma_new;
937         dma->dai.pcm_free = fsl_dma_free_dma_buffers;
938 
939         /* Store the SSI-specific information that we need */
940         dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0);
941         dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0);
942 
943         iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
944         if (iprop)
945                 dma->ssi_fifo_depth = be32_to_cpup(iprop);
946         else
947                 /* Older 8610 DTs didn't have the fifo-depth property */
948                 dma->ssi_fifo_depth = 8;
949 
950         of_node_put(ssi_np);
951 
952         ret = snd_soc_register_platform(&pdev->dev, &dma->dai);
953         if (ret) {
954                 dev_err(&pdev->dev, "could not register platform\n");
955                 kfree(dma);
956                 return ret;
957         }
958 
959         dma->channel = of_iomap(np, 0);
960         dma->irq = irq_of_parse_and_map(np, 0);
961 
962         dev_set_drvdata(&pdev->dev, dma);
963 
964         return 0;
965 }
966 
967 static int __devexit fsl_soc_dma_remove(struct platform_device *pdev)
968 {
969         struct dma_object *dma = dev_get_drvdata(&pdev->dev);
970 
971         snd_soc_unregister_platform(&pdev->dev);
972         iounmap(dma->channel);
973         irq_dispose_mapping(dma->irq);
974         kfree(dma);
975 
976         return 0;
977 }
978 
979 static const struct of_device_id fsl_soc_dma_ids[] = {
980         { .compatible = "fsl,ssi-dma-channel", },
981         {}
982 };
983 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
984 
985 static struct platform_driver fsl_soc_dma_driver = {
986         .driver = {
987                 .name = "fsl-pcm-audio",
988                 .owner = THIS_MODULE,
989                 .of_match_table = fsl_soc_dma_ids,
990         },
991         .probe = fsl_soc_dma_probe,
992         .remove = __devexit_p(fsl_soc_dma_remove),
993 };
994 
995 module_platform_driver(fsl_soc_dma_driver);
996 
997 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
998 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
999 MODULE_LICENSE("GPL v2");
1000 

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