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Linux/sound/soc/fsl/fsl_esai.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 //
  3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
  4 //
  5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
  6 
  7 #include <linux/clk.h>
  8 #include <linux/dmaengine.h>
  9 #include <linux/module.h>
 10 #include <linux/of_irq.h>
 11 #include <linux/of_platform.h>
 12 #include <sound/dmaengine_pcm.h>
 13 #include <sound/pcm_params.h>
 14 
 15 #include "fsl_esai.h"
 16 #include "imx-pcm.h"
 17 
 18 #define FSL_ESAI_FORMATS        (SNDRV_PCM_FMTBIT_S8 | \
 19                                 SNDRV_PCM_FMTBIT_S16_LE | \
 20                                 SNDRV_PCM_FMTBIT_S20_3LE | \
 21                                 SNDRV_PCM_FMTBIT_S24_LE)
 22 
 23 /**
 24  * fsl_esai: ESAI private data
 25  *
 26  * @dma_params_rx: DMA parameters for receive channel
 27  * @dma_params_tx: DMA parameters for transmit channel
 28  * @pdev: platform device pointer
 29  * @regmap: regmap handler
 30  * @coreclk: clock source to access register
 31  * @extalclk: esai clock source to derive HCK, SCK and FS
 32  * @fsysclk: system clock source to derive HCK, SCK and FS
 33  * @spbaclk: SPBA clock (optional, depending on SoC design)
 34  * @fifo_depth: depth of tx/rx FIFO
 35  * @slot_width: width of each DAI slot
 36  * @slots: number of slots
 37  * @hck_rate: clock rate of desired HCKx clock
 38  * @sck_rate: clock rate of desired SCKx clock
 39  * @hck_dir: the direction of HCKx pads
 40  * @sck_div: if using PSR/PM dividers for SCKx clock
 41  * @slave_mode: if fully using DAI slave mode
 42  * @synchronous: if using tx/rx synchronous mode
 43  * @name: driver name
 44  */
 45 struct fsl_esai {
 46         struct snd_dmaengine_dai_dma_data dma_params_rx;
 47         struct snd_dmaengine_dai_dma_data dma_params_tx;
 48         struct platform_device *pdev;
 49         struct regmap *regmap;
 50         struct clk *coreclk;
 51         struct clk *extalclk;
 52         struct clk *fsysclk;
 53         struct clk *spbaclk;
 54         u32 fifo_depth;
 55         u32 slot_width;
 56         u32 slots;
 57         u32 tx_mask;
 58         u32 rx_mask;
 59         u32 hck_rate[2];
 60         u32 sck_rate[2];
 61         bool hck_dir[2];
 62         bool sck_div[2];
 63         bool slave_mode;
 64         bool synchronous;
 65         char name[32];
 66 };
 67 
 68 static irqreturn_t esai_isr(int irq, void *devid)
 69 {
 70         struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
 71         struct platform_device *pdev = esai_priv->pdev;
 72         u32 esr;
 73 
 74         regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
 75 
 76         if (esr & ESAI_ESR_TINIT_MASK)
 77                 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
 78 
 79         if (esr & ESAI_ESR_RFF_MASK)
 80                 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
 81 
 82         if (esr & ESAI_ESR_TFE_MASK)
 83                 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
 84 
 85         if (esr & ESAI_ESR_TLS_MASK)
 86                 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
 87 
 88         if (esr & ESAI_ESR_TDE_MASK)
 89                 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
 90 
 91         if (esr & ESAI_ESR_TED_MASK)
 92                 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
 93 
 94         if (esr & ESAI_ESR_TD_MASK)
 95                 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
 96 
 97         if (esr & ESAI_ESR_RLS_MASK)
 98                 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
 99 
100         if (esr & ESAI_ESR_RDE_MASK)
101                 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
102 
103         if (esr & ESAI_ESR_RED_MASK)
104                 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
105 
106         if (esr & ESAI_ESR_RD_MASK)
107                 dev_dbg(&pdev->dev, "isr: Receiving data\n");
108 
109         return IRQ_HANDLED;
110 }
111 
112 /**
113  * This function is used to calculate the divisors of psr, pm, fp and it is
114  * supposed to be called in set_dai_sysclk() and set_bclk().
115  *
116  * @ratio: desired overall ratio for the paticipating dividers
117  * @usefp: for HCK setting, there is no need to set fp divider
118  * @fp: bypass other dividers by setting fp directly if fp != 0
119  * @tx: current setting is for playback or capture
120  */
121 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
122                                 bool usefp, u32 fp)
123 {
124         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
125         u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
126 
127         maxfp = usefp ? 16 : 1;
128 
129         if (usefp && fp)
130                 goto out_fp;
131 
132         if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
133                 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
134                                 2 * 8 * 256 * maxfp);
135                 return -EINVAL;
136         } else if (ratio % 2) {
137                 dev_err(dai->dev, "the raio must be even if using upper divider\n");
138                 return -EINVAL;
139         }
140 
141         ratio /= 2;
142 
143         psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
144 
145         /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
146         if (ratio <= 256) {
147                 pm = ratio;
148                 fp = 1;
149                 goto out;
150         }
151 
152         /* Set the max fluctuation -- 0.1% of the max devisor */
153         savesub = (psr ? 1 : 8)  * 256 * maxfp / 1000;
154 
155         /* Find the best value for PM */
156         for (i = 1; i <= 256; i++) {
157                 for (j = 1; j <= maxfp; j++) {
158                         /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
159                         prod = (psr ? 1 : 8) * i * j;
160 
161                         if (prod == ratio)
162                                 sub = 0;
163                         else if (prod / ratio == 1)
164                                 sub = prod - ratio;
165                         else if (ratio / prod == 1)
166                                 sub = ratio - prod;
167                         else
168                                 continue;
169 
170                         /* Calculate the fraction */
171                         sub = sub * 1000 / ratio;
172                         if (sub < savesub) {
173                                 savesub = sub;
174                                 pm = i;
175                                 fp = j;
176                         }
177 
178                         /* We are lucky */
179                         if (savesub == 0)
180                                 goto out;
181                 }
182         }
183 
184         if (pm == 999) {
185                 dev_err(dai->dev, "failed to calculate proper divisors\n");
186                 return -EINVAL;
187         }
188 
189 out:
190         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
191                            ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
192                            psr | ESAI_xCCR_xPM(pm));
193 
194 out_fp:
195         /* Bypass fp if not being required */
196         if (maxfp <= 1)
197                 return 0;
198 
199         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
200                            ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
201 
202         return 0;
203 }
204 
205 /**
206  * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
207  *
208  * @Parameters:
209  * clk_id: The clock source of HCKT/HCKR
210  *        (Input from outside; output from inside, FSYS or EXTAL)
211  * freq: The required clock rate of HCKT/HCKR
212  * dir: The clock direction of HCKT/HCKR
213  *
214  * Note: If the direction is input, we do not care about clk_id.
215  */
216 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
217                                    unsigned int freq, int dir)
218 {
219         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
220         struct clk *clksrc = esai_priv->extalclk;
221         bool tx = clk_id <= ESAI_HCKT_EXTAL;
222         bool in = dir == SND_SOC_CLOCK_IN;
223         u32 ratio, ecr = 0;
224         unsigned long clk_rate;
225         int ret;
226 
227         if (freq == 0) {
228                 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
229                         in ? "in" : "out", tx ? 'T' : 'R');
230                 return -EINVAL;
231         }
232 
233         /* Bypass divider settings if the requirement doesn't change */
234         if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
235                 return 0;
236 
237         /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
238         esai_priv->sck_div[tx] = true;
239 
240         /* Set the direction of HCKT/HCKR pins */
241         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
242                            ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
243 
244         if (in)
245                 goto out;
246 
247         switch (clk_id) {
248         case ESAI_HCKT_FSYS:
249         case ESAI_HCKR_FSYS:
250                 clksrc = esai_priv->fsysclk;
251                 break;
252         case ESAI_HCKT_EXTAL:
253                 ecr |= ESAI_ECR_ETI;
254                 /* fall through */
255         case ESAI_HCKR_EXTAL:
256                 ecr |= ESAI_ECR_ERI;
257                 break;
258         default:
259                 return -EINVAL;
260         }
261 
262         if (IS_ERR(clksrc)) {
263                 dev_err(dai->dev, "no assigned %s clock\n",
264                                 clk_id % 2 ? "extal" : "fsys");
265                 return PTR_ERR(clksrc);
266         }
267         clk_rate = clk_get_rate(clksrc);
268 
269         ratio = clk_rate / freq;
270         if (ratio * freq > clk_rate)
271                 ret = ratio * freq - clk_rate;
272         else if (ratio * freq < clk_rate)
273                 ret = clk_rate - ratio * freq;
274         else
275                 ret = 0;
276 
277         /* Block if clock source can not be divided into the required rate */
278         if (ret != 0 && clk_rate / ret < 1000) {
279                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
280                                 tx ? 'T' : 'R');
281                 return -EINVAL;
282         }
283 
284         /* Only EXTAL source can be output directly without using PSR and PM */
285         if (ratio == 1 && clksrc == esai_priv->extalclk) {
286                 /* Bypass all the dividers if not being needed */
287                 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
288                 goto out;
289         } else if (ratio < 2) {
290                 /* The ratio should be no less than 2 if using other sources */
291                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
292                                 tx ? 'T' : 'R');
293                 return -EINVAL;
294         }
295 
296         ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
297         if (ret)
298                 return ret;
299 
300         esai_priv->sck_div[tx] = false;
301 
302 out:
303         esai_priv->hck_dir[tx] = dir;
304         esai_priv->hck_rate[tx] = freq;
305 
306         regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
307                            tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
308                            ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
309 
310         return 0;
311 }
312 
313 /**
314  * This function configures the related dividers according to the bclk rate
315  */
316 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
317 {
318         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
319         u32 hck_rate = esai_priv->hck_rate[tx];
320         u32 sub, ratio = hck_rate / freq;
321         int ret;
322 
323         /* Don't apply for fully slave mode or unchanged bclk */
324         if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
325                 return 0;
326 
327         if (ratio * freq > hck_rate)
328                 sub = ratio * freq - hck_rate;
329         else if (ratio * freq < hck_rate)
330                 sub = hck_rate - ratio * freq;
331         else
332                 sub = 0;
333 
334         /* Block if clock source can not be divided into the required rate */
335         if (sub != 0 && hck_rate / sub < 1000) {
336                 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
337                                 tx ? 'T' : 'R');
338                 return -EINVAL;
339         }
340 
341         /* The ratio should be contented by FP alone if bypassing PM and PSR */
342         if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
343                 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
344                 return -EINVAL;
345         }
346 
347         ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
348                         esai_priv->sck_div[tx] ? 0 : ratio);
349         if (ret)
350                 return ret;
351 
352         /* Save current bclk rate */
353         esai_priv->sck_rate[tx] = freq;
354 
355         return 0;
356 }
357 
358 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
359                                      u32 rx_mask, int slots, int slot_width)
360 {
361         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
362 
363         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
364                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
365 
366         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
367                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
368 
369         esai_priv->slot_width = slot_width;
370         esai_priv->slots = slots;
371         esai_priv->tx_mask = tx_mask;
372         esai_priv->rx_mask = rx_mask;
373 
374         return 0;
375 }
376 
377 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
378 {
379         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
380         u32 xcr = 0, xccr = 0, mask;
381 
382         /* DAI mode */
383         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
384         case SND_SOC_DAIFMT_I2S:
385                 /* Data on rising edge of bclk, frame low, 1clk before data */
386                 xcr |= ESAI_xCR_xFSR;
387                 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
388                 break;
389         case SND_SOC_DAIFMT_LEFT_J:
390                 /* Data on rising edge of bclk, frame high */
391                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
392                 break;
393         case SND_SOC_DAIFMT_RIGHT_J:
394                 /* Data on rising edge of bclk, frame high, right aligned */
395                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
396                 xcr  |= ESAI_xCR_xWA;
397                 break;
398         case SND_SOC_DAIFMT_DSP_A:
399                 /* Data on rising edge of bclk, frame high, 1clk before data */
400                 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
401                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
402                 break;
403         case SND_SOC_DAIFMT_DSP_B:
404                 /* Data on rising edge of bclk, frame high */
405                 xcr |= ESAI_xCR_xFSL;
406                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
407                 break;
408         default:
409                 return -EINVAL;
410         }
411 
412         /* DAI clock inversion */
413         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
414         case SND_SOC_DAIFMT_NB_NF:
415                 /* Nothing to do for both normal cases */
416                 break;
417         case SND_SOC_DAIFMT_IB_NF:
418                 /* Invert bit clock */
419                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
420                 break;
421         case SND_SOC_DAIFMT_NB_IF:
422                 /* Invert frame clock */
423                 xccr ^= ESAI_xCCR_xFSP;
424                 break;
425         case SND_SOC_DAIFMT_IB_IF:
426                 /* Invert both clocks */
427                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
428                 break;
429         default:
430                 return -EINVAL;
431         }
432 
433         esai_priv->slave_mode = false;
434 
435         /* DAI clock master masks */
436         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
437         case SND_SOC_DAIFMT_CBM_CFM:
438                 esai_priv->slave_mode = true;
439                 break;
440         case SND_SOC_DAIFMT_CBS_CFM:
441                 xccr |= ESAI_xCCR_xCKD;
442                 break;
443         case SND_SOC_DAIFMT_CBM_CFS:
444                 xccr |= ESAI_xCCR_xFSD;
445                 break;
446         case SND_SOC_DAIFMT_CBS_CFS:
447                 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
448                 break;
449         default:
450                 return -EINVAL;
451         }
452 
453         mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
454         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
455         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
456 
457         mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
458                 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
459         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
460         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
461 
462         return 0;
463 }
464 
465 static int fsl_esai_startup(struct snd_pcm_substream *substream,
466                             struct snd_soc_dai *dai)
467 {
468         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
469         int ret;
470 
471         /*
472          * Some platforms might use the same bit to gate all three or two of
473          * clocks, so keep all clocks open/close at the same time for safety
474          */
475         ret = clk_prepare_enable(esai_priv->coreclk);
476         if (ret)
477                 return ret;
478         if (!IS_ERR(esai_priv->spbaclk)) {
479                 ret = clk_prepare_enable(esai_priv->spbaclk);
480                 if (ret)
481                         goto err_spbaclk;
482         }
483         if (!IS_ERR(esai_priv->extalclk)) {
484                 ret = clk_prepare_enable(esai_priv->extalclk);
485                 if (ret)
486                         goto err_extalck;
487         }
488         if (!IS_ERR(esai_priv->fsysclk)) {
489                 ret = clk_prepare_enable(esai_priv->fsysclk);
490                 if (ret)
491                         goto err_fsysclk;
492         }
493 
494         if (!dai->active) {
495                 /* Set synchronous mode */
496                 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
497                                    ESAI_SAICR_SYNC, esai_priv->synchronous ?
498                                    ESAI_SAICR_SYNC : 0);
499 
500                 /* Set a default slot number -- 2 */
501                 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
502                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
503                 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
504                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
505         }
506 
507         return 0;
508 
509 err_fsysclk:
510         if (!IS_ERR(esai_priv->extalclk))
511                 clk_disable_unprepare(esai_priv->extalclk);
512 err_extalck:
513         if (!IS_ERR(esai_priv->spbaclk))
514                 clk_disable_unprepare(esai_priv->spbaclk);
515 err_spbaclk:
516         clk_disable_unprepare(esai_priv->coreclk);
517 
518         return ret;
519 }
520 
521 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
522                               struct snd_pcm_hw_params *params,
523                               struct snd_soc_dai *dai)
524 {
525         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
526         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
527         u32 width = params_width(params);
528         u32 channels = params_channels(params);
529         u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
530         u32 slot_width = width;
531         u32 bclk, mask, val;
532         int ret;
533 
534         /* Override slot_width if being specifically set */
535         if (esai_priv->slot_width)
536                 slot_width = esai_priv->slot_width;
537 
538         bclk = params_rate(params) * slot_width * esai_priv->slots;
539 
540         ret = fsl_esai_set_bclk(dai, tx, bclk);
541         if (ret)
542                 return ret;
543 
544         /* Use Normal mode to support monaural audio */
545         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
546                            ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
547                            ESAI_xCR_xMOD_NETWORK : 0);
548 
549         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
550                            ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
551 
552         mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
553               (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
554         val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
555              (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
556 
557         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
558 
559         mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
560         val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
561 
562         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
563 
564         /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
565         regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
566                            ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
567         regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
568                            ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
569         return 0;
570 }
571 
572 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
573                               struct snd_soc_dai *dai)
574 {
575         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
576 
577         if (!IS_ERR(esai_priv->fsysclk))
578                 clk_disable_unprepare(esai_priv->fsysclk);
579         if (!IS_ERR(esai_priv->extalclk))
580                 clk_disable_unprepare(esai_priv->extalclk);
581         if (!IS_ERR(esai_priv->spbaclk))
582                 clk_disable_unprepare(esai_priv->spbaclk);
583         clk_disable_unprepare(esai_priv->coreclk);
584 }
585 
586 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
587                             struct snd_soc_dai *dai)
588 {
589         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
590         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
591         u8 i, channels = substream->runtime->channels;
592         u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
593         u32 mask;
594 
595         switch (cmd) {
596         case SNDRV_PCM_TRIGGER_START:
597         case SNDRV_PCM_TRIGGER_RESUME:
598         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
599                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
600                                    ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
601 
602                 /* Write initial words reqiured by ESAI as normal procedure */
603                 for (i = 0; tx && i < channels; i++)
604                         regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
605 
606                 /*
607                  * When set the TE/RE in the end of enablement flow, there
608                  * will be channel swap issue for multi data line case.
609                  * In order to workaround this issue, we switch the bit
610                  * enablement sequence to below sequence
611                  * 1) clear the xSMB & xSMA: which is done in probe and
612                  *                           stop state.
613                  * 2) set TE/RE
614                  * 3) set xSMB
615                  * 4) set xSMA:  xSMA is the last one in this flow, which
616                  *               will trigger esai to start.
617                  */
618                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
619                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
620                                    tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
621                 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
622 
623                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
624                                    ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
625                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
626                                    ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
627 
628                 break;
629         case SNDRV_PCM_TRIGGER_SUSPEND:
630         case SNDRV_PCM_TRIGGER_STOP:
631         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
632                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
633                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
634                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
635                                    ESAI_xSMA_xS_MASK, 0);
636                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
637                                    ESAI_xSMB_xS_MASK, 0);
638 
639                 /* Disable and reset FIFO */
640                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
641                                    ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
642                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
643                                    ESAI_xFCR_xFR, 0);
644                 break;
645         default:
646                 return -EINVAL;
647         }
648 
649         return 0;
650 }
651 
652 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
653         .startup = fsl_esai_startup,
654         .shutdown = fsl_esai_shutdown,
655         .trigger = fsl_esai_trigger,
656         .hw_params = fsl_esai_hw_params,
657         .set_sysclk = fsl_esai_set_dai_sysclk,
658         .set_fmt = fsl_esai_set_dai_fmt,
659         .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
660 };
661 
662 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
663 {
664         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
665 
666         snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
667                                   &esai_priv->dma_params_rx);
668 
669         return 0;
670 }
671 
672 static struct snd_soc_dai_driver fsl_esai_dai = {
673         .probe = fsl_esai_dai_probe,
674         .playback = {
675                 .stream_name = "CPU-Playback",
676                 .channels_min = 1,
677                 .channels_max = 12,
678                 .rates = SNDRV_PCM_RATE_8000_192000,
679                 .formats = FSL_ESAI_FORMATS,
680         },
681         .capture = {
682                 .stream_name = "CPU-Capture",
683                 .channels_min = 1,
684                 .channels_max = 8,
685                 .rates = SNDRV_PCM_RATE_8000_192000,
686                 .formats = FSL_ESAI_FORMATS,
687         },
688         .ops = &fsl_esai_dai_ops,
689 };
690 
691 static const struct snd_soc_component_driver fsl_esai_component = {
692         .name           = "fsl-esai",
693 };
694 
695 static const struct reg_default fsl_esai_reg_defaults[] = {
696         {REG_ESAI_ETDR,  0x00000000},
697         {REG_ESAI_ECR,   0x00000000},
698         {REG_ESAI_TFCR,  0x00000000},
699         {REG_ESAI_RFCR,  0x00000000},
700         {REG_ESAI_TX0,   0x00000000},
701         {REG_ESAI_TX1,   0x00000000},
702         {REG_ESAI_TX2,   0x00000000},
703         {REG_ESAI_TX3,   0x00000000},
704         {REG_ESAI_TX4,   0x00000000},
705         {REG_ESAI_TX5,   0x00000000},
706         {REG_ESAI_TSR,   0x00000000},
707         {REG_ESAI_SAICR, 0x00000000},
708         {REG_ESAI_TCR,   0x00000000},
709         {REG_ESAI_TCCR,  0x00000000},
710         {REG_ESAI_RCR,   0x00000000},
711         {REG_ESAI_RCCR,  0x00000000},
712         {REG_ESAI_TSMA,  0x0000ffff},
713         {REG_ESAI_TSMB,  0x0000ffff},
714         {REG_ESAI_RSMA,  0x0000ffff},
715         {REG_ESAI_RSMB,  0x0000ffff},
716         {REG_ESAI_PRRC,  0x00000000},
717         {REG_ESAI_PCRC,  0x00000000},
718 };
719 
720 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
721 {
722         switch (reg) {
723         case REG_ESAI_ERDR:
724         case REG_ESAI_ECR:
725         case REG_ESAI_ESR:
726         case REG_ESAI_TFCR:
727         case REG_ESAI_TFSR:
728         case REG_ESAI_RFCR:
729         case REG_ESAI_RFSR:
730         case REG_ESAI_RX0:
731         case REG_ESAI_RX1:
732         case REG_ESAI_RX2:
733         case REG_ESAI_RX3:
734         case REG_ESAI_SAISR:
735         case REG_ESAI_SAICR:
736         case REG_ESAI_TCR:
737         case REG_ESAI_TCCR:
738         case REG_ESAI_RCR:
739         case REG_ESAI_RCCR:
740         case REG_ESAI_TSMA:
741         case REG_ESAI_TSMB:
742         case REG_ESAI_RSMA:
743         case REG_ESAI_RSMB:
744         case REG_ESAI_PRRC:
745         case REG_ESAI_PCRC:
746                 return true;
747         default:
748                 return false;
749         }
750 }
751 
752 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
753 {
754         switch (reg) {
755         case REG_ESAI_ERDR:
756         case REG_ESAI_ESR:
757         case REG_ESAI_TFSR:
758         case REG_ESAI_RFSR:
759         case REG_ESAI_RX0:
760         case REG_ESAI_RX1:
761         case REG_ESAI_RX2:
762         case REG_ESAI_RX3:
763         case REG_ESAI_SAISR:
764                 return true;
765         default:
766                 return false;
767         }
768 }
769 
770 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
771 {
772         switch (reg) {
773         case REG_ESAI_ETDR:
774         case REG_ESAI_ECR:
775         case REG_ESAI_TFCR:
776         case REG_ESAI_RFCR:
777         case REG_ESAI_TX0:
778         case REG_ESAI_TX1:
779         case REG_ESAI_TX2:
780         case REG_ESAI_TX3:
781         case REG_ESAI_TX4:
782         case REG_ESAI_TX5:
783         case REG_ESAI_TSR:
784         case REG_ESAI_SAICR:
785         case REG_ESAI_TCR:
786         case REG_ESAI_TCCR:
787         case REG_ESAI_RCR:
788         case REG_ESAI_RCCR:
789         case REG_ESAI_TSMA:
790         case REG_ESAI_TSMB:
791         case REG_ESAI_RSMA:
792         case REG_ESAI_RSMB:
793         case REG_ESAI_PRRC:
794         case REG_ESAI_PCRC:
795                 return true;
796         default:
797                 return false;
798         }
799 }
800 
801 static const struct regmap_config fsl_esai_regmap_config = {
802         .reg_bits = 32,
803         .reg_stride = 4,
804         .val_bits = 32,
805 
806         .max_register = REG_ESAI_PCRC,
807         .reg_defaults = fsl_esai_reg_defaults,
808         .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
809         .readable_reg = fsl_esai_readable_reg,
810         .volatile_reg = fsl_esai_volatile_reg,
811         .writeable_reg = fsl_esai_writeable_reg,
812         .cache_type = REGCACHE_FLAT,
813 };
814 
815 static int fsl_esai_probe(struct platform_device *pdev)
816 {
817         struct device_node *np = pdev->dev.of_node;
818         struct fsl_esai *esai_priv;
819         struct resource *res;
820         const __be32 *iprop;
821         void __iomem *regs;
822         int irq, ret;
823 
824         esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
825         if (!esai_priv)
826                 return -ENOMEM;
827 
828         esai_priv->pdev = pdev;
829         snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
830 
831         /* Get the addresses and IRQ */
832         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833         regs = devm_ioremap_resource(&pdev->dev, res);
834         if (IS_ERR(regs))
835                 return PTR_ERR(regs);
836 
837         esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
838                         "core", regs, &fsl_esai_regmap_config);
839         if (IS_ERR(esai_priv->regmap)) {
840                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
841                                 PTR_ERR(esai_priv->regmap));
842                 return PTR_ERR(esai_priv->regmap);
843         }
844 
845         esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
846         if (IS_ERR(esai_priv->coreclk)) {
847                 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
848                                 PTR_ERR(esai_priv->coreclk));
849                 return PTR_ERR(esai_priv->coreclk);
850         }
851 
852         esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
853         if (IS_ERR(esai_priv->extalclk))
854                 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
855                                 PTR_ERR(esai_priv->extalclk));
856 
857         esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
858         if (IS_ERR(esai_priv->fsysclk))
859                 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
860                                 PTR_ERR(esai_priv->fsysclk));
861 
862         esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
863         if (IS_ERR(esai_priv->spbaclk))
864                 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
865                                 PTR_ERR(esai_priv->spbaclk));
866 
867         irq = platform_get_irq(pdev, 0);
868         if (irq < 0) {
869                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
870                 return irq;
871         }
872 
873         ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
874                                esai_priv->name, esai_priv);
875         if (ret) {
876                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
877                 return ret;
878         }
879 
880         /* Set a default slot number */
881         esai_priv->slots = 2;
882 
883         /* Set a default master/slave state */
884         esai_priv->slave_mode = true;
885 
886         /* Determine the FIFO depth */
887         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
888         if (iprop)
889                 esai_priv->fifo_depth = be32_to_cpup(iprop);
890         else
891                 esai_priv->fifo_depth = 64;
892 
893         esai_priv->dma_params_tx.maxburst = 16;
894         esai_priv->dma_params_rx.maxburst = 16;
895         esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
896         esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
897 
898         esai_priv->synchronous =
899                 of_property_read_bool(np, "fsl,esai-synchronous");
900 
901         /* Implement full symmetry for synchronous mode */
902         if (esai_priv->synchronous) {
903                 fsl_esai_dai.symmetric_rates = 1;
904                 fsl_esai_dai.symmetric_channels = 1;
905                 fsl_esai_dai.symmetric_samplebits = 1;
906         }
907 
908         dev_set_drvdata(&pdev->dev, esai_priv);
909 
910         /* Reset ESAI unit */
911         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
912         if (ret) {
913                 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
914                 return ret;
915         }
916 
917         /*
918          * We need to enable ESAI so as to access some of its registers.
919          * Otherwise, we would fail to dump regmap from user space.
920          */
921         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
922         if (ret) {
923                 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
924                 return ret;
925         }
926 
927         esai_priv->tx_mask = 0xFFFFFFFF;
928         esai_priv->rx_mask = 0xFFFFFFFF;
929 
930         /* Clear the TSMA, TSMB, RSMA, RSMB */
931         regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
932         regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
933         regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
934         regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
935 
936         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
937                                               &fsl_esai_dai, 1);
938         if (ret) {
939                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
940                 return ret;
941         }
942 
943         ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
944         if (ret)
945                 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
946 
947         return ret;
948 }
949 
950 static const struct of_device_id fsl_esai_dt_ids[] = {
951         { .compatible = "fsl,imx35-esai", },
952         { .compatible = "fsl,vf610-esai", },
953         {}
954 };
955 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
956 
957 #ifdef CONFIG_PM_SLEEP
958 static int fsl_esai_suspend(struct device *dev)
959 {
960         struct fsl_esai *esai = dev_get_drvdata(dev);
961 
962         regcache_cache_only(esai->regmap, true);
963         regcache_mark_dirty(esai->regmap);
964 
965         return 0;
966 }
967 
968 static int fsl_esai_resume(struct device *dev)
969 {
970         struct fsl_esai *esai = dev_get_drvdata(dev);
971         int ret;
972 
973         regcache_cache_only(esai->regmap, false);
974 
975         /* FIFO reset for safety */
976         regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
977                            ESAI_xFCR_xFR, ESAI_xFCR_xFR);
978         regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
979                            ESAI_xFCR_xFR, ESAI_xFCR_xFR);
980 
981         ret = regcache_sync(esai->regmap);
982         if (ret)
983                 return ret;
984 
985         /* FIFO reset done */
986         regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
987         regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
988 
989         return 0;
990 }
991 #endif /* CONFIG_PM_SLEEP */
992 
993 static const struct dev_pm_ops fsl_esai_pm_ops = {
994         SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
995 };
996 
997 static struct platform_driver fsl_esai_driver = {
998         .probe = fsl_esai_probe,
999         .driver = {
1000                 .name = "fsl-esai-dai",
1001                 .pm = &fsl_esai_pm_ops,
1002                 .of_match_table = fsl_esai_dt_ids,
1003         },
1004 };
1005 
1006 module_platform_driver(fsl_esai_driver);
1007 
1008 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1009 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1010 MODULE_LICENSE("GPL v2");
1011 MODULE_ALIAS("platform:fsl-esai-dai");
1012 

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