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Linux/sound/soc/fsl/fsl_esai.c

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  1 /*
  2  * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  5  *
  6  * This file is licensed under the terms of the GNU General Public License
  7  * version 2. This program is licensed "as is" without any warranty of any
  8  * kind, whether express or implied.
  9  */
 10 
 11 #include <linux/clk.h>
 12 #include <linux/dmaengine.h>
 13 #include <linux/module.h>
 14 #include <linux/of_irq.h>
 15 #include <linux/of_platform.h>
 16 #include <sound/dmaengine_pcm.h>
 17 #include <sound/pcm_params.h>
 18 
 19 #include "fsl_esai.h"
 20 #include "imx-pcm.h"
 21 
 22 #define FSL_ESAI_RATES          SNDRV_PCM_RATE_8000_192000
 23 #define FSL_ESAI_FORMATS        (SNDRV_PCM_FMTBIT_S8 | \
 24                                 SNDRV_PCM_FMTBIT_S16_LE | \
 25                                 SNDRV_PCM_FMTBIT_S20_3LE | \
 26                                 SNDRV_PCM_FMTBIT_S24_LE)
 27 
 28 /**
 29  * fsl_esai: ESAI private data
 30  *
 31  * @dma_params_rx: DMA parameters for receive channel
 32  * @dma_params_tx: DMA parameters for transmit channel
 33  * @pdev: platform device pointer
 34  * @regmap: regmap handler
 35  * @coreclk: clock source to access register
 36  * @extalclk: esai clock source to derive HCK, SCK and FS
 37  * @fsysclk: system clock source to derive HCK, SCK and FS
 38  * @fifo_depth: depth of tx/rx FIFO
 39  * @slot_width: width of each DAI slot
 40  * @slots: number of slots
 41  * @hck_rate: clock rate of desired HCKx clock
 42  * @sck_rate: clock rate of desired SCKx clock
 43  * @hck_dir: the direction of HCKx pads
 44  * @sck_div: if using PSR/PM dividers for SCKx clock
 45  * @slave_mode: if fully using DAI slave mode
 46  * @synchronous: if using tx/rx synchronous mode
 47  * @name: driver name
 48  */
 49 struct fsl_esai {
 50         struct snd_dmaengine_dai_dma_data dma_params_rx;
 51         struct snd_dmaengine_dai_dma_data dma_params_tx;
 52         struct platform_device *pdev;
 53         struct regmap *regmap;
 54         struct clk *coreclk;
 55         struct clk *extalclk;
 56         struct clk *fsysclk;
 57         u32 fifo_depth;
 58         u32 slot_width;
 59         u32 slots;
 60         u32 hck_rate[2];
 61         u32 sck_rate[2];
 62         bool hck_dir[2];
 63         bool sck_div[2];
 64         bool slave_mode;
 65         bool synchronous;
 66         char name[32];
 67 };
 68 
 69 static irqreturn_t esai_isr(int irq, void *devid)
 70 {
 71         struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
 72         struct platform_device *pdev = esai_priv->pdev;
 73         u32 esr;
 74 
 75         regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
 76 
 77         if (esr & ESAI_ESR_TINIT_MASK)
 78                 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
 79 
 80         if (esr & ESAI_ESR_RFF_MASK)
 81                 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
 82 
 83         if (esr & ESAI_ESR_TFE_MASK)
 84                 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
 85 
 86         if (esr & ESAI_ESR_TLS_MASK)
 87                 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
 88 
 89         if (esr & ESAI_ESR_TDE_MASK)
 90                 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
 91 
 92         if (esr & ESAI_ESR_TED_MASK)
 93                 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
 94 
 95         if (esr & ESAI_ESR_TD_MASK)
 96                 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
 97 
 98         if (esr & ESAI_ESR_RLS_MASK)
 99                 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
100 
101         if (esr & ESAI_ESR_RDE_MASK)
102                 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
103 
104         if (esr & ESAI_ESR_RED_MASK)
105                 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
106 
107         if (esr & ESAI_ESR_RD_MASK)
108                 dev_dbg(&pdev->dev, "isr: Receiving data\n");
109 
110         return IRQ_HANDLED;
111 }
112 
113 /**
114  * This function is used to calculate the divisors of psr, pm, fp and it is
115  * supposed to be called in set_dai_sysclk() and set_bclk().
116  *
117  * @ratio: desired overall ratio for the paticipating dividers
118  * @usefp: for HCK setting, there is no need to set fp divider
119  * @fp: bypass other dividers by setting fp directly if fp != 0
120  * @tx: current setting is for playback or capture
121  */
122 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
123                                 bool usefp, u32 fp)
124 {
125         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
126         u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
127 
128         maxfp = usefp ? 16 : 1;
129 
130         if (usefp && fp)
131                 goto out_fp;
132 
133         if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
134                 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
135                                 2 * 8 * 256 * maxfp);
136                 return -EINVAL;
137         } else if (ratio % 2) {
138                 dev_err(dai->dev, "the raio must be even if using upper divider\n");
139                 return -EINVAL;
140         }
141 
142         ratio /= 2;
143 
144         psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
145 
146         /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
147         if (ratio <= 256) {
148                 pm = ratio;
149                 fp = 1;
150                 goto out;
151         }
152 
153         /* Set the max fluctuation -- 0.1% of the max devisor */
154         savesub = (psr ? 1 : 8)  * 256 * maxfp / 1000;
155 
156         /* Find the best value for PM */
157         for (i = 1; i <= 256; i++) {
158                 for (j = 1; j <= maxfp; j++) {
159                         /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
160                         prod = (psr ? 1 : 8) * i * j;
161 
162                         if (prod == ratio)
163                                 sub = 0;
164                         else if (prod / ratio == 1)
165                                 sub = prod - ratio;
166                         else if (ratio / prod == 1)
167                                 sub = ratio - prod;
168                         else
169                                 continue;
170 
171                         /* Calculate the fraction */
172                         sub = sub * 1000 / ratio;
173                         if (sub < savesub) {
174                                 savesub = sub;
175                                 pm = i;
176                                 fp = j;
177                         }
178 
179                         /* We are lucky */
180                         if (savesub == 0)
181                                 goto out;
182                 }
183         }
184 
185         if (pm == 999) {
186                 dev_err(dai->dev, "failed to calculate proper divisors\n");
187                 return -EINVAL;
188         }
189 
190 out:
191         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
192                            ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
193                            psr | ESAI_xCCR_xPM(pm));
194 
195 out_fp:
196         /* Bypass fp if not being required */
197         if (maxfp <= 1)
198                 return 0;
199 
200         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
201                            ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
202 
203         return 0;
204 }
205 
206 /**
207  * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
208  *
209  * @Parameters:
210  * clk_id: The clock source of HCKT/HCKR
211  *        (Input from outside; output from inside, FSYS or EXTAL)
212  * freq: The required clock rate of HCKT/HCKR
213  * dir: The clock direction of HCKT/HCKR
214  *
215  * Note: If the direction is input, we do not care about clk_id.
216  */
217 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
218                                    unsigned int freq, int dir)
219 {
220         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
221         struct clk *clksrc = esai_priv->extalclk;
222         bool tx = clk_id <= ESAI_HCKT_EXTAL;
223         bool in = dir == SND_SOC_CLOCK_IN;
224         u32 ratio, ecr = 0;
225         unsigned long clk_rate;
226         int ret;
227 
228         /* Bypass divider settings if the requirement doesn't change */
229         if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
230                 return 0;
231 
232         /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
233         esai_priv->sck_div[tx] = true;
234 
235         /* Set the direction of HCKT/HCKR pins */
236         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
237                            ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
238 
239         if (in)
240                 goto out;
241 
242         switch (clk_id) {
243         case ESAI_HCKT_FSYS:
244         case ESAI_HCKR_FSYS:
245                 clksrc = esai_priv->fsysclk;
246                 break;
247         case ESAI_HCKT_EXTAL:
248                 ecr |= ESAI_ECR_ETI;
249         case ESAI_HCKR_EXTAL:
250                 ecr |= ESAI_ECR_ERI;
251                 break;
252         default:
253                 return -EINVAL;
254         }
255 
256         if (IS_ERR(clksrc)) {
257                 dev_err(dai->dev, "no assigned %s clock\n",
258                                 clk_id % 2 ? "extal" : "fsys");
259                 return PTR_ERR(clksrc);
260         }
261         clk_rate = clk_get_rate(clksrc);
262 
263         ratio = clk_rate / freq;
264         if (ratio * freq > clk_rate)
265                 ret = ratio * freq - clk_rate;
266         else if (ratio * freq < clk_rate)
267                 ret = clk_rate - ratio * freq;
268         else
269                 ret = 0;
270 
271         /* Block if clock source can not be divided into the required rate */
272         if (ret != 0 && clk_rate / ret < 1000) {
273                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
274                                 tx ? 'T' : 'R');
275                 return -EINVAL;
276         }
277 
278         /* Only EXTAL source can be output directly without using PSR and PM */
279         if (ratio == 1 && clksrc == esai_priv->extalclk) {
280                 /* Bypass all the dividers if not being needed */
281                 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
282                 goto out;
283         } else if (ratio < 2) {
284                 /* The ratio should be no less than 2 if using other sources */
285                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
286                                 tx ? 'T' : 'R');
287                 return -EINVAL;
288         }
289 
290         ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
291         if (ret)
292                 return ret;
293 
294         esai_priv->sck_div[tx] = false;
295 
296 out:
297         esai_priv->hck_dir[tx] = dir;
298         esai_priv->hck_rate[tx] = freq;
299 
300         regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
301                            tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
302                            ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
303 
304         return 0;
305 }
306 
307 /**
308  * This function configures the related dividers according to the bclk rate
309  */
310 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
311 {
312         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
313         u32 hck_rate = esai_priv->hck_rate[tx];
314         u32 sub, ratio = hck_rate / freq;
315         int ret;
316 
317         /* Don't apply for fully slave mode or unchanged bclk */
318         if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
319                 return 0;
320 
321         if (ratio * freq > hck_rate)
322                 sub = ratio * freq - hck_rate;
323         else if (ratio * freq < hck_rate)
324                 sub = hck_rate - ratio * freq;
325         else
326                 sub = 0;
327 
328         /* Block if clock source can not be divided into the required rate */
329         if (sub != 0 && hck_rate / sub < 1000) {
330                 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
331                                 tx ? 'T' : 'R');
332                 return -EINVAL;
333         }
334 
335         /* The ratio should be contented by FP alone if bypassing PM and PSR */
336         if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
337                 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
338                 return -EINVAL;
339         }
340 
341         ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
342                         esai_priv->sck_div[tx] ? 0 : ratio);
343         if (ret)
344                 return ret;
345 
346         /* Save current bclk rate */
347         esai_priv->sck_rate[tx] = freq;
348 
349         return 0;
350 }
351 
352 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
353                                      u32 rx_mask, int slots, int slot_width)
354 {
355         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
356 
357         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
358                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
359 
360         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
361                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
362         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
363                            ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
364 
365         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
366                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
367 
368         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
369                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
370         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
371                            ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
372 
373         esai_priv->slot_width = slot_width;
374         esai_priv->slots = slots;
375 
376         return 0;
377 }
378 
379 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
380 {
381         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
382         u32 xcr = 0, xccr = 0, mask;
383 
384         /* DAI mode */
385         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
386         case SND_SOC_DAIFMT_I2S:
387                 /* Data on rising edge of bclk, frame low, 1clk before data */
388                 xcr |= ESAI_xCR_xFSR;
389                 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
390                 break;
391         case SND_SOC_DAIFMT_LEFT_J:
392                 /* Data on rising edge of bclk, frame high */
393                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
394                 break;
395         case SND_SOC_DAIFMT_RIGHT_J:
396                 /* Data on rising edge of bclk, frame high, right aligned */
397                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
398                 break;
399         case SND_SOC_DAIFMT_DSP_A:
400                 /* Data on rising edge of bclk, frame high, 1clk before data */
401                 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
402                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
403                 break;
404         case SND_SOC_DAIFMT_DSP_B:
405                 /* Data on rising edge of bclk, frame high */
406                 xcr |= ESAI_xCR_xFSL;
407                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
408                 break;
409         default:
410                 return -EINVAL;
411         }
412 
413         /* DAI clock inversion */
414         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
415         case SND_SOC_DAIFMT_NB_NF:
416                 /* Nothing to do for both normal cases */
417                 break;
418         case SND_SOC_DAIFMT_IB_NF:
419                 /* Invert bit clock */
420                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
421                 break;
422         case SND_SOC_DAIFMT_NB_IF:
423                 /* Invert frame clock */
424                 xccr ^= ESAI_xCCR_xFSP;
425                 break;
426         case SND_SOC_DAIFMT_IB_IF:
427                 /* Invert both clocks */
428                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
429                 break;
430         default:
431                 return -EINVAL;
432         }
433 
434         esai_priv->slave_mode = false;
435 
436         /* DAI clock master masks */
437         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
438         case SND_SOC_DAIFMT_CBM_CFM:
439                 esai_priv->slave_mode = true;
440                 break;
441         case SND_SOC_DAIFMT_CBS_CFM:
442                 xccr |= ESAI_xCCR_xCKD;
443                 break;
444         case SND_SOC_DAIFMT_CBM_CFS:
445                 xccr |= ESAI_xCCR_xFSD;
446                 break;
447         case SND_SOC_DAIFMT_CBS_CFS:
448                 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
449                 break;
450         default:
451                 return -EINVAL;
452         }
453 
454         mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
455         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
456         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
457 
458         mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
459                 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
460         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
461         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
462 
463         return 0;
464 }
465 
466 static int fsl_esai_startup(struct snd_pcm_substream *substream,
467                             struct snd_soc_dai *dai)
468 {
469         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
470         int ret;
471 
472         /*
473          * Some platforms might use the same bit to gate all three or two of
474          * clocks, so keep all clocks open/close at the same time for safety
475          */
476         ret = clk_prepare_enable(esai_priv->coreclk);
477         if (ret)
478                 return ret;
479         if (!IS_ERR(esai_priv->extalclk)) {
480                 ret = clk_prepare_enable(esai_priv->extalclk);
481                 if (ret)
482                         goto err_extalck;
483         }
484         if (!IS_ERR(esai_priv->fsysclk)) {
485                 ret = clk_prepare_enable(esai_priv->fsysclk);
486                 if (ret)
487                         goto err_fsysclk;
488         }
489 
490         if (!dai->active) {
491                 /* Set synchronous mode */
492                 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
493                                    ESAI_SAICR_SYNC, esai_priv->synchronous ?
494                                    ESAI_SAICR_SYNC : 0);
495 
496                 /* Set a default slot number -- 2 */
497                 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
498                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
499                 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
500                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
501         }
502 
503         return 0;
504 
505 err_fsysclk:
506         if (!IS_ERR(esai_priv->extalclk))
507                 clk_disable_unprepare(esai_priv->extalclk);
508 err_extalck:
509         clk_disable_unprepare(esai_priv->coreclk);
510 
511         return ret;
512 }
513 
514 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
515                               struct snd_pcm_hw_params *params,
516                               struct snd_soc_dai *dai)
517 {
518         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
519         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
520         u32 width = snd_pcm_format_width(params_format(params));
521         u32 channels = params_channels(params);
522         u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
523         u32 slot_width = width;
524         u32 bclk, mask, val;
525         int ret;
526 
527         /* Override slot_width if being specifially set */
528         if (esai_priv->slot_width)
529                 slot_width = esai_priv->slot_width;
530 
531         bclk = params_rate(params) * slot_width * esai_priv->slots;
532 
533         ret = fsl_esai_set_bclk(dai, tx, bclk);
534         if (ret)
535                 return ret;
536 
537         /* Use Normal mode to support monaural audio */
538         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
539                            ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
540                            ESAI_xCR_xMOD_NETWORK : 0);
541 
542         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
543                            ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
544 
545         mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
546               (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
547         val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
548              (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
549 
550         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
551 
552         mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
553         val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
554 
555         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
556 
557         /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
558         regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
559                            ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
560         regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
561                            ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
562         return 0;
563 }
564 
565 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
566                               struct snd_soc_dai *dai)
567 {
568         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
569 
570         if (!IS_ERR(esai_priv->fsysclk))
571                 clk_disable_unprepare(esai_priv->fsysclk);
572         if (!IS_ERR(esai_priv->extalclk))
573                 clk_disable_unprepare(esai_priv->extalclk);
574         clk_disable_unprepare(esai_priv->coreclk);
575 }
576 
577 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
578                             struct snd_soc_dai *dai)
579 {
580         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
581         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
582         u8 i, channels = substream->runtime->channels;
583         u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
584 
585         switch (cmd) {
586         case SNDRV_PCM_TRIGGER_START:
587         case SNDRV_PCM_TRIGGER_RESUME:
588         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
589                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
590                                    ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
591 
592                 /* Write initial words reqiured by ESAI as normal procedure */
593                 for (i = 0; tx && i < channels; i++)
594                         regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
595 
596                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
597                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
598                                    tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
599                 break;
600         case SNDRV_PCM_TRIGGER_SUSPEND:
601         case SNDRV_PCM_TRIGGER_STOP:
602         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
603                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
604                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
605 
606                 /* Disable and reset FIFO */
607                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
608                                    ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
609                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
610                                    ESAI_xFCR_xFR, 0);
611                 break;
612         default:
613                 return -EINVAL;
614         }
615 
616         return 0;
617 }
618 
619 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
620         .startup = fsl_esai_startup,
621         .shutdown = fsl_esai_shutdown,
622         .trigger = fsl_esai_trigger,
623         .hw_params = fsl_esai_hw_params,
624         .set_sysclk = fsl_esai_set_dai_sysclk,
625         .set_fmt = fsl_esai_set_dai_fmt,
626         .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
627 };
628 
629 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
630 {
631         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
632 
633         snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
634                                   &esai_priv->dma_params_rx);
635 
636         return 0;
637 }
638 
639 static struct snd_soc_dai_driver fsl_esai_dai = {
640         .probe = fsl_esai_dai_probe,
641         .playback = {
642                 .stream_name = "CPU-Playback",
643                 .channels_min = 1,
644                 .channels_max = 12,
645                 .rates = FSL_ESAI_RATES,
646                 .formats = FSL_ESAI_FORMATS,
647         },
648         .capture = {
649                 .stream_name = "CPU-Capture",
650                 .channels_min = 1,
651                 .channels_max = 8,
652                 .rates = FSL_ESAI_RATES,
653                 .formats = FSL_ESAI_FORMATS,
654         },
655         .ops = &fsl_esai_dai_ops,
656 };
657 
658 static const struct snd_soc_component_driver fsl_esai_component = {
659         .name           = "fsl-esai",
660 };
661 
662 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
663 {
664         switch (reg) {
665         case REG_ESAI_ERDR:
666         case REG_ESAI_ECR:
667         case REG_ESAI_ESR:
668         case REG_ESAI_TFCR:
669         case REG_ESAI_TFSR:
670         case REG_ESAI_RFCR:
671         case REG_ESAI_RFSR:
672         case REG_ESAI_RX0:
673         case REG_ESAI_RX1:
674         case REG_ESAI_RX2:
675         case REG_ESAI_RX3:
676         case REG_ESAI_SAISR:
677         case REG_ESAI_SAICR:
678         case REG_ESAI_TCR:
679         case REG_ESAI_TCCR:
680         case REG_ESAI_RCR:
681         case REG_ESAI_RCCR:
682         case REG_ESAI_TSMA:
683         case REG_ESAI_TSMB:
684         case REG_ESAI_RSMA:
685         case REG_ESAI_RSMB:
686         case REG_ESAI_PRRC:
687         case REG_ESAI_PCRC:
688                 return true;
689         default:
690                 return false;
691         }
692 }
693 
694 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
695 {
696         switch (reg) {
697         case REG_ESAI_ETDR:
698         case REG_ESAI_ECR:
699         case REG_ESAI_TFCR:
700         case REG_ESAI_RFCR:
701         case REG_ESAI_TX0:
702         case REG_ESAI_TX1:
703         case REG_ESAI_TX2:
704         case REG_ESAI_TX3:
705         case REG_ESAI_TX4:
706         case REG_ESAI_TX5:
707         case REG_ESAI_TSR:
708         case REG_ESAI_SAICR:
709         case REG_ESAI_TCR:
710         case REG_ESAI_TCCR:
711         case REG_ESAI_RCR:
712         case REG_ESAI_RCCR:
713         case REG_ESAI_TSMA:
714         case REG_ESAI_TSMB:
715         case REG_ESAI_RSMA:
716         case REG_ESAI_RSMB:
717         case REG_ESAI_PRRC:
718         case REG_ESAI_PCRC:
719                 return true;
720         default:
721                 return false;
722         }
723 }
724 
725 static const struct regmap_config fsl_esai_regmap_config = {
726         .reg_bits = 32,
727         .reg_stride = 4,
728         .val_bits = 32,
729 
730         .max_register = REG_ESAI_PCRC,
731         .readable_reg = fsl_esai_readable_reg,
732         .writeable_reg = fsl_esai_writeable_reg,
733 };
734 
735 static int fsl_esai_probe(struct platform_device *pdev)
736 {
737         struct device_node *np = pdev->dev.of_node;
738         struct fsl_esai *esai_priv;
739         struct resource *res;
740         const uint32_t *iprop;
741         void __iomem *regs;
742         int irq, ret;
743 
744         esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
745         if (!esai_priv)
746                 return -ENOMEM;
747 
748         esai_priv->pdev = pdev;
749         strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
750 
751         /* Get the addresses and IRQ */
752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753         regs = devm_ioremap_resource(&pdev->dev, res);
754         if (IS_ERR(regs))
755                 return PTR_ERR(regs);
756 
757         esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
758                         "core", regs, &fsl_esai_regmap_config);
759         if (IS_ERR(esai_priv->regmap)) {
760                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
761                                 PTR_ERR(esai_priv->regmap));
762                 return PTR_ERR(esai_priv->regmap);
763         }
764 
765         esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
766         if (IS_ERR(esai_priv->coreclk)) {
767                 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
768                                 PTR_ERR(esai_priv->coreclk));
769                 return PTR_ERR(esai_priv->coreclk);
770         }
771 
772         esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
773         if (IS_ERR(esai_priv->extalclk))
774                 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
775                                 PTR_ERR(esai_priv->extalclk));
776 
777         esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
778         if (IS_ERR(esai_priv->fsysclk))
779                 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
780                                 PTR_ERR(esai_priv->fsysclk));
781 
782         irq = platform_get_irq(pdev, 0);
783         if (irq < 0) {
784                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
785                 return irq;
786         }
787 
788         ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
789                                esai_priv->name, esai_priv);
790         if (ret) {
791                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
792                 return ret;
793         }
794 
795         /* Set a default slot number */
796         esai_priv->slots = 2;
797 
798         /* Set a default master/slave state */
799         esai_priv->slave_mode = true;
800 
801         /* Determine the FIFO depth */
802         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
803         if (iprop)
804                 esai_priv->fifo_depth = be32_to_cpup(iprop);
805         else
806                 esai_priv->fifo_depth = 64;
807 
808         esai_priv->dma_params_tx.maxburst = 16;
809         esai_priv->dma_params_rx.maxburst = 16;
810         esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
811         esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
812 
813         esai_priv->synchronous =
814                 of_property_read_bool(np, "fsl,esai-synchronous");
815 
816         /* Implement full symmetry for synchronous mode */
817         if (esai_priv->synchronous) {
818                 fsl_esai_dai.symmetric_rates = 1;
819                 fsl_esai_dai.symmetric_channels = 1;
820                 fsl_esai_dai.symmetric_samplebits = 1;
821         }
822 
823         dev_set_drvdata(&pdev->dev, esai_priv);
824 
825         /* Reset ESAI unit */
826         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
827         if (ret) {
828                 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
829                 return ret;
830         }
831 
832         /*
833          * We need to enable ESAI so as to access some of its registers.
834          * Otherwise, we would fail to dump regmap from user space.
835          */
836         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
837         if (ret) {
838                 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
839                 return ret;
840         }
841 
842         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
843                                               &fsl_esai_dai, 1);
844         if (ret) {
845                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
846                 return ret;
847         }
848 
849         ret = imx_pcm_dma_init(pdev);
850         if (ret)
851                 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
852 
853         return ret;
854 }
855 
856 static const struct of_device_id fsl_esai_dt_ids[] = {
857         { .compatible = "fsl,imx35-esai", },
858         { .compatible = "fsl,vf610-esai", },
859         {}
860 };
861 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
862 
863 static struct platform_driver fsl_esai_driver = {
864         .probe = fsl_esai_probe,
865         .driver = {
866                 .name = "fsl-esai-dai",
867                 .of_match_table = fsl_esai_dt_ids,
868         },
869 };
870 
871 module_platform_driver(fsl_esai_driver);
872 
873 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
874 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
875 MODULE_LICENSE("GPL v2");
876 MODULE_ALIAS("platform:fsl-esai-dai");
877 

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