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Linux/sound/soc/fsl/fsl_sai.c

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  1 // SPDX-License-Identifier: GPL-2.0+
  2 //
  3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
  4 //
  5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
  6 
  7 #include <linux/clk.h>
  8 #include <linux/delay.h>
  9 #include <linux/dmaengine.h>
 10 #include <linux/module.h>
 11 #include <linux/of_address.h>
 12 #include <linux/regmap.h>
 13 #include <linux/slab.h>
 14 #include <linux/time.h>
 15 #include <sound/core.h>
 16 #include <sound/dmaengine_pcm.h>
 17 #include <sound/pcm_params.h>
 18 #include <linux/mfd/syscon.h>
 19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 20 
 21 #include "fsl_sai.h"
 22 #include "imx-pcm.h"
 23 
 24 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
 25                        FSL_SAI_CSR_FEIE)
 26 
 27 static const unsigned int fsl_sai_rates[] = {
 28         8000, 11025, 12000, 16000, 22050,
 29         24000, 32000, 44100, 48000, 64000,
 30         88200, 96000, 176400, 192000
 31 };
 32 
 33 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
 34         .count = ARRAY_SIZE(fsl_sai_rates),
 35         .list = fsl_sai_rates,
 36 };
 37 
 38 static irqreturn_t fsl_sai_isr(int irq, void *devid)
 39 {
 40         struct fsl_sai *sai = (struct fsl_sai *)devid;
 41         struct device *dev = &sai->pdev->dev;
 42         u32 flags, xcsr, mask;
 43         bool irq_none = true;
 44 
 45         /*
 46          * Both IRQ status bits and IRQ mask bits are in the xCSR but
 47          * different shifts. And we here create a mask only for those
 48          * IRQs that we activated.
 49          */
 50         mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
 51 
 52         /* Tx IRQ */
 53         regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
 54         flags = xcsr & mask;
 55 
 56         if (flags)
 57                 irq_none = false;
 58         else
 59                 goto irq_rx;
 60 
 61         if (flags & FSL_SAI_CSR_WSF)
 62                 dev_dbg(dev, "isr: Start of Tx word detected\n");
 63 
 64         if (flags & FSL_SAI_CSR_SEF)
 65                 dev_warn(dev, "isr: Tx Frame sync error detected\n");
 66 
 67         if (flags & FSL_SAI_CSR_FEF) {
 68                 dev_warn(dev, "isr: Transmit underrun detected\n");
 69                 /* FIFO reset for safety */
 70                 xcsr |= FSL_SAI_CSR_FR;
 71         }
 72 
 73         if (flags & FSL_SAI_CSR_FWF)
 74                 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
 75 
 76         if (flags & FSL_SAI_CSR_FRF)
 77                 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
 78 
 79         flags &= FSL_SAI_CSR_xF_W_MASK;
 80         xcsr &= ~FSL_SAI_CSR_xF_MASK;
 81 
 82         if (flags)
 83                 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
 84 
 85 irq_rx:
 86         /* Rx IRQ */
 87         regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
 88         flags = xcsr & mask;
 89 
 90         if (flags)
 91                 irq_none = false;
 92         else
 93                 goto out;
 94 
 95         if (flags & FSL_SAI_CSR_WSF)
 96                 dev_dbg(dev, "isr: Start of Rx word detected\n");
 97 
 98         if (flags & FSL_SAI_CSR_SEF)
 99                 dev_warn(dev, "isr: Rx Frame sync error detected\n");
100 
101         if (flags & FSL_SAI_CSR_FEF) {
102                 dev_warn(dev, "isr: Receive overflow detected\n");
103                 /* FIFO reset for safety */
104                 xcsr |= FSL_SAI_CSR_FR;
105         }
106 
107         if (flags & FSL_SAI_CSR_FWF)
108                 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
109 
110         if (flags & FSL_SAI_CSR_FRF)
111                 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
112 
113         flags &= FSL_SAI_CSR_xF_W_MASK;
114         xcsr &= ~FSL_SAI_CSR_xF_MASK;
115 
116         if (flags)
117                 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
118 
119 out:
120         if (irq_none)
121                 return IRQ_NONE;
122         else
123                 return IRQ_HANDLED;
124 }
125 
126 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
127                                 u32 rx_mask, int slots, int slot_width)
128 {
129         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
130 
131         sai->slots = slots;
132         sai->slot_width = slot_width;
133 
134         return 0;
135 }
136 
137 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
138                 int clk_id, unsigned int freq, int fsl_dir)
139 {
140         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
141         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
142         u32 val_cr2 = 0;
143 
144         switch (clk_id) {
145         case FSL_SAI_CLK_BUS:
146                 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
147                 break;
148         case FSL_SAI_CLK_MAST1:
149                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
150                 break;
151         case FSL_SAI_CLK_MAST2:
152                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
153                 break;
154         case FSL_SAI_CLK_MAST3:
155                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
156                 break;
157         default:
158                 return -EINVAL;
159         }
160 
161         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
162                            FSL_SAI_CR2_MSEL_MASK, val_cr2);
163 
164         return 0;
165 }
166 
167 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
168                 int clk_id, unsigned int freq, int dir)
169 {
170         int ret;
171 
172         if (dir == SND_SOC_CLOCK_IN)
173                 return 0;
174 
175         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
176                                         FSL_FMT_TRANSMITTER);
177         if (ret) {
178                 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
179                 return ret;
180         }
181 
182         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
183                                         FSL_FMT_RECEIVER);
184         if (ret)
185                 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
186 
187         return ret;
188 }
189 
190 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
191                                 unsigned int fmt, int fsl_dir)
192 {
193         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
194         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
195         u32 val_cr2 = 0, val_cr4 = 0;
196 
197         if (!sai->is_lsb_first)
198                 val_cr4 |= FSL_SAI_CR4_MF;
199 
200         /* DAI mode */
201         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
202         case SND_SOC_DAIFMT_I2S:
203                 /*
204                  * Frame low, 1clk before data, one word length for frame sync,
205                  * frame sync starts one serial clock cycle earlier,
206                  * that is, together with the last bit of the previous
207                  * data word.
208                  */
209                 val_cr2 |= FSL_SAI_CR2_BCP;
210                 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
211                 break;
212         case SND_SOC_DAIFMT_LEFT_J:
213                 /*
214                  * Frame high, one word length for frame sync,
215                  * frame sync asserts with the first bit of the frame.
216                  */
217                 val_cr2 |= FSL_SAI_CR2_BCP;
218                 break;
219         case SND_SOC_DAIFMT_DSP_A:
220                 /*
221                  * Frame high, 1clk before data, one bit for frame sync,
222                  * frame sync starts one serial clock cycle earlier,
223                  * that is, together with the last bit of the previous
224                  * data word.
225                  */
226                 val_cr2 |= FSL_SAI_CR2_BCP;
227                 val_cr4 |= FSL_SAI_CR4_FSE;
228                 sai->is_dsp_mode = true;
229                 break;
230         case SND_SOC_DAIFMT_DSP_B:
231                 /*
232                  * Frame high, one bit for frame sync,
233                  * frame sync asserts with the first bit of the frame.
234                  */
235                 val_cr2 |= FSL_SAI_CR2_BCP;
236                 sai->is_dsp_mode = true;
237                 break;
238         case SND_SOC_DAIFMT_RIGHT_J:
239                 /* To be done */
240         default:
241                 return -EINVAL;
242         }
243 
244         /* DAI clock inversion */
245         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
246         case SND_SOC_DAIFMT_IB_IF:
247                 /* Invert both clocks */
248                 val_cr2 ^= FSL_SAI_CR2_BCP;
249                 val_cr4 ^= FSL_SAI_CR4_FSP;
250                 break;
251         case SND_SOC_DAIFMT_IB_NF:
252                 /* Invert bit clock */
253                 val_cr2 ^= FSL_SAI_CR2_BCP;
254                 break;
255         case SND_SOC_DAIFMT_NB_IF:
256                 /* Invert frame clock */
257                 val_cr4 ^= FSL_SAI_CR4_FSP;
258                 break;
259         case SND_SOC_DAIFMT_NB_NF:
260                 /* Nothing to do for both normal cases */
261                 break;
262         default:
263                 return -EINVAL;
264         }
265 
266         /* DAI clock master masks */
267         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
268         case SND_SOC_DAIFMT_CBS_CFS:
269                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
270                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
271                 break;
272         case SND_SOC_DAIFMT_CBM_CFM:
273                 sai->is_slave_mode = true;
274                 break;
275         case SND_SOC_DAIFMT_CBS_CFM:
276                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
277                 break;
278         case SND_SOC_DAIFMT_CBM_CFS:
279                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
280                 sai->is_slave_mode = true;
281                 break;
282         default:
283                 return -EINVAL;
284         }
285 
286         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
287                            FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
288         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
289                            FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
290                            FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
291 
292         return 0;
293 }
294 
295 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
296 {
297         int ret;
298 
299         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
300         if (ret) {
301                 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
302                 return ret;
303         }
304 
305         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
306         if (ret)
307                 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
308 
309         return ret;
310 }
311 
312 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
313 {
314         struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
315         unsigned long clk_rate;
316         u32 savediv = 0, ratio, savesub = freq;
317         u32 id;
318         int ret = 0;
319 
320         /* Don't apply to slave mode */
321         if (sai->is_slave_mode)
322                 return 0;
323 
324         for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
325                 clk_rate = clk_get_rate(sai->mclk_clk[id]);
326                 if (!clk_rate)
327                         continue;
328 
329                 ratio = clk_rate / freq;
330 
331                 ret = clk_rate - ratio * freq;
332 
333                 /*
334                  * Drop the source that can not be
335                  * divided into the required rate.
336                  */
337                 if (ret != 0 && clk_rate / ret < 1000)
338                         continue;
339 
340                 dev_dbg(dai->dev,
341                         "ratio %d for freq %dHz based on clock %ldHz\n",
342                         ratio, freq, clk_rate);
343 
344                 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
345                         ratio /= 2;
346                 else
347                         continue;
348 
349                 if (ret < savesub) {
350                         savediv = ratio;
351                         sai->mclk_id[tx] = id;
352                         savesub = ret;
353                 }
354 
355                 if (ret == 0)
356                         break;
357         }
358 
359         if (savediv == 0) {
360                 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
361                                 tx ? 'T' : 'R', freq);
362                 return -EINVAL;
363         }
364 
365         /*
366          * 1) For Asynchronous mode, we must set RCR2 register for capture, and
367          *    set TCR2 register for playback.
368          * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
369          *    and capture.
370          * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
371          *    and capture.
372          * 4) For Tx and Rx are both Synchronous with another SAI, we just
373          *    ignore it.
374          */
375         if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
376             (!tx && !sai->synchronous[RX])) {
377                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
378                                    FSL_SAI_CR2_MSEL_MASK,
379                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
380                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
381                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
382         } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
383                    (tx && !sai->synchronous[TX])) {
384                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
385                                    FSL_SAI_CR2_MSEL_MASK,
386                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
387                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
388                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
389         }
390 
391         dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
392                         sai->mclk_id[tx], savediv, savesub);
393 
394         return 0;
395 }
396 
397 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
398                 struct snd_pcm_hw_params *params,
399                 struct snd_soc_dai *cpu_dai)
400 {
401         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
402         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
403         unsigned int channels = params_channels(params);
404         u32 word_width = params_width(params);
405         u32 val_cr4 = 0, val_cr5 = 0;
406         u32 slots = (channels == 1) ? 2 : channels;
407         u32 slot_width = word_width;
408         int ret;
409 
410         if (sai->slots)
411                 slots = sai->slots;
412 
413         if (sai->slot_width)
414                 slot_width = sai->slot_width;
415 
416         if (!sai->is_slave_mode) {
417                 ret = fsl_sai_set_bclk(cpu_dai, tx,
418                                 slots * slot_width * params_rate(params));
419                 if (ret)
420                         return ret;
421 
422                 /* Do not enable the clock if it is already enabled */
423                 if (!(sai->mclk_streams & BIT(substream->stream))) {
424                         ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
425                         if (ret)
426                                 return ret;
427 
428                         sai->mclk_streams |= BIT(substream->stream);
429                 }
430         }
431 
432         if (!sai->is_dsp_mode)
433                 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
434 
435         val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
436         val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
437 
438         if (sai->is_lsb_first)
439                 val_cr5 |= FSL_SAI_CR5_FBT(0);
440         else
441                 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
442 
443         val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
444 
445         /*
446          * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
447          * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
448          * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
449          * error.
450          */
451 
452         if (!sai->is_slave_mode) {
453                 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
454                         regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
455                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
456                                 val_cr4);
457                         regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
458                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
459                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
460                         regmap_write(sai->regmap, FSL_SAI_TMR,
461                                 ~0UL - ((1 << channels) - 1));
462                 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
463                         regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
464                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
465                                 val_cr4);
466                         regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
467                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
468                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
469                         regmap_write(sai->regmap, FSL_SAI_RMR,
470                                 ~0UL - ((1 << channels) - 1));
471                 }
472         }
473 
474         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
475                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
476                            val_cr4);
477         regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
478                            FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
479                            FSL_SAI_CR5_FBT_MASK, val_cr5);
480         regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
481 
482         return 0;
483 }
484 
485 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
486                 struct snd_soc_dai *cpu_dai)
487 {
488         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
489         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
490 
491         if (!sai->is_slave_mode &&
492                         sai->mclk_streams & BIT(substream->stream)) {
493                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
494                 sai->mclk_streams &= ~BIT(substream->stream);
495         }
496 
497         return 0;
498 }
499 
500 
501 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
502                 struct snd_soc_dai *cpu_dai)
503 {
504         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
505         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
506         u32 xcsr, count = 100;
507 
508         /*
509          * Asynchronous mode: Clear SYNC for both Tx and Rx.
510          * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
511          * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
512          */
513         regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
514                            sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
515         regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
516                            sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
517 
518         /*
519          * It is recommended that the transmitter is the last enabled
520          * and the first disabled.
521          */
522         switch (cmd) {
523         case SNDRV_PCM_TRIGGER_START:
524         case SNDRV_PCM_TRIGGER_RESUME:
525         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
526                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
527                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
528 
529                 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
530                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
531                 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
532                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
533 
534                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
535                                    FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
536                 break;
537         case SNDRV_PCM_TRIGGER_STOP:
538         case SNDRV_PCM_TRIGGER_SUSPEND:
539         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
540                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
541                                    FSL_SAI_CSR_FRDE, 0);
542                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
543                                    FSL_SAI_CSR_xIE_MASK, 0);
544 
545                 /* Check if the opposite FRDE is also disabled */
546                 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
547                 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
548                         /* Disable both directions and reset their FIFOs */
549                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
550                                            FSL_SAI_CSR_TERE, 0);
551                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
552                                            FSL_SAI_CSR_TERE, 0);
553 
554                         /* TERE will remain set till the end of current frame */
555                         do {
556                                 udelay(10);
557                                 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
558                         } while (--count && xcsr & FSL_SAI_CSR_TERE);
559 
560                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
561                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
562                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
563                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
564 
565                         /*
566                          * For sai master mode, after several open/close sai,
567                          * there will be no frame clock, and can't recover
568                          * anymore. Add software reset to fix this issue.
569                          * This is a hardware bug, and will be fix in the
570                          * next sai version.
571                          */
572                         if (!sai->is_slave_mode) {
573                                 /* Software Reset for both Tx and Rx */
574                                 regmap_write(sai->regmap,
575                                              FSL_SAI_TCSR, FSL_SAI_CSR_SR);
576                                 regmap_write(sai->regmap,
577                                              FSL_SAI_RCSR, FSL_SAI_CSR_SR);
578                                 /* Clear SR bit to finish the reset */
579                                 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
580                                 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
581                         }
582                 }
583                 break;
584         default:
585                 return -EINVAL;
586         }
587 
588         return 0;
589 }
590 
591 static int fsl_sai_startup(struct snd_pcm_substream *substream,
592                 struct snd_soc_dai *cpu_dai)
593 {
594         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
595         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
596         struct device *dev = &sai->pdev->dev;
597         int ret;
598 
599         ret = clk_prepare_enable(sai->bus_clk);
600         if (ret) {
601                 dev_err(dev, "failed to enable bus clock: %d\n", ret);
602                 return ret;
603         }
604 
605         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
606                            FSL_SAI_CR3_TRCE);
607 
608         ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
609                         SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
610 
611         return ret;
612 }
613 
614 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
615                 struct snd_soc_dai *cpu_dai)
616 {
617         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
618         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
619 
620         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
621 
622         clk_disable_unprepare(sai->bus_clk);
623 }
624 
625 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
626         .set_sysclk     = fsl_sai_set_dai_sysclk,
627         .set_fmt        = fsl_sai_set_dai_fmt,
628         .set_tdm_slot   = fsl_sai_set_dai_tdm_slot,
629         .hw_params      = fsl_sai_hw_params,
630         .hw_free        = fsl_sai_hw_free,
631         .trigger        = fsl_sai_trigger,
632         .startup        = fsl_sai_startup,
633         .shutdown       = fsl_sai_shutdown,
634 };
635 
636 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
637 {
638         struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
639 
640         /* Software Reset for both Tx and Rx */
641         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
642         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
643         /* Clear SR bit to finish the reset */
644         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
645         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
646 
647         regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
648                            FSL_SAI_MAXBURST_TX * 2);
649         regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
650                            FSL_SAI_MAXBURST_RX - 1);
651 
652         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
653                                 &sai->dma_params_rx);
654 
655         snd_soc_dai_set_drvdata(cpu_dai, sai);
656 
657         return 0;
658 }
659 
660 static struct snd_soc_dai_driver fsl_sai_dai = {
661         .probe = fsl_sai_dai_probe,
662         .playback = {
663                 .stream_name = "CPU-Playback",
664                 .channels_min = 1,
665                 .channels_max = 32,
666                 .rate_min = 8000,
667                 .rate_max = 192000,
668                 .rates = SNDRV_PCM_RATE_KNOT,
669                 .formats = FSL_SAI_FORMATS,
670         },
671         .capture = {
672                 .stream_name = "CPU-Capture",
673                 .channels_min = 1,
674                 .channels_max = 32,
675                 .rate_min = 8000,
676                 .rate_max = 192000,
677                 .rates = SNDRV_PCM_RATE_KNOT,
678                 .formats = FSL_SAI_FORMATS,
679         },
680         .ops = &fsl_sai_pcm_dai_ops,
681 };
682 
683 static const struct snd_soc_component_driver fsl_component = {
684         .name           = "fsl-sai",
685 };
686 
687 static struct reg_default fsl_sai_reg_defaults[] = {
688         {FSL_SAI_TCR1, 0},
689         {FSL_SAI_TCR2, 0},
690         {FSL_SAI_TCR3, 0},
691         {FSL_SAI_TCR4, 0},
692         {FSL_SAI_TCR5, 0},
693         {FSL_SAI_TDR,  0},
694         {FSL_SAI_TMR,  0},
695         {FSL_SAI_RCR1, 0},
696         {FSL_SAI_RCR2, 0},
697         {FSL_SAI_RCR3, 0},
698         {FSL_SAI_RCR4, 0},
699         {FSL_SAI_RCR5, 0},
700         {FSL_SAI_RMR,  0},
701 };
702 
703 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
704 {
705         switch (reg) {
706         case FSL_SAI_TCSR:
707         case FSL_SAI_TCR1:
708         case FSL_SAI_TCR2:
709         case FSL_SAI_TCR3:
710         case FSL_SAI_TCR4:
711         case FSL_SAI_TCR5:
712         case FSL_SAI_TFR:
713         case FSL_SAI_TMR:
714         case FSL_SAI_RCSR:
715         case FSL_SAI_RCR1:
716         case FSL_SAI_RCR2:
717         case FSL_SAI_RCR3:
718         case FSL_SAI_RCR4:
719         case FSL_SAI_RCR5:
720         case FSL_SAI_RDR:
721         case FSL_SAI_RFR:
722         case FSL_SAI_RMR:
723                 return true;
724         default:
725                 return false;
726         }
727 }
728 
729 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
730 {
731         switch (reg) {
732         case FSL_SAI_TCSR:
733         case FSL_SAI_RCSR:
734         case FSL_SAI_TFR:
735         case FSL_SAI_RFR:
736         case FSL_SAI_RDR:
737                 return true;
738         default:
739                 return false;
740         }
741 }
742 
743 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
744 {
745         switch (reg) {
746         case FSL_SAI_TCSR:
747         case FSL_SAI_TCR1:
748         case FSL_SAI_TCR2:
749         case FSL_SAI_TCR3:
750         case FSL_SAI_TCR4:
751         case FSL_SAI_TCR5:
752         case FSL_SAI_TDR:
753         case FSL_SAI_TMR:
754         case FSL_SAI_RCSR:
755         case FSL_SAI_RCR1:
756         case FSL_SAI_RCR2:
757         case FSL_SAI_RCR3:
758         case FSL_SAI_RCR4:
759         case FSL_SAI_RCR5:
760         case FSL_SAI_RMR:
761                 return true;
762         default:
763                 return false;
764         }
765 }
766 
767 static const struct regmap_config fsl_sai_regmap_config = {
768         .reg_bits = 32,
769         .reg_stride = 4,
770         .val_bits = 32,
771 
772         .max_register = FSL_SAI_RMR,
773         .reg_defaults = fsl_sai_reg_defaults,
774         .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
775         .readable_reg = fsl_sai_readable_reg,
776         .volatile_reg = fsl_sai_volatile_reg,
777         .writeable_reg = fsl_sai_writeable_reg,
778         .cache_type = REGCACHE_FLAT,
779 };
780 
781 static int fsl_sai_probe(struct platform_device *pdev)
782 {
783         struct device_node *np = pdev->dev.of_node;
784         struct fsl_sai *sai;
785         struct regmap *gpr;
786         struct resource *res;
787         void __iomem *base;
788         char tmp[8];
789         int irq, ret, i;
790         int index;
791 
792         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
793         if (!sai)
794                 return -ENOMEM;
795 
796         sai->pdev = pdev;
797 
798         if (of_device_is_compatible(np, "fsl,imx6sx-sai") ||
799             of_device_is_compatible(np, "fsl,imx6ul-sai"))
800                 sai->sai_on_imx = true;
801 
802         sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
803 
804         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
805         base = devm_ioremap_resource(&pdev->dev, res);
806         if (IS_ERR(base))
807                 return PTR_ERR(base);
808 
809         sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
810                         "bus", base, &fsl_sai_regmap_config);
811 
812         /* Compatible with old DTB cases */
813         if (IS_ERR(sai->regmap))
814                 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
815                                 "sai", base, &fsl_sai_regmap_config);
816         if (IS_ERR(sai->regmap)) {
817                 dev_err(&pdev->dev, "regmap init failed\n");
818                 return PTR_ERR(sai->regmap);
819         }
820 
821         /* No error out for old DTB cases but only mark the clock NULL */
822         sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
823         if (IS_ERR(sai->bus_clk)) {
824                 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
825                                 PTR_ERR(sai->bus_clk));
826                 sai->bus_clk = NULL;
827         }
828 
829         sai->mclk_clk[0] = sai->bus_clk;
830         for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
831                 sprintf(tmp, "mclk%d", i);
832                 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
833                 if (IS_ERR(sai->mclk_clk[i])) {
834                         dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
835                                         i + 1, PTR_ERR(sai->mclk_clk[i]));
836                         sai->mclk_clk[i] = NULL;
837                 }
838         }
839 
840         irq = platform_get_irq(pdev, 0);
841         if (irq < 0) {
842                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
843                 return irq;
844         }
845 
846         ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
847         if (ret) {
848                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
849                 return ret;
850         }
851 
852         /* Sync Tx with Rx as default by following old DT binding */
853         sai->synchronous[RX] = true;
854         sai->synchronous[TX] = false;
855         fsl_sai_dai.symmetric_rates = 1;
856         fsl_sai_dai.symmetric_channels = 1;
857         fsl_sai_dai.symmetric_samplebits = 1;
858 
859         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
860             of_find_property(np, "fsl,sai-asynchronous", NULL)) {
861                 /* error out if both synchronous and asynchronous are present */
862                 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
863                 return -EINVAL;
864         }
865 
866         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
867                 /* Sync Rx with Tx */
868                 sai->synchronous[RX] = false;
869                 sai->synchronous[TX] = true;
870         } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
871                 /* Discard all settings for asynchronous mode */
872                 sai->synchronous[RX] = false;
873                 sai->synchronous[TX] = false;
874                 fsl_sai_dai.symmetric_rates = 0;
875                 fsl_sai_dai.symmetric_channels = 0;
876                 fsl_sai_dai.symmetric_samplebits = 0;
877         }
878 
879         if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
880             of_device_is_compatible(np, "fsl,imx6ul-sai")) {
881                 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
882                 if (IS_ERR(gpr)) {
883                         dev_err(&pdev->dev, "cannot find iomuxc registers\n");
884                         return PTR_ERR(gpr);
885                 }
886 
887                 index = of_alias_get_id(np, "sai");
888                 if (index < 0)
889                         return index;
890 
891                 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
892                                    MCLK_DIR(index));
893         }
894 
895         sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
896         sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
897         sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
898         sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
899 
900         platform_set_drvdata(pdev, sai);
901 
902         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
903                         &fsl_sai_dai, 1);
904         if (ret)
905                 return ret;
906 
907         if (sai->sai_on_imx)
908                 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
909         else
910                 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
911 }
912 
913 static const struct of_device_id fsl_sai_ids[] = {
914         { .compatible = "fsl,vf610-sai", },
915         { .compatible = "fsl,imx6sx-sai", },
916         { .compatible = "fsl,imx6ul-sai", },
917         { /* sentinel */ }
918 };
919 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
920 
921 #ifdef CONFIG_PM_SLEEP
922 static int fsl_sai_suspend(struct device *dev)
923 {
924         struct fsl_sai *sai = dev_get_drvdata(dev);
925 
926         regcache_cache_only(sai->regmap, true);
927         regcache_mark_dirty(sai->regmap);
928 
929         return 0;
930 }
931 
932 static int fsl_sai_resume(struct device *dev)
933 {
934         struct fsl_sai *sai = dev_get_drvdata(dev);
935 
936         regcache_cache_only(sai->regmap, false);
937         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
938         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
939         usleep_range(1000, 2000);
940         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
941         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
942         return regcache_sync(sai->regmap);
943 }
944 #endif /* CONFIG_PM_SLEEP */
945 
946 static const struct dev_pm_ops fsl_sai_pm_ops = {
947         SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
948 };
949 
950 static struct platform_driver fsl_sai_driver = {
951         .probe = fsl_sai_probe,
952         .driver = {
953                 .name = "fsl-sai",
954                 .pm = &fsl_sai_pm_ops,
955                 .of_match_table = fsl_sai_ids,
956         },
957 };
958 module_platform_driver(fsl_sai_driver);
959 
960 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
961 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
962 MODULE_ALIAS("platform:fsl-sai");
963 MODULE_LICENSE("GPL");
964 

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