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Linux/sound/soc/fsl/fsl_sai.c

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  1 // SPDX-License-Identifier: GPL-2.0+
  2 //
  3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
  4 //
  5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
  6 
  7 #include <linux/clk.h>
  8 #include <linux/delay.h>
  9 #include <linux/dmaengine.h>
 10 #include <linux/module.h>
 11 #include <linux/of_address.h>
 12 #include <linux/pm_runtime.h>
 13 #include <linux/regmap.h>
 14 #include <linux/slab.h>
 15 #include <linux/time.h>
 16 #include <sound/core.h>
 17 #include <sound/dmaengine_pcm.h>
 18 #include <sound/pcm_params.h>
 19 #include <linux/mfd/syscon.h>
 20 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 21 
 22 #include "fsl_sai.h"
 23 #include "imx-pcm.h"
 24 
 25 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
 26                        FSL_SAI_CSR_FEIE)
 27 
 28 static const unsigned int fsl_sai_rates[] = {
 29         8000, 11025, 12000, 16000, 22050,
 30         24000, 32000, 44100, 48000, 64000,
 31         88200, 96000, 176400, 192000
 32 };
 33 
 34 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
 35         .count = ARRAY_SIZE(fsl_sai_rates),
 36         .list = fsl_sai_rates,
 37 };
 38 
 39 static irqreturn_t fsl_sai_isr(int irq, void *devid)
 40 {
 41         struct fsl_sai *sai = (struct fsl_sai *)devid;
 42         struct device *dev = &sai->pdev->dev;
 43         u32 flags, xcsr, mask;
 44         bool irq_none = true;
 45 
 46         /*
 47          * Both IRQ status bits and IRQ mask bits are in the xCSR but
 48          * different shifts. And we here create a mask only for those
 49          * IRQs that we activated.
 50          */
 51         mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
 52 
 53         /* Tx IRQ */
 54         regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
 55         flags = xcsr & mask;
 56 
 57         if (flags)
 58                 irq_none = false;
 59         else
 60                 goto irq_rx;
 61 
 62         if (flags & FSL_SAI_CSR_WSF)
 63                 dev_dbg(dev, "isr: Start of Tx word detected\n");
 64 
 65         if (flags & FSL_SAI_CSR_SEF)
 66                 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
 67 
 68         if (flags & FSL_SAI_CSR_FEF) {
 69                 dev_dbg(dev, "isr: Transmit underrun detected\n");
 70                 /* FIFO reset for safety */
 71                 xcsr |= FSL_SAI_CSR_FR;
 72         }
 73 
 74         if (flags & FSL_SAI_CSR_FWF)
 75                 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
 76 
 77         if (flags & FSL_SAI_CSR_FRF)
 78                 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
 79 
 80         flags &= FSL_SAI_CSR_xF_W_MASK;
 81         xcsr &= ~FSL_SAI_CSR_xF_MASK;
 82 
 83         if (flags)
 84                 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
 85 
 86 irq_rx:
 87         /* Rx IRQ */
 88         regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
 89         flags = xcsr & mask;
 90 
 91         if (flags)
 92                 irq_none = false;
 93         else
 94                 goto out;
 95 
 96         if (flags & FSL_SAI_CSR_WSF)
 97                 dev_dbg(dev, "isr: Start of Rx word detected\n");
 98 
 99         if (flags & FSL_SAI_CSR_SEF)
100                 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
101 
102         if (flags & FSL_SAI_CSR_FEF) {
103                 dev_dbg(dev, "isr: Receive overflow detected\n");
104                 /* FIFO reset for safety */
105                 xcsr |= FSL_SAI_CSR_FR;
106         }
107 
108         if (flags & FSL_SAI_CSR_FWF)
109                 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
110 
111         if (flags & FSL_SAI_CSR_FRF)
112                 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
113 
114         flags &= FSL_SAI_CSR_xF_W_MASK;
115         xcsr &= ~FSL_SAI_CSR_xF_MASK;
116 
117         if (flags)
118                 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
119 
120 out:
121         if (irq_none)
122                 return IRQ_NONE;
123         else
124                 return IRQ_HANDLED;
125 }
126 
127 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
128                                 u32 rx_mask, int slots, int slot_width)
129 {
130         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
131 
132         sai->slots = slots;
133         sai->slot_width = slot_width;
134 
135         return 0;
136 }
137 
138 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
139                 int clk_id, unsigned int freq, int fsl_dir)
140 {
141         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
142         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
143         u32 val_cr2 = 0;
144 
145         switch (clk_id) {
146         case FSL_SAI_CLK_BUS:
147                 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
148                 break;
149         case FSL_SAI_CLK_MAST1:
150                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
151                 break;
152         case FSL_SAI_CLK_MAST2:
153                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
154                 break;
155         case FSL_SAI_CLK_MAST3:
156                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
157                 break;
158         default:
159                 return -EINVAL;
160         }
161 
162         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
163                            FSL_SAI_CR2_MSEL_MASK, val_cr2);
164 
165         return 0;
166 }
167 
168 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
169                 int clk_id, unsigned int freq, int dir)
170 {
171         int ret;
172 
173         if (dir == SND_SOC_CLOCK_IN)
174                 return 0;
175 
176         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
177                                         FSL_FMT_TRANSMITTER);
178         if (ret) {
179                 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
180                 return ret;
181         }
182 
183         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
184                                         FSL_FMT_RECEIVER);
185         if (ret)
186                 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
187 
188         return ret;
189 }
190 
191 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
192                                 unsigned int fmt, int fsl_dir)
193 {
194         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
195         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
196         u32 val_cr2 = 0, val_cr4 = 0;
197 
198         if (!sai->is_lsb_first)
199                 val_cr4 |= FSL_SAI_CR4_MF;
200 
201         /* DAI mode */
202         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
203         case SND_SOC_DAIFMT_I2S:
204                 /*
205                  * Frame low, 1clk before data, one word length for frame sync,
206                  * frame sync starts one serial clock cycle earlier,
207                  * that is, together with the last bit of the previous
208                  * data word.
209                  */
210                 val_cr2 |= FSL_SAI_CR2_BCP;
211                 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
212                 break;
213         case SND_SOC_DAIFMT_LEFT_J:
214                 /*
215                  * Frame high, one word length for frame sync,
216                  * frame sync asserts with the first bit of the frame.
217                  */
218                 val_cr2 |= FSL_SAI_CR2_BCP;
219                 break;
220         case SND_SOC_DAIFMT_DSP_A:
221                 /*
222                  * Frame high, 1clk before data, one bit for frame sync,
223                  * frame sync starts one serial clock cycle earlier,
224                  * that is, together with the last bit of the previous
225                  * data word.
226                  */
227                 val_cr2 |= FSL_SAI_CR2_BCP;
228                 val_cr4 |= FSL_SAI_CR4_FSE;
229                 sai->is_dsp_mode = true;
230                 break;
231         case SND_SOC_DAIFMT_DSP_B:
232                 /*
233                  * Frame high, one bit for frame sync,
234                  * frame sync asserts with the first bit of the frame.
235                  */
236                 val_cr2 |= FSL_SAI_CR2_BCP;
237                 sai->is_dsp_mode = true;
238                 break;
239         case SND_SOC_DAIFMT_RIGHT_J:
240                 /* To be done */
241         default:
242                 return -EINVAL;
243         }
244 
245         /* DAI clock inversion */
246         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
247         case SND_SOC_DAIFMT_IB_IF:
248                 /* Invert both clocks */
249                 val_cr2 ^= FSL_SAI_CR2_BCP;
250                 val_cr4 ^= FSL_SAI_CR4_FSP;
251                 break;
252         case SND_SOC_DAIFMT_IB_NF:
253                 /* Invert bit clock */
254                 val_cr2 ^= FSL_SAI_CR2_BCP;
255                 break;
256         case SND_SOC_DAIFMT_NB_IF:
257                 /* Invert frame clock */
258                 val_cr4 ^= FSL_SAI_CR4_FSP;
259                 break;
260         case SND_SOC_DAIFMT_NB_NF:
261                 /* Nothing to do for both normal cases */
262                 break;
263         default:
264                 return -EINVAL;
265         }
266 
267         /* DAI clock master masks */
268         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
269         case SND_SOC_DAIFMT_CBS_CFS:
270                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
271                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
272                 sai->is_slave_mode = false;
273                 break;
274         case SND_SOC_DAIFMT_CBM_CFM:
275                 sai->is_slave_mode = true;
276                 break;
277         case SND_SOC_DAIFMT_CBS_CFM:
278                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
279                 sai->is_slave_mode = false;
280                 break;
281         case SND_SOC_DAIFMT_CBM_CFS:
282                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
283                 sai->is_slave_mode = true;
284                 break;
285         default:
286                 return -EINVAL;
287         }
288 
289         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
290                            FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
291         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
292                            FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
293                            FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
294 
295         return 0;
296 }
297 
298 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
299 {
300         int ret;
301 
302         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
303         if (ret) {
304                 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
305                 return ret;
306         }
307 
308         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
309         if (ret)
310                 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
311 
312         return ret;
313 }
314 
315 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
316 {
317         struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
318         unsigned long clk_rate;
319         u32 savediv = 0, ratio, savesub = freq;
320         u32 id;
321         int ret = 0;
322 
323         /* Don't apply to slave mode */
324         if (sai->is_slave_mode)
325                 return 0;
326 
327         for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
328                 clk_rate = clk_get_rate(sai->mclk_clk[id]);
329                 if (!clk_rate)
330                         continue;
331 
332                 ratio = clk_rate / freq;
333 
334                 ret = clk_rate - ratio * freq;
335 
336                 /*
337                  * Drop the source that can not be
338                  * divided into the required rate.
339                  */
340                 if (ret != 0 && clk_rate / ret < 1000)
341                         continue;
342 
343                 dev_dbg(dai->dev,
344                         "ratio %d for freq %dHz based on clock %ldHz\n",
345                         ratio, freq, clk_rate);
346 
347                 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
348                         ratio /= 2;
349                 else
350                         continue;
351 
352                 if (ret < savesub) {
353                         savediv = ratio;
354                         sai->mclk_id[tx] = id;
355                         savesub = ret;
356                 }
357 
358                 if (ret == 0)
359                         break;
360         }
361 
362         if (savediv == 0) {
363                 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
364                                 tx ? 'T' : 'R', freq);
365                 return -EINVAL;
366         }
367 
368         /*
369          * 1) For Asynchronous mode, we must set RCR2 register for capture, and
370          *    set TCR2 register for playback.
371          * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
372          *    and capture.
373          * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
374          *    and capture.
375          * 4) For Tx and Rx are both Synchronous with another SAI, we just
376          *    ignore it.
377          */
378         if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
379             (!tx && !sai->synchronous[RX])) {
380                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
381                                    FSL_SAI_CR2_MSEL_MASK,
382                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
383                 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
384                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
385         } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
386                    (tx && !sai->synchronous[TX])) {
387                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
388                                    FSL_SAI_CR2_MSEL_MASK,
389                                    FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
390                 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
391                                    FSL_SAI_CR2_DIV_MASK, savediv - 1);
392         }
393 
394         dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
395                         sai->mclk_id[tx], savediv, savesub);
396 
397         return 0;
398 }
399 
400 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
401                 struct snd_pcm_hw_params *params,
402                 struct snd_soc_dai *cpu_dai)
403 {
404         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
405         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
406         unsigned int channels = params_channels(params);
407         u32 word_width = params_width(params);
408         u32 val_cr4 = 0, val_cr5 = 0;
409         u32 slots = (channels == 1) ? 2 : channels;
410         u32 slot_width = word_width;
411         int ret;
412 
413         if (sai->slots)
414                 slots = sai->slots;
415 
416         if (sai->slot_width)
417                 slot_width = sai->slot_width;
418 
419         if (!sai->is_slave_mode) {
420                 ret = fsl_sai_set_bclk(cpu_dai, tx,
421                                 slots * slot_width * params_rate(params));
422                 if (ret)
423                         return ret;
424 
425                 /* Do not enable the clock if it is already enabled */
426                 if (!(sai->mclk_streams & BIT(substream->stream))) {
427                         ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
428                         if (ret)
429                                 return ret;
430 
431                         sai->mclk_streams |= BIT(substream->stream);
432                 }
433         }
434 
435         if (!sai->is_dsp_mode)
436                 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
437 
438         val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
439         val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
440 
441         if (sai->is_lsb_first)
442                 val_cr5 |= FSL_SAI_CR5_FBT(0);
443         else
444                 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
445 
446         val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
447 
448         /*
449          * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
450          * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
451          * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
452          * error.
453          */
454 
455         if (!sai->is_slave_mode) {
456                 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
457                         regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
458                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
459                                 val_cr4);
460                         regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
461                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
462                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
463                         regmap_write(sai->regmap, FSL_SAI_TMR,
464                                 ~0UL - ((1 << channels) - 1));
465                 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
466                         regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
467                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
468                                 val_cr4);
469                         regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
470                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
471                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
472                         regmap_write(sai->regmap, FSL_SAI_RMR,
473                                 ~0UL - ((1 << channels) - 1));
474                 }
475         }
476 
477         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
478                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
479                            val_cr4);
480         regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
481                            FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
482                            FSL_SAI_CR5_FBT_MASK, val_cr5);
483         regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
484 
485         return 0;
486 }
487 
488 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
489                 struct snd_soc_dai *cpu_dai)
490 {
491         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
492         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
493 
494         if (!sai->is_slave_mode &&
495                         sai->mclk_streams & BIT(substream->stream)) {
496                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
497                 sai->mclk_streams &= ~BIT(substream->stream);
498         }
499 
500         return 0;
501 }
502 
503 
504 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
505                 struct snd_soc_dai *cpu_dai)
506 {
507         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
508         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
509         u32 xcsr, count = 100;
510 
511         /*
512          * Asynchronous mode: Clear SYNC for both Tx and Rx.
513          * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
514          * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
515          */
516         regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
517                            sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
518         regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
519                            sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
520 
521         /*
522          * It is recommended that the transmitter is the last enabled
523          * and the first disabled.
524          */
525         switch (cmd) {
526         case SNDRV_PCM_TRIGGER_START:
527         case SNDRV_PCM_TRIGGER_RESUME:
528         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
529                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
530                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
531 
532                 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
533                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
534                 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
535                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
536 
537                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
538                                    FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
539                 break;
540         case SNDRV_PCM_TRIGGER_STOP:
541         case SNDRV_PCM_TRIGGER_SUSPEND:
542         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
543                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
544                                    FSL_SAI_CSR_FRDE, 0);
545                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
546                                    FSL_SAI_CSR_xIE_MASK, 0);
547 
548                 /* Check if the opposite FRDE is also disabled */
549                 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
550                 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
551                         /* Disable both directions and reset their FIFOs */
552                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
553                                            FSL_SAI_CSR_TERE, 0);
554                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
555                                            FSL_SAI_CSR_TERE, 0);
556 
557                         /* TERE will remain set till the end of current frame */
558                         do {
559                                 udelay(10);
560                                 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
561                         } while (--count && xcsr & FSL_SAI_CSR_TERE);
562 
563                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
564                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
565                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
566                                            FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
567 
568                         /*
569                          * For sai master mode, after several open/close sai,
570                          * there will be no frame clock, and can't recover
571                          * anymore. Add software reset to fix this issue.
572                          * This is a hardware bug, and will be fix in the
573                          * next sai version.
574                          */
575                         if (!sai->is_slave_mode) {
576                                 /* Software Reset for both Tx and Rx */
577                                 regmap_write(sai->regmap,
578                                              FSL_SAI_TCSR, FSL_SAI_CSR_SR);
579                                 regmap_write(sai->regmap,
580                                              FSL_SAI_RCSR, FSL_SAI_CSR_SR);
581                                 /* Clear SR bit to finish the reset */
582                                 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
583                                 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
584                         }
585                 }
586                 break;
587         default:
588                 return -EINVAL;
589         }
590 
591         return 0;
592 }
593 
594 static int fsl_sai_startup(struct snd_pcm_substream *substream,
595                 struct snd_soc_dai *cpu_dai)
596 {
597         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
598         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
599         int ret;
600 
601         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
602                            FSL_SAI_CR3_TRCE);
603 
604         ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
605                         SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
606 
607         return ret;
608 }
609 
610 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
611                 struct snd_soc_dai *cpu_dai)
612 {
613         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
614         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
615 
616         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
617 }
618 
619 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
620         .set_sysclk     = fsl_sai_set_dai_sysclk,
621         .set_fmt        = fsl_sai_set_dai_fmt,
622         .set_tdm_slot   = fsl_sai_set_dai_tdm_slot,
623         .hw_params      = fsl_sai_hw_params,
624         .hw_free        = fsl_sai_hw_free,
625         .trigger        = fsl_sai_trigger,
626         .startup        = fsl_sai_startup,
627         .shutdown       = fsl_sai_shutdown,
628 };
629 
630 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
631 {
632         struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
633 
634         /* Software Reset for both Tx and Rx */
635         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
636         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
637         /* Clear SR bit to finish the reset */
638         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
639         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
640 
641         regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
642                            FSL_SAI_MAXBURST_TX * 2);
643         regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
644                            FSL_SAI_MAXBURST_RX - 1);
645 
646         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
647                                 &sai->dma_params_rx);
648 
649         snd_soc_dai_set_drvdata(cpu_dai, sai);
650 
651         return 0;
652 }
653 
654 static struct snd_soc_dai_driver fsl_sai_dai = {
655         .probe = fsl_sai_dai_probe,
656         .playback = {
657                 .stream_name = "CPU-Playback",
658                 .channels_min = 1,
659                 .channels_max = 32,
660                 .rate_min = 8000,
661                 .rate_max = 192000,
662                 .rates = SNDRV_PCM_RATE_KNOT,
663                 .formats = FSL_SAI_FORMATS,
664         },
665         .capture = {
666                 .stream_name = "CPU-Capture",
667                 .channels_min = 1,
668                 .channels_max = 32,
669                 .rate_min = 8000,
670                 .rate_max = 192000,
671                 .rates = SNDRV_PCM_RATE_KNOT,
672                 .formats = FSL_SAI_FORMATS,
673         },
674         .ops = &fsl_sai_pcm_dai_ops,
675 };
676 
677 static const struct snd_soc_component_driver fsl_component = {
678         .name           = "fsl-sai",
679 };
680 
681 static struct reg_default fsl_sai_reg_defaults[] = {
682         {FSL_SAI_TCR1, 0},
683         {FSL_SAI_TCR2, 0},
684         {FSL_SAI_TCR3, 0},
685         {FSL_SAI_TCR4, 0},
686         {FSL_SAI_TCR5, 0},
687         {FSL_SAI_TDR,  0},
688         {FSL_SAI_TMR,  0},
689         {FSL_SAI_RCR1, 0},
690         {FSL_SAI_RCR2, 0},
691         {FSL_SAI_RCR3, 0},
692         {FSL_SAI_RCR4, 0},
693         {FSL_SAI_RCR5, 0},
694         {FSL_SAI_RMR,  0},
695 };
696 
697 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
698 {
699         switch (reg) {
700         case FSL_SAI_TCSR:
701         case FSL_SAI_TCR1:
702         case FSL_SAI_TCR2:
703         case FSL_SAI_TCR3:
704         case FSL_SAI_TCR4:
705         case FSL_SAI_TCR5:
706         case FSL_SAI_TFR:
707         case FSL_SAI_TMR:
708         case FSL_SAI_RCSR:
709         case FSL_SAI_RCR1:
710         case FSL_SAI_RCR2:
711         case FSL_SAI_RCR3:
712         case FSL_SAI_RCR4:
713         case FSL_SAI_RCR5:
714         case FSL_SAI_RDR:
715         case FSL_SAI_RFR:
716         case FSL_SAI_RMR:
717                 return true;
718         default:
719                 return false;
720         }
721 }
722 
723 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
724 {
725         switch (reg) {
726         case FSL_SAI_TCSR:
727         case FSL_SAI_RCSR:
728         case FSL_SAI_TFR:
729         case FSL_SAI_RFR:
730         case FSL_SAI_RDR:
731                 return true;
732         default:
733                 return false;
734         }
735 }
736 
737 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
738 {
739         switch (reg) {
740         case FSL_SAI_TCSR:
741         case FSL_SAI_TCR1:
742         case FSL_SAI_TCR2:
743         case FSL_SAI_TCR3:
744         case FSL_SAI_TCR4:
745         case FSL_SAI_TCR5:
746         case FSL_SAI_TDR:
747         case FSL_SAI_TMR:
748         case FSL_SAI_RCSR:
749         case FSL_SAI_RCR1:
750         case FSL_SAI_RCR2:
751         case FSL_SAI_RCR3:
752         case FSL_SAI_RCR4:
753         case FSL_SAI_RCR5:
754         case FSL_SAI_RMR:
755                 return true;
756         default:
757                 return false;
758         }
759 }
760 
761 static const struct regmap_config fsl_sai_regmap_config = {
762         .reg_bits = 32,
763         .reg_stride = 4,
764         .val_bits = 32,
765 
766         .max_register = FSL_SAI_RMR,
767         .reg_defaults = fsl_sai_reg_defaults,
768         .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
769         .readable_reg = fsl_sai_readable_reg,
770         .volatile_reg = fsl_sai_volatile_reg,
771         .writeable_reg = fsl_sai_writeable_reg,
772         .cache_type = REGCACHE_FLAT,
773 };
774 
775 static int fsl_sai_probe(struct platform_device *pdev)
776 {
777         struct device_node *np = pdev->dev.of_node;
778         struct fsl_sai *sai;
779         struct regmap *gpr;
780         struct resource *res;
781         void __iomem *base;
782         char tmp[8];
783         int irq, ret, i;
784         int index;
785 
786         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
787         if (!sai)
788                 return -ENOMEM;
789 
790         sai->pdev = pdev;
791 
792         if (of_device_is_compatible(np, "fsl,imx6sx-sai") ||
793             of_device_is_compatible(np, "fsl,imx6ul-sai"))
794                 sai->sai_on_imx = true;
795 
796         sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
797 
798         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
799         base = devm_ioremap_resource(&pdev->dev, res);
800         if (IS_ERR(base))
801                 return PTR_ERR(base);
802 
803         sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
804                         "bus", base, &fsl_sai_regmap_config);
805 
806         /* Compatible with old DTB cases */
807         if (IS_ERR(sai->regmap))
808                 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
809                                 "sai", base, &fsl_sai_regmap_config);
810         if (IS_ERR(sai->regmap)) {
811                 dev_err(&pdev->dev, "regmap init failed\n");
812                 return PTR_ERR(sai->regmap);
813         }
814 
815         /* No error out for old DTB cases but only mark the clock NULL */
816         sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
817         if (IS_ERR(sai->bus_clk)) {
818                 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
819                                 PTR_ERR(sai->bus_clk));
820                 sai->bus_clk = NULL;
821         }
822 
823         sai->mclk_clk[0] = sai->bus_clk;
824         for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
825                 sprintf(tmp, "mclk%d", i);
826                 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
827                 if (IS_ERR(sai->mclk_clk[i])) {
828                         dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
829                                         i + 1, PTR_ERR(sai->mclk_clk[i]));
830                         sai->mclk_clk[i] = NULL;
831                 }
832         }
833 
834         irq = platform_get_irq(pdev, 0);
835         if (irq < 0) {
836                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
837                 return irq;
838         }
839 
840         ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
841         if (ret) {
842                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
843                 return ret;
844         }
845 
846         /* Sync Tx with Rx as default by following old DT binding */
847         sai->synchronous[RX] = true;
848         sai->synchronous[TX] = false;
849         fsl_sai_dai.symmetric_rates = 1;
850         fsl_sai_dai.symmetric_channels = 1;
851         fsl_sai_dai.symmetric_samplebits = 1;
852 
853         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
854             of_find_property(np, "fsl,sai-asynchronous", NULL)) {
855                 /* error out if both synchronous and asynchronous are present */
856                 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
857                 return -EINVAL;
858         }
859 
860         if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
861                 /* Sync Rx with Tx */
862                 sai->synchronous[RX] = false;
863                 sai->synchronous[TX] = true;
864         } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
865                 /* Discard all settings for asynchronous mode */
866                 sai->synchronous[RX] = false;
867                 sai->synchronous[TX] = false;
868                 fsl_sai_dai.symmetric_rates = 0;
869                 fsl_sai_dai.symmetric_channels = 0;
870                 fsl_sai_dai.symmetric_samplebits = 0;
871         }
872 
873         if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
874             of_device_is_compatible(np, "fsl,imx6ul-sai")) {
875                 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
876                 if (IS_ERR(gpr)) {
877                         dev_err(&pdev->dev, "cannot find iomuxc registers\n");
878                         return PTR_ERR(gpr);
879                 }
880 
881                 index = of_alias_get_id(np, "sai");
882                 if (index < 0)
883                         return index;
884 
885                 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
886                                    MCLK_DIR(index));
887         }
888 
889         sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
890         sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
891         sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
892         sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
893 
894         platform_set_drvdata(pdev, sai);
895 
896         pm_runtime_enable(&pdev->dev);
897 
898         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
899                         &fsl_sai_dai, 1);
900         if (ret)
901                 return ret;
902 
903         if (sai->sai_on_imx)
904                 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
905         else
906                 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
907 }
908 
909 static int fsl_sai_remove(struct platform_device *pdev)
910 {
911         pm_runtime_disable(&pdev->dev);
912 
913         return 0;
914 }
915 
916 static const struct of_device_id fsl_sai_ids[] = {
917         { .compatible = "fsl,vf610-sai", },
918         { .compatible = "fsl,imx6sx-sai", },
919         { .compatible = "fsl,imx6ul-sai", },
920         { /* sentinel */ }
921 };
922 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
923 
924 #ifdef CONFIG_PM
925 static int fsl_sai_runtime_suspend(struct device *dev)
926 {
927         struct fsl_sai *sai = dev_get_drvdata(dev);
928 
929         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
930                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
931 
932         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
933                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
934 
935         clk_disable_unprepare(sai->bus_clk);
936 
937         regcache_cache_only(sai->regmap, true);
938         regcache_mark_dirty(sai->regmap);
939 
940         return 0;
941 }
942 
943 static int fsl_sai_runtime_resume(struct device *dev)
944 {
945         struct fsl_sai *sai = dev_get_drvdata(dev);
946         int ret;
947 
948         ret = clk_prepare_enable(sai->bus_clk);
949         if (ret) {
950                 dev_err(dev, "failed to enable bus clock: %d\n", ret);
951                 return ret;
952         }
953 
954         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
955                 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
956                 if (ret)
957                         goto disable_bus_clk;
958         }
959 
960         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
961                 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
962                 if (ret)
963                         goto disable_tx_clk;
964         }
965 
966         regcache_cache_only(sai->regmap, false);
967         regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
968         regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
969         usleep_range(1000, 2000);
970         regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
971         regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
972 
973         ret = regcache_sync(sai->regmap);
974         if (ret)
975                 goto disable_rx_clk;
976 
977         return 0;
978 
979 disable_rx_clk:
980         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
981                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
982 disable_tx_clk:
983         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
984                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
985 disable_bus_clk:
986         clk_disable_unprepare(sai->bus_clk);
987 
988         return ret;
989 }
990 #endif /* CONFIG_PM */
991 
992 static const struct dev_pm_ops fsl_sai_pm_ops = {
993         SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
994                            fsl_sai_runtime_resume, NULL)
995         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
996                                 pm_runtime_force_resume)
997 };
998 
999 static struct platform_driver fsl_sai_driver = {
1000         .probe = fsl_sai_probe,
1001         .remove = fsl_sai_remove,
1002         .driver = {
1003                 .name = "fsl-sai",
1004                 .pm = &fsl_sai_pm_ops,
1005                 .of_match_table = fsl_sai_ids,
1006         },
1007 };
1008 module_platform_driver(fsl_sai_driver);
1009 
1010 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1011 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1012 MODULE_ALIAS("platform:fsl-sai");
1013 MODULE_LICENSE("GPL");
1014 

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