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TOMOYO Linux Cross Reference
Linux/sound/soc/hisilicon/hi6210-i2s.c

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  1 /*
  2  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
  3  *
  4  * Copyright (C) 2015 Linaro, Ltd
  5  * Author: Andy Green <andy.green@linaro.org>
  6  *
  7  * This program is free software: you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation, version 2 of the License.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * This driver only deals with S2 interface (BT)
 17  */
 18 
 19 #include <linux/init.h>
 20 #include <linux/module.h>
 21 #include <linux/device.h>
 22 #include <linux/delay.h>
 23 #include <linux/clk.h>
 24 #include <linux/jiffies.h>
 25 #include <linux/io.h>
 26 #include <linux/gpio.h>
 27 #include <sound/core.h>
 28 #include <sound/pcm.h>
 29 #include <sound/pcm_params.h>
 30 #include <sound/dmaengine_pcm.h>
 31 #include <sound/initval.h>
 32 #include <sound/soc.h>
 33 #include <linux/interrupt.h>
 34 #include <linux/reset.h>
 35 #include <linux/of_address.h>
 36 #include <linux/of_irq.h>
 37 #include <linux/mfd/syscon.h>
 38 #include <linux/reset-controller.h>
 39 
 40 #include "hi6210-i2s.h"
 41 
 42 struct hi6210_i2s {
 43         struct device *dev;
 44         struct reset_control *rc;
 45         struct clk *clk[8];
 46         int clocks;
 47         struct snd_soc_dai_driver dai;
 48         void __iomem *base;
 49         struct regmap *sysctrl;
 50         phys_addr_t base_phys;
 51         struct snd_dmaengine_dai_dma_data dma_data[2];
 52         int clk_rate;
 53         spinlock_t lock;
 54         int rate;
 55         int format;
 56         u8 bits;
 57         u8 channels;
 58         u8 id;
 59         u8 channel_length;
 60         u8 use;
 61         u32 master:1;
 62         u32 status:1;
 63 };
 64 
 65 #define SC_PERIPH_CLKEN1        0x210
 66 #define SC_PERIPH_CLKDIS1       0x214
 67 
 68 #define SC_PERIPH_CLKEN3        0x230
 69 #define SC_PERIPH_CLKDIS3       0x234
 70 
 71 #define SC_PERIPH_CLKEN12       0x270
 72 #define SC_PERIPH_CLKDIS12      0x274
 73 
 74 #define SC_PERIPH_RSTEN1        0x310
 75 #define SC_PERIPH_RSTDIS1       0x314
 76 #define SC_PERIPH_RSTSTAT1      0x318
 77 
 78 #define SC_PERIPH_RSTEN2        0x320
 79 #define SC_PERIPH_RSTDIS2       0x324
 80 #define SC_PERIPH_RSTSTAT2      0x328
 81 
 82 #define SOC_PMCTRL_BBPPLLALIAS  0x48
 83 
 84 enum {
 85         CLK_DACODEC,
 86         CLK_I2S_BASE,
 87 };
 88 
 89 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
 90 {
 91         writel(val, i2s->base + reg);
 92 }
 93 
 94 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
 95 {
 96         return readl(i2s->base + reg);
 97 }
 98 
 99 static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
100                               struct snd_soc_dai *cpu_dai)
101 {
102         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
103         int ret, n;
104         u32 val;
105 
106         /* deassert reset on ABB */
107         regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
108         if (val & BIT(4))
109                 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
110 
111         for (n = 0; n < i2s->clocks; n++) {
112                 ret = clk_prepare_enable(i2s->clk[n]);
113                 if (ret) {
114                         while (n--)
115                                 clk_disable_unprepare(i2s->clk[n]);
116                         return ret;
117                 }
118         }
119 
120         ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
121         if (ret) {
122                 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
123                         __func__, ret);
124                 return ret;
125         }
126 
127         /* enable clock before frequency division */
128         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
129 
130         /* enable codec working clock / == "codec bus clock" */
131         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
132 
133         /* deassert reset on codec / interface clock / working clock */
134         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
135         regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
136 
137         /* not interested in i2s irqs */
138         val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
139         val |= 0x3f;
140         hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
141 
142 
143         /* reset the stereo downlink fifo */
144         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
145         val |= (BIT(5) | BIT(4));
146         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
147 
148         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
149         val &= ~(BIT(5) | BIT(4));
150         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
151 
152 
153         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
154         val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
155                         HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
156         val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
157         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
158 
159         val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
160         /* mux 11/12 = APB not i2s */
161         val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
162         /* BT R ch  0 = mixer op of DACR ch */
163         val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
164         val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
165 
166         val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
167         /* BT L ch = 1 = mux 7 = "mixer output of DACL */
168         val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
169         hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
170 
171         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
172         val |= HII2S_SW_RST_N__SW_RST_N;
173         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
174 
175         return 0;
176 }
177 
178 static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
179                                 struct snd_soc_dai *cpu_dai)
180 {
181         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
182         int n;
183 
184         for (n = 0; n < i2s->clocks; n++)
185                 clk_disable_unprepare(i2s->clk[n]);
186 
187         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
188 }
189 
190 static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
191 {
192         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
193         u32 val;
194 
195         spin_lock(&i2s->lock);
196         if (on) {
197                 /* enable S2 TX */
198                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
199                 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
200                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
201         } else {
202                 /* disable S2 TX */
203                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
204                 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
205                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
206         }
207         spin_unlock(&i2s->lock);
208 }
209 
210 static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
211 {
212         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
213         u32 val;
214 
215         spin_lock(&i2s->lock);
216         if (on) {
217                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
218                 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
219                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
220         } else {
221                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
222                 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
223                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
224         }
225         spin_unlock(&i2s->lock);
226 }
227 
228 static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
229 {
230         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
231 
232         /*
233          * We don't actually set the hardware until the hw_params
234          * call, but we need to validate the user input here.
235          */
236         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
237         case SND_SOC_DAIFMT_CBM_CFM:
238         case SND_SOC_DAIFMT_CBS_CFS:
239                 break;
240         default:
241                 return -EINVAL;
242         }
243 
244         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
245         case SND_SOC_DAIFMT_I2S:
246         case SND_SOC_DAIFMT_LEFT_J:
247         case SND_SOC_DAIFMT_RIGHT_J:
248                 break;
249         default:
250                 return -EINVAL;
251         }
252 
253         i2s->format = fmt;
254         i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
255                       SND_SOC_DAIFMT_CBS_CFS;
256 
257         return 0;
258 }
259 
260 static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
261                             struct snd_pcm_hw_params *params,
262                             struct snd_soc_dai *cpu_dai)
263 {
264         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
265         u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
266         u32 val;
267         struct snd_dmaengine_dai_dma_data *dma_data;
268 
269         switch (params_format(params)) {
270         case SNDRV_PCM_FORMAT_U16_LE:
271                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
272                 /* fall through */
273         case SNDRV_PCM_FORMAT_S16_LE:
274                 bits = HII2S_BITS_16;
275                 break;
276         case SNDRV_PCM_FORMAT_U24_LE:
277                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
278                 /* fall through */
279         case SNDRV_PCM_FORMAT_S24_LE:
280                 bits = HII2S_BITS_24;
281                 break;
282         default:
283                 dev_err(cpu_dai->dev, "Bad format\n");
284                 return -EINVAL;
285         }
286 
287 
288         switch (params_rate(params)) {
289         case 8000:
290                 rate = HII2S_FS_RATE_8KHZ;
291                 break;
292         case 16000:
293                 rate = HII2S_FS_RATE_16KHZ;
294                 break;
295         case 32000:
296                 rate = HII2S_FS_RATE_32KHZ;
297                 break;
298         case 48000:
299                 rate = HII2S_FS_RATE_48KHZ;
300                 break;
301         case 96000:
302                 rate = HII2S_FS_RATE_96KHZ;
303                 break;
304         case 192000:
305                 rate = HII2S_FS_RATE_192KHZ;
306                 break;
307         default:
308                 dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
309                 return -EINVAL;
310         }
311 
312         if (!(params_channels(params))) {
313                 dev_err(cpu_dai->dev, "Bad channels\n");
314                 return -EINVAL;
315         }
316 
317         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
318 
319         switch (bits) {
320         case HII2S_BITS_24:
321                 i2s->bits = 32;
322                 dma_data->addr_width = 3;
323                 break;
324         default:
325                 i2s->bits = 16;
326                 dma_data->addr_width = 2;
327                 break;
328         }
329         i2s->rate = params_rate(params);
330         i2s->channels = params_channels(params);
331         i2s->channel_length = i2s->channels * i2s->bits;
332 
333         val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
334         val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
335                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
336                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
337                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
338                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
339                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
340                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
341                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
342         val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
343                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
344                 (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
345                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
346         hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
347 
348 
349         val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
350         val |= (BIT(19) | BIT(18) | BIT(17) |
351                 HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
352                 HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
353                 HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
354                 HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
355                 HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
356         hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
357 
358 
359         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
360         val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
361                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
362                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
363                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
364                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
365                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
366         val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
367                 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
368         hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
369 
370 
371         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
372         val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
373                  HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
374         hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
375 
376         val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
377         val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
378                  HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
379                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
380                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
381         hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
382 
383 
384         switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
385         case SND_SOC_DAIFMT_CBM_CFM:
386                 i2s->master = false;
387                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
388                 val |= HII2S_I2S_CFG__S2_MST_SLV;
389                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
390                 break;
391         case SND_SOC_DAIFMT_CBS_CFS:
392                 i2s->master = true;
393                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
394                 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
395                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
396                 break;
397         default:
398                 WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
399                 return -EINVAL;
400         }
401 
402         switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
403         case SND_SOC_DAIFMT_I2S:
404                 fmt = HII2S_FORMAT_I2S;
405                 break;
406         case SND_SOC_DAIFMT_LEFT_J:
407                 fmt = HII2S_FORMAT_LEFT_JUST;
408                 break;
409         case SND_SOC_DAIFMT_RIGHT_J:
410                 fmt = HII2S_FORMAT_RIGHT_JUST;
411                 break;
412         default:
413                 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
414                 return -EINVAL;
415         }
416 
417         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
418         val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
419                         HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
420         val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
421         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
422 
423 
424         val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
425         val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
426                         HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
427         hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
428 
429         dma_data->maxburst = 2;
430 
431         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
432                 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
433         else
434                 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
435 
436         switch (i2s->channels) {
437         case 1:
438                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
439                 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
440                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
441                 break;
442         default:
443                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
444                 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
445                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
446                 break;
447         }
448 
449         /* clear loopback, set signed type and word length */
450         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
451         val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
452         val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
453                         HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
454         val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
455                         HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
456         val |= signed_data;
457         val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
458         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
459 
460 
461         if (!i2s->master)
462                 return 0;
463 
464         /* set DAC and related units to correct rate */
465         val = hi6210_read_reg(i2s, HII2S_FS_CFG);
466         val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
467         val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
468         val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
469                                         HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
470         val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
471                                         HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
472         val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
473         val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
474         val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
475         val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
476         hi6210_write_reg(i2s, HII2S_FS_CFG, val);
477 
478         return 0;
479 }
480 
481 static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
482                           struct snd_soc_dai *cpu_dai)
483 {
484         pr_debug("%s\n", __func__);
485         switch (cmd) {
486         case SNDRV_PCM_TRIGGER_START:
487         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
488                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
489                         hi6210_i2s_rxctrl(cpu_dai, 1);
490                 else
491                         hi6210_i2s_txctrl(cpu_dai, 1);
492                 break;
493         case SNDRV_PCM_TRIGGER_STOP:
494         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
495                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
496                         hi6210_i2s_rxctrl(cpu_dai, 0);
497                 else
498                         hi6210_i2s_txctrl(cpu_dai, 0);
499                 break;
500         default:
501                 dev_err(cpu_dai->dev, "unknown cmd\n");
502                 return -EINVAL;
503         }
504         return 0;
505 }
506 
507 static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
508 {
509         struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
510 
511         snd_soc_dai_init_dma_data(dai,
512                                   &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
513                                   &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
514 
515         return 0;
516 }
517 
518 
519 static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
520         .trigger        = hi6210_i2s_trigger,
521         .hw_params      = hi6210_i2s_hw_params,
522         .set_fmt        = hi6210_i2s_set_fmt,
523         .startup        = hi6210_i2s_startup,
524         .shutdown       = hi6210_i2s_shutdown,
525 };
526 
527 static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
528         .probe          = hi6210_i2s_dai_probe,
529         .playback = {
530                 .channels_min = 2,
531                 .channels_max = 2,
532                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
533                            SNDRV_PCM_FMTBIT_U16_LE,
534                 .rates = SNDRV_PCM_RATE_48000,
535         },
536         .capture = {
537                 .channels_min = 2,
538                 .channels_max = 2,
539                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
540                            SNDRV_PCM_FMTBIT_U16_LE,
541                 .rates = SNDRV_PCM_RATE_48000,
542         },
543         .ops = &hi6210_i2s_dai_ops,
544 };
545 
546 static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
547         .name = "hi6210_i2s-i2s",
548 };
549 
550 static int hi6210_i2s_probe(struct platform_device *pdev)
551 {
552         struct device_node *node = pdev->dev.of_node;
553         struct device *dev = &pdev->dev;
554         struct hi6210_i2s *i2s;
555         struct resource *res;
556         int ret;
557 
558         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
559         if (!i2s)
560                 return -ENOMEM;
561 
562         i2s->dev = dev;
563         spin_lock_init(&i2s->lock);
564 
565         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
566         i2s->base = devm_ioremap_resource(dev, res);
567         if (IS_ERR(i2s->base))
568                 return PTR_ERR(i2s->base);
569 
570         i2s->base_phys = (phys_addr_t)res->start;
571         i2s->dai = hi6210_i2s_dai_init;
572 
573         dev_set_drvdata(&pdev->dev, i2s);
574 
575         i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
576                                                 "hisilicon,sysctrl-syscon");
577         if (IS_ERR(i2s->sysctrl))
578                 return PTR_ERR(i2s->sysctrl);
579 
580         i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
581         if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
582                 return PTR_ERR(i2s->clk[CLK_DACODEC]);
583         i2s->clocks++;
584 
585         i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
586         if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
587                 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
588         i2s->clocks++;
589 
590         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
591         if (ret)
592                 return ret;
593 
594         ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
595                                          &i2s->dai, 1);
596         return ret;
597 }
598 
599 static const struct of_device_id hi6210_i2s_dt_ids[] = {
600         { .compatible = "hisilicon,hi6210-i2s" },
601         { /* sentinel */ }
602 };
603 
604 MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
605 
606 static struct platform_driver hi6210_i2s_driver = {
607         .probe = hi6210_i2s_probe,
608         .driver = {
609                 .name = "hi6210_i2s",
610                 .of_match_table = hi6210_i2s_dt_ids,
611         },
612 };
613 
614 module_platform_driver(hi6210_i2s_driver);
615 
616 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
617 MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
618 MODULE_LICENSE("GPL");
619 

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