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Linux/sound/soc/img/img-parallel-out.c

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  1 /*
  2  * IMG parallel output controller driver
  3  *
  4  * Copyright (C) 2015 Imagination Technologies Ltd.
  5  *
  6  * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify it
  9  * under the terms and conditions of the GNU General Public License,
 10  * version 2, as published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/clk.h>
 14 #include <linux/init.h>
 15 #include <linux/kernel.h>
 16 #include <linux/module.h>
 17 #include <linux/of.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/pm_runtime.h>
 20 #include <linux/reset.h>
 21 
 22 #include <sound/core.h>
 23 #include <sound/dmaengine_pcm.h>
 24 #include <sound/initval.h>
 25 #include <sound/pcm.h>
 26 #include <sound/pcm_params.h>
 27 #include <sound/soc.h>
 28 
 29 #define IMG_PRL_OUT_TX_FIFO             0
 30 
 31 #define IMG_PRL_OUT_CTL                 0x4
 32 #define IMG_PRL_OUT_CTL_CH_MASK         BIT(4)
 33 #define IMG_PRL_OUT_CTL_PACKH_MASK      BIT(3)
 34 #define IMG_PRL_OUT_CTL_EDGE_MASK       BIT(2)
 35 #define IMG_PRL_OUT_CTL_ME_MASK         BIT(1)
 36 #define IMG_PRL_OUT_CTL_SRST_MASK       BIT(0)
 37 
 38 struct img_prl_out {
 39         void __iomem *base;
 40         struct clk *clk_sys;
 41         struct clk *clk_ref;
 42         struct snd_dmaengine_dai_dma_data dma_data;
 43         struct device *dev;
 44         struct reset_control *rst;
 45 };
 46 
 47 static int img_prl_out_suspend(struct device *dev)
 48 {
 49         struct img_prl_out *prl = dev_get_drvdata(dev);
 50 
 51         clk_disable_unprepare(prl->clk_ref);
 52 
 53         return 0;
 54 }
 55 
 56 static int img_prl_out_resume(struct device *dev)
 57 {
 58         struct img_prl_out *prl = dev_get_drvdata(dev);
 59         int ret;
 60 
 61         ret = clk_prepare_enable(prl->clk_ref);
 62         if (ret) {
 63                 dev_err(dev, "clk_enable failed: %d\n", ret);
 64                 return ret;
 65         }
 66 
 67         return 0;
 68 }
 69 
 70 static inline void img_prl_out_writel(struct img_prl_out *prl,
 71                                 u32 val, u32 reg)
 72 {
 73         writel(val, prl->base + reg);
 74 }
 75 
 76 static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
 77 {
 78         return readl(prl->base + reg);
 79 }
 80 
 81 static void img_prl_out_reset(struct img_prl_out *prl)
 82 {
 83         u32 ctl;
 84 
 85         ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
 86                         ~IMG_PRL_OUT_CTL_ME_MASK;
 87 
 88         reset_control_assert(prl->rst);
 89         reset_control_deassert(prl->rst);
 90 
 91         img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
 92 }
 93 
 94 static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
 95                         struct snd_soc_dai *dai)
 96 {
 97         struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
 98         u32 reg;
 99 
100         switch (cmd) {
101         case SNDRV_PCM_TRIGGER_START:
102         case SNDRV_PCM_TRIGGER_RESUME:
103         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
104                 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
105                 reg |= IMG_PRL_OUT_CTL_ME_MASK;
106                 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
107                 break;
108         case SNDRV_PCM_TRIGGER_STOP:
109         case SNDRV_PCM_TRIGGER_SUSPEND:
110         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
111                 img_prl_out_reset(prl);
112                 break;
113         default:
114                 return -EINVAL;
115         }
116 
117         return 0;
118 }
119 
120 static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
121         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
122 {
123         struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
124         unsigned int rate, channels;
125         u32 reg, control_set = 0;
126 
127         rate = params_rate(params);
128         channels = params_channels(params);
129 
130         switch (params_format(params)) {
131         case SNDRV_PCM_FORMAT_S32_LE:
132                 control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
133                 break;
134         case SNDRV_PCM_FORMAT_S24_LE:
135                 break;
136         default:
137                 return -EINVAL;
138         }
139 
140         if (channels != 2)
141                 return -EINVAL;
142 
143         clk_set_rate(prl->clk_ref, rate * 256);
144 
145         reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
146         reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
147         img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
148 
149         return 0;
150 }
151 
152 static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
153 {
154         struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
155         u32 reg, control_set = 0;
156 
157         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
158         case SND_SOC_DAIFMT_NB_NF:
159                 break;
160         case SND_SOC_DAIFMT_NB_IF:
161                 control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
162                 break;
163         default:
164                 return -EINVAL;
165         }
166 
167         reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
168         reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
169         img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
170 
171         return 0;
172 }
173 
174 static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
175         .trigger = img_prl_out_trigger,
176         .hw_params = img_prl_out_hw_params,
177         .set_fmt = img_prl_out_set_fmt
178 };
179 
180 static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
181 {
182         struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
183 
184         snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
185 
186         return 0;
187 }
188 
189 static struct snd_soc_dai_driver img_prl_out_dai = {
190         .probe = img_prl_out_dai_probe,
191         .playback = {
192                 .channels_min = 2,
193                 .channels_max = 2,
194                 .rates = SNDRV_PCM_RATE_8000_192000,
195                 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
196         },
197         .ops = &img_prl_out_dai_ops
198 };
199 
200 static const struct snd_soc_component_driver img_prl_out_component = {
201         .name = "img-prl-out"
202 };
203 
204 static int img_prl_out_probe(struct platform_device *pdev)
205 {
206         struct img_prl_out *prl;
207         struct resource *res;
208         void __iomem *base;
209         int ret;
210         struct device *dev = &pdev->dev;
211 
212         prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
213         if (!prl)
214                 return -ENOMEM;
215 
216         platform_set_drvdata(pdev, prl);
217 
218         prl->dev = &pdev->dev;
219 
220         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
221         base = devm_ioremap_resource(&pdev->dev, res);
222         if (IS_ERR(base))
223                 return PTR_ERR(base);
224 
225         prl->base = base;
226 
227         prl->rst = devm_reset_control_get(&pdev->dev, "rst");
228         if (IS_ERR(prl->rst)) {
229                 if (PTR_ERR(prl->rst) != -EPROBE_DEFER)
230                         dev_err(&pdev->dev, "No top level reset found\n");
231                 return PTR_ERR(prl->rst);
232         }
233 
234         prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
235         if (IS_ERR(prl->clk_sys)) {
236                 if (PTR_ERR(prl->clk_sys) != -EPROBE_DEFER)
237                         dev_err(dev, "Failed to acquire clock 'sys'\n");
238                 return PTR_ERR(prl->clk_sys);
239         }
240 
241         prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
242         if (IS_ERR(prl->clk_ref)) {
243                 if (PTR_ERR(prl->clk_ref) != -EPROBE_DEFER)
244                         dev_err(dev, "Failed to acquire clock 'ref'\n");
245                 return PTR_ERR(prl->clk_ref);
246         }
247 
248         ret = clk_prepare_enable(prl->clk_sys);
249         if (ret)
250                 return ret;
251 
252         img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
253         img_prl_out_reset(prl);
254 
255         pm_runtime_enable(&pdev->dev);
256         if (!pm_runtime_enabled(&pdev->dev)) {
257                 ret = img_prl_out_resume(&pdev->dev);
258                 if (ret)
259                         goto err_pm_disable;
260         }
261 
262         prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
263         prl->dma_data.addr_width = 4;
264         prl->dma_data.maxburst = 4;
265 
266         ret = devm_snd_soc_register_component(&pdev->dev,
267                         &img_prl_out_component,
268                         &img_prl_out_dai, 1);
269         if (ret)
270                 goto err_suspend;
271 
272         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
273         if (ret)
274                 goto err_suspend;
275 
276         return 0;
277 
278 err_suspend:
279         if (!pm_runtime_status_suspended(&pdev->dev))
280                 img_prl_out_suspend(&pdev->dev);
281 err_pm_disable:
282         pm_runtime_disable(&pdev->dev);
283         clk_disable_unprepare(prl->clk_sys);
284 
285         return ret;
286 }
287 
288 static int img_prl_out_dev_remove(struct platform_device *pdev)
289 {
290         struct img_prl_out *prl = platform_get_drvdata(pdev);
291 
292         pm_runtime_disable(&pdev->dev);
293         if (!pm_runtime_status_suspended(&pdev->dev))
294                 img_prl_out_suspend(&pdev->dev);
295 
296         clk_disable_unprepare(prl->clk_sys);
297 
298         return 0;
299 }
300 
301 static const struct of_device_id img_prl_out_of_match[] = {
302         { .compatible = "img,parallel-out" },
303         {}
304 };
305 MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
306 
307 static const struct dev_pm_ops img_prl_out_pm_ops = {
308         SET_RUNTIME_PM_OPS(img_prl_out_suspend,
309                            img_prl_out_resume, NULL)
310 };
311 
312 static struct platform_driver img_prl_out_driver = {
313         .driver = {
314                 .name = "img-parallel-out",
315                 .of_match_table = img_prl_out_of_match,
316                 .pm = &img_prl_out_pm_ops
317         },
318         .probe = img_prl_out_probe,
319         .remove = img_prl_out_dev_remove
320 };
321 module_platform_driver(img_prl_out_driver);
322 
323 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
324 MODULE_DESCRIPTION("IMG Parallel Output Driver");
325 MODULE_LICENSE("GPL v2");
326 

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