~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/intel/skylake/skl-pcm.c

Version: ~ [ linux-5.10-rc1 ] ~ [ linux-5.9.1 ] ~ [ linux-5.8.16 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.72 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.152 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.202 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.240 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.240 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
  3  *
  4  *  Copyright (C) 2014-2015 Intel Corp
  5  *  Author:  Jeeja KP <jeeja.kp@intel.com>
  6  *
  7  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  8  *
  9  *  This program is free software; you can redistribute it and/or modify
 10  *  it under the terms of the GNU General Public License as published by
 11  *  the Free Software Foundation; version 2 of the License.
 12  *
 13  *  This program is distributed in the hope that it will be useful, but
 14  *  WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  *  General Public License for more details.
 17  *
 18  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 19  *
 20  */
 21 
 22 #include <linux/pci.h>
 23 #include <linux/pm_runtime.h>
 24 #include <linux/delay.h>
 25 #include <sound/pcm_params.h>
 26 #include <sound/soc.h>
 27 #include "skl.h"
 28 #include "skl-topology.h"
 29 #include "skl-sst-dsp.h"
 30 #include "skl-sst-ipc.h"
 31 
 32 #define HDA_MONO 1
 33 #define HDA_STEREO 2
 34 #define HDA_QUAD 4
 35 
 36 static const struct snd_pcm_hardware azx_pcm_hw = {
 37         .info =                 (SNDRV_PCM_INFO_MMAP |
 38                                  SNDRV_PCM_INFO_INTERLEAVED |
 39                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 40                                  SNDRV_PCM_INFO_MMAP_VALID |
 41                                  SNDRV_PCM_INFO_PAUSE |
 42                                  SNDRV_PCM_INFO_RESUME |
 43                                  SNDRV_PCM_INFO_SYNC_START |
 44                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 45                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 46                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 47         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
 48                                 SNDRV_PCM_FMTBIT_S32_LE |
 49                                 SNDRV_PCM_FMTBIT_S24_LE,
 50         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 51                                 SNDRV_PCM_RATE_8000,
 52         .rate_min =             8000,
 53         .rate_max =             48000,
 54         .channels_min =         1,
 55         .channels_max =         8,
 56         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 57         .period_bytes_min =     128,
 58         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 59         .periods_min =          2,
 60         .periods_max =          AZX_MAX_FRAG,
 61         .fifo_size =            0,
 62 };
 63 
 64 static inline
 65 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
 66 {
 67         return substream->runtime->private_data;
 68 }
 69 
 70 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
 71 {
 72         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 73         struct hdac_stream *hstream = hdac_stream(stream);
 74         struct hdac_bus *bus = hstream->bus;
 75 
 76         return hbus_to_ebus(bus);
 77 }
 78 
 79 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
 80                                  struct snd_pcm_substream *substream,
 81                                  size_t size)
 82 {
 83         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 84 
 85         hdac_stream(stream)->bufsize = 0;
 86         hdac_stream(stream)->period_bytes = 0;
 87         hdac_stream(stream)->format_val = 0;
 88 
 89         return snd_pcm_lib_malloc_pages(substream, size);
 90 }
 91 
 92 static int skl_substream_free_pages(struct hdac_bus *bus,
 93                                 struct snd_pcm_substream *substream)
 94 {
 95         return snd_pcm_lib_free_pages(substream);
 96 }
 97 
 98 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
 99                                  struct snd_pcm_runtime *runtime)
100 {
101         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
102 
103         /* avoid wrap-around with wall-clock */
104         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
105                                      20, 178000000);
106 }
107 
108 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
109 {
110         if ((ebus_to_hbus(ebus))->ppcap)
111                 return HDAC_EXT_STREAM_TYPE_HOST;
112         else
113                 return HDAC_EXT_STREAM_TYPE_COUPLED;
114 }
115 
116 /*
117  * check if the stream opened is marked as ignore_suspend by machine, if so
118  * then enable suspend_active refcount
119  *
120  * The count supend_active does not need lock as it is used in open/close
121  * and suspend context
122  */
123 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
124                                          struct snd_soc_dai *dai, bool enable)
125 {
126         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
127         struct snd_soc_dapm_widget *w;
128         struct skl *skl = ebus_to_skl(ebus);
129 
130         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
131                 w = dai->playback_widget;
132         else
133                 w = dai->capture_widget;
134 
135         if (w->ignore_suspend && enable)
136                 skl->supend_active++;
137         else if (w->ignore_suspend && !enable)
138                 skl->supend_active--;
139 }
140 
141 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
142 {
143         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
144         struct hdac_bus *bus = ebus_to_hbus(ebus);
145         unsigned int format_val;
146         struct hdac_stream *hstream;
147         struct hdac_ext_stream *stream;
148         int err;
149 
150         hstream = snd_hdac_get_stream(bus, params->stream,
151                                         params->host_dma_id + 1);
152         if (!hstream)
153                 return -EINVAL;
154 
155         stream = stream_to_hdac_ext_stream(hstream);
156         snd_hdac_ext_stream_decouple(ebus, stream, true);
157 
158         format_val = snd_hdac_calc_stream_format(params->s_freq,
159                         params->ch, params->format, params->host_bps, 0);
160 
161         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
162                 format_val, params->s_freq, params->ch, params->format);
163 
164         snd_hdac_stream_reset(hdac_stream(stream));
165         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
166         if (err < 0)
167                 return err;
168 
169         err = snd_hdac_stream_setup(hdac_stream(stream));
170         if (err < 0)
171                 return err;
172 
173         hdac_stream(stream)->prepared = 1;
174 
175         return 0;
176 }
177 
178 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
179 {
180         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
181         struct hdac_bus *bus = ebus_to_hbus(ebus);
182         unsigned int format_val;
183         struct hdac_stream *hstream;
184         struct hdac_ext_stream *stream;
185         struct hdac_ext_link *link;
186 
187         hstream = snd_hdac_get_stream(bus, params->stream,
188                                         params->link_dma_id + 1);
189         if (!hstream)
190                 return -EINVAL;
191 
192         stream = stream_to_hdac_ext_stream(hstream);
193         snd_hdac_ext_stream_decouple(ebus, stream, true);
194         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
195                                         params->format, params->link_bps, 0);
196 
197         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
198                 format_val, params->s_freq, params->ch, params->format);
199 
200         snd_hdac_ext_link_stream_reset(stream);
201 
202         snd_hdac_ext_link_stream_setup(stream, format_val);
203 
204         list_for_each_entry(link, &ebus->hlink_list, list) {
205                 if (link->index == params->link_index)
206                         snd_hdac_ext_link_set_stream_id(link,
207                                         hstream->stream_tag);
208         }
209 
210         stream->link_prepared = 1;
211 
212         return 0;
213 }
214 
215 static int skl_pcm_open(struct snd_pcm_substream *substream,
216                 struct snd_soc_dai *dai)
217 {
218         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
219         struct hdac_ext_stream *stream;
220         struct snd_pcm_runtime *runtime = substream->runtime;
221         struct skl_dma_params *dma_params;
222         struct skl *skl = get_skl_ctx(dai->dev);
223         struct skl_module_cfg *mconfig;
224 
225         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
226 
227         stream = snd_hdac_ext_stream_assign(ebus, substream,
228                                         skl_get_host_stream_type(ebus));
229         if (stream == NULL)
230                 return -EBUSY;
231 
232         skl_set_pcm_constrains(ebus, runtime);
233 
234         /*
235          * disable WALLCLOCK timestamps for capture streams
236          * until we figure out how to handle digital inputs
237          */
238         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
239                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
240                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
241         }
242 
243         runtime->private_data = stream;
244 
245         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
246         if (!dma_params)
247                 return -ENOMEM;
248 
249         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
250         snd_soc_dai_set_dma_data(dai, substream, dma_params);
251 
252         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
253                                  dma_params->stream_tag);
254         skl_set_suspend_active(substream, dai, true);
255         snd_pcm_set_sync(substream);
256 
257         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
258         if (!mconfig)
259                 return -EINVAL;
260 
261         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
262 
263         return 0;
264 }
265 
266 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
267                 struct snd_soc_dai *dai)
268 {
269         struct skl *skl = get_skl_ctx(dai->dev);
270         struct skl_module_cfg *mconfig;
271         int ret;
272 
273         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
274 
275         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
276 
277         /*
278          * In case of XRUN recovery or in the case when the application
279          * calls prepare another time, reset the FW pipe to clean state
280          */
281         if (mconfig &&
282                 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
283                  mconfig->pipe->state == SKL_PIPE_CREATED ||
284                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
285 
286                 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
287 
288                 if (ret < 0)
289                         return ret;
290 
291                 ret = skl_pcm_host_dma_prepare(dai->dev,
292                                         mconfig->pipe->p_params);
293                 if (ret < 0)
294                         return ret;
295         }
296 
297         return 0;
298 }
299 
300 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
301                                 struct snd_pcm_hw_params *params,
302                                 struct snd_soc_dai *dai)
303 {
304         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
305         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
306         struct snd_pcm_runtime *runtime = substream->runtime;
307         struct skl_pipe_params p_params = {0};
308         struct skl_module_cfg *m_cfg;
309         int ret, dma_id;
310 
311         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
312         ret = skl_substream_alloc_pages(ebus, substream,
313                                           params_buffer_bytes(params));
314         if (ret < 0)
315                 return ret;
316 
317         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
318                         runtime->rate, runtime->channels, runtime->format);
319 
320         dma_id = hdac_stream(stream)->stream_tag - 1;
321         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
322 
323         p_params.s_fmt = snd_pcm_format_width(params_format(params));
324         p_params.ch = params_channels(params);
325         p_params.s_freq = params_rate(params);
326         p_params.host_dma_id = dma_id;
327         p_params.stream = substream->stream;
328         p_params.format = params_format(params);
329         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
330                 p_params.host_bps = dai->driver->playback.sig_bits;
331         else
332                 p_params.host_bps = dai->driver->capture.sig_bits;
333 
334 
335         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
336         if (m_cfg)
337                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
338 
339         return 0;
340 }
341 
342 static void skl_pcm_close(struct snd_pcm_substream *substream,
343                 struct snd_soc_dai *dai)
344 {
345         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
346         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
347         struct skl_dma_params *dma_params = NULL;
348         struct skl *skl = ebus_to_skl(ebus);
349         struct skl_module_cfg *mconfig;
350 
351         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
352 
353         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
354 
355         dma_params = snd_soc_dai_get_dma_data(dai, substream);
356         /*
357          * now we should set this to NULL as we are freeing by the
358          * dma_params
359          */
360         snd_soc_dai_set_dma_data(dai, substream, NULL);
361         skl_set_suspend_active(substream, dai, false);
362 
363         /*
364          * check if close is for "Reference Pin" and set back the
365          * CGCTL.MISCBDCGE if disabled by driver
366          */
367         if (!strncmp(dai->name, "Reference Pin", 13) &&
368                         skl->skl_sst->miscbdcg_disabled) {
369                 skl->skl_sst->enable_miscbdcge(dai->dev, true);
370                 skl->skl_sst->miscbdcg_disabled = false;
371         }
372 
373         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
374         if (mconfig)
375                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
376 
377         kfree(dma_params);
378 }
379 
380 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
381                 struct snd_soc_dai *dai)
382 {
383         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
384         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
385         struct skl *skl = get_skl_ctx(dai->dev);
386         struct skl_module_cfg *mconfig;
387         int ret;
388 
389         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
390 
391         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
392 
393         if (mconfig) {
394                 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
395                 if (ret < 0)
396                         dev_err(dai->dev, "%s:Reset failed ret =%d",
397                                                 __func__, ret);
398         }
399 
400         snd_hdac_stream_cleanup(hdac_stream(stream));
401         hdac_stream(stream)->prepared = 0;
402 
403         return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
404 }
405 
406 static int skl_be_hw_params(struct snd_pcm_substream *substream,
407                                 struct snd_pcm_hw_params *params,
408                                 struct snd_soc_dai *dai)
409 {
410         struct skl_pipe_params p_params = {0};
411 
412         p_params.s_fmt = snd_pcm_format_width(params_format(params));
413         p_params.ch = params_channels(params);
414         p_params.s_freq = params_rate(params);
415         p_params.stream = substream->stream;
416 
417         return skl_tplg_be_update_params(dai, &p_params);
418 }
419 
420 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
421                 int cmd)
422 {
423         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
424         struct hdac_bus *bus = ebus_to_hbus(ebus);
425         struct hdac_ext_stream *stream;
426         int start;
427         unsigned long cookie;
428         struct hdac_stream *hstr;
429 
430         stream = get_hdac_ext_stream(substream);
431         hstr = hdac_stream(stream);
432 
433         if (!hstr->prepared)
434                 return -EPIPE;
435 
436         switch (cmd) {
437         case SNDRV_PCM_TRIGGER_START:
438         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
439         case SNDRV_PCM_TRIGGER_RESUME:
440                 start = 1;
441                 break;
442 
443         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
444         case SNDRV_PCM_TRIGGER_SUSPEND:
445         case SNDRV_PCM_TRIGGER_STOP:
446                 start = 0;
447                 break;
448 
449         default:
450                 return -EINVAL;
451         }
452 
453         spin_lock_irqsave(&bus->reg_lock, cookie);
454 
455         if (start) {
456                 snd_hdac_stream_start(hdac_stream(stream), true);
457                 snd_hdac_stream_timecounter_init(hstr, 0);
458         } else {
459                 snd_hdac_stream_stop(hdac_stream(stream));
460         }
461 
462         spin_unlock_irqrestore(&bus->reg_lock, cookie);
463 
464         return 0;
465 }
466 
467 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
468                 struct snd_soc_dai *dai)
469 {
470         struct skl *skl = get_skl_ctx(dai->dev);
471         struct skl_sst *ctx = skl->skl_sst;
472         struct skl_module_cfg *mconfig;
473         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
474         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
475         struct snd_soc_dapm_widget *w;
476         int ret;
477 
478         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
479         if (!mconfig)
480                 return -EIO;
481 
482         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
483                 w = dai->playback_widget;
484         else
485                 w = dai->capture_widget;
486 
487         switch (cmd) {
488         case SNDRV_PCM_TRIGGER_RESUME:
489                 if (!w->ignore_suspend) {
490                         /*
491                          * enable DMA Resume enable bit for the stream, set the
492                          * dpib & lpib position to resume before starting the
493                          * DMA
494                          */
495                         snd_hdac_ext_stream_drsm_enable(ebus, true,
496                                                 hdac_stream(stream)->index);
497                         snd_hdac_ext_stream_set_dpibr(ebus, stream,
498                                                         stream->lpib);
499                         snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
500                 }
501 
502         case SNDRV_PCM_TRIGGER_START:
503         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
504                 /*
505                  * Start HOST DMA and Start FE Pipe.This is to make sure that
506                  * there are no underrun/overrun in the case when the FE
507                  * pipeline is started but there is a delay in starting the
508                  * DMA channel on the host.
509                  */
510                 ret = skl_decoupled_trigger(substream, cmd);
511                 if (ret < 0)
512                         return ret;
513                 return skl_run_pipe(ctx, mconfig->pipe);
514                 break;
515 
516         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
517         case SNDRV_PCM_TRIGGER_SUSPEND:
518         case SNDRV_PCM_TRIGGER_STOP:
519                 /*
520                  * Stop FE Pipe first and stop DMA. This is to make sure that
521                  * there are no underrun/overrun in the case if there is a delay
522                  * between the two operations.
523                  */
524                 ret = skl_stop_pipe(ctx, mconfig->pipe);
525                 if (ret < 0)
526                         return ret;
527 
528                 ret = skl_decoupled_trigger(substream, cmd);
529                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
530                         /* save the dpib and lpib positions */
531                         stream->dpib = readl(ebus->bus.remap_addr +
532                                         AZX_REG_VS_SDXDPIB_XBASE +
533                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
534                                         hdac_stream(stream)->index));
535 
536                         stream->lpib = snd_hdac_stream_get_pos_lpib(
537                                                         hdac_stream(stream));
538                         snd_hdac_ext_stream_decouple(ebus, stream, false);
539                 }
540                 break;
541 
542         default:
543                 return -EINVAL;
544         }
545 
546         return 0;
547 }
548 
549 static int skl_link_hw_params(struct snd_pcm_substream *substream,
550                                 struct snd_pcm_hw_params *params,
551                                 struct snd_soc_dai *dai)
552 {
553         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
554         struct hdac_ext_stream *link_dev;
555         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
556         struct snd_soc_dai *codec_dai = rtd->codec_dai;
557         struct skl_pipe_params p_params = {0};
558         struct hdac_ext_link *link;
559         int stream_tag;
560 
561         link_dev = snd_hdac_ext_stream_assign(ebus, substream,
562                                         HDAC_EXT_STREAM_TYPE_LINK);
563         if (!link_dev)
564                 return -EBUSY;
565 
566         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
567 
568         link = snd_hdac_ext_bus_get_link(ebus, codec_dai->component->name);
569         if (!link)
570                 return -EINVAL;
571 
572         stream_tag = hdac_stream(link_dev)->stream_tag;
573 
574         /* set the stream tag in the codec dai dma params  */
575         snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
576 
577         p_params.s_fmt = snd_pcm_format_width(params_format(params));
578         p_params.ch = params_channels(params);
579         p_params.s_freq = params_rate(params);
580         p_params.stream = substream->stream;
581         p_params.link_dma_id = stream_tag - 1;
582         p_params.link_index = link->index;
583         p_params.format = params_format(params);
584 
585         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
586                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
587         else
588                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
589 
590         return skl_tplg_be_update_params(dai, &p_params);
591 }
592 
593 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
594                 struct snd_soc_dai *dai)
595 {
596         struct skl *skl = get_skl_ctx(dai->dev);
597         struct skl_module_cfg *mconfig = NULL;
598 
599         /* In case of XRUN recovery, reset the FW pipe to clean state */
600         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
601         if (mconfig && !mconfig->pipe->passthru &&
602                 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
603                 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
604 
605         return 0;
606 }
607 
608 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
609         int cmd, struct snd_soc_dai *dai)
610 {
611         struct hdac_ext_stream *link_dev =
612                                 snd_soc_dai_get_dma_data(dai, substream);
613         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
614         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
615 
616         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
617         switch (cmd) {
618         case SNDRV_PCM_TRIGGER_RESUME:
619         case SNDRV_PCM_TRIGGER_START:
620         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
621                 snd_hdac_ext_link_stream_start(link_dev);
622                 break;
623 
624         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
625         case SNDRV_PCM_TRIGGER_SUSPEND:
626         case SNDRV_PCM_TRIGGER_STOP:
627                 snd_hdac_ext_link_stream_clear(link_dev);
628                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
629                         snd_hdac_ext_stream_decouple(ebus, stream, false);
630                 break;
631 
632         default:
633                 return -EINVAL;
634         }
635         return 0;
636 }
637 
638 static int skl_link_hw_free(struct snd_pcm_substream *substream,
639                 struct snd_soc_dai *dai)
640 {
641         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
642         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
643         struct hdac_ext_stream *link_dev =
644                                 snd_soc_dai_get_dma_data(dai, substream);
645         struct hdac_ext_link *link;
646 
647         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
648 
649         link_dev->link_prepared = 0;
650 
651         link = snd_hdac_ext_bus_get_link(ebus, rtd->codec_dai->component->name);
652         if (!link)
653                 return -EINVAL;
654 
655         snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
656         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
657         return 0;
658 }
659 
660 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
661         .startup = skl_pcm_open,
662         .shutdown = skl_pcm_close,
663         .prepare = skl_pcm_prepare,
664         .hw_params = skl_pcm_hw_params,
665         .hw_free = skl_pcm_hw_free,
666         .trigger = skl_pcm_trigger,
667 };
668 
669 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
670         .hw_params = skl_be_hw_params,
671 };
672 
673 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
674         .hw_params = skl_be_hw_params,
675 };
676 
677 static const struct snd_soc_dai_ops skl_link_dai_ops = {
678         .prepare = skl_link_pcm_prepare,
679         .hw_params = skl_link_hw_params,
680         .hw_free = skl_link_hw_free,
681         .trigger = skl_link_pcm_trigger,
682 };
683 
684 static struct snd_soc_dai_driver skl_fe_dai[] = {
685 {
686         .name = "System Pin",
687         .ops = &skl_pcm_dai_ops,
688         .playback = {
689                 .stream_name = "System Playback",
690                 .channels_min = HDA_MONO,
691                 .channels_max = HDA_STEREO,
692                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
693                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
694                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
695                 .sig_bits = 32,
696         },
697         .capture = {
698                 .stream_name = "System Capture",
699                 .channels_min = HDA_MONO,
700                 .channels_max = HDA_STEREO,
701                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
702                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
703                 .sig_bits = 32,
704         },
705 },
706 {
707         .name = "System Pin2",
708         .ops = &skl_pcm_dai_ops,
709         .playback = {
710                 .stream_name = "Headset Playback",
711                 .channels_min = HDA_MONO,
712                 .channels_max = HDA_STEREO,
713                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
714                         SNDRV_PCM_RATE_8000,
715                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
716                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
717         },
718 },
719 {
720         .name = "Echoref Pin",
721         .ops = &skl_pcm_dai_ops,
722         .capture = {
723                 .stream_name = "Echoreference Capture",
724                 .channels_min = HDA_STEREO,
725                 .channels_max = HDA_STEREO,
726                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
727                         SNDRV_PCM_RATE_8000,
728                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
729                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
730         },
731 },
732 {
733         .name = "Reference Pin",
734         .ops = &skl_pcm_dai_ops,
735         .capture = {
736                 .stream_name = "Reference Capture",
737                 .channels_min = HDA_MONO,
738                 .channels_max = HDA_QUAD,
739                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
740                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
741                 .sig_bits = 32,
742         },
743 },
744 {
745         .name = "Deepbuffer Pin",
746         .ops = &skl_pcm_dai_ops,
747         .playback = {
748                 .stream_name = "Deepbuffer Playback",
749                 .channels_min = HDA_STEREO,
750                 .channels_max = HDA_STEREO,
751                 .rates = SNDRV_PCM_RATE_48000,
752                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
753                 .sig_bits = 32,
754         },
755 },
756 {
757         .name = "LowLatency Pin",
758         .ops = &skl_pcm_dai_ops,
759         .playback = {
760                 .stream_name = "Low Latency Playback",
761                 .channels_min = HDA_STEREO,
762                 .channels_max = HDA_STEREO,
763                 .rates = SNDRV_PCM_RATE_48000,
764                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
765                 .sig_bits = 32,
766         },
767 },
768 {
769         .name = "DMIC Pin",
770         .ops = &skl_pcm_dai_ops,
771         .capture = {
772                 .stream_name = "DMIC Capture",
773                 .channels_min = HDA_MONO,
774                 .channels_max = HDA_QUAD,
775                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
776                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
777                 .sig_bits = 32,
778         },
779 },
780 {
781         .name = "HDMI1 Pin",
782         .ops = &skl_pcm_dai_ops,
783         .playback = {
784                 .stream_name = "HDMI1 Playback",
785                 .channels_min = HDA_STEREO,
786                 .channels_max = 8,
787                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
788                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
789                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
790                         SNDRV_PCM_RATE_192000,
791                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
792                         SNDRV_PCM_FMTBIT_S32_LE,
793                 .sig_bits = 32,
794         },
795 },
796 {
797         .name = "HDMI2 Pin",
798         .ops = &skl_pcm_dai_ops,
799         .playback = {
800                 .stream_name = "HDMI2 Playback",
801                 .channels_min = HDA_STEREO,
802                 .channels_max = 8,
803                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
804                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
805                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
806                         SNDRV_PCM_RATE_192000,
807                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
808                         SNDRV_PCM_FMTBIT_S32_LE,
809                 .sig_bits = 32,
810         },
811 },
812 {
813         .name = "HDMI3 Pin",
814         .ops = &skl_pcm_dai_ops,
815         .playback = {
816                 .stream_name = "HDMI3 Playback",
817                 .channels_min = HDA_STEREO,
818                 .channels_max = 8,
819                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
820                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
821                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
822                         SNDRV_PCM_RATE_192000,
823                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
824                         SNDRV_PCM_FMTBIT_S32_LE,
825                 .sig_bits = 32,
826         },
827 },
828 };
829 
830 /* BE CPU  Dais */
831 static struct snd_soc_dai_driver skl_platform_dai[] = {
832 {
833         .name = "SSP0 Pin",
834         .ops = &skl_be_ssp_dai_ops,
835         .playback = {
836                 .stream_name = "ssp0 Tx",
837                 .channels_min = HDA_STEREO,
838                 .channels_max = HDA_STEREO,
839                 .rates = SNDRV_PCM_RATE_48000,
840                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
841         },
842         .capture = {
843                 .stream_name = "ssp0 Rx",
844                 .channels_min = HDA_STEREO,
845                 .channels_max = HDA_STEREO,
846                 .rates = SNDRV_PCM_RATE_48000,
847                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
848         },
849 },
850 {
851         .name = "SSP1 Pin",
852         .ops = &skl_be_ssp_dai_ops,
853         .playback = {
854                 .stream_name = "ssp1 Tx",
855                 .channels_min = HDA_STEREO,
856                 .channels_max = HDA_STEREO,
857                 .rates = SNDRV_PCM_RATE_48000,
858                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
859         },
860         .capture = {
861                 .stream_name = "ssp1 Rx",
862                 .channels_min = HDA_STEREO,
863                 .channels_max = HDA_STEREO,
864                 .rates = SNDRV_PCM_RATE_48000,
865                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
866         },
867 },
868 {
869         .name = "SSP2 Pin",
870         .ops = &skl_be_ssp_dai_ops,
871         .playback = {
872                 .stream_name = "ssp2 Tx",
873                 .channels_min = HDA_STEREO,
874                 .channels_max = HDA_STEREO,
875                 .rates = SNDRV_PCM_RATE_48000,
876                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
877         },
878         .capture = {
879                 .stream_name = "ssp2 Rx",
880                 .channels_min = HDA_STEREO,
881                 .channels_max = HDA_STEREO,
882                 .rates = SNDRV_PCM_RATE_48000,
883                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
884         },
885 },
886 {
887         .name = "SSP3 Pin",
888         .ops = &skl_be_ssp_dai_ops,
889         .playback = {
890                 .stream_name = "ssp3 Tx",
891                 .channels_min = HDA_STEREO,
892                 .channels_max = HDA_STEREO,
893                 .rates = SNDRV_PCM_RATE_48000,
894                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
895         },
896         .capture = {
897                 .stream_name = "ssp3 Rx",
898                 .channels_min = HDA_STEREO,
899                 .channels_max = HDA_STEREO,
900                 .rates = SNDRV_PCM_RATE_48000,
901                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
902         },
903 },
904 {
905         .name = "SSP4 Pin",
906         .ops = &skl_be_ssp_dai_ops,
907         .playback = {
908                 .stream_name = "ssp4 Tx",
909                 .channels_min = HDA_STEREO,
910                 .channels_max = HDA_STEREO,
911                 .rates = SNDRV_PCM_RATE_48000,
912                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
913         },
914         .capture = {
915                 .stream_name = "ssp4 Rx",
916                 .channels_min = HDA_STEREO,
917                 .channels_max = HDA_STEREO,
918                 .rates = SNDRV_PCM_RATE_48000,
919                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
920         },
921 },
922 {
923         .name = "SSP5 Pin",
924         .ops = &skl_be_ssp_dai_ops,
925         .playback = {
926                 .stream_name = "ssp5 Tx",
927                 .channels_min = HDA_STEREO,
928                 .channels_max = HDA_STEREO,
929                 .rates = SNDRV_PCM_RATE_48000,
930                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
931         },
932         .capture = {
933                 .stream_name = "ssp5 Rx",
934                 .channels_min = HDA_STEREO,
935                 .channels_max = HDA_STEREO,
936                 .rates = SNDRV_PCM_RATE_48000,
937                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
938         },
939 },
940 {
941         .name = "iDisp1 Pin",
942         .ops = &skl_link_dai_ops,
943         .playback = {
944                 .stream_name = "iDisp1 Tx",
945                 .channels_min = HDA_STEREO,
946                 .channels_max = 8,
947                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
948                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
949                         SNDRV_PCM_FMTBIT_S24_LE,
950         },
951 },
952 {
953         .name = "iDisp2 Pin",
954         .ops = &skl_link_dai_ops,
955         .playback = {
956                 .stream_name = "iDisp2 Tx",
957                 .channels_min = HDA_STEREO,
958                 .channels_max = 8,
959                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
960                         SNDRV_PCM_RATE_48000,
961                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
962                         SNDRV_PCM_FMTBIT_S24_LE,
963         },
964 },
965 {
966         .name = "iDisp3 Pin",
967         .ops = &skl_link_dai_ops,
968         .playback = {
969                 .stream_name = "iDisp3 Tx",
970                 .channels_min = HDA_STEREO,
971                 .channels_max = 8,
972                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
973                         SNDRV_PCM_RATE_48000,
974                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
975                         SNDRV_PCM_FMTBIT_S24_LE,
976         },
977 },
978 {
979         .name = "DMIC01 Pin",
980         .ops = &skl_dmic_dai_ops,
981         .capture = {
982                 .stream_name = "DMIC01 Rx",
983                 .channels_min = HDA_MONO,
984                 .channels_max = HDA_QUAD,
985                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
986                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
987         },
988 },
989 {
990         .name = "DMIC16k Pin",
991         .ops = &skl_dmic_dai_ops,
992         .capture = {
993                 .stream_name = "DMIC16k Rx",
994                 .channels_min = HDA_MONO,
995                 .channels_max = HDA_QUAD,
996                 .rates = SNDRV_PCM_RATE_16000,
997                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
998         },
999 },
1000 {
1001         .name = "HD-Codec Pin",
1002         .ops = &skl_link_dai_ops,
1003         .playback = {
1004                 .stream_name = "HD-Codec Tx",
1005                 .channels_min = HDA_STEREO,
1006                 .channels_max = HDA_STEREO,
1007                 .rates = SNDRV_PCM_RATE_48000,
1008                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1009         },
1010         .capture = {
1011                 .stream_name = "HD-Codec Rx",
1012                 .channels_min = HDA_STEREO,
1013                 .channels_max = HDA_STEREO,
1014                 .rates = SNDRV_PCM_RATE_48000,
1015                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1016         },
1017 },
1018 };
1019 
1020 int skl_dai_load(struct snd_soc_component *cmp,
1021                  struct snd_soc_dai_driver *pcm_dai)
1022 {
1023         pcm_dai->ops = &skl_pcm_dai_ops;
1024 
1025         return 0;
1026 }
1027 
1028 static int skl_platform_open(struct snd_pcm_substream *substream)
1029 {
1030         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1031         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1032 
1033         dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
1034                                         dai_link->cpu_dai_name);
1035 
1036         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1037 
1038         return 0;
1039 }
1040 
1041 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1042                                         int cmd)
1043 {
1044         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1045         struct hdac_bus *bus = ebus_to_hbus(ebus);
1046         struct hdac_ext_stream *stream;
1047         struct snd_pcm_substream *s;
1048         bool start;
1049         int sbits = 0;
1050         unsigned long cookie;
1051         struct hdac_stream *hstr;
1052 
1053         stream = get_hdac_ext_stream(substream);
1054         hstr = hdac_stream(stream);
1055 
1056         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1057 
1058         if (!hstr->prepared)
1059                 return -EPIPE;
1060 
1061         switch (cmd) {
1062         case SNDRV_PCM_TRIGGER_START:
1063         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1064         case SNDRV_PCM_TRIGGER_RESUME:
1065                 start = true;
1066                 break;
1067 
1068         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1069         case SNDRV_PCM_TRIGGER_SUSPEND:
1070         case SNDRV_PCM_TRIGGER_STOP:
1071                 start = false;
1072                 break;
1073 
1074         default:
1075                 return -EINVAL;
1076         }
1077 
1078         snd_pcm_group_for_each_entry(s, substream) {
1079                 if (s->pcm->card != substream->pcm->card)
1080                         continue;
1081                 stream = get_hdac_ext_stream(s);
1082                 sbits |= 1 << hdac_stream(stream)->index;
1083                 snd_pcm_trigger_done(s, substream);
1084         }
1085 
1086         spin_lock_irqsave(&bus->reg_lock, cookie);
1087 
1088         /* first, set SYNC bits of corresponding streams */
1089         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1090 
1091         snd_pcm_group_for_each_entry(s, substream) {
1092                 if (s->pcm->card != substream->pcm->card)
1093                         continue;
1094                 stream = get_hdac_ext_stream(s);
1095                 if (start)
1096                         snd_hdac_stream_start(hdac_stream(stream), true);
1097                 else
1098                         snd_hdac_stream_stop(hdac_stream(stream));
1099         }
1100         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1101 
1102         snd_hdac_stream_sync(hstr, start, sbits);
1103 
1104         spin_lock_irqsave(&bus->reg_lock, cookie);
1105 
1106         /* reset SYNC bits */
1107         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1108         if (start)
1109                 snd_hdac_stream_timecounter_init(hstr, sbits);
1110         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1111 
1112         return 0;
1113 }
1114 
1115 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1116                                         int cmd)
1117 {
1118         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1119 
1120         if (!(ebus_to_hbus(ebus))->ppcap)
1121                 return skl_coupled_trigger(substream, cmd);
1122 
1123         return 0;
1124 }
1125 
1126 static snd_pcm_uframes_t skl_platform_pcm_pointer
1127                         (struct snd_pcm_substream *substream)
1128 {
1129         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1130         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1131         unsigned int pos;
1132 
1133         /*
1134          * Use DPIB for Playback stream as the periodic DMA Position-in-
1135          * Buffer Writes may be scheduled at the same time or later than
1136          * the MSI and does not guarantee to reflect the Position of the
1137          * last buffer that was transferred. Whereas DPIB register in
1138          * HAD space reflects the actual data that is transferred.
1139          * Use the position buffer for capture, as DPIB write gets
1140          * completed earlier than the actual data written to the DDR.
1141          *
1142          * For capture stream following workaround is required to fix the
1143          * incorrect position reporting.
1144          *
1145          * 1. Wait for 20us before reading the DMA position in buffer once
1146          * the interrupt is generated for stream completion as update happens
1147          * on the HDA frame boundary i.e. 20.833uSec.
1148          * 2. Read DPIB register to flush the DMA position value. This dummy
1149          * read is required to flush DMA position value.
1150          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1151          * or greater than period boundary.
1152          */
1153 
1154         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1155                 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1156                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1157                                 hdac_stream(hstream)->index));
1158         } else {
1159                 udelay(20);
1160                 readl(ebus->bus.remap_addr +
1161                                 AZX_REG_VS_SDXDPIB_XBASE +
1162                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1163                                  hdac_stream(hstream)->index));
1164                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1165         }
1166 
1167         if (pos >= hdac_stream(hstream)->bufsize)
1168                 pos = 0;
1169 
1170         return bytes_to_frames(substream->runtime, pos);
1171 }
1172 
1173 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1174                                 u64 nsec)
1175 {
1176         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1177         struct snd_soc_dai *codec_dai = rtd->codec_dai;
1178         u64 codec_frames, codec_nsecs;
1179 
1180         if (!codec_dai->driver->ops->delay)
1181                 return nsec;
1182 
1183         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1184         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1185                               substream->runtime->rate);
1186 
1187         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1188                 return nsec + codec_nsecs;
1189 
1190         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1191 }
1192 
1193 static int skl_get_time_info(struct snd_pcm_substream *substream,
1194                         struct timespec *system_ts, struct timespec *audio_ts,
1195                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1196                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1197 {
1198         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1199         struct hdac_stream *hstr = hdac_stream(sstream);
1200         u64 nsec;
1201 
1202         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1203                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1204 
1205                 snd_pcm_gettime(substream->runtime, system_ts);
1206 
1207                 nsec = timecounter_read(&hstr->tc);
1208                 nsec = div_u64(nsec, 3); /* can be optimized */
1209                 if (audio_tstamp_config->report_delay)
1210                         nsec = skl_adjust_codec_delay(substream, nsec);
1211 
1212                 *audio_ts = ns_to_timespec(nsec);
1213 
1214                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1215                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1216                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1217 
1218         } else {
1219                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1220         }
1221 
1222         return 0;
1223 }
1224 
1225 static const struct snd_pcm_ops skl_platform_ops = {
1226         .open = skl_platform_open,
1227         .ioctl = snd_pcm_lib_ioctl,
1228         .trigger = skl_platform_pcm_trigger,
1229         .pointer = skl_platform_pcm_pointer,
1230         .get_time_info =  skl_get_time_info,
1231         .mmap = snd_pcm_lib_default_mmap,
1232         .page = snd_pcm_sgbuf_ops_page,
1233 };
1234 
1235 static void skl_pcm_free(struct snd_pcm *pcm)
1236 {
1237         snd_pcm_lib_preallocate_free_for_all(pcm);
1238 }
1239 
1240 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1241 
1242 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1243 {
1244         struct snd_soc_dai *dai = rtd->cpu_dai;
1245         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1246         struct snd_pcm *pcm = rtd->pcm;
1247         unsigned int size;
1248         int retval = 0;
1249         struct skl *skl = ebus_to_skl(ebus);
1250 
1251         if (dai->driver->playback.channels_min ||
1252                 dai->driver->capture.channels_min) {
1253                 /* buffer pre-allocation */
1254                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1255                 if (size > MAX_PREALLOC_SIZE)
1256                         size = MAX_PREALLOC_SIZE;
1257                 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1258                                                 SNDRV_DMA_TYPE_DEV_SG,
1259                                                 snd_dma_pci_data(skl->pci),
1260                                                 size, MAX_PREALLOC_SIZE);
1261                 if (retval) {
1262                         dev_err(dai->dev, "dma buffer allocation fail\n");
1263                         return retval;
1264                 }
1265         }
1266 
1267         return retval;
1268 }
1269 
1270 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig)
1271 {
1272         struct skl_sst *ctx = skl->skl_sst;
1273         struct skl_module_inst_id *pin_id;
1274         uuid_le *uuid_mod, *uuid_tplg;
1275         struct skl_module *skl_module;
1276         struct uuid_module *module;
1277         int i, ret = -EIO;
1278 
1279         uuid_mod = (uuid_le *)mconfig->guid;
1280 
1281         if (list_empty(&ctx->uuid_list)) {
1282                 dev_err(ctx->dev, "Module list is empty\n");
1283                 return -EIO;
1284         }
1285 
1286         list_for_each_entry(module, &ctx->uuid_list, list) {
1287                 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) {
1288                         mconfig->id.module_id = module->id;
1289                         if (mconfig->module)
1290                                 mconfig->module->loadable = module->is_loadable;
1291                         ret = 0;
1292                         break;
1293                 }
1294         }
1295 
1296         if (ret)
1297                 return ret;
1298 
1299         uuid_mod = &module->uuid;
1300         ret = -EIO;
1301         for (i = 0; i < skl->nr_modules; i++) {
1302                 skl_module = skl->modules[i];
1303                 uuid_tplg = &skl_module->uuid;
1304                 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) {
1305                         mconfig->module = skl_module;
1306                         ret = 0;
1307                         break;
1308                 }
1309         }
1310         if (skl->nr_modules && ret)
1311                 return ret;
1312 
1313         list_for_each_entry(module, &ctx->uuid_list, list) {
1314                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1315                         pin_id = &mconfig->m_in_pin[i].id;
1316                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1317                                 pin_id->module_id = module->id;
1318                 }
1319 
1320                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1321                         pin_id = &mconfig->m_out_pin[i].id;
1322                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1323                                 pin_id->module_id = module->id;
1324                 }
1325         }
1326 
1327         return 0;
1328 }
1329 
1330 static int skl_populate_modules(struct skl *skl)
1331 {
1332         struct skl_pipeline *p;
1333         struct skl_pipe_module *m;
1334         struct snd_soc_dapm_widget *w;
1335         struct skl_module_cfg *mconfig;
1336         int ret = 0;
1337 
1338         list_for_each_entry(p, &skl->ppl_list, node) {
1339                 list_for_each_entry(m, &p->pipe->w_list, node) {
1340                         w = m->w;
1341                         mconfig = w->priv;
1342 
1343                         ret = skl_get_module_info(skl, mconfig);
1344                         if (ret < 0) {
1345                                 dev_err(skl->skl_sst->dev,
1346                                         "query module info failed\n");
1347                                 return ret;
1348                         }
1349 
1350                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1351                 }
1352         }
1353 
1354         return ret;
1355 }
1356 
1357 static int skl_platform_soc_probe(struct snd_soc_component *component)
1358 {
1359         struct hdac_ext_bus *ebus = dev_get_drvdata(component->dev);
1360         struct skl *skl = ebus_to_skl(ebus);
1361         const struct skl_dsp_ops *ops;
1362         int ret;
1363 
1364         pm_runtime_get_sync(component->dev);
1365         if ((ebus_to_hbus(ebus))->ppcap) {
1366                 skl->component = component;
1367 
1368                 /* init debugfs */
1369                 skl->debugfs = skl_debugfs_init(skl);
1370 
1371                 ret = skl_tplg_init(component, ebus);
1372                 if (ret < 0) {
1373                         dev_err(component->dev, "Failed to init topology!\n");
1374                         return ret;
1375                 }
1376 
1377                 /* load the firmwares, since all is set */
1378                 ops = skl_get_dsp_ops(skl->pci->device);
1379                 if (!ops)
1380                         return -EIO;
1381 
1382                 if (skl->skl_sst->is_first_boot == false) {
1383                         dev_err(component->dev, "DSP reports first boot done!!!\n");
1384                         return -EIO;
1385                 }
1386 
1387                 /*
1388                  * Disable dynamic clock and power gating during firmware
1389                  * and library download
1390                  */
1391                 skl->skl_sst->enable_miscbdcge(component->dev, false);
1392                 skl->skl_sst->clock_power_gating(component->dev, false);
1393 
1394                 ret = ops->init_fw(component->dev, skl->skl_sst);
1395                 skl->skl_sst->enable_miscbdcge(component->dev, true);
1396                 skl->skl_sst->clock_power_gating(component->dev, true);
1397                 if (ret < 0) {
1398                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1399                         return ret;
1400                 }
1401                 skl_populate_modules(skl);
1402                 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1403                 skl_dsp_enable_notification(skl->skl_sst, false);
1404 
1405                 if (skl->cfg.astate_cfg != NULL) {
1406                         skl_dsp_set_astate_cfg(skl->skl_sst,
1407                                         skl->cfg.astate_cfg->count,
1408                                         skl->cfg.astate_cfg);
1409                 }
1410         }
1411         pm_runtime_mark_last_busy(component->dev);
1412         pm_runtime_put_autosuspend(component->dev);
1413 
1414         return 0;
1415 }
1416 
1417 static const struct snd_soc_component_driver skl_component  = {
1418         .name           = "pcm",
1419         .probe          = skl_platform_soc_probe,
1420         .ops            = &skl_platform_ops,
1421         .pcm_new        = skl_pcm_new,
1422         .pcm_free       = skl_pcm_free,
1423 };
1424 
1425 int skl_platform_register(struct device *dev)
1426 {
1427         int ret;
1428         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1429         struct skl *skl = ebus_to_skl(ebus);
1430         struct snd_soc_dai_driver *dais;
1431         int num_dais = ARRAY_SIZE(skl_platform_dai);
1432 
1433         INIT_LIST_HEAD(&skl->ppl_list);
1434         INIT_LIST_HEAD(&skl->bind_list);
1435 
1436         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1437                             GFP_KERNEL);
1438         if (!skl->dais) {
1439                 ret = -ENOMEM;
1440                 goto err;
1441         }
1442 
1443         if (!skl->use_tplg_pcm) {
1444                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1445                                 sizeof(skl_platform_dai), GFP_KERNEL);
1446                 if (!dais) {
1447                         ret = -ENOMEM;
1448                         goto err;
1449                 }
1450 
1451                 skl->dais = dais;
1452                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1453                        sizeof(skl_fe_dai));
1454                 num_dais += ARRAY_SIZE(skl_fe_dai);
1455         }
1456 
1457         ret = devm_snd_soc_register_component(dev, &skl_component,
1458                                          skl->dais, num_dais);
1459         if (ret)
1460                 dev_err(dev, "soc component registration failed %d\n", ret);
1461 err:
1462         return ret;
1463 }
1464 
1465 int skl_platform_unregister(struct device *dev)
1466 {
1467         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1468         struct skl *skl = ebus_to_skl(ebus);
1469         struct skl_module_deferred_bind *modules, *tmp;
1470 
1471         if (!list_empty(&skl->bind_list)) {
1472                 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1473                         list_del(&modules->node);
1474                         kfree(modules);
1475                 }
1476         }
1477 
1478         kfree(skl->dais);
1479 
1480         return 0;
1481 }
1482 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp