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Linux/sound/soc/intel/skylake/skl-sst-cldma.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * skl-sst-cldma.c - Code Loader DMA handler
  4  *
  5  * Copyright (C) 2015, Intel Corporation.
  6  * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
  7  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  8  */
  9 
 10 #include <linux/device.h>
 11 #include <linux/mm.h>
 12 #include <linux/delay.h>
 13 #include "../common/sst-dsp.h"
 14 #include "../common/sst-dsp-priv.h"
 15 
 16 static void skl_cldma_int_enable(struct sst_dsp *ctx)
 17 {
 18         sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
 19                                 SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
 20 }
 21 
 22 void skl_cldma_int_disable(struct sst_dsp *ctx)
 23 {
 24         sst_dsp_shim_update_bits_unlocked(ctx,
 25                         SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
 26 }
 27 
 28 static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
 29 {
 30         unsigned char val;
 31         int timeout;
 32 
 33         sst_dsp_shim_update_bits_unlocked(ctx,
 34                         SKL_ADSP_REG_CL_SD_CTL,
 35                         CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
 36 
 37         udelay(3);
 38         timeout = 300;
 39         do {
 40                 /* waiting for hardware to report that the stream Run bit set */
 41                 val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
 42                         CL_SD_CTL_RUN_MASK;
 43                 if (enable && val)
 44                         break;
 45                 else if (!enable && !val)
 46                         break;
 47                 udelay(3);
 48         } while (--timeout);
 49 
 50         if (timeout == 0)
 51                 dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
 52 }
 53 
 54 static void skl_cldma_stream_clear(struct sst_dsp  *ctx)
 55 {
 56         /* make sure Run bit is cleared before setting stream register */
 57         skl_cldma_stream_run(ctx, 0);
 58 
 59         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
 60                                 CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
 61         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
 62                                 CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
 63         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
 64                                 CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
 65         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
 66                                 CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
 67 
 68         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
 69         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
 70 
 71         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
 72         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
 73 }
 74 
 75 /* Code loader helper APIs */
 76 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 77                 struct snd_dma_buffer *dmab_data,
 78                 __le32 **bdlp, int size, int with_ioc)
 79 {
 80         __le32 *bdl = *bdlp;
 81 
 82         ctx->cl_dev.frags = 0;
 83         while (size > 0) {
 84                 phys_addr_t addr = virt_to_phys(dmab_data->area +
 85                                 (ctx->cl_dev.frags * ctx->cl_dev.bufsize));
 86 
 87                 bdl[0] = cpu_to_le32(lower_32_bits(addr));
 88                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 89 
 90                 bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
 91 
 92                 size -= ctx->cl_dev.bufsize;
 93                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 94 
 95                 bdl += 4;
 96                 ctx->cl_dev.frags++;
 97         }
 98 }
 99 
100 /*
101  * Setup controller
102  * Configure the registers to update the dma buffer address and
103  * enable interrupts.
104  * Note: Using the channel 1 for transfer
105  */
106 static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
107                 struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
108                 u32 count)
109 {
110         skl_cldma_stream_clear(ctx);
111         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
112                         CL_SD_BDLPLBA(dmab_bdl->addr));
113         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
114                         CL_SD_BDLPUBA(dmab_bdl->addr));
115 
116         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
117         sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
118         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
119                         CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
120         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
121                         CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
122         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
123                         CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
124         sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
125                         CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
126 }
127 
128 static void skl_cldma_setup_spb(struct sst_dsp  *ctx,
129                 unsigned int size, bool enable)
130 {
131         if (enable)
132                 sst_dsp_shim_update_bits_unlocked(ctx,
133                                 SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
134                                 CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
135                                 CL_SPBFIFO_SPBFCCTL_SPIBE(1));
136 
137         sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
138 }
139 
140 static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
141 {
142         sst_dsp_shim_update_bits_unlocked(ctx,
143                         SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
144                         CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
145                         CL_SPBFIFO_SPBFCCTL_SPIBE(0));
146 
147         sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
148 }
149 
150 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
151 {
152         skl_cldma_cleanup_spb(ctx);
153         skl_cldma_stream_clear(ctx);
154 
155         ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
156         ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
157 }
158 
159 int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
160 {
161         int ret = 0;
162 
163         if (!wait_event_timeout(ctx->cl_dev.wait_queue,
164                                 ctx->cl_dev.wait_condition,
165                                 msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
166                 dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
167                 ret = -EIO;
168                 goto cleanup;
169         }
170 
171         dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
172         if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
173                 dev_err(ctx->dev, "%s: DMA Error\n", __func__);
174                 ret = -EIO;
175         }
176 
177 cleanup:
178         ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
179         return ret;
180 }
181 
182 static void skl_cldma_stop(struct sst_dsp *ctx)
183 {
184         skl_cldma_stream_run(ctx, false);
185 }
186 
187 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
188                 const void *curr_pos, bool intr_enable, bool trigger)
189 {
190         dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
191         dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
192                         ctx->cl_dev.dma_buffer_offset, trigger);
193         dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
194 
195         /*
196          * Check if the size exceeds buffer boundary. If it exceeds
197          * max_buffer size, then copy till buffer size and then copy
198          * remaining buffer from the start of ring buffer.
199          */
200         if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
201                 unsigned int size_b = ctx->cl_dev.bufsize -
202                                         ctx->cl_dev.dma_buffer_offset;
203                 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
204                         curr_pos, size_b);
205                 size -= size_b;
206                 curr_pos += size_b;
207                 ctx->cl_dev.dma_buffer_offset = 0;
208         }
209 
210         memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
211                         curr_pos, size);
212 
213         if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
214                 ctx->cl_dev.dma_buffer_offset = 0;
215         else
216                 ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
217 
218         ctx->cl_dev.wait_condition = false;
219 
220         if (intr_enable)
221                 skl_cldma_int_enable(ctx);
222 
223         ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
224         if (trigger)
225                 ctx->cl_dev.ops.cl_trigger(ctx, true);
226 }
227 
228 /*
229  * The CL dma doesn't have any way to update the transfer status until a BDL
230  * buffer is fully transferred
231  *
232  * So Copying is divided in two parts.
233  * 1. Interrupt on buffer done where the size to be transferred is more than
234  *    ring buffer size.
235  * 2. Polling on fw register to identify if data left to transferred doesn't
236  *    fill the ring buffer. Caller takes care of polling the required status
237  *    register to identify the transfer status.
238  * 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
239  *    bytes_left is 0.
240  *    if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
241  *    the first chunk return the no of bytes_left to be copied.
242  */
243 static int
244 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
245                         u32 total_size, bool wait)
246 {
247         int ret = 0;
248         bool start = true;
249         unsigned int excess_bytes;
250         u32 size;
251         unsigned int bytes_left = total_size;
252         const void *curr_pos = bin;
253 
254         if (total_size <= 0)
255                 return -EINVAL;
256 
257         dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
258 
259         while (bytes_left) {
260                 if (bytes_left > ctx->cl_dev.bufsize) {
261 
262                         /*
263                          * dma transfers only till the write pointer as
264                          * updated in spib
265                          */
266                         if (ctx->cl_dev.curr_spib_pos == 0)
267                                 ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
268 
269                         size = ctx->cl_dev.bufsize;
270                         skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
271 
272                         if (wait) {
273                                 start = false;
274                                 ret = skl_cldma_wait_interruptible(ctx);
275                                 if (ret < 0) {
276                                         skl_cldma_stop(ctx);
277                                         return ret;
278                                 }
279                         }
280                 } else {
281                         skl_cldma_int_disable(ctx);
282 
283                         if ((ctx->cl_dev.curr_spib_pos + bytes_left)
284                                                         <= ctx->cl_dev.bufsize) {
285                                 ctx->cl_dev.curr_spib_pos += bytes_left;
286                         } else {
287                                 excess_bytes = bytes_left -
288                                         (ctx->cl_dev.bufsize -
289                                         ctx->cl_dev.curr_spib_pos);
290                                 ctx->cl_dev.curr_spib_pos = excess_bytes;
291                         }
292 
293                         size = bytes_left;
294                         skl_cldma_fill_buffer(ctx, size,
295                                         curr_pos, false, start);
296                 }
297                 bytes_left -= size;
298                 curr_pos = curr_pos + size;
299                 if (!wait)
300                         return bytes_left;
301         }
302 
303         return bytes_left;
304 }
305 
306 void skl_cldma_process_intr(struct sst_dsp *ctx)
307 {
308         u8 cl_dma_intr_status;
309 
310         cl_dma_intr_status =
311                 sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
312 
313         if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
314                 ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
315         else
316                 ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
317 
318         ctx->cl_dev.wait_condition = true;
319         wake_up(&ctx->cl_dev.wait_queue);
320 }
321 
322 int skl_cldma_prepare(struct sst_dsp *ctx)
323 {
324         int ret;
325         __le32 *bdl;
326 
327         ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
328 
329         /* Allocate cl ops */
330         ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
331         ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
332         ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
333         ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
334         ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
335         ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
336         ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
337         ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
338 
339         /* Allocate buffer*/
340         ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
341                         &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
342         if (ret < 0) {
343                 dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
344                 return ret;
345         }
346         /* Setup Code loader BDL */
347         ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
348                         &ctx->cl_dev.dmab_bdl, PAGE_SIZE);
349         if (ret < 0) {
350                 dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
351                 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
352                 return ret;
353         }
354         bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
355 
356         /* Allocate BDLs */
357         ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
358                         &bdl, ctx->cl_dev.bufsize, 1);
359         ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
360                         ctx->cl_dev.bufsize, ctx->cl_dev.frags);
361 
362         ctx->cl_dev.curr_spib_pos = 0;
363         ctx->cl_dev.dma_buffer_offset = 0;
364         init_waitqueue_head(&ctx->cl_dev.wait_queue);
365 
366         return ret;
367 }
368 

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