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Linux/sound/soc/intel/skylake/skl.h

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  1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*
  3  *  skl.h - HD Audio skylake defintions.
  4  *
  5  *  Copyright (C) 2015 Intel Corp
  6  *  Author: Jeeja KP <jeeja.kp@intel.com>
  7  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  8  *
  9  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 10  */
 11 
 12 #ifndef __SOUND_SOC_SKL_H
 13 #define __SOUND_SOC_SKL_H
 14 
 15 #include <sound/hda_register.h>
 16 #include <sound/hdaudio_ext.h>
 17 #include <sound/hda_codec.h>
 18 #include <sound/soc.h>
 19 #include "skl-ssp-clk.h"
 20 #include "skl-sst-ipc.h"
 21 
 22 #define SKL_SUSPEND_DELAY 2000
 23 
 24 #define SKL_MAX_ASTATE_CFG              3
 25 
 26 #define AZX_PCIREG_PGCTL                0x44
 27 #define AZX_PGCTL_LSRMD_MASK            (1 << 4)
 28 #define AZX_PGCTL_ADSPPGD               BIT(2)
 29 #define AZX_PCIREG_CGCTL                0x48
 30 #define AZX_CGCTL_MISCBDCGE_MASK        (1 << 6)
 31 #define AZX_CGCTL_ADSPDCGE              BIT(1)
 32 /* D0I3C Register fields */
 33 #define AZX_REG_VS_D0I3C_CIP      0x1 /* Command in progress */
 34 #define AZX_REG_VS_D0I3C_I3       0x4 /* D0i3 enable */
 35 #define SKL_MAX_DMACTRL_CFG     18
 36 #define DMA_CLK_CONTROLS        1
 37 #define DMA_TRANSMITION_START   2
 38 #define DMA_TRANSMITION_STOP    3
 39 
 40 #define AZX_VS_EM2_DUM                  BIT(23)
 41 #define AZX_REG_VS_EM2_L1SEN            BIT(13)
 42 
 43 struct skl_debug;
 44 
 45 struct skl_astate_param {
 46         u32 kcps;
 47         u32 clk_src;
 48 };
 49 
 50 struct skl_astate_config {
 51         u32 count;
 52         struct skl_astate_param astate_table[];
 53 };
 54 
 55 struct skl_fw_config {
 56         struct skl_astate_config *astate_cfg;
 57 };
 58 
 59 struct skl_dev {
 60         struct hda_bus hbus;
 61         struct pci_dev *pci;
 62 
 63         unsigned int init_done:1; /* delayed init status */
 64         struct platform_device *dmic_dev;
 65         struct platform_device *i2s_dev;
 66         struct platform_device *clk_dev;
 67         struct snd_soc_component *component;
 68         struct snd_soc_dai_driver *dais;
 69 
 70         struct nhlt_acpi_table *nhlt; /* nhlt ptr */
 71 
 72         struct list_head ppl_list;
 73         struct list_head bind_list;
 74 
 75         const char *fw_name;
 76         char tplg_name[64];
 77         unsigned short pci_id;
 78 
 79         int supend_active;
 80 
 81         struct work_struct probe_work;
 82 
 83         struct skl_debug *debugfs;
 84         u8 nr_modules;
 85         struct skl_module **modules;
 86         bool use_tplg_pcm;
 87         struct skl_fw_config cfg;
 88         struct snd_soc_acpi_mach *mach;
 89 
 90         struct device *dev;
 91         struct sst_dsp *dsp;
 92 
 93         /* boot */
 94         wait_queue_head_t boot_wait;
 95         bool boot_complete;
 96 
 97         /* module load */
 98         wait_queue_head_t mod_load_wait;
 99         bool mod_load_complete;
100         bool mod_load_status;
101 
102         /* IPC messaging */
103         struct sst_generic_ipc ipc;
104 
105         /* callback for miscbdge */
106         void (*enable_miscbdcge)(struct device *dev, bool enable);
107         /* Is CGCTL.MISCBDCGE disabled */
108         bool miscbdcg_disabled;
109 
110         /* Populate module information */
111         struct list_head uuid_list;
112 
113         /* Is firmware loaded */
114         bool fw_loaded;
115 
116         /* first boot ? */
117         bool is_first_boot;
118 
119         /* multi-core */
120         struct skl_dsp_cores cores;
121 
122         /* library info */
123         struct skl_lib_info  lib_info[SKL_MAX_LIB];
124         int lib_count;
125 
126         /* Callback to update D0i3C register */
127         void (*update_d0i3c)(struct device *dev, bool enable);
128 
129         struct skl_d0i3_data d0i3;
130 
131         const struct skl_dsp_ops *dsp_ops;
132 
133         /* Callback to update dynamic clock and power gating registers */
134         void (*clock_power_gating)(struct device *dev, bool enable);
135 };
136 
137 #define skl_to_bus(s)  (&(s)->hbus.core)
138 #define bus_to_skl(bus) container_of(bus, struct skl_dev, hbus.core)
139 
140 #define skl_to_hbus(s) (&(s)->hbus)
141 #define hbus_to_skl(hbus) container_of((hbus), struct skl_dev, (hbus))
142 
143 /* to pass dai dma data */
144 struct skl_dma_params {
145         u32 format;
146         u8 stream_tag;
147 };
148 
149 struct skl_machine_pdata {
150         bool use_tplg_pcm; /* use dais and dai links from topology */
151 };
152 
153 struct skl_dsp_ops {
154         int id;
155         unsigned int num_cores;
156         struct skl_dsp_loader_ops (*loader_ops)(void);
157         int (*init)(struct device *dev, void __iomem *mmio_base,
158                         int irq, const char *fw_name,
159                         struct skl_dsp_loader_ops loader_ops,
160                         struct skl_dev **skl_sst);
161         int (*init_fw)(struct device *dev, struct skl_dev *skl);
162         void (*cleanup)(struct device *dev, struct skl_dev *skl);
163 };
164 
165 int skl_platform_unregister(struct device *dev);
166 int skl_platform_register(struct device *dev);
167 
168 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl_dev *skl, u32 instance,
169                                         u8 link_type, u8 s_fmt, u8 num_ch,
170                                         u32 s_rate, u8 dirn, u8 dev_type);
171 
172 int skl_nhlt_update_topology_bin(struct skl_dev *skl);
173 int skl_init_dsp(struct skl_dev *skl);
174 int skl_free_dsp(struct skl_dev *skl);
175 int skl_suspend_late_dsp(struct skl_dev *skl);
176 int skl_suspend_dsp(struct skl_dev *skl);
177 int skl_resume_dsp(struct skl_dev *skl);
178 void skl_cleanup_resources(struct skl_dev *skl);
179 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
180 void skl_update_d0i3c(struct device *dev, bool enable);
181 int skl_nhlt_create_sysfs(struct skl_dev *skl);
182 void skl_nhlt_remove_sysfs(struct skl_dev *skl);
183 void skl_get_clks(struct skl_dev *skl, struct skl_ssp_clk *ssp_clks);
184 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id);
185 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
186                                 u32 caps_size, u32 node_id);
187 
188 struct skl_module_cfg;
189 
190 #ifdef CONFIG_DEBUG_FS
191 struct skl_debug *skl_debugfs_init(struct skl_dev *skl);
192 void skl_debugfs_exit(struct skl_dev *skl);
193 void skl_debug_init_module(struct skl_debug *d,
194                         struct snd_soc_dapm_widget *w,
195                         struct skl_module_cfg *mconfig);
196 #else
197 static inline struct skl_debug *skl_debugfs_init(struct skl_dev *skl)
198 {
199         return NULL;
200 }
201 
202 static inline void skl_debugfs_exit(struct skl_dev *skl)
203 {}
204 
205 static inline void skl_debug_init_module(struct skl_debug *d,
206                                          struct snd_soc_dapm_widget *w,
207                                          struct skl_module_cfg *mconfig)
208 {}
209 #endif
210 
211 #endif /* __SOUND_SOC_SKL_H */
212 

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