~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c

Version: ~ [ linux-5.10-rc1 ] ~ [ linux-5.9.1 ] ~ [ linux-5.8.16 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.72 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.152 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.202 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.240 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.240 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * Mediatek ALSA SoC AFE platform driver for 2701
  4  *
  5  * Copyright (c) 2016 MediaTek Inc.
  6  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
  7  *         Ir Lian <ir.lian@mediatek.com>
  8  *         Ryder Lee <ryder.lee@mediatek.com>
  9  */
 10 
 11 #include <linux/delay.h>
 12 #include <linux/module.h>
 13 #include <linux/mfd/syscon.h>
 14 #include <linux/of.h>
 15 #include <linux/of_address.h>
 16 #include <linux/of_device.h>
 17 #include <linux/pm_runtime.h>
 18 
 19 #include "mt2701-afe-common.h"
 20 #include "mt2701-afe-clock-ctrl.h"
 21 #include "../common/mtk-afe-platform-driver.h"
 22 #include "../common/mtk-afe-fe-dai.h"
 23 
 24 static const struct snd_pcm_hardware mt2701_afe_hardware = {
 25         .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
 26                 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
 27         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
 28                    | SNDRV_PCM_FMTBIT_S32_LE,
 29         .period_bytes_min = 1024,
 30         .period_bytes_max = 1024 * 256,
 31         .periods_min = 4,
 32         .periods_max = 1024,
 33         .buffer_bytes_max = 1024 * 1024,
 34         .fifo_size = 0,
 35 };
 36 
 37 struct mt2701_afe_rate {
 38         unsigned int rate;
 39         unsigned int regvalue;
 40 };
 41 
 42 static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
 43         { .rate = 8000, .regvalue = 0 },
 44         { .rate = 12000, .regvalue = 1 },
 45         { .rate = 16000, .regvalue = 2 },
 46         { .rate = 24000, .regvalue = 3 },
 47         { .rate = 32000, .regvalue = 4 },
 48         { .rate = 48000, .regvalue = 5 },
 49         { .rate = 96000, .regvalue = 6 },
 50         { .rate = 192000, .regvalue = 7 },
 51         { .rate = 384000, .regvalue = 8 },
 52         { .rate = 7350, .regvalue = 16 },
 53         { .rate = 11025, .regvalue = 17 },
 54         { .rate = 14700, .regvalue = 18 },
 55         { .rate = 22050, .regvalue = 19 },
 56         { .rate = 29400, .regvalue = 20 },
 57         { .rate = 44100, .regvalue = 21 },
 58         { .rate = 88200, .regvalue = 22 },
 59         { .rate = 176400, .regvalue = 23 },
 60         { .rate = 352800, .regvalue = 24 },
 61 };
 62 
 63 static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
 64 {
 65         struct mt2701_afe_private *afe_priv = afe->platform_priv;
 66         int val = num - MT2701_IO_I2S;
 67 
 68         if (val < 0 || val >= afe_priv->soc->i2s_num) {
 69                 dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
 70                         __func__, num, val);
 71                 return -EINVAL;
 72         }
 73         return val;
 74 }
 75 
 76 static int mt2701_afe_i2s_fs(unsigned int sample_rate)
 77 {
 78         int i;
 79 
 80         for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
 81                 if (mt2701_afe_i2s_rates[i].rate == sample_rate)
 82                         return mt2701_afe_i2s_rates[i].regvalue;
 83 
 84         return -EINVAL;
 85 }
 86 
 87 static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
 88                                   struct snd_soc_dai *dai)
 89 {
 90         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 91         struct mt2701_afe_private *afe_priv = afe->platform_priv;
 92         int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
 93         bool mode = afe_priv->soc->has_one_heart_mode;
 94 
 95         if (i2s_num < 0)
 96                 return i2s_num;
 97 
 98         return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
 99 }
100 
101 static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
102                                        struct mt2701_i2s_path *i2s_path,
103                                        int stream_dir)
104 {
105         const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
106 
107         if (--i2s_path->on[stream_dir] < 0)
108                 i2s_path->on[stream_dir] = 0;
109 
110         if (i2s_path->on[stream_dir])
111                 return 0;
112 
113         /* disable i2s */
114         regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
115                            ASYS_I2S_CON_I2S_EN, 0);
116 
117         mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
118 
119         return 0;
120 }
121 
122 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
123                                     struct snd_soc_dai *dai)
124 {
125         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
126         struct mt2701_afe_private *afe_priv = afe->platform_priv;
127         int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
128         struct mt2701_i2s_path *i2s_path;
129         bool mode = afe_priv->soc->has_one_heart_mode;
130 
131         if (i2s_num < 0)
132                 return;
133 
134         i2s_path = &afe_priv->i2s_path[i2s_num];
135 
136         if (i2s_path->occupied[substream->stream])
137                 i2s_path->occupied[substream->stream] = 0;
138         else
139                 goto exit;
140 
141         mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
142 
143         /* need to disable i2s-out path when disable i2s-in */
144         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
145                 mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
146 
147 exit:
148         /* disable mclk */
149         mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
150 }
151 
152 static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
153                                   struct mt2701_i2s_path *i2s_path,
154                                   int stream_dir, int rate)
155 {
156         const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
157         struct mt2701_afe_private *afe_priv = afe->platform_priv;
158         int reg, fs, w_len = 1; /* now we support bck 64bits only */
159         unsigned int mask, val;
160 
161         /* no need to enable if already done */
162         if (++i2s_path->on[stream_dir] != 1)
163                 return 0;
164 
165         fs = mt2701_afe_i2s_fs(rate);
166 
167         mask = ASYS_I2S_CON_FS |
168                ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
169                ASYS_I2S_CON_I2S_MODE |
170                ASYS_I2S_CON_WIDE_MODE;
171 
172         val = ASYS_I2S_CON_FS_SET(fs) |
173               ASYS_I2S_CON_I2S_MODE |
174               ASYS_I2S_CON_WIDE_MODE_SET(w_len);
175 
176         if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
177                 mask |= ASYS_I2S_IN_PHASE_FIX;
178                 val |= ASYS_I2S_IN_PHASE_FIX;
179                 reg = ASMI_TIMING_CON1;
180         } else {
181                 if (afe_priv->soc->has_one_heart_mode) {
182                         mask |= ASYS_I2S_CON_ONE_HEART_MODE;
183                         val |= ASYS_I2S_CON_ONE_HEART_MODE;
184                 }
185                 reg = ASMO_TIMING_CON1;
186         }
187 
188         regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
189 
190         regmap_update_bits(afe->regmap, reg,
191                            i2s_data->i2s_asrc_fs_mask
192                            << i2s_data->i2s_asrc_fs_shift,
193                            fs << i2s_data->i2s_asrc_fs_shift);
194 
195         /* enable i2s */
196         mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
197 
198         /* reset i2s hw status before enable */
199         regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
200                            ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
201         udelay(1);
202         regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
203                            ASYS_I2S_CON_RESET, 0);
204         udelay(1);
205         regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
206                            ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
207         return 0;
208 }
209 
210 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
211                                   struct snd_soc_dai *dai)
212 {
213         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
214         struct mt2701_afe_private *afe_priv = afe->platform_priv;
215         int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
216         struct mt2701_i2s_path *i2s_path;
217         bool mode = afe_priv->soc->has_one_heart_mode;
218 
219         if (i2s_num < 0)
220                 return i2s_num;
221 
222         i2s_path = &afe_priv->i2s_path[i2s_num];
223 
224         if (i2s_path->occupied[substream->stream])
225                 return -EBUSY;
226 
227         ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
228         if (ret)
229                 return ret;
230 
231         i2s_path->occupied[substream->stream] = 1;
232 
233         /* need to enable i2s-out path when enable i2s-in */
234         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
235                 mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
236                                        substream->runtime->rate);
237 
238         mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
239                                substream->runtime->rate);
240 
241         return 0;
242 }
243 
244 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
245                                      unsigned int freq, int dir)
246 {
247         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
248         struct mt2701_afe_private *afe_priv = afe->platform_priv;
249         int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
250         bool mode = afe_priv->soc->has_one_heart_mode;
251 
252         if (i2s_num < 0)
253                 return i2s_num;
254 
255         /* mclk */
256         if (dir == SND_SOC_CLOCK_IN) {
257                 dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
258                 return -EINVAL;
259         }
260 
261         afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
262 
263         return 0;
264 }
265 
266 static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
267                                 struct snd_soc_dai *dai)
268 {
269         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
270         struct mt2701_afe_private *afe_priv = afe->platform_priv;
271         int ret;
272 
273         ret = mt2701_enable_btmrg_clk(afe);
274         if (ret)
275                 return ret;
276 
277         afe_priv->mrg_enable[substream->stream] = 1;
278 
279         return 0;
280 }
281 
282 static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
283                                   struct snd_pcm_hw_params *params,
284                                   struct snd_soc_dai *dai)
285 {
286         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
287         int stream_fs;
288         u32 val, msk;
289 
290         stream_fs = params_rate(params);
291 
292         if (stream_fs != 8000 && stream_fs != 16000) {
293                 dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
294                 return -EINVAL;
295         }
296 
297         regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
298                            AFE_MRGIF_CON_I2S_MODE_MASK,
299                            AFE_MRGIF_CON_I2S_MODE_32K);
300 
301         val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
302               | AFE_DAIBT_CON0_MRG_USE;
303         msk = val;
304 
305         if (stream_fs == 16000)
306                 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
307 
308         msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
309 
310         regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
311 
312         regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
313                            AFE_DAIBT_CON0_DAIBT_EN,
314                            AFE_DAIBT_CON0_DAIBT_EN);
315         regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
316                            AFE_MRGIF_CON_MRG_I2S_EN,
317                            AFE_MRGIF_CON_MRG_I2S_EN);
318         regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
319                            AFE_MRGIF_CON_MRG_EN,
320                            AFE_MRGIF_CON_MRG_EN);
321         return 0;
322 }
323 
324 static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
325                                   struct snd_soc_dai *dai)
326 {
327         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
328         struct mt2701_afe_private *afe_priv = afe->platform_priv;
329 
330         /* if the other direction stream is not occupied */
331         if (!afe_priv->mrg_enable[!substream->stream]) {
332                 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
333                                    AFE_DAIBT_CON0_DAIBT_EN, 0);
334                 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
335                                    AFE_MRGIF_CON_MRG_EN, 0);
336                 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
337                                    AFE_MRGIF_CON_MRG_I2S_EN, 0);
338                 mt2701_disable_btmrg_clk(afe);
339         }
340 
341         afe_priv->mrg_enable[substream->stream] = 0;
342 }
343 
344 static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
345                                     struct snd_soc_dai *dai)
346 {
347         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
348         struct mtk_base_afe_memif *memif_tmp;
349         int stream_dir = substream->stream;
350 
351         /* can't run single DL & DLM at the same time */
352         if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
353                 memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
354                 if (memif_tmp->substream) {
355                         dev_warn(afe->dev, "memif is not available");
356                         return -EBUSY;
357                 }
358         }
359 
360         return mtk_afe_fe_startup(substream, dai);
361 }
362 
363 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
364                                       struct snd_pcm_hw_params *params,
365                                       struct snd_soc_dai *dai)
366 {
367         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
368         int stream_dir = substream->stream;
369 
370         /* single DL use PAIR_INTERLEAVE */
371         if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
372                 regmap_update_bits(afe->regmap,
373                                    AFE_MEMIF_PBUF_SIZE,
374                                    AFE_MEMIF_PBUF_SIZE_DLM_MASK,
375                                    AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
376 
377         return mtk_afe_fe_hw_params(substream, params, dai);
378 }
379 
380 static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
381                                  struct snd_soc_dai *dai)
382 {
383         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
384         struct mtk_base_afe_memif *memif_tmp;
385         const struct mtk_base_memif_data *memif_data;
386         int i;
387 
388         for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
389                 memif_tmp = &afe->memif[i];
390                 if (memif_tmp->substream)
391                         return -EBUSY;
392         }
393 
394         /* enable agent for all signal DL (due to hw design) */
395         for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
396                 memif_data = afe->memif[i].data;
397                 regmap_update_bits(afe->regmap,
398                                    memif_data->agent_disable_reg,
399                                    1 << memif_data->agent_disable_shift,
400                                    0 << memif_data->agent_disable_shift);
401         }
402 
403         return mtk_afe_fe_startup(substream, dai);
404 }
405 
406 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
407                                    struct snd_soc_dai *dai)
408 {
409         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
410         const struct mtk_base_memif_data *memif_data;
411         int i;
412 
413         for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
414                 memif_data = afe->memif[i].data;
415                 regmap_update_bits(afe->regmap,
416                                    memif_data->agent_disable_reg,
417                                    1 << memif_data->agent_disable_shift,
418                                    1 << memif_data->agent_disable_shift);
419         }
420 
421         return mtk_afe_fe_shutdown(substream, dai);
422 }
423 
424 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
425                                    struct snd_pcm_hw_params *params,
426                                    struct snd_soc_dai *dai)
427 {
428         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
429         int channels = params_channels(params);
430 
431         regmap_update_bits(afe->regmap,
432                            AFE_MEMIF_PBUF_SIZE,
433                            AFE_MEMIF_PBUF_SIZE_DLM_MASK,
434                            AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
435         regmap_update_bits(afe->regmap,
436                            AFE_MEMIF_PBUF_SIZE,
437                            AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
438                            AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
439         regmap_update_bits(afe->regmap,
440                            AFE_MEMIF_PBUF_SIZE,
441                            AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
442                            AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
443 
444         return mtk_afe_fe_hw_params(substream, params, dai);
445 }
446 
447 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
448                                  int cmd, struct snd_soc_dai *dai)
449 {
450         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
451         struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
452 
453         switch (cmd) {
454         case SNDRV_PCM_TRIGGER_START:
455         case SNDRV_PCM_TRIGGER_RESUME:
456                 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
457                                    1 << memif_tmp->data->enable_shift,
458                                    1 << memif_tmp->data->enable_shift);
459                 mtk_afe_fe_trigger(substream, cmd, dai);
460                 return 0;
461         case SNDRV_PCM_TRIGGER_STOP:
462         case SNDRV_PCM_TRIGGER_SUSPEND:
463                 mtk_afe_fe_trigger(substream, cmd, dai);
464                 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
465                                    1 << memif_tmp->data->enable_shift, 0);
466 
467                 return 0;
468         default:
469                 return -EINVAL;
470         }
471 }
472 
473 static int mt2701_memif_fs(struct snd_pcm_substream *substream,
474                            unsigned int rate)
475 {
476         struct snd_soc_pcm_runtime *rtd = substream->private_data;
477         int fs;
478 
479         if (rtd->cpu_dai->id != MT2701_MEMIF_ULBT)
480                 fs = mt2701_afe_i2s_fs(rate);
481         else
482                 fs = (rate == 16000 ? 1 : 0);
483 
484         return fs;
485 }
486 
487 static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
488 {
489         return mt2701_afe_i2s_fs(rate);
490 }
491 
492 /* FE DAIs */
493 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
494         .startup        = mt2701_simple_fe_startup,
495         .shutdown       = mtk_afe_fe_shutdown,
496         .hw_params      = mt2701_simple_fe_hw_params,
497         .hw_free        = mtk_afe_fe_hw_free,
498         .prepare        = mtk_afe_fe_prepare,
499         .trigger        = mtk_afe_fe_trigger,
500 };
501 
502 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
503         .startup        = mt2701_dlm_fe_startup,
504         .shutdown       = mt2701_dlm_fe_shutdown,
505         .hw_params      = mt2701_dlm_fe_hw_params,
506         .hw_free        = mtk_afe_fe_hw_free,
507         .prepare        = mtk_afe_fe_prepare,
508         .trigger        = mt2701_dlm_fe_trigger,
509 };
510 
511 /* I2S BE DAIs */
512 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
513         .startup        = mt2701_afe_i2s_startup,
514         .shutdown       = mt2701_afe_i2s_shutdown,
515         .prepare        = mt2701_afe_i2s_prepare,
516         .set_sysclk     = mt2701_afe_i2s_set_sysclk,
517 };
518 
519 /* MRG BE DAIs */
520 static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
521         .startup = mt2701_btmrg_startup,
522         .shutdown = mt2701_btmrg_shutdown,
523         .hw_params = mt2701_btmrg_hw_params,
524 };
525 
526 static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
527         /* FE DAIs: memory intefaces to CPU */
528         {
529                 .name = "PCMO0",
530                 .id = MT2701_MEMIF_DL1,
531                 .suspend = mtk_afe_dai_suspend,
532                 .resume = mtk_afe_dai_resume,
533                 .playback = {
534                         .stream_name = "DL1",
535                         .channels_min = 1,
536                         .channels_max = 2,
537                         .rates = SNDRV_PCM_RATE_8000_192000,
538                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
539                                 | SNDRV_PCM_FMTBIT_S24_LE
540                                 | SNDRV_PCM_FMTBIT_S32_LE)
541                 },
542                 .ops = &mt2701_single_memif_dai_ops,
543         },
544         {
545                 .name = "PCM_multi",
546                 .id = MT2701_MEMIF_DLM,
547                 .suspend = mtk_afe_dai_suspend,
548                 .resume = mtk_afe_dai_resume,
549                 .playback = {
550                         .stream_name = "DLM",
551                         .channels_min = 1,
552                         .channels_max = 8,
553                         .rates = SNDRV_PCM_RATE_8000_192000,
554                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
555                                 | SNDRV_PCM_FMTBIT_S24_LE
556                                 | SNDRV_PCM_FMTBIT_S32_LE)
557 
558                 },
559                 .ops = &mt2701_dlm_memif_dai_ops,
560         },
561         {
562                 .name = "PCM0",
563                 .id = MT2701_MEMIF_UL1,
564                 .suspend = mtk_afe_dai_suspend,
565                 .resume = mtk_afe_dai_resume,
566                 .capture = {
567                         .stream_name = "UL1",
568                         .channels_min = 1,
569                         .channels_max = 2,
570                         .rates = SNDRV_PCM_RATE_8000_48000,
571                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
572                                 | SNDRV_PCM_FMTBIT_S24_LE
573                                 | SNDRV_PCM_FMTBIT_S32_LE)
574                 },
575                 .ops = &mt2701_single_memif_dai_ops,
576         },
577         {
578                 .name = "PCM1",
579                 .id = MT2701_MEMIF_UL2,
580                 .suspend = mtk_afe_dai_suspend,
581                 .resume = mtk_afe_dai_resume,
582                 .capture = {
583                         .stream_name = "UL2",
584                         .channels_min = 1,
585                         .channels_max = 2,
586                         .rates = SNDRV_PCM_RATE_8000_192000,
587                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
588                                 | SNDRV_PCM_FMTBIT_S24_LE
589                                 | SNDRV_PCM_FMTBIT_S32_LE)
590 
591                 },
592                 .ops = &mt2701_single_memif_dai_ops,
593         },
594         {
595                 .name = "PCM_BT_DL",
596                 .id = MT2701_MEMIF_DLBT,
597                 .suspend = mtk_afe_dai_suspend,
598                 .resume = mtk_afe_dai_resume,
599                 .playback = {
600                         .stream_name = "DLBT",
601                         .channels_min = 1,
602                         .channels_max = 1,
603                         .rates = (SNDRV_PCM_RATE_8000
604                                 | SNDRV_PCM_RATE_16000),
605                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
606                 },
607                 .ops = &mt2701_single_memif_dai_ops,
608         },
609         {
610                 .name = "PCM_BT_UL",
611                 .id = MT2701_MEMIF_ULBT,
612                 .suspend = mtk_afe_dai_suspend,
613                 .resume = mtk_afe_dai_resume,
614                 .capture = {
615                         .stream_name = "ULBT",
616                         .channels_min = 1,
617                         .channels_max = 1,
618                         .rates = (SNDRV_PCM_RATE_8000
619                                 | SNDRV_PCM_RATE_16000),
620                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
621                 },
622                 .ops = &mt2701_single_memif_dai_ops,
623         },
624         /* BE DAIs */
625         {
626                 .name = "I2S0",
627                 .id = MT2701_IO_I2S,
628                 .playback = {
629                         .stream_name = "I2S0 Playback",
630                         .channels_min = 1,
631                         .channels_max = 2,
632                         .rates = SNDRV_PCM_RATE_8000_192000,
633                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
634                                 | SNDRV_PCM_FMTBIT_S24_LE
635                                 | SNDRV_PCM_FMTBIT_S32_LE)
636 
637                 },
638                 .capture = {
639                         .stream_name = "I2S0 Capture",
640                         .channels_min = 1,
641                         .channels_max = 2,
642                         .rates = SNDRV_PCM_RATE_8000_192000,
643                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
644                                 | SNDRV_PCM_FMTBIT_S24_LE
645                                 | SNDRV_PCM_FMTBIT_S32_LE)
646 
647                 },
648                 .ops = &mt2701_afe_i2s_ops,
649                 .symmetric_rates = 1,
650         },
651         {
652                 .name = "I2S1",
653                 .id = MT2701_IO_2ND_I2S,
654                 .playback = {
655                         .stream_name = "I2S1 Playback",
656                         .channels_min = 1,
657                         .channels_max = 2,
658                         .rates = SNDRV_PCM_RATE_8000_192000,
659                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
660                                 | SNDRV_PCM_FMTBIT_S24_LE
661                                 | SNDRV_PCM_FMTBIT_S32_LE)
662                         },
663                 .capture = {
664                         .stream_name = "I2S1 Capture",
665                         .channels_min = 1,
666                         .channels_max = 2,
667                         .rates = SNDRV_PCM_RATE_8000_192000,
668                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
669                                 | SNDRV_PCM_FMTBIT_S24_LE
670                                 | SNDRV_PCM_FMTBIT_S32_LE)
671                         },
672                 .ops = &mt2701_afe_i2s_ops,
673                 .symmetric_rates = 1,
674         },
675         {
676                 .name = "I2S2",
677                 .id = MT2701_IO_3RD_I2S,
678                 .playback = {
679                         .stream_name = "I2S2 Playback",
680                         .channels_min = 1,
681                         .channels_max = 2,
682                         .rates = SNDRV_PCM_RATE_8000_192000,
683                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
684                                 | SNDRV_PCM_FMTBIT_S24_LE
685                                 | SNDRV_PCM_FMTBIT_S32_LE)
686                         },
687                 .capture = {
688                         .stream_name = "I2S2 Capture",
689                         .channels_min = 1,
690                         .channels_max = 2,
691                         .rates = SNDRV_PCM_RATE_8000_192000,
692                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
693                                 | SNDRV_PCM_FMTBIT_S24_LE
694                                 | SNDRV_PCM_FMTBIT_S32_LE)
695                         },
696                 .ops = &mt2701_afe_i2s_ops,
697                 .symmetric_rates = 1,
698         },
699         {
700                 .name = "I2S3",
701                 .id = MT2701_IO_4TH_I2S,
702                 .playback = {
703                         .stream_name = "I2S3 Playback",
704                         .channels_min = 1,
705                         .channels_max = 2,
706                         .rates = SNDRV_PCM_RATE_8000_192000,
707                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
708                                 | SNDRV_PCM_FMTBIT_S24_LE
709                                 | SNDRV_PCM_FMTBIT_S32_LE)
710                         },
711                 .capture = {
712                         .stream_name = "I2S3 Capture",
713                         .channels_min = 1,
714                         .channels_max = 2,
715                         .rates = SNDRV_PCM_RATE_8000_192000,
716                         .formats = (SNDRV_PCM_FMTBIT_S16_LE
717                                 | SNDRV_PCM_FMTBIT_S24_LE
718                                 | SNDRV_PCM_FMTBIT_S32_LE)
719                         },
720                 .ops = &mt2701_afe_i2s_ops,
721                 .symmetric_rates = 1,
722         },
723         {
724                 .name = "MRG BT",
725                 .id = MT2701_IO_MRG,
726                 .playback = {
727                         .stream_name = "BT Playback",
728                         .channels_min = 1,
729                         .channels_max = 1,
730                         .rates = (SNDRV_PCM_RATE_8000
731                                 | SNDRV_PCM_RATE_16000),
732                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
733                 },
734                 .capture = {
735                         .stream_name = "BT Capture",
736                         .channels_min = 1,
737                         .channels_max = 1,
738                         .rates = (SNDRV_PCM_RATE_8000
739                                 | SNDRV_PCM_RATE_16000),
740                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
741                 },
742                 .ops = &mt2701_btmrg_ops,
743                 .symmetric_rates = 1,
744         }
745 };
746 
747 static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
748         SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
749 };
750 
751 static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
752         SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
753 };
754 
755 static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
756         SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
757 };
758 
759 static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
760         SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
761 };
762 
763 static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
764         SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
765 };
766 
767 static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
768         SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
769 };
770 
771 static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
772         SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
773 };
774 
775 static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
776         SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
777 };
778 
779 static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
780         SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
781 };
782 
783 static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
784         SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
785 };
786 
787 static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
788         SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
789 };
790 
791 static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
792         SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
793 };
794 
795 static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
796         SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
797 };
798 
799 static const struct snd_kcontrol_new mt2701_afe_o23_mix[] = {
800         SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0),
801 };
802 
803 static const struct snd_kcontrol_new mt2701_afe_o24_mix[] = {
804         SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0),
805 };
806 
807 static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
808         SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
809 };
810 
811 static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
812         SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
813 };
814 
815 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
816         SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
817                                     ASYS_I2SO1_CON, 26, 1, 0),
818 };
819 
820 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
821         SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
822                                     ASYS_I2SO2_CON, 26, 1, 0),
823 };
824 
825 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
826         SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
827                                     PWR2_TOP_CON, 17, 1, 0),
828 };
829 
830 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
831         SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
832                                     PWR2_TOP_CON, 18, 1, 0),
833 };
834 
835 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
836         SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S4 Out Switch",
837                                     PWR2_TOP_CON, 19, 1, 0),
838 };
839 
840 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
841         /* inter-connections */
842         SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
843         SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
844         SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
845                            ARRAY_SIZE(mt2701_afe_i02_mix)),
846         SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
847         SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
848         SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
849         SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
850         SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
851         SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
852         SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
853         SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
854         SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
855         SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
856         SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
857 
858         SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
859                            ARRAY_SIZE(mt2701_afe_o00_mix)),
860         SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
861                            ARRAY_SIZE(mt2701_afe_o01_mix)),
862         SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
863                            ARRAY_SIZE(mt2701_afe_o02_mix)),
864         SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
865                            ARRAY_SIZE(mt2701_afe_o03_mix)),
866         SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
867                            ARRAY_SIZE(mt2701_afe_o14_mix)),
868         SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
869                            ARRAY_SIZE(mt2701_afe_o15_mix)),
870         SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
871                            ARRAY_SIZE(mt2701_afe_o16_mix)),
872         SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
873                            ARRAY_SIZE(mt2701_afe_o17_mix)),
874         SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
875                            ARRAY_SIZE(mt2701_afe_o18_mix)),
876         SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
877                            ARRAY_SIZE(mt2701_afe_o19_mix)),
878         SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
879                            ARRAY_SIZE(mt2701_afe_o20_mix)),
880         SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
881                            ARRAY_SIZE(mt2701_afe_o21_mix)),
882         SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
883                            ARRAY_SIZE(mt2701_afe_o22_mix)),
884         SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
885                            ARRAY_SIZE(mt2701_afe_o31_mix)),
886 
887         SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
888                            mt2701_afe_multi_ch_out_i2s0,
889                            ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
890         SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
891                            mt2701_afe_multi_ch_out_i2s1,
892                            ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
893         SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
894                            mt2701_afe_multi_ch_out_i2s2,
895                            ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
896         SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
897                            mt2701_afe_multi_ch_out_i2s3,
898                            ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
899 };
900 
901 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
902         {"I12", NULL, "DL1"},
903         {"I13", NULL, "DL1"},
904         {"I35", NULL, "DLBT"},
905 
906         {"I2S0 Playback", NULL, "O15"},
907         {"I2S0 Playback", NULL, "O16"},
908         {"I2S1 Playback", NULL, "O17"},
909         {"I2S1 Playback", NULL, "O18"},
910         {"I2S2 Playback", NULL, "O19"},
911         {"I2S2 Playback", NULL, "O20"},
912         {"I2S3 Playback", NULL, "O21"},
913         {"I2S3 Playback", NULL, "O22"},
914         {"BT Playback", NULL, "O31"},
915 
916         {"UL1", NULL, "O00"},
917         {"UL1", NULL, "O01"},
918         {"UL2", NULL, "O02"},
919         {"UL2", NULL, "O03"},
920         {"ULBT", NULL, "O14"},
921 
922         {"I00", NULL, "I2S0 Capture"},
923         {"I01", NULL, "I2S0 Capture"},
924         {"I02", NULL, "I2S1 Capture"},
925         {"I03", NULL, "I2S1 Capture"},
926         /* I02,03 link to UL2, also need to open I2S0 */
927         {"I02", "I2S0 Switch", "I2S0 Capture"},
928 
929         {"I26", NULL, "BT Capture"},
930 
931         {"I12I13", "Multich I2S0 Out Switch", "DLM"},
932         {"I14I15", "Multich I2S1 Out Switch", "DLM"},
933         {"I16I17", "Multich I2S2 Out Switch", "DLM"},
934         {"I18I19", "Multich I2S3 Out Switch", "DLM"},
935 
936         { "I12", NULL, "I12I13" },
937         { "I13", NULL, "I12I13" },
938         { "I14", NULL, "I14I15" },
939         { "I15", NULL, "I14I15" },
940         { "I16", NULL, "I16I17" },
941         { "I17", NULL, "I16I17" },
942         { "I18", NULL, "I18I19" },
943         { "I19", NULL, "I18I19" },
944 
945         { "O00", "I00 Switch", "I00" },
946         { "O01", "I01 Switch", "I01" },
947         { "O02", "I02 Switch", "I02" },
948         { "O03", "I03 Switch", "I03" },
949         { "O14", "I26 Switch", "I26" },
950         { "O15", "I12 Switch", "I12" },
951         { "O16", "I13 Switch", "I13" },
952         { "O17", "I14 Switch", "I14" },
953         { "O18", "I15 Switch", "I15" },
954         { "O19", "I16 Switch", "I16" },
955         { "O20", "I17 Switch", "I17" },
956         { "O21", "I18 Switch", "I18" },
957         { "O22", "I19 Switch", "I19" },
958         { "O31", "I35 Switch", "I35" },
959 };
960 
961 static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
962 {
963         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
964 
965         snd_soc_component_init_regmap(component, afe->regmap);
966 
967         return 0;
968 }
969 
970 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
971         .probe = mt2701_afe_pcm_probe,
972         .name = "mt2701-afe-pcm-dai",
973         .dapm_widgets = mt2701_afe_pcm_widgets,
974         .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
975         .dapm_routes = mt2701_afe_pcm_routes,
976         .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
977 };
978 
979 static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
980         {
981                 .name = "DL1",
982                 .id = MT2701_MEMIF_DL1,
983                 .reg_ofs_base = AFE_DL1_BASE,
984                 .reg_ofs_cur = AFE_DL1_CUR,
985                 .fs_reg = AFE_DAC_CON1,
986                 .fs_shift = 0,
987                 .fs_maskbit = 0x1f,
988                 .mono_reg = AFE_DAC_CON3,
989                 .mono_shift = 16,
990                 .enable_reg = AFE_DAC_CON0,
991                 .enable_shift = 1,
992                 .hd_reg = AFE_MEMIF_HD_CON0,
993                 .hd_shift = 0,
994                 .agent_disable_reg = AUDIO_TOP_CON5,
995                 .agent_disable_shift = 6,
996                 .msb_reg = -1,
997         },
998         {
999                 .name = "DL2",
1000                 .id = MT2701_MEMIF_DL2,
1001                 .reg_ofs_base = AFE_DL2_BASE,
1002                 .reg_ofs_cur = AFE_DL2_CUR,
1003                 .fs_reg = AFE_DAC_CON1,
1004                 .fs_shift = 5,
1005                 .fs_maskbit = 0x1f,
1006                 .mono_reg = AFE_DAC_CON3,
1007                 .mono_shift = 17,
1008                 .enable_reg = AFE_DAC_CON0,
1009                 .enable_shift = 2,
1010                 .hd_reg = AFE_MEMIF_HD_CON0,
1011                 .hd_shift = 2,
1012                 .agent_disable_reg = AUDIO_TOP_CON5,
1013                 .agent_disable_shift = 7,
1014                 .msb_reg = -1,
1015         },
1016         {
1017                 .name = "DL3",
1018                 .id = MT2701_MEMIF_DL3,
1019                 .reg_ofs_base = AFE_DL3_BASE,
1020                 .reg_ofs_cur = AFE_DL3_CUR,
1021                 .fs_reg = AFE_DAC_CON1,
1022                 .fs_shift = 10,
1023                 .fs_maskbit = 0x1f,
1024                 .mono_reg = AFE_DAC_CON3,
1025                 .mono_shift = 18,
1026                 .enable_reg = AFE_DAC_CON0,
1027                 .enable_shift = 3,
1028                 .hd_reg = AFE_MEMIF_HD_CON0,
1029                 .hd_shift = 4,
1030                 .agent_disable_reg = AUDIO_TOP_CON5,
1031                 .agent_disable_shift = 8,
1032                 .msb_reg = -1,
1033         },
1034         {
1035                 .name = "DL4",
1036                 .id = MT2701_MEMIF_DL4,
1037                 .reg_ofs_base = AFE_DL4_BASE,
1038                 .reg_ofs_cur = AFE_DL4_CUR,
1039                 .fs_reg = AFE_DAC_CON1,
1040                 .fs_shift = 15,
1041                 .fs_maskbit = 0x1f,
1042                 .mono_reg = AFE_DAC_CON3,
1043                 .mono_shift = 19,
1044                 .enable_reg = AFE_DAC_CON0,
1045                 .enable_shift = 4,
1046                 .hd_reg = AFE_MEMIF_HD_CON0,
1047                 .hd_shift = 6,
1048                 .agent_disable_reg = AUDIO_TOP_CON5,
1049                 .agent_disable_shift = 9,
1050                 .msb_reg = -1,
1051         },
1052         {
1053                 .name = "DL5",
1054                 .id = MT2701_MEMIF_DL5,
1055                 .reg_ofs_base = AFE_DL5_BASE,
1056                 .reg_ofs_cur = AFE_DL5_CUR,
1057                 .fs_reg = AFE_DAC_CON1,
1058                 .fs_shift = 20,
1059                 .fs_maskbit = 0x1f,
1060                 .mono_reg = AFE_DAC_CON3,
1061                 .mono_shift = 20,
1062                 .enable_reg = AFE_DAC_CON0,
1063                 .enable_shift = 5,
1064                 .hd_reg = AFE_MEMIF_HD_CON0,
1065                 .hd_shift = 8,
1066                 .agent_disable_reg = AUDIO_TOP_CON5,
1067                 .agent_disable_shift = 10,
1068                 .msb_reg = -1,
1069         },
1070         {
1071                 .name = "DLM",
1072                 .id = MT2701_MEMIF_DLM,
1073                 .reg_ofs_base = AFE_DLMCH_BASE,
1074                 .reg_ofs_cur = AFE_DLMCH_CUR,
1075                 .fs_reg = AFE_DAC_CON1,
1076                 .fs_shift = 0,
1077                 .fs_maskbit = 0x1f,
1078                 .mono_reg = -1,
1079                 .mono_shift = -1,
1080                 .enable_reg = AFE_DAC_CON0,
1081                 .enable_shift = 7,
1082                 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1083                 .hd_shift = 28,
1084                 .agent_disable_reg = AUDIO_TOP_CON5,
1085                 .agent_disable_shift = 12,
1086                 .msb_reg = -1,
1087         },
1088         {
1089                 .name = "UL1",
1090                 .id = MT2701_MEMIF_UL1,
1091                 .reg_ofs_base = AFE_VUL_BASE,
1092                 .reg_ofs_cur = AFE_VUL_CUR,
1093                 .fs_reg = AFE_DAC_CON2,
1094                 .fs_shift = 0,
1095                 .fs_maskbit = 0x1f,
1096                 .mono_reg = AFE_DAC_CON4,
1097                 .mono_shift = 0,
1098                 .enable_reg = AFE_DAC_CON0,
1099                 .enable_shift = 10,
1100                 .hd_reg = AFE_MEMIF_HD_CON1,
1101                 .hd_shift = 0,
1102                 .agent_disable_reg = AUDIO_TOP_CON5,
1103                 .agent_disable_shift = 0,
1104                 .msb_reg = -1,
1105         },
1106         {
1107                 .name = "UL2",
1108                 .id = MT2701_MEMIF_UL2,
1109                 .reg_ofs_base = AFE_UL2_BASE,
1110                 .reg_ofs_cur = AFE_UL2_CUR,
1111                 .fs_reg = AFE_DAC_CON2,
1112                 .fs_shift = 5,
1113                 .fs_maskbit = 0x1f,
1114                 .mono_reg = AFE_DAC_CON4,
1115                 .mono_shift = 2,
1116                 .enable_reg = AFE_DAC_CON0,
1117                 .enable_shift = 11,
1118                 .hd_reg = AFE_MEMIF_HD_CON1,
1119                 .hd_shift = 2,
1120                 .agent_disable_reg = AUDIO_TOP_CON5,
1121                 .agent_disable_shift = 1,
1122                 .msb_reg = -1,
1123         },
1124         {
1125                 .name = "UL3",
1126                 .id = MT2701_MEMIF_UL3,
1127                 .reg_ofs_base = AFE_UL3_BASE,
1128                 .reg_ofs_cur = AFE_UL3_CUR,
1129                 .fs_reg = AFE_DAC_CON2,
1130                 .fs_shift = 10,
1131                 .fs_maskbit = 0x1f,
1132                 .mono_reg = AFE_DAC_CON4,
1133                 .mono_shift = 4,
1134                 .enable_reg = AFE_DAC_CON0,
1135                 .enable_shift = 12,
1136                 .hd_reg = AFE_MEMIF_HD_CON0,
1137                 .hd_shift = 0,
1138                 .agent_disable_reg = AUDIO_TOP_CON5,
1139                 .agent_disable_shift = 2,
1140                 .msb_reg = -1,
1141         },
1142         {
1143                 .name = "UL4",
1144                 .id = MT2701_MEMIF_UL4,
1145                 .reg_ofs_base = AFE_UL4_BASE,
1146                 .reg_ofs_cur = AFE_UL4_CUR,
1147                 .fs_reg = AFE_DAC_CON2,
1148                 .fs_shift = 15,
1149                 .fs_maskbit = 0x1f,
1150                 .mono_reg = AFE_DAC_CON4,
1151                 .mono_shift = 6,
1152                 .enable_reg = AFE_DAC_CON0,
1153                 .enable_shift = 13,
1154                 .hd_reg = AFE_MEMIF_HD_CON0,
1155                 .hd_shift = 6,
1156                 .agent_disable_reg = AUDIO_TOP_CON5,
1157                 .agent_disable_shift = 3,
1158                 .msb_reg = -1,
1159         },
1160         {
1161                 .name = "UL5",
1162                 .id = MT2701_MEMIF_UL5,
1163                 .reg_ofs_base = AFE_UL5_BASE,
1164                 .reg_ofs_cur = AFE_UL5_CUR,
1165                 .fs_reg = AFE_DAC_CON2,
1166                 .fs_shift = 20,
1167                 .mono_reg = AFE_DAC_CON4,
1168                 .mono_shift = 8,
1169                 .fs_maskbit = 0x1f,
1170                 .enable_reg = AFE_DAC_CON0,
1171                 .enable_shift = 14,
1172                 .hd_reg = AFE_MEMIF_HD_CON0,
1173                 .hd_shift = 8,
1174                 .agent_disable_reg = AUDIO_TOP_CON5,
1175                 .agent_disable_shift = 4,
1176                 .msb_reg = -1,
1177         },
1178         {
1179                 .name = "DLBT",
1180                 .id = MT2701_MEMIF_DLBT,
1181                 .reg_ofs_base = AFE_ARB1_BASE,
1182                 .reg_ofs_cur = AFE_ARB1_CUR,
1183                 .fs_reg = AFE_DAC_CON3,
1184                 .fs_shift = 10,
1185                 .fs_maskbit = 0x1f,
1186                 .mono_reg = AFE_DAC_CON3,
1187                 .mono_shift = 22,
1188                 .enable_reg = AFE_DAC_CON0,
1189                 .enable_shift = 8,
1190                 .hd_reg = AFE_MEMIF_HD_CON0,
1191                 .hd_shift = 14,
1192                 .agent_disable_reg = AUDIO_TOP_CON5,
1193                 .agent_disable_shift = 13,
1194                 .msb_reg = -1,
1195         },
1196         {
1197                 .name = "ULBT",
1198                 .id = MT2701_MEMIF_ULBT,
1199                 .reg_ofs_base = AFE_DAI_BASE,
1200                 .reg_ofs_cur = AFE_DAI_CUR,
1201                 .fs_reg = AFE_DAC_CON2,
1202                 .fs_shift = 30,
1203                 .fs_maskbit = 0x1,
1204                 .mono_reg = -1,
1205                 .mono_shift = -1,
1206                 .enable_reg = AFE_DAC_CON0,
1207                 .enable_shift = 17,
1208                 .hd_reg = AFE_MEMIF_HD_CON1,
1209                 .hd_shift = 20,
1210                 .agent_disable_reg = AUDIO_TOP_CON5,
1211                 .agent_disable_shift = 16,
1212                 .msb_reg = -1,
1213         },
1214 };
1215 
1216 static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1217         {
1218                 .id = MT2701_IRQ_ASYS_IRQ1,
1219                 .irq_cnt_reg = ASYS_IRQ1_CON,
1220                 .irq_cnt_shift = 0,
1221                 .irq_cnt_maskbit = 0xffffff,
1222                 .irq_fs_reg = ASYS_IRQ1_CON,
1223                 .irq_fs_shift = 24,
1224                 .irq_fs_maskbit = 0x1f,
1225                 .irq_en_reg = ASYS_IRQ1_CON,
1226                 .irq_en_shift = 31,
1227                 .irq_clr_reg = ASYS_IRQ_CLR,
1228                 .irq_clr_shift = 0,
1229         },
1230         {
1231                 .id = MT2701_IRQ_ASYS_IRQ2,
1232                 .irq_cnt_reg = ASYS_IRQ2_CON,
1233                 .irq_cnt_shift = 0,
1234                 .irq_cnt_maskbit = 0xffffff,
1235                 .irq_fs_reg = ASYS_IRQ2_CON,
1236                 .irq_fs_shift = 24,
1237                 .irq_fs_maskbit = 0x1f,
1238                 .irq_en_reg = ASYS_IRQ2_CON,
1239                 .irq_en_shift = 31,
1240                 .irq_clr_reg = ASYS_IRQ_CLR,
1241                 .irq_clr_shift = 1,
1242         },
1243         {
1244                 .id = MT2701_IRQ_ASYS_IRQ3,
1245                 .irq_cnt_reg = ASYS_IRQ3_CON,
1246                 .irq_cnt_shift = 0,
1247                 .irq_cnt_maskbit = 0xffffff,
1248                 .irq_fs_reg = ASYS_IRQ3_CON,
1249                 .irq_fs_shift = 24,
1250                 .irq_fs_maskbit = 0x1f,
1251                 .irq_en_reg = ASYS_IRQ3_CON,
1252                 .irq_en_shift = 31,
1253                 .irq_clr_reg = ASYS_IRQ_CLR,
1254                 .irq_clr_shift = 2,
1255         }
1256 };
1257 
1258 static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
1259         {
1260                 { ASYS_I2SO1_CON, 0, 0x1f },
1261                 { ASYS_I2SIN1_CON, 0, 0x1f },
1262         },
1263         {
1264                 { ASYS_I2SO2_CON, 5, 0x1f },
1265                 { ASYS_I2SIN2_CON, 5, 0x1f },
1266         },
1267         {
1268                 { ASYS_I2SO3_CON, 10, 0x1f },
1269                 { ASYS_I2SIN3_CON, 10, 0x1f },
1270         },
1271         {
1272                 { ASYS_I2SO4_CON, 15, 0x1f },
1273                 { ASYS_I2SIN4_CON, 15, 0x1f },
1274         },
1275         /* TODO - extend control registers supported by newer SoCs */
1276 };
1277 
1278 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1279 {
1280         int id;
1281         struct mtk_base_afe *afe = dev;
1282         struct mtk_base_afe_memif *memif;
1283         struct mtk_base_afe_irq *irq;
1284         u32 status;
1285 
1286         regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1287         regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1288 
1289         for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1290                 memif = &afe->memif[id];
1291                 if (memif->irq_usage < 0)
1292                         continue;
1293 
1294                 irq = &afe->irqs[memif->irq_usage];
1295                 if (status & 1 << irq->irq_data->irq_clr_shift)
1296                         snd_pcm_period_elapsed(memif->substream);
1297         }
1298 
1299         return IRQ_HANDLED;
1300 }
1301 
1302 static int mt2701_afe_runtime_suspend(struct device *dev)
1303 {
1304         struct mtk_base_afe *afe = dev_get_drvdata(dev);
1305 
1306         return mt2701_afe_disable_clock(afe);
1307 }
1308 
1309 static int mt2701_afe_runtime_resume(struct device *dev)
1310 {
1311         struct mtk_base_afe *afe = dev_get_drvdata(dev);
1312 
1313         return mt2701_afe_enable_clock(afe);
1314 }
1315 
1316 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1317 {
1318         struct mtk_base_afe *afe;
1319         struct mt2701_afe_private *afe_priv;
1320         struct device *dev;
1321         int i, irq_id, ret;
1322 
1323         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1324         if (!afe)
1325                 return -ENOMEM;
1326 
1327         afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1328                                           GFP_KERNEL);
1329         if (!afe->platform_priv)
1330                 return -ENOMEM;
1331 
1332         afe_priv = afe->platform_priv;
1333         afe_priv->soc = of_device_get_match_data(&pdev->dev);
1334         afe->dev = &pdev->dev;
1335         dev = afe->dev;
1336 
1337         afe_priv->i2s_path = devm_kcalloc(dev,
1338                                           afe_priv->soc->i2s_num,
1339                                           sizeof(struct mt2701_i2s_path),
1340                                           GFP_KERNEL);
1341         if (!afe_priv->i2s_path)
1342                 return -ENOMEM;
1343 
1344         irq_id = platform_get_irq_byname(pdev, "asys");
1345         if (irq_id < 0) {
1346                 dev_err(dev, "unable to get ASYS IRQ\n");
1347                 return irq_id;
1348         }
1349 
1350         ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1351                                IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1352         if (ret) {
1353                 dev_err(dev, "could not request_irq for asys-isr\n");
1354                 return ret;
1355         }
1356 
1357         afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1358         if (IS_ERR(afe->regmap)) {
1359                 dev_err(dev, "could not get regmap from parent\n");
1360                 return PTR_ERR(afe->regmap);
1361         }
1362 
1363         mutex_init(&afe->irq_alloc_lock);
1364 
1365         /* memif initialize */
1366         afe->memif_size = MT2701_MEMIF_NUM;
1367         afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1368                                   GFP_KERNEL);
1369         if (!afe->memif)
1370                 return -ENOMEM;
1371 
1372         for (i = 0; i < afe->memif_size; i++) {
1373                 afe->memif[i].data = &memif_data[i];
1374                 afe->memif[i].irq_usage = -1;
1375         }
1376 
1377         /* irq initialize */
1378         afe->irqs_size = MT2701_IRQ_ASYS_END;
1379         afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1380                                  GFP_KERNEL);
1381         if (!afe->irqs)
1382                 return -ENOMEM;
1383 
1384         for (i = 0; i < afe->irqs_size; i++)
1385                 afe->irqs[i].irq_data = &irq_data[i];
1386 
1387         /* I2S initialize */
1388         for (i = 0; i < afe_priv->soc->i2s_num; i++) {
1389                 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
1390                         &mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
1391                 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
1392                         &mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
1393         }
1394 
1395         afe->mtk_afe_hardware = &mt2701_afe_hardware;
1396         afe->memif_fs = mt2701_memif_fs;
1397         afe->irq_fs = mt2701_irq_fs;
1398         afe->reg_back_up_list = mt2701_afe_backup_list;
1399         afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1400         afe->runtime_resume = mt2701_afe_runtime_resume;
1401         afe->runtime_suspend = mt2701_afe_runtime_suspend;
1402 
1403         /* initial audio related clock */
1404         ret = mt2701_init_clock(afe);
1405         if (ret) {
1406                 dev_err(dev, "init clock error\n");
1407                 return ret;
1408         }
1409 
1410         platform_set_drvdata(pdev, afe);
1411 
1412         pm_runtime_enable(dev);
1413         if (!pm_runtime_enabled(dev)) {
1414                 ret = mt2701_afe_runtime_resume(dev);
1415                 if (ret)
1416                         goto err_pm_disable;
1417         }
1418         pm_runtime_get_sync(dev);
1419 
1420         ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
1421                                               NULL, 0);
1422         if (ret) {
1423                 dev_warn(dev, "err_platform\n");
1424                 goto err_platform;
1425         }
1426 
1427         ret = devm_snd_soc_register_component(&pdev->dev,
1428                                          &mt2701_afe_pcm_dai_component,
1429                                          mt2701_afe_pcm_dais,
1430                                          ARRAY_SIZE(mt2701_afe_pcm_dais));
1431         if (ret) {
1432                 dev_warn(dev, "err_dai_component\n");
1433                 goto err_platform;
1434         }
1435 
1436         return 0;
1437 
1438 err_platform:
1439         pm_runtime_put_sync(dev);
1440 err_pm_disable:
1441         pm_runtime_disable(dev);
1442 
1443         return ret;
1444 }
1445 
1446 static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1447 {
1448         pm_runtime_put_sync(&pdev->dev);
1449         pm_runtime_disable(&pdev->dev);
1450         if (!pm_runtime_status_suspended(&pdev->dev))
1451                 mt2701_afe_runtime_suspend(&pdev->dev);
1452 
1453         return 0;
1454 }
1455 
1456 static const struct mt2701_soc_variants mt2701_soc_v1 = {
1457         .i2s_num = 4,
1458 };
1459 
1460 static const struct mt2701_soc_variants mt2701_soc_v2 = {
1461         .has_one_heart_mode = true,
1462         .i2s_num = 4,
1463 };
1464 
1465 static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1466         { .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
1467         { .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
1468         {},
1469 };
1470 MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1471 
1472 static const struct dev_pm_ops mt2701_afe_pm_ops = {
1473         SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1474                            mt2701_afe_runtime_resume, NULL)
1475 };
1476 
1477 static struct platform_driver mt2701_afe_pcm_driver = {
1478         .driver = {
1479                    .name = "mt2701-audio",
1480                    .of_match_table = mt2701_afe_pcm_dt_match,
1481 #ifdef CONFIG_PM
1482                    .pm = &mt2701_afe_pm_ops,
1483 #endif
1484         },
1485         .probe = mt2701_afe_pcm_dev_probe,
1486         .remove = mt2701_afe_pcm_dev_remove,
1487 };
1488 
1489 module_platform_driver(mt2701_afe_pcm_driver);
1490 
1491 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1492 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1493 MODULE_LICENSE("GPL v2");
1494 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp