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TOMOYO Linux Cross Reference
Linux/sound/soc/rockchip/rockchip_i2s.c

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  1 /* sound/soc/rockchip/rockchip_i2s.c
  2  *
  3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
  4  *
  5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
  6  * Author: Jianqun <jay.xu@rock-chips.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/delay.h>
 15 #include <linux/of_gpio.h>
 16 #include <linux/clk.h>
 17 #include <linux/pm_runtime.h>
 18 #include <linux/regmap.h>
 19 #include <sound/pcm_params.h>
 20 #include <sound/dmaengine_pcm.h>
 21 
 22 #include "rockchip_i2s.h"
 23 
 24 #define DRV_NAME "rockchip-i2s"
 25 
 26 struct rk_i2s_dev {
 27         struct device *dev;
 28 
 29         struct clk *hclk;
 30         struct clk *mclk;
 31 
 32         struct snd_dmaengine_dai_dma_data capture_dma_data;
 33         struct snd_dmaengine_dai_dma_data playback_dma_data;
 34 
 35         struct regmap *regmap;
 36 
 37         bool is_master_mode;
 38 };
 39 
 40 static int i2s_runtime_suspend(struct device *dev)
 41 {
 42         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 43 
 44         clk_disable_unprepare(i2s->mclk);
 45 
 46         return 0;
 47 }
 48 
 49 static int i2s_runtime_resume(struct device *dev)
 50 {
 51         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 52         int ret;
 53 
 54         ret = clk_prepare_enable(i2s->mclk);
 55         if (ret) {
 56                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
 57                 return ret;
 58         }
 59 
 60         return 0;
 61 }
 62 
 63 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
 64 {
 65         return snd_soc_dai_get_drvdata(dai);
 66 }
 67 
 68 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
 69 {
 70         unsigned int val = 0;
 71         int retry = 10;
 72 
 73         if (on) {
 74                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 75                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 76 
 77                 regmap_update_bits(i2s->regmap, I2S_XFER,
 78                                    I2S_XFER_TXS_START,
 79                                    I2S_XFER_TXS_START);
 80         } else {
 81                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 82                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 83 
 84                 regmap_update_bits(i2s->regmap, I2S_XFER,
 85                                    I2S_XFER_TXS_START,
 86                                    I2S_XFER_TXS_STOP);
 87 
 88                 regmap_update_bits(i2s->regmap, I2S_CLR,
 89                                    I2S_CLR_TXC,
 90                                    I2S_CLR_TXC);
 91 
 92                 regmap_read(i2s->regmap, I2S_CLR, &val);
 93 
 94                 /* Should wait for clear operation to finish */
 95                 while (val & I2S_CLR_TXC) {
 96                         regmap_read(i2s->regmap, I2S_CLR, &val);
 97                         retry--;
 98                         if (!retry) {
 99                                 dev_warn(i2s->dev, "fail to clear\n");
100                                 break;
101                         }
102                 }
103         }
104 }
105 
106 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
107 {
108         unsigned int val = 0;
109         int retry = 10;
110 
111         if (on) {
112                 regmap_update_bits(i2s->regmap, I2S_DMACR,
113                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
114 
115                 regmap_update_bits(i2s->regmap, I2S_XFER,
116                                    I2S_XFER_RXS_START,
117                                    I2S_XFER_RXS_START);
118         } else {
119                 regmap_update_bits(i2s->regmap, I2S_DMACR,
120                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
121 
122                 regmap_update_bits(i2s->regmap, I2S_XFER,
123                                    I2S_XFER_RXS_START,
124                                    I2S_XFER_RXS_STOP);
125 
126                 regmap_update_bits(i2s->regmap, I2S_CLR,
127                                    I2S_CLR_RXC,
128                                    I2S_CLR_RXC);
129 
130                 regmap_read(i2s->regmap, I2S_CLR, &val);
131 
132                 /* Should wait for clear operation to finish */
133                 while (val & I2S_CLR_RXC) {
134                         regmap_read(i2s->regmap, I2S_CLR, &val);
135                         retry--;
136                         if (!retry) {
137                                 dev_warn(i2s->dev, "fail to clear\n");
138                                 break;
139                         }
140                 }
141         }
142 }
143 
144 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
145                                 unsigned int fmt)
146 {
147         struct rk_i2s_dev *i2s = to_info(cpu_dai);
148         unsigned int mask = 0, val = 0;
149 
150         mask = I2S_CKR_MSS_MASK;
151         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
152         case SND_SOC_DAIFMT_CBS_CFS:
153                 /* Set source clock in Master mode */
154                 val = I2S_CKR_MSS_MASTER;
155                 i2s->is_master_mode = true;
156                 break;
157         case SND_SOC_DAIFMT_CBM_CFM:
158                 val = I2S_CKR_MSS_SLAVE;
159                 i2s->is_master_mode = false;
160                 break;
161         default:
162                 return -EINVAL;
163         }
164 
165         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
166 
167         mask = I2S_TXCR_IBM_MASK;
168         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
169         case SND_SOC_DAIFMT_RIGHT_J:
170                 val = I2S_TXCR_IBM_RSJM;
171                 break;
172         case SND_SOC_DAIFMT_LEFT_J:
173                 val = I2S_TXCR_IBM_LSJM;
174                 break;
175         case SND_SOC_DAIFMT_I2S:
176                 val = I2S_TXCR_IBM_NORMAL;
177                 break;
178         default:
179                 return -EINVAL;
180         }
181 
182         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
183 
184         mask = I2S_RXCR_IBM_MASK;
185         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
186         case SND_SOC_DAIFMT_RIGHT_J:
187                 val = I2S_RXCR_IBM_RSJM;
188                 break;
189         case SND_SOC_DAIFMT_LEFT_J:
190                 val = I2S_RXCR_IBM_LSJM;
191                 break;
192         case SND_SOC_DAIFMT_I2S:
193                 val = I2S_RXCR_IBM_NORMAL;
194                 break;
195         default:
196                 return -EINVAL;
197         }
198 
199         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
200 
201         return 0;
202 }
203 
204 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
205                                   struct snd_pcm_hw_params *params,
206                                   struct snd_soc_dai *dai)
207 {
208         struct rk_i2s_dev *i2s = to_info(dai);
209         struct snd_soc_pcm_runtime *rtd = substream->private_data;
210         unsigned int val = 0;
211         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
212 
213         if (i2s->is_master_mode) {
214                 mclk_rate = clk_get_rate(i2s->mclk);
215                 bclk_rate = 2 * 32 * params_rate(params);
216                 if (bclk_rate && mclk_rate % bclk_rate)
217                         return -EINVAL;
218 
219                 div_bclk = mclk_rate / bclk_rate;
220                 div_lrck = bclk_rate / params_rate(params);
221                 regmap_update_bits(i2s->regmap, I2S_CKR,
222                                    I2S_CKR_MDIV_MASK,
223                                    I2S_CKR_MDIV(div_bclk));
224 
225                 regmap_update_bits(i2s->regmap, I2S_CKR,
226                                    I2S_CKR_TSD_MASK |
227                                    I2S_CKR_RSD_MASK,
228                                    I2S_CKR_TSD(div_lrck) |
229                                    I2S_CKR_RSD(div_lrck));
230         }
231 
232         switch (params_format(params)) {
233         case SNDRV_PCM_FORMAT_S8:
234                 val |= I2S_TXCR_VDW(8);
235                 break;
236         case SNDRV_PCM_FORMAT_S16_LE:
237                 val |= I2S_TXCR_VDW(16);
238                 break;
239         case SNDRV_PCM_FORMAT_S20_3LE:
240                 val |= I2S_TXCR_VDW(20);
241                 break;
242         case SNDRV_PCM_FORMAT_S24_LE:
243                 val |= I2S_TXCR_VDW(24);
244                 break;
245         case SNDRV_PCM_FORMAT_S32_LE:
246                 val |= I2S_TXCR_VDW(32);
247                 break;
248         default:
249                 return -EINVAL;
250         }
251 
252         switch (params_channels(params)) {
253         case 8:
254                 val |= I2S_CHN_8;
255                 break;
256         case 6:
257                 val |= I2S_CHN_6;
258                 break;
259         case 4:
260                 val |= I2S_CHN_4;
261                 break;
262         case 2:
263                 val |= I2S_CHN_2;
264                 break;
265         default:
266                 dev_err(i2s->dev, "invalid channel: %d\n",
267                         params_channels(params));
268                 return -EINVAL;
269         }
270 
271         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
272                 regmap_update_bits(i2s->regmap, I2S_RXCR,
273                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
274                                    val);
275         else
276                 regmap_update_bits(i2s->regmap, I2S_TXCR,
277                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
278                                    val);
279 
280         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
281                            I2S_DMACR_TDL(16));
282         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
283                            I2S_DMACR_RDL(16));
284 
285         val = I2S_CKR_TRCM_TXRX;
286         if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
287                 val = I2S_CKR_TRCM_TXSHARE;
288 
289         regmap_update_bits(i2s->regmap, I2S_CKR,
290                            I2S_CKR_TRCM_MASK,
291                            val);
292         return 0;
293 }
294 
295 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
296                                 int cmd, struct snd_soc_dai *dai)
297 {
298         struct rk_i2s_dev *i2s = to_info(dai);
299         int ret = 0;
300 
301         switch (cmd) {
302         case SNDRV_PCM_TRIGGER_START:
303         case SNDRV_PCM_TRIGGER_RESUME:
304         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
305                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
306                         rockchip_snd_rxctrl(i2s, 1);
307                 else
308                         rockchip_snd_txctrl(i2s, 1);
309                 break;
310         case SNDRV_PCM_TRIGGER_SUSPEND:
311         case SNDRV_PCM_TRIGGER_STOP:
312         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
313                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
314                         rockchip_snd_rxctrl(i2s, 0);
315                 else
316                         rockchip_snd_txctrl(i2s, 0);
317                 break;
318         default:
319                 ret = -EINVAL;
320                 break;
321         }
322 
323         return ret;
324 }
325 
326 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
327                                    unsigned int freq, int dir)
328 {
329         struct rk_i2s_dev *i2s = to_info(cpu_dai);
330         int ret;
331 
332         ret = clk_set_rate(i2s->mclk, freq);
333         if (ret)
334                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
335 
336         return ret;
337 }
338 
339 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
340 {
341         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
342 
343         dai->capture_dma_data = &i2s->capture_dma_data;
344         dai->playback_dma_data = &i2s->playback_dma_data;
345 
346         return 0;
347 }
348 
349 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
350         .hw_params = rockchip_i2s_hw_params,
351         .set_sysclk = rockchip_i2s_set_sysclk,
352         .set_fmt = rockchip_i2s_set_fmt,
353         .trigger = rockchip_i2s_trigger,
354 };
355 
356 static struct snd_soc_dai_driver rockchip_i2s_dai = {
357         .probe = rockchip_i2s_dai_probe,
358         .playback = {
359                 .stream_name = "Playback",
360                 .channels_min = 2,
361                 .channels_max = 8,
362                 .rates = SNDRV_PCM_RATE_8000_192000,
363                 .formats = (SNDRV_PCM_FMTBIT_S8 |
364                             SNDRV_PCM_FMTBIT_S16_LE |
365                             SNDRV_PCM_FMTBIT_S20_3LE |
366                             SNDRV_PCM_FMTBIT_S24_LE |
367                             SNDRV_PCM_FMTBIT_S32_LE),
368         },
369         .capture = {
370                 .stream_name = "Capture",
371                 .channels_min = 2,
372                 .channels_max = 2,
373                 .rates = SNDRV_PCM_RATE_8000_192000,
374                 .formats = (SNDRV_PCM_FMTBIT_S8 |
375                             SNDRV_PCM_FMTBIT_S16_LE |
376                             SNDRV_PCM_FMTBIT_S20_3LE |
377                             SNDRV_PCM_FMTBIT_S24_LE |
378                             SNDRV_PCM_FMTBIT_S32_LE),
379         },
380         .ops = &rockchip_i2s_dai_ops,
381         .symmetric_rates = 1,
382 };
383 
384 static const struct snd_soc_component_driver rockchip_i2s_component = {
385         .name = DRV_NAME,
386 };
387 
388 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
389 {
390         switch (reg) {
391         case I2S_TXCR:
392         case I2S_RXCR:
393         case I2S_CKR:
394         case I2S_DMACR:
395         case I2S_INTCR:
396         case I2S_XFER:
397         case I2S_CLR:
398         case I2S_TXDR:
399                 return true;
400         default:
401                 return false;
402         }
403 }
404 
405 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
406 {
407         switch (reg) {
408         case I2S_TXCR:
409         case I2S_RXCR:
410         case I2S_CKR:
411         case I2S_DMACR:
412         case I2S_INTCR:
413         case I2S_XFER:
414         case I2S_CLR:
415         case I2S_RXDR:
416         case I2S_FIFOLR:
417         case I2S_INTSR:
418                 return true;
419         default:
420                 return false;
421         }
422 }
423 
424 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
425 {
426         switch (reg) {
427         case I2S_INTSR:
428         case I2S_CLR:
429                 return true;
430         default:
431                 return false;
432         }
433 }
434 
435 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
436 {
437         switch (reg) {
438         default:
439                 return false;
440         }
441 }
442 
443 static const struct regmap_config rockchip_i2s_regmap_config = {
444         .reg_bits = 32,
445         .reg_stride = 4,
446         .val_bits = 32,
447         .max_register = I2S_RXDR,
448         .writeable_reg = rockchip_i2s_wr_reg,
449         .readable_reg = rockchip_i2s_rd_reg,
450         .volatile_reg = rockchip_i2s_volatile_reg,
451         .precious_reg = rockchip_i2s_precious_reg,
452         .cache_type = REGCACHE_FLAT,
453 };
454 
455 static int rockchip_i2s_probe(struct platform_device *pdev)
456 {
457         struct device_node *node = pdev->dev.of_node;
458         struct rk_i2s_dev *i2s;
459         struct snd_soc_dai_driver *soc_dai;
460         struct resource *res;
461         void __iomem *regs;
462         int ret;
463         int val;
464 
465         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
466         if (!i2s) {
467                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
468                 return -ENOMEM;
469         }
470 
471         /* try to prepare related clocks */
472         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
473         if (IS_ERR(i2s->hclk)) {
474                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
475                 return PTR_ERR(i2s->hclk);
476         }
477         ret = clk_prepare_enable(i2s->hclk);
478         if (ret) {
479                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
480                 return ret;
481         }
482 
483         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
484         if (IS_ERR(i2s->mclk)) {
485                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
486                 return PTR_ERR(i2s->mclk);
487         }
488 
489         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490         regs = devm_ioremap_resource(&pdev->dev, res);
491         if (IS_ERR(regs))
492                 return PTR_ERR(regs);
493 
494         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
495                                             &rockchip_i2s_regmap_config);
496         if (IS_ERR(i2s->regmap)) {
497                 dev_err(&pdev->dev,
498                         "Failed to initialise managed register map\n");
499                 return PTR_ERR(i2s->regmap);
500         }
501 
502         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
503         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
504         i2s->playback_dma_data.maxburst = 4;
505 
506         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
507         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
508         i2s->capture_dma_data.maxburst = 4;
509 
510         i2s->dev = &pdev->dev;
511         dev_set_drvdata(&pdev->dev, i2s);
512 
513         pm_runtime_enable(&pdev->dev);
514         if (!pm_runtime_enabled(&pdev->dev)) {
515                 ret = i2s_runtime_resume(&pdev->dev);
516                 if (ret)
517                         goto err_pm_disable;
518         }
519 
520         soc_dai = devm_kzalloc(&pdev->dev,
521                                sizeof(*soc_dai), GFP_KERNEL);
522         if (!soc_dai)
523                 return -ENOMEM;
524 
525         memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
526         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
527                 if (val >= 2 && val <= 8)
528                         soc_dai->playback.channels_max = val;
529         }
530 
531         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
532                 if (val >= 2 && val <= 8)
533                         soc_dai->capture.channels_max = val;
534         }
535 
536         ret = devm_snd_soc_register_component(&pdev->dev,
537                                               &rockchip_i2s_component,
538                                               soc_dai, 1);
539 
540         if (ret) {
541                 dev_err(&pdev->dev, "Could not register DAI\n");
542                 goto err_suspend;
543         }
544 
545         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
546         if (ret) {
547                 dev_err(&pdev->dev, "Could not register PCM\n");
548                 return ret;
549         }
550 
551         return 0;
552 
553 err_suspend:
554         if (!pm_runtime_status_suspended(&pdev->dev))
555                 i2s_runtime_suspend(&pdev->dev);
556 err_pm_disable:
557         pm_runtime_disable(&pdev->dev);
558 
559         return ret;
560 }
561 
562 static int rockchip_i2s_remove(struct platform_device *pdev)
563 {
564         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
565 
566         pm_runtime_disable(&pdev->dev);
567         if (!pm_runtime_status_suspended(&pdev->dev))
568                 i2s_runtime_suspend(&pdev->dev);
569 
570         clk_disable_unprepare(i2s->mclk);
571         clk_disable_unprepare(i2s->hclk);
572 
573         return 0;
574 }
575 
576 static const struct of_device_id rockchip_i2s_match[] = {
577         { .compatible = "rockchip,rk3066-i2s", },
578         {},
579 };
580 
581 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
582         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
583                            NULL)
584 };
585 
586 static struct platform_driver rockchip_i2s_driver = {
587         .probe = rockchip_i2s_probe,
588         .remove = rockchip_i2s_remove,
589         .driver = {
590                 .name = DRV_NAME,
591                 .of_match_table = of_match_ptr(rockchip_i2s_match),
592                 .pm = &rockchip_i2s_pm_ops,
593         },
594 };
595 module_platform_driver(rockchip_i2s_driver);
596 
597 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
598 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
599 MODULE_LICENSE("GPL v2");
600 MODULE_ALIAS("platform:" DRV_NAME);
601 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
602 

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