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Linux/sound/soc/stm/stm32_sai_sub.c

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  1 /*
  2  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
  3  *
  4  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  5  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
  6  *
  7  * License terms: GPL V2.0.
  8  *
  9  * This program is free software; you can redistribute it and/or modify it
 10  * under the terms of the GNU General Public License version 2 as published by
 11  * the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
 16  * details.
 17  */
 18 
 19 #include <linux/clk.h>
 20 #include <linux/clk-provider.h>
 21 #include <linux/kernel.h>
 22 #include <linux/module.h>
 23 #include <linux/of_irq.h>
 24 #include <linux/of_platform.h>
 25 #include <linux/regmap.h>
 26 
 27 #include <sound/asoundef.h>
 28 #include <sound/core.h>
 29 #include <sound/dmaengine_pcm.h>
 30 #include <sound/pcm_params.h>
 31 
 32 #include "stm32_sai.h"
 33 
 34 #define SAI_FREE_PROTOCOL       0x0
 35 #define SAI_SPDIF_PROTOCOL      0x1
 36 
 37 #define SAI_SLOT_SIZE_AUTO      0x0
 38 #define SAI_SLOT_SIZE_16        0x1
 39 #define SAI_SLOT_SIZE_32        0x2
 40 
 41 #define SAI_DATASIZE_8          0x2
 42 #define SAI_DATASIZE_10         0x3
 43 #define SAI_DATASIZE_16         0x4
 44 #define SAI_DATASIZE_20         0x5
 45 #define SAI_DATASIZE_24         0x6
 46 #define SAI_DATASIZE_32         0x7
 47 
 48 #define STM_SAI_FIFO_SIZE       8
 49 #define STM_SAI_DAI_NAME_SIZE   15
 50 
 51 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
 52 #define STM_SAI_IS_CAPTURE(ip)  ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
 53 
 54 #define STM_SAI_A_ID            0x0
 55 #define STM_SAI_B_ID            0x1
 56 
 57 #define STM_SAI_IS_SUB_A(x)     ((x)->id == STM_SAI_A_ID)
 58 #define STM_SAI_IS_SUB_B(x)     ((x)->id == STM_SAI_B_ID)
 59 #define STM_SAI_BLOCK_NAME(x)   (((x)->id == STM_SAI_A_ID) ? "A" : "B")
 60 
 61 #define SAI_SYNC_NONE           0x0
 62 #define SAI_SYNC_INTERNAL       0x1
 63 #define SAI_SYNC_EXTERNAL       0x2
 64 
 65 #define STM_SAI_PROTOCOL_IS_SPDIF(ip)   ((ip)->spdif)
 66 #define STM_SAI_HAS_SPDIF(x)    ((x)->pdata->conf->has_spdif)
 67 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
 68 
 69 #define SAI_IEC60958_BLOCK_FRAMES       192
 70 #define SAI_IEC60958_STATUS_BYTES       24
 71 
 72 #define SAI_MCLK_NAME_LEN               32
 73 
 74 /**
 75  * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
 76  * @pdev: device data pointer
 77  * @regmap: SAI register map pointer
 78  * @regmap_config: SAI sub block register map configuration pointer
 79  * @dma_params: dma configuration data for rx or tx channel
 80  * @cpu_dai_drv: DAI driver data pointer
 81  * @cpu_dai: DAI runtime data pointer
 82  * @substream: PCM substream data pointer
 83  * @pdata: SAI block parent data pointer
 84  * @np_sync_provider: synchronization provider node
 85  * @sai_ck: kernel clock feeding the SAI clock generator
 86  * @sai_mclk: master clock from SAI mclk provider
 87  * @phys_addr: SAI registers physical base address
 88  * @mclk_rate: SAI block master clock frequency (Hz). set at init
 89  * @id: SAI sub block id corresponding to sub-block A or B
 90  * @dir: SAI block direction (playback or capture). set at init
 91  * @master: SAI block mode flag. (true=master, false=slave) set at init
 92  * @spdif: SAI S/PDIF iec60958 mode flag. set at init
 93  * @fmt: SAI block format. relevant only for custom protocols. set at init
 94  * @sync: SAI block synchronization mode. (none, internal or external)
 95  * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
 96  * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
 97  * @fs_length: frame synchronization length. depends on protocol settings
 98  * @slots: rx or tx slot number
 99  * @slot_width: rx or tx slot width in bits
100  * @slot_mask: rx or tx active slots mask. set at init or at runtime
101  * @data_size: PCM data width. corresponds to PCM substream width.
102  * @spdif_frm_cnt: S/PDIF playback frame counter
103  * @snd_aes_iec958: iec958 data
104  * @ctrl_lock: control lock
105  */
106 struct stm32_sai_sub_data {
107         struct platform_device *pdev;
108         struct regmap *regmap;
109         const struct regmap_config *regmap_config;
110         struct snd_dmaengine_dai_dma_data dma_params;
111         struct snd_soc_dai_driver *cpu_dai_drv;
112         struct snd_soc_dai *cpu_dai;
113         struct snd_pcm_substream *substream;
114         struct stm32_sai_data *pdata;
115         struct device_node *np_sync_provider;
116         struct clk *sai_ck;
117         struct clk *sai_mclk;
118         dma_addr_t phys_addr;
119         unsigned int mclk_rate;
120         unsigned int id;
121         int dir;
122         bool master;
123         bool spdif;
124         int fmt;
125         int sync;
126         int synco;
127         int synci;
128         int fs_length;
129         int slots;
130         int slot_width;
131         int slot_mask;
132         int data_size;
133         unsigned int spdif_frm_cnt;
134         struct snd_aes_iec958 iec958;
135         struct mutex ctrl_lock; /* protect resources accessed by controls */
136 };
137 
138 enum stm32_sai_fifo_th {
139         STM_SAI_FIFO_TH_EMPTY,
140         STM_SAI_FIFO_TH_QUARTER,
141         STM_SAI_FIFO_TH_HALF,
142         STM_SAI_FIFO_TH_3_QUARTER,
143         STM_SAI_FIFO_TH_FULL,
144 };
145 
146 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
147 {
148         switch (reg) {
149         case STM_SAI_CR1_REGX:
150         case STM_SAI_CR2_REGX:
151         case STM_SAI_FRCR_REGX:
152         case STM_SAI_SLOTR_REGX:
153         case STM_SAI_IMR_REGX:
154         case STM_SAI_SR_REGX:
155         case STM_SAI_CLRFR_REGX:
156         case STM_SAI_DR_REGX:
157         case STM_SAI_PDMCR_REGX:
158         case STM_SAI_PDMLY_REGX:
159                 return true;
160         default:
161                 return false;
162         }
163 }
164 
165 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
166 {
167         switch (reg) {
168         case STM_SAI_DR_REGX:
169                 return true;
170         default:
171                 return false;
172         }
173 }
174 
175 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
176 {
177         switch (reg) {
178         case STM_SAI_CR1_REGX:
179         case STM_SAI_CR2_REGX:
180         case STM_SAI_FRCR_REGX:
181         case STM_SAI_SLOTR_REGX:
182         case STM_SAI_IMR_REGX:
183         case STM_SAI_SR_REGX:
184         case STM_SAI_CLRFR_REGX:
185         case STM_SAI_DR_REGX:
186         case STM_SAI_PDMCR_REGX:
187         case STM_SAI_PDMLY_REGX:
188                 return true;
189         default:
190                 return false;
191         }
192 }
193 
194 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
195         .reg_bits = 32,
196         .reg_stride = 4,
197         .val_bits = 32,
198         .max_register = STM_SAI_DR_REGX,
199         .readable_reg = stm32_sai_sub_readable_reg,
200         .volatile_reg = stm32_sai_sub_volatile_reg,
201         .writeable_reg = stm32_sai_sub_writeable_reg,
202         .fast_io = true,
203 };
204 
205 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
206         .reg_bits = 32,
207         .reg_stride = 4,
208         .val_bits = 32,
209         .max_register = STM_SAI_PDMLY_REGX,
210         .readable_reg = stm32_sai_sub_readable_reg,
211         .volatile_reg = stm32_sai_sub_volatile_reg,
212         .writeable_reg = stm32_sai_sub_writeable_reg,
213         .fast_io = true,
214 };
215 
216 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
217                                struct snd_ctl_elem_info *uinfo)
218 {
219         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
220         uinfo->count = 1;
221 
222         return 0;
223 }
224 
225 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
226                               struct snd_ctl_elem_value *uctl)
227 {
228         struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
229 
230         mutex_lock(&sai->ctrl_lock);
231         memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
232         mutex_unlock(&sai->ctrl_lock);
233 
234         return 0;
235 }
236 
237 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
238                               struct snd_ctl_elem_value *uctl)
239 {
240         struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
241 
242         mutex_lock(&sai->ctrl_lock);
243         memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
244         mutex_unlock(&sai->ctrl_lock);
245 
246         return 0;
247 }
248 
249 static const struct snd_kcontrol_new iec958_ctls = {
250         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
251                         SNDRV_CTL_ELEM_ACCESS_VOLATILE),
252         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
253         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
254         .info = snd_pcm_iec958_info,
255         .get = snd_pcm_iec958_get,
256         .put = snd_pcm_iec958_put,
257 };
258 
259 struct stm32_sai_mclk_data {
260         struct clk_hw hw;
261         unsigned long freq;
262         struct stm32_sai_sub_data *sai_data;
263 };
264 
265 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
266 #define STM32_SAI_MAX_CLKS 1
267 
268 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
269                                  unsigned long input_rate,
270                                  unsigned long output_rate)
271 {
272         int version = sai->pdata->conf->version;
273         int div;
274 
275         div = DIV_ROUND_CLOSEST(input_rate, output_rate);
276         if (div > SAI_XCR1_MCKDIV_MAX(version)) {
277                 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
278                 return -EINVAL;
279         }
280         dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
281 
282         if (input_rate % div)
283                 dev_dbg(&sai->pdev->dev,
284                         "Rate not accurate. requested (%ld), actual (%ld)\n",
285                         output_rate, input_rate / div);
286 
287         return div;
288 }
289 
290 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
291                                  unsigned int div)
292 {
293         int version = sai->pdata->conf->version;
294         int ret, cr1, mask;
295 
296         if (div > SAI_XCR1_MCKDIV_MAX(version)) {
297                 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
298                 return -EINVAL;
299         }
300 
301         mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
302         cr1 = SAI_XCR1_MCKDIV_SET(div);
303         ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
304         if (ret < 0)
305                 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
306 
307         return ret;
308 }
309 
310 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
311                                       unsigned long *prate)
312 {
313         struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
314         struct stm32_sai_sub_data *sai = mclk->sai_data;
315         int div;
316 
317         div = stm32_sai_get_clk_div(sai, *prate, rate);
318         if (div < 0)
319                 return div;
320 
321         mclk->freq = *prate / div;
322 
323         return mclk->freq;
324 }
325 
326 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
327                                                 unsigned long parent_rate)
328 {
329         struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
330 
331         return mclk->freq;
332 }
333 
334 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
335                                    unsigned long parent_rate)
336 {
337         struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
338         struct stm32_sai_sub_data *sai = mclk->sai_data;
339         unsigned int div;
340         int ret;
341 
342         div = stm32_sai_get_clk_div(sai, parent_rate, rate);
343         if (div < 0)
344                 return div;
345 
346         ret = stm32_sai_set_clk_div(sai, div);
347         if (ret)
348                 return ret;
349 
350         mclk->freq = rate;
351 
352         return 0;
353 }
354 
355 static int stm32_sai_mclk_enable(struct clk_hw *hw)
356 {
357         struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
358         struct stm32_sai_sub_data *sai = mclk->sai_data;
359 
360         dev_dbg(&sai->pdev->dev, "Enable master clock\n");
361 
362         return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
363                                   SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
364 }
365 
366 static void stm32_sai_mclk_disable(struct clk_hw *hw)
367 {
368         struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
369         struct stm32_sai_sub_data *sai = mclk->sai_data;
370 
371         dev_dbg(&sai->pdev->dev, "Disable master clock\n");
372 
373         regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
374 }
375 
376 static const struct clk_ops mclk_ops = {
377         .enable = stm32_sai_mclk_enable,
378         .disable = stm32_sai_mclk_disable,
379         .recalc_rate = stm32_sai_mclk_recalc_rate,
380         .round_rate = stm32_sai_mclk_round_rate,
381         .set_rate = stm32_sai_mclk_set_rate,
382 };
383 
384 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
385 {
386         struct clk_hw *hw;
387         struct stm32_sai_mclk_data *mclk;
388         struct device *dev = &sai->pdev->dev;
389         const char *pname = __clk_get_name(sai->sai_ck);
390         char *mclk_name, *p, *s = (char *)pname;
391         int ret, i = 0;
392 
393         mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
394         if (!mclk)
395                 return -ENOMEM;
396 
397         mclk_name = devm_kcalloc(dev, sizeof(char),
398                                  SAI_MCLK_NAME_LEN, GFP_KERNEL);
399         if (!mclk_name)
400                 return -ENOMEM;
401 
402         /*
403          * Forge mclk clock name from parent clock name and suffix.
404          * String after "_" char is stripped in parent name.
405          */
406         p = mclk_name;
407         while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
408                 *p++ = *s++;
409                 i++;
410         }
411         STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
412 
413         mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
414         mclk->sai_data = sai;
415         hw = &mclk->hw;
416 
417         dev_dbg(dev, "Register master clock %s\n", mclk_name);
418         ret = devm_clk_hw_register(&sai->pdev->dev, hw);
419         if (ret) {
420                 dev_err(dev, "mclk register returned %d\n", ret);
421                 return ret;
422         }
423         sai->sai_mclk = hw->clk;
424 
425         /* register mclk provider */
426         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
427 }
428 
429 static irqreturn_t stm32_sai_isr(int irq, void *devid)
430 {
431         struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
432         struct platform_device *pdev = sai->pdev;
433         unsigned int sr, imr, flags;
434         snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
435 
436         regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
437         regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
438 
439         flags = sr & imr;
440         if (!flags)
441                 return IRQ_NONE;
442 
443         regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
444                            SAI_XCLRFR_MASK);
445 
446         if (!sai->substream) {
447                 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
448                 return IRQ_NONE;
449         }
450 
451         if (flags & SAI_XIMR_OVRUDRIE) {
452                 dev_err(&pdev->dev, "IRQ %s\n",
453                         STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
454                 status = SNDRV_PCM_STATE_XRUN;
455         }
456 
457         if (flags & SAI_XIMR_MUTEDETIE)
458                 dev_dbg(&pdev->dev, "IRQ mute detected\n");
459 
460         if (flags & SAI_XIMR_WCKCFGIE) {
461                 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
462                 status = SNDRV_PCM_STATE_DISCONNECTED;
463         }
464 
465         if (flags & SAI_XIMR_CNRDYIE)
466                 dev_err(&pdev->dev, "IRQ Codec not ready\n");
467 
468         if (flags & SAI_XIMR_AFSDETIE) {
469                 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
470                 status = SNDRV_PCM_STATE_XRUN;
471         }
472 
473         if (flags & SAI_XIMR_LFSDETIE) {
474                 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
475                 status = SNDRV_PCM_STATE_XRUN;
476         }
477 
478         if (status != SNDRV_PCM_STATE_RUNNING)
479                 snd_pcm_stop_xrun(sai->substream);
480 
481         return IRQ_HANDLED;
482 }
483 
484 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
485                                 int clk_id, unsigned int freq, int dir)
486 {
487         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
488         int ret;
489 
490         if (dir == SND_SOC_CLOCK_OUT) {
491                 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
492                                          SAI_XCR1_NODIV,
493                                          (unsigned int)~SAI_XCR1_NODIV);
494                 if (ret < 0)
495                         return ret;
496 
497                 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
498                 sai->mclk_rate = freq;
499 
500                 if (sai->sai_mclk) {
501                         ret = clk_set_rate_exclusive(sai->sai_mclk,
502                                                      sai->mclk_rate);
503                         if (ret) {
504                                 dev_err(cpu_dai->dev,
505                                         "Could not set mclk rate\n");
506                                 return ret;
507                         }
508                 }
509         }
510 
511         return 0;
512 }
513 
514 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
515                                       u32 rx_mask, int slots, int slot_width)
516 {
517         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
518         int slotr, slotr_mask, slot_size;
519 
520         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
521                 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
522                 return 0;
523         }
524 
525         dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
526                 tx_mask, rx_mask, slots, slot_width);
527 
528         switch (slot_width) {
529         case 16:
530                 slot_size = SAI_SLOT_SIZE_16;
531                 break;
532         case 32:
533                 slot_size = SAI_SLOT_SIZE_32;
534                 break;
535         default:
536                 slot_size = SAI_SLOT_SIZE_AUTO;
537                 break;
538         }
539 
540         slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
541                 SAI_XSLOTR_NBSLOT_SET(slots - 1);
542         slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
543 
544         /* tx/rx mask set in machine init, if slot number defined in DT */
545         if (STM_SAI_IS_PLAYBACK(sai)) {
546                 sai->slot_mask = tx_mask;
547                 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
548         }
549 
550         if (STM_SAI_IS_CAPTURE(sai)) {
551                 sai->slot_mask = rx_mask;
552                 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
553         }
554 
555         slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
556 
557         regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
558 
559         sai->slot_width = slot_width;
560         sai->slots = slots;
561 
562         return 0;
563 }
564 
565 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
566 {
567         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
568         int cr1, frcr = 0;
569         int cr1_mask, frcr_mask = 0;
570         int ret;
571 
572         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
573 
574         /* Do not generate master by default */
575         cr1 = SAI_XCR1_NODIV;
576         cr1_mask = SAI_XCR1_NODIV;
577 
578         cr1_mask |= SAI_XCR1_PRTCFG_MASK;
579         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
580                 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
581                 goto conf_update;
582         }
583 
584         cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
585 
586         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
587         /* SCK active high for all protocols */
588         case SND_SOC_DAIFMT_I2S:
589                 cr1 |= SAI_XCR1_CKSTR;
590                 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
591                 break;
592         /* Left justified */
593         case SND_SOC_DAIFMT_MSB:
594                 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
595                 break;
596         /* Right justified */
597         case SND_SOC_DAIFMT_LSB:
598                 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
599                 break;
600         case SND_SOC_DAIFMT_DSP_A:
601                 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
602                 break;
603         case SND_SOC_DAIFMT_DSP_B:
604                 frcr |= SAI_XFRCR_FSPOL;
605                 break;
606         default:
607                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
608                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
609                 return -EINVAL;
610         }
611 
612         cr1_mask |= SAI_XCR1_CKSTR;
613         frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
614                      SAI_XFRCR_FSDEF;
615 
616         /* DAI clock strobing. Invert setting previously set */
617         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
618         case SND_SOC_DAIFMT_NB_NF:
619                 break;
620         case SND_SOC_DAIFMT_IB_NF:
621                 cr1 ^= SAI_XCR1_CKSTR;
622                 break;
623         case SND_SOC_DAIFMT_NB_IF:
624                 frcr ^= SAI_XFRCR_FSPOL;
625                 break;
626         case SND_SOC_DAIFMT_IB_IF:
627                 /* Invert fs & sck */
628                 cr1 ^= SAI_XCR1_CKSTR;
629                 frcr ^= SAI_XFRCR_FSPOL;
630                 break;
631         default:
632                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
633                         fmt & SND_SOC_DAIFMT_INV_MASK);
634                 return -EINVAL;
635         }
636         cr1_mask |= SAI_XCR1_CKSTR;
637         frcr_mask |= SAI_XFRCR_FSPOL;
638 
639         regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
640 
641         /* DAI clock master masks */
642         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
643         case SND_SOC_DAIFMT_CBM_CFM:
644                 /* codec is master */
645                 cr1 |= SAI_XCR1_SLAVE;
646                 sai->master = false;
647                 break;
648         case SND_SOC_DAIFMT_CBS_CFS:
649                 sai->master = true;
650                 break;
651         default:
652                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
653                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
654                 return -EINVAL;
655         }
656 
657         /* Set slave mode if sub-block is synchronized with another SAI */
658         if (sai->sync) {
659                 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
660                 cr1 |= SAI_XCR1_SLAVE;
661                 sai->master = false;
662         }
663 
664         cr1_mask |= SAI_XCR1_SLAVE;
665 
666 conf_update:
667         ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
668         if (ret < 0) {
669                 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
670                 return ret;
671         }
672 
673         sai->fmt = fmt;
674 
675         return 0;
676 }
677 
678 static int stm32_sai_startup(struct snd_pcm_substream *substream,
679                              struct snd_soc_dai *cpu_dai)
680 {
681         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
682         int imr, cr2, ret;
683 
684         sai->substream = substream;
685 
686         ret = clk_prepare_enable(sai->sai_ck);
687         if (ret < 0) {
688                 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
689                 return ret;
690         }
691 
692         /* Enable ITs */
693 
694         regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
695                            SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
696 
697         imr = SAI_XIMR_OVRUDRIE;
698         if (STM_SAI_IS_CAPTURE(sai)) {
699                 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
700                 if (cr2 & SAI_XCR2_MUTECNT_MASK)
701                         imr |= SAI_XIMR_MUTEDETIE;
702         }
703 
704         if (sai->master)
705                 imr |= SAI_XIMR_WCKCFGIE;
706         else
707                 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
708 
709         regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
710                            SAI_XIMR_MASK, imr);
711 
712         return 0;
713 }
714 
715 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
716                                 struct snd_pcm_substream *substream,
717                                 struct snd_pcm_hw_params *params)
718 {
719         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
720         int cr1, cr1_mask, ret;
721 
722         /*
723          * DMA bursts increment is set to 4 words.
724          * SAI fifo threshold is set to half fifo, to keep enough space
725          * for DMA incoming bursts.
726          */
727         regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
728                            SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
729                            SAI_XCR2_FFLUSH |
730                            SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
731 
732         /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
733         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
734                 sai->spdif_frm_cnt = 0;
735                 return 0;
736         }
737 
738         /* Mode, data format and channel config */
739         cr1_mask = SAI_XCR1_DS_MASK;
740         switch (params_format(params)) {
741         case SNDRV_PCM_FORMAT_S8:
742                 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
743                 break;
744         case SNDRV_PCM_FORMAT_S16_LE:
745                 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
746                 break;
747         case SNDRV_PCM_FORMAT_S32_LE:
748                 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
749                 break;
750         default:
751                 dev_err(cpu_dai->dev, "Data format not supported");
752                 return -EINVAL;
753         }
754 
755         cr1_mask |= SAI_XCR1_MONO;
756         if ((sai->slots == 2) && (params_channels(params) == 1))
757                 cr1 |= SAI_XCR1_MONO;
758 
759         ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
760         if (ret < 0) {
761                 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
762                 return ret;
763         }
764 
765         return 0;
766 }
767 
768 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
769 {
770         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
771         int slotr, slot_sz;
772 
773         regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
774 
775         /*
776          * If SLOTSZ is set to auto in SLOTR, align slot width on data size
777          * By default slot width = data size, if not forced from DT
778          */
779         slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
780         if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
781                 sai->slot_width = sai->data_size;
782 
783         if (sai->slot_width < sai->data_size) {
784                 dev_err(cpu_dai->dev,
785                         "Data size %d larger than slot width\n",
786                         sai->data_size);
787                 return -EINVAL;
788         }
789 
790         /* Slot number is set to 2, if not specified in DT */
791         if (!sai->slots)
792                 sai->slots = 2;
793 
794         /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
795         regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
796                            SAI_XSLOTR_NBSLOT_MASK,
797                            SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
798 
799         /* Set default slots mask if not already set from DT */
800         if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
801                 sai->slot_mask = (1 << sai->slots) - 1;
802                 regmap_update_bits(sai->regmap,
803                                    STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
804                                    SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
805         }
806 
807         dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
808                 sai->slots, sai->slot_width);
809 
810         return 0;
811 }
812 
813 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
814 {
815         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
816         int fs_active, offset, format;
817         int frcr, frcr_mask;
818 
819         format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
820         sai->fs_length = sai->slot_width * sai->slots;
821 
822         fs_active = sai->fs_length / 2;
823         if ((format == SND_SOC_DAIFMT_DSP_A) ||
824             (format == SND_SOC_DAIFMT_DSP_B))
825                 fs_active = 1;
826 
827         frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
828         frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
829         frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
830 
831         dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
832                 sai->fs_length, fs_active);
833 
834         regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
835 
836         if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
837                 offset = sai->slot_width - sai->data_size;
838 
839                 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
840                                    SAI_XSLOTR_FBOFF_MASK,
841                                    SAI_XSLOTR_FBOFF_SET(offset));
842         }
843 }
844 
845 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
846 {
847         unsigned char *cs = sai->iec958.status;
848 
849         cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
850         cs[1] = IEC958_AES1_CON_GENERAL;
851         cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
852         cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
853 }
854 
855 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
856                                         struct snd_pcm_runtime *runtime)
857 {
858         if (!runtime)
859                 return;
860 
861         /* Force the sample rate according to runtime rate */
862         mutex_lock(&sai->ctrl_lock);
863         switch (runtime->rate) {
864         case 22050:
865                 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
866                 break;
867         case 44100:
868                 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
869                 break;
870         case 88200:
871                 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
872                 break;
873         case 176400:
874                 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
875                 break;
876         case 24000:
877                 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
878                 break;
879         case 48000:
880                 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
881                 break;
882         case 96000:
883                 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
884                 break;
885         case 192000:
886                 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
887                 break;
888         case 32000:
889                 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
890                 break;
891         default:
892                 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
893                 break;
894         }
895         mutex_unlock(&sai->ctrl_lock);
896 }
897 
898 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
899                                      struct snd_pcm_hw_params *params)
900 {
901         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
902         int cr1, mask, div = 0;
903         int sai_clk_rate, mclk_ratio, den;
904         unsigned int rate = params_rate(params);
905 
906         if (!(rate % 11025))
907                 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
908         else
909                 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
910         sai_clk_rate = clk_get_rate(sai->sai_ck);
911 
912         if (STM_SAI_IS_F4(sai->pdata)) {
913                 /* mclk on (NODIV=0)
914                  *   mclk_rate = 256 * fs
915                  *   MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
916                  *   MCKDIV = sai_ck / (2 * mclk_rate) otherwise
917                  * mclk off (NODIV=1)
918                  *   MCKDIV ignored. sck = sai_ck
919                  */
920                 if (!sai->mclk_rate)
921                         return 0;
922 
923                 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
924                         div = stm32_sai_get_clk_div(sai, sai_clk_rate,
925                                                     2 * sai->mclk_rate);
926                         if (div < 0)
927                                 return div;
928                 }
929         } else {
930                 /*
931                  * TDM mode :
932                  *   mclk on
933                  *      MCKDIV = sai_ck / (ws x 256)    (NOMCK=0. OSR=0)
934                  *      MCKDIV = sai_ck / (ws x 512)    (NOMCK=0. OSR=1)
935                  *   mclk off
936                  *      MCKDIV = sai_ck / (frl x ws)    (NOMCK=1)
937                  * Note: NOMCK/NODIV correspond to same bit.
938                  */
939                 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
940                         div = stm32_sai_get_clk_div(sai, sai_clk_rate,
941                                                     rate * 128);
942                         if (div < 0)
943                                 return div;
944                 } else {
945                         if (sai->mclk_rate) {
946                                 mclk_ratio = sai->mclk_rate / rate;
947                                 if (mclk_ratio == 512) {
948                                         mask = SAI_XCR1_OSR;
949                                         cr1 = SAI_XCR1_OSR;
950                                 } else if (mclk_ratio != 256) {
951                                         dev_err(cpu_dai->dev,
952                                                 "Wrong mclk ratio %d\n",
953                                                 mclk_ratio);
954                                         return -EINVAL;
955                                 }
956                                 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
957                                                             sai->mclk_rate);
958                                 if (div < 0)
959                                         return div;
960                         } else {
961                                 /* mclk-fs not set, master clock not active */
962                                 den = sai->fs_length * params_rate(params);
963                                 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
964                                                             den);
965                                 if (div < 0)
966                                         return div;
967                         }
968                 }
969         }
970 
971         return stm32_sai_set_clk_div(sai, div);
972 }
973 
974 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
975                                struct snd_pcm_hw_params *params,
976                                struct snd_soc_dai *cpu_dai)
977 {
978         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
979         int ret;
980 
981         sai->data_size = params_width(params);
982 
983         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
984                 /* Rate not already set in runtime structure */
985                 substream->runtime->rate = params_rate(params);
986                 stm32_sai_set_iec958_status(sai, substream->runtime);
987         } else {
988                 ret = stm32_sai_set_slots(cpu_dai);
989                 if (ret < 0)
990                         return ret;
991                 stm32_sai_set_frame(cpu_dai);
992         }
993 
994         ret = stm32_sai_set_config(cpu_dai, substream, params);
995         if (ret)
996                 return ret;
997 
998         if (sai->master)
999                 ret = stm32_sai_configure_clock(cpu_dai, params);
1000 
1001         return ret;
1002 }
1003 
1004 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1005                              struct snd_soc_dai *cpu_dai)
1006 {
1007         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1008         int ret;
1009 
1010         switch (cmd) {
1011         case SNDRV_PCM_TRIGGER_START:
1012         case SNDRV_PCM_TRIGGER_RESUME:
1013         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1014                 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1015 
1016                 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1017                                    SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1018 
1019                 /* Enable SAI */
1020                 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1021                                          SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1022                 if (ret < 0)
1023                         dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1024                 break;
1025         case SNDRV_PCM_TRIGGER_SUSPEND:
1026         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1027         case SNDRV_PCM_TRIGGER_STOP:
1028                 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1029 
1030                 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
1031                                    SAI_XIMR_MASK, 0);
1032 
1033                 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1034                                    SAI_XCR1_SAIEN,
1035                                    (unsigned int)~SAI_XCR1_SAIEN);
1036 
1037                 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1038                                          SAI_XCR1_DMAEN,
1039                                          (unsigned int)~SAI_XCR1_DMAEN);
1040                 if (ret < 0)
1041                         dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1042 
1043                 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1044                         sai->spdif_frm_cnt = 0;
1045                 break;
1046         default:
1047                 return -EINVAL;
1048         }
1049 
1050         return ret;
1051 }
1052 
1053 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1054                                struct snd_soc_dai *cpu_dai)
1055 {
1056         struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1057 
1058         regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1059 
1060         regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
1061                            SAI_XCR1_NODIV);
1062 
1063         clk_disable_unprepare(sai->sai_ck);
1064 
1065         clk_rate_exclusive_put(sai->sai_mclk);
1066 
1067         sai->substream = NULL;
1068 }
1069 
1070 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1071                              struct snd_soc_dai *cpu_dai)
1072 {
1073         struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1074 
1075         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1076                 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1077                 return snd_ctl_add(rtd->pcm->card,
1078                                    snd_ctl_new1(&iec958_ctls, sai));
1079         }
1080 
1081         return 0;
1082 }
1083 
1084 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1085 {
1086         struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1087         int cr1 = 0, cr1_mask;
1088 
1089         sai->cpu_dai = cpu_dai;
1090 
1091         sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1092         /*
1093          * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1094          * as it allows bytes, half-word and words transfers. (See DMA fifos
1095          * constraints).
1096          */
1097         sai->dma_params.maxburst = 4;
1098         /* Buswidth will be set by framework at runtime */
1099         sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1100 
1101         if (STM_SAI_IS_PLAYBACK(sai))
1102                 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1103         else
1104                 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1105 
1106         /* Next settings are not relevant for spdif mode */
1107         if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1108                 return 0;
1109 
1110         cr1_mask = SAI_XCR1_RX_TX;
1111         if (STM_SAI_IS_CAPTURE(sai))
1112                 cr1 |= SAI_XCR1_RX_TX;
1113 
1114         /* Configure synchronization */
1115         if (sai->sync == SAI_SYNC_EXTERNAL) {
1116                 /* Configure synchro client and provider */
1117                 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1118                                      sai->synco, sai->synci);
1119         }
1120 
1121         cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1122         cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1123 
1124         return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
1125 }
1126 
1127 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1128         .set_sysclk     = stm32_sai_set_sysclk,
1129         .set_fmt        = stm32_sai_set_dai_fmt,
1130         .set_tdm_slot   = stm32_sai_set_dai_tdm_slot,
1131         .startup        = stm32_sai_startup,
1132         .hw_params      = stm32_sai_hw_params,
1133         .trigger        = stm32_sai_trigger,
1134         .shutdown       = stm32_sai_shutdown,
1135 };
1136 
1137 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1138                                        int channel, unsigned long hwoff,
1139                                        void *buf, unsigned long bytes)
1140 {
1141         struct snd_pcm_runtime *runtime = substream->runtime;
1142         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1143         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
1144         struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1145         int *ptr = (int *)(runtime->dma_area + hwoff +
1146                            channel * (runtime->dma_bytes / runtime->channels));
1147         ssize_t cnt = bytes_to_samples(runtime, bytes);
1148         unsigned int frm_cnt = sai->spdif_frm_cnt;
1149         unsigned int byte;
1150         unsigned int mask;
1151 
1152         do {
1153                 *ptr = ((*ptr >> 8) & 0x00ffffff);
1154 
1155                 /* Set channel status bit */
1156                 byte = frm_cnt >> 3;
1157                 mask = 1 << (frm_cnt - (byte << 3));
1158                 if (sai->iec958.status[byte] & mask)
1159                         *ptr |= 0x04000000;
1160                 ptr++;
1161 
1162                 if (!(cnt % 2))
1163                         frm_cnt++;
1164 
1165                 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1166                         frm_cnt = 0;
1167         } while (--cnt);
1168         sai->spdif_frm_cnt = frm_cnt;
1169 
1170         return 0;
1171 }
1172 
1173 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1174         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1175         .buffer_bytes_max = 8 * PAGE_SIZE,
1176         .period_bytes_min = 1024, /* 5ms at 48kHz */
1177         .period_bytes_max = PAGE_SIZE,
1178         .periods_min = 2,
1179         .periods_max = 8,
1180 };
1181 
1182 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
1183 {
1184                 .probe = stm32_sai_dai_probe,
1185                 .pcm_new = stm32_sai_pcm_new,
1186                 .id = 1, /* avoid call to fmt_single_name() */
1187                 .playback = {
1188                         .channels_min = 1,
1189                         .channels_max = 2,
1190                         .rate_min = 8000,
1191                         .rate_max = 192000,
1192                         .rates = SNDRV_PCM_RATE_CONTINUOUS,
1193                         /* DMA does not support 24 bits transfers */
1194                         .formats =
1195                                 SNDRV_PCM_FMTBIT_S8 |
1196                                 SNDRV_PCM_FMTBIT_S16_LE |
1197                                 SNDRV_PCM_FMTBIT_S32_LE,
1198                 },
1199                 .ops = &stm32_sai_pcm_dai_ops,
1200         }
1201 };
1202 
1203 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
1204 {
1205                 .probe = stm32_sai_dai_probe,
1206                 .id = 1, /* avoid call to fmt_single_name() */
1207                 .capture = {
1208                         .channels_min = 1,
1209                         .channels_max = 2,
1210                         .rate_min = 8000,
1211                         .rate_max = 192000,
1212                         .rates = SNDRV_PCM_RATE_CONTINUOUS,
1213                         /* DMA does not support 24 bits transfers */
1214                         .formats =
1215                                 SNDRV_PCM_FMTBIT_S8 |
1216                                 SNDRV_PCM_FMTBIT_S16_LE |
1217                                 SNDRV_PCM_FMTBIT_S32_LE,
1218                 },
1219                 .ops = &stm32_sai_pcm_dai_ops,
1220         }
1221 };
1222 
1223 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1224         .pcm_hardware = &stm32_sai_pcm_hw,
1225         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1226 };
1227 
1228 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1229         .pcm_hardware = &stm32_sai_pcm_hw,
1230         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1231         .process = stm32_sai_pcm_process_spdif,
1232 };
1233 
1234 static const struct snd_soc_component_driver stm32_component = {
1235         .name = "stm32-sai",
1236 };
1237 
1238 static const struct of_device_id stm32_sai_sub_ids[] = {
1239         { .compatible = "st,stm32-sai-sub-a",
1240           .data = (void *)STM_SAI_A_ID},
1241         { .compatible = "st,stm32-sai-sub-b",
1242           .data = (void *)STM_SAI_B_ID},
1243         {}
1244 };
1245 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1246 
1247 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1248                                   struct stm32_sai_sub_data *sai)
1249 {
1250         struct device_node *np = pdev->dev.of_node;
1251         struct resource *res;
1252         void __iomem *base;
1253         struct of_phandle_args args;
1254         int ret;
1255 
1256         if (!np)
1257                 return -ENODEV;
1258 
1259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260         base = devm_ioremap_resource(&pdev->dev, res);
1261         if (IS_ERR(base))
1262                 return PTR_ERR(base);
1263 
1264         sai->phys_addr = res->start;
1265 
1266         sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1267         /* Note: PDM registers not available for H7 sub-block B */
1268         if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
1269                 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1270 
1271         sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1272                                                 base, sai->regmap_config);
1273         if (IS_ERR(sai->regmap)) {
1274                 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1275                 return PTR_ERR(sai->regmap);
1276         }
1277 
1278         /* Get direction property */
1279         if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1280                 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1281         } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1282                 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1283         } else {
1284                 dev_err(&pdev->dev, "Unsupported direction\n");
1285                 return -EINVAL;
1286         }
1287 
1288         /* Get spdif iec60958 property */
1289         sai->spdif = false;
1290         if (of_get_property(np, "st,iec60958", NULL)) {
1291                 if (!STM_SAI_HAS_SPDIF(sai) ||
1292                     sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1293                         dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1294                         return -EINVAL;
1295                 }
1296                 stm32_sai_init_iec958_status(sai);
1297                 sai->spdif = true;
1298                 sai->master = true;
1299         }
1300 
1301         /* Get synchronization property */
1302         args.np = NULL;
1303         ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1304         if (ret < 0  && ret != -ENOENT) {
1305                 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1306                 return ret;
1307         }
1308 
1309         sai->sync = SAI_SYNC_NONE;
1310         if (args.np) {
1311                 if (args.np == np) {
1312                         dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1313                         of_node_put(args.np);
1314                         return -EINVAL;
1315                 }
1316 
1317                 sai->np_sync_provider  = of_get_parent(args.np);
1318                 if (!sai->np_sync_provider) {
1319                         dev_err(&pdev->dev, "%pOFn parent node not found\n",
1320                                 np);
1321                         of_node_put(args.np);
1322                         return -ENODEV;
1323                 }
1324 
1325                 sai->sync = SAI_SYNC_INTERNAL;
1326                 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1327                         if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1328                                 dev_err(&pdev->dev,
1329                                         "External synchro not supported\n");
1330                                 of_node_put(args.np);
1331                                 return -EINVAL;
1332                         }
1333                         sai->sync = SAI_SYNC_EXTERNAL;
1334 
1335                         sai->synci = args.args[0];
1336                         if (sai->synci < 1 ||
1337                             (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1338                                 dev_err(&pdev->dev, "Wrong SAI index\n");
1339                                 of_node_put(args.np);
1340                                 return -EINVAL;
1341                         }
1342 
1343                         if (of_property_match_string(args.np, "compatible",
1344                                                      "st,stm32-sai-sub-a") >= 0)
1345                                 sai->synco = STM_SAI_SYNC_OUT_A;
1346 
1347                         if (of_property_match_string(args.np, "compatible",
1348                                                      "st,stm32-sai-sub-b") >= 0)
1349                                 sai->synco = STM_SAI_SYNC_OUT_B;
1350 
1351                         if (!sai->synco) {
1352                                 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1353                                 of_node_put(args.np);
1354                                 return -EINVAL;
1355                         }
1356                 }
1357 
1358                 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1359                         pdev->name, args.np->full_name);
1360         }
1361 
1362         of_node_put(args.np);
1363         sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1364         if (IS_ERR(sai->sai_ck)) {
1365                 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1366                 return PTR_ERR(sai->sai_ck);
1367         }
1368 
1369         if (STM_SAI_IS_F4(sai->pdata))
1370                 return 0;
1371 
1372         /* Register mclk provider if requested */
1373         if (of_find_property(np, "#clock-cells", NULL)) {
1374                 ret = stm32_sai_add_mclk_provider(sai);
1375                 if (ret < 0)
1376                         return ret;
1377         } else {
1378                 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
1379                 if (IS_ERR(sai->sai_mclk)) {
1380                         if (PTR_ERR(sai->sai_mclk) != -ENOENT)
1381                                 return PTR_ERR(sai->sai_mclk);
1382                         sai->sai_mclk = NULL;
1383                 }
1384         }
1385 
1386         return 0;
1387 }
1388 
1389 static int stm32_sai_sub_dais_init(struct platform_device *pdev,
1390                                    struct stm32_sai_sub_data *sai)
1391 {
1392         sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
1393                                         sizeof(struct snd_soc_dai_driver),
1394                                         GFP_KERNEL);
1395         if (!sai->cpu_dai_drv)
1396                 return -ENOMEM;
1397 
1398         sai->cpu_dai_drv->name = dev_name(&pdev->dev);
1399         if (STM_SAI_IS_PLAYBACK(sai)) {
1400                 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
1401                        sizeof(stm32_sai_playback_dai));
1402                 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
1403         } else {
1404                 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
1405                        sizeof(stm32_sai_capture_dai));
1406                 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
1407         }
1408 
1409         return 0;
1410 }
1411 
1412 static int stm32_sai_sub_probe(struct platform_device *pdev)
1413 {
1414         struct stm32_sai_sub_data *sai;
1415         const struct of_device_id *of_id;
1416         const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1417         int ret;
1418 
1419         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1420         if (!sai)
1421                 return -ENOMEM;
1422 
1423         of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1424         if (!of_id)
1425                 return -EINVAL;
1426         sai->id = (uintptr_t)of_id->data;
1427 
1428         sai->pdev = pdev;
1429         mutex_init(&sai->ctrl_lock);
1430         platform_set_drvdata(pdev, sai);
1431 
1432         sai->pdata = dev_get_drvdata(pdev->dev.parent);
1433         if (!sai->pdata) {
1434                 dev_err(&pdev->dev, "Parent device data not available\n");
1435                 return -EINVAL;
1436         }
1437 
1438         ret = stm32_sai_sub_parse_of(pdev, sai);
1439         if (ret)
1440                 return ret;
1441 
1442         ret = stm32_sai_sub_dais_init(pdev, sai);
1443         if (ret)
1444                 return ret;
1445 
1446         ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1447                                IRQF_SHARED, dev_name(&pdev->dev), sai);
1448         if (ret) {
1449                 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1450                 return ret;
1451         }
1452 
1453         ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1454                                               sai->cpu_dai_drv, 1);
1455         if (ret)
1456                 return ret;
1457 
1458         if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1459                 conf = &stm32_sai_pcm_config_spdif;
1460 
1461         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1462         if (ret) {
1463                 dev_err(&pdev->dev, "Could not register pcm dma\n");
1464                 return ret;
1465         }
1466 
1467         return 0;
1468 }
1469 
1470 static struct platform_driver stm32_sai_sub_driver = {
1471         .driver = {
1472                 .name = "st,stm32-sai-sub",
1473                 .of_match_table = stm32_sai_sub_ids,
1474         },
1475         .probe = stm32_sai_sub_probe,
1476 };
1477 
1478 module_platform_driver(stm32_sai_sub_driver);
1479 
1480 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1481 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1482 MODULE_ALIAS("platform:st,stm32-sai-sub");
1483 MODULE_LICENSE("GPL v2");
1484 

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