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Linux/sound/soc/tegra/tegra30_i2s.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * tegra30_i2s.c - Tegra30 I2S driver
  4  *
  5  * Author: Stephen Warren <swarren@nvidia.com>
  6  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
  7  *
  8  * Based on code copyright/by:
  9  *
 10  * Copyright (c) 2009-2010, NVIDIA Corporation.
 11  * Scott Peterson <speterson@nvidia.com>
 12  *
 13  * Copyright (C) 2010 Google, Inc.
 14  * Iliyan Malchev <malchev@google.com>
 15  */
 16 
 17 #include <linux/clk.h>
 18 #include <linux/device.h>
 19 #include <linux/io.h>
 20 #include <linux/module.h>
 21 #include <linux/of.h>
 22 #include <linux/of_device.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/pm_runtime.h>
 25 #include <linux/regmap.h>
 26 #include <linux/slab.h>
 27 #include <sound/core.h>
 28 #include <sound/pcm.h>
 29 #include <sound/pcm_params.h>
 30 #include <sound/soc.h>
 31 #include <sound/dmaengine_pcm.h>
 32 
 33 #include "tegra30_ahub.h"
 34 #include "tegra30_i2s.h"
 35 
 36 #define DRV_NAME "tegra30-i2s"
 37 
 38 static int tegra30_i2s_runtime_suspend(struct device *dev)
 39 {
 40         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 41 
 42         regcache_cache_only(i2s->regmap, true);
 43 
 44         clk_disable_unprepare(i2s->clk_i2s);
 45 
 46         return 0;
 47 }
 48 
 49 static int tegra30_i2s_runtime_resume(struct device *dev)
 50 {
 51         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 52         int ret;
 53 
 54         ret = clk_prepare_enable(i2s->clk_i2s);
 55         if (ret) {
 56                 dev_err(dev, "clk_enable failed: %d\n", ret);
 57                 return ret;
 58         }
 59 
 60         regcache_cache_only(i2s->regmap, false);
 61 
 62         return 0;
 63 }
 64 
 65 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 66                                 unsigned int fmt)
 67 {
 68         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 69         unsigned int mask = 0, val = 0;
 70 
 71         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 72         case SND_SOC_DAIFMT_NB_NF:
 73                 break;
 74         default:
 75                 return -EINVAL;
 76         }
 77 
 78         mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
 79         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 80         case SND_SOC_DAIFMT_CBS_CFS:
 81                 val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
 82                 break;
 83         case SND_SOC_DAIFMT_CBM_CFM:
 84                 break;
 85         default:
 86                 return -EINVAL;
 87         }
 88 
 89         mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
 90                 TEGRA30_I2S_CTRL_LRCK_MASK;
 91         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 92         case SND_SOC_DAIFMT_DSP_A:
 93                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 94                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 95                 break;
 96         case SND_SOC_DAIFMT_DSP_B:
 97                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 98                 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
 99                 break;
100         case SND_SOC_DAIFMT_I2S:
101                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
102                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
103                 break;
104         case SND_SOC_DAIFMT_RIGHT_J:
105                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
106                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
107                 break;
108         case SND_SOC_DAIFMT_LEFT_J:
109                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
110                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
111                 break;
112         default:
113                 return -EINVAL;
114         }
115 
116         pm_runtime_get_sync(dai->dev);
117         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
118         pm_runtime_put(dai->dev);
119 
120         return 0;
121 }
122 
123 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
124                                  struct snd_pcm_hw_params *params,
125                                  struct snd_soc_dai *dai)
126 {
127         struct device *dev = dai->dev;
128         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
129         unsigned int mask, val, reg;
130         int ret, sample_size, srate, i2sclock, bitcnt;
131         struct tegra30_ahub_cif_conf cif_conf;
132 
133         if (params_channels(params) != 2)
134                 return -EINVAL;
135 
136         mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
137         switch (params_format(params)) {
138         case SNDRV_PCM_FORMAT_S16_LE:
139                 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
140                 sample_size = 16;
141                 break;
142         default:
143                 return -EINVAL;
144         }
145 
146         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
147 
148         srate = params_rate(params);
149 
150         /* Final "* 2" required by Tegra hardware */
151         i2sclock = srate * params_channels(params) * sample_size * 2;
152 
153         bitcnt = (i2sclock / (2 * srate)) - 1;
154         if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
155                 return -EINVAL;
156 
157         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
158         if (ret) {
159                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
160                 return ret;
161         }
162 
163         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
164 
165         if (i2sclock % (2 * srate))
166                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
167 
168         regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
169 
170         cif_conf.threshold = 0;
171         cif_conf.audio_channels = 2;
172         cif_conf.client_channels = 2;
173         cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
174         cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
175         cif_conf.expand = 0;
176         cif_conf.stereo_conv = 0;
177         cif_conf.replicate = 0;
178         cif_conf.truncate = 0;
179         cif_conf.mono_conv = 0;
180 
181         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
182                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
183                 reg = TEGRA30_I2S_CIF_RX_CTRL;
184         } else {
185                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
186                 reg = TEGRA30_I2S_CIF_TX_CTRL;
187         }
188 
189         i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
190 
191         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
192               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
193         regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
194 
195         return 0;
196 }
197 
198 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
199 {
200         tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
201         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
202                            TEGRA30_I2S_CTRL_XFER_EN_TX,
203                            TEGRA30_I2S_CTRL_XFER_EN_TX);
204 }
205 
206 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
207 {
208         tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
209         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
210                            TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
211 }
212 
213 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
214 {
215         tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
216         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
217                            TEGRA30_I2S_CTRL_XFER_EN_RX,
218                            TEGRA30_I2S_CTRL_XFER_EN_RX);
219 }
220 
221 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
222 {
223         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
224                            TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
225         tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
226 }
227 
228 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
229                                 struct snd_soc_dai *dai)
230 {
231         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
232 
233         switch (cmd) {
234         case SNDRV_PCM_TRIGGER_START:
235         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
236         case SNDRV_PCM_TRIGGER_RESUME:
237                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
238                         tegra30_i2s_start_playback(i2s);
239                 else
240                         tegra30_i2s_start_capture(i2s);
241                 break;
242         case SNDRV_PCM_TRIGGER_STOP:
243         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
244         case SNDRV_PCM_TRIGGER_SUSPEND:
245                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
246                         tegra30_i2s_stop_playback(i2s);
247                 else
248                         tegra30_i2s_stop_capture(i2s);
249                 break;
250         default:
251                 return -EINVAL;
252         }
253 
254         return 0;
255 }
256 
257 static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai,
258                                unsigned int tx_mask, unsigned int rx_mask,
259                                int slots, int slot_width)
260 {
261         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
262         unsigned int mask, val;
263 
264         dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n",
265                  __func__, tx_mask, rx_mask, slots, slot_width);
266 
267         mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK |
268                TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK |
269                TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
270 
271         val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
272               (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) |
273               ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT);
274 
275         pm_runtime_get_sync(dai->dev);
276         regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
277         /* set the fsync width to minimum of 1 clock width */
278         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
279                            TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0);
280         pm_runtime_put(dai->dev);
281 
282         return 0;
283 }
284 
285 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
286 {
287         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
288 
289         dai->capture_dma_data = &i2s->capture_dma_data;
290         dai->playback_dma_data = &i2s->playback_dma_data;
291 
292         return 0;
293 }
294 
295 static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
296         .set_fmt        = tegra30_i2s_set_fmt,
297         .hw_params      = tegra30_i2s_hw_params,
298         .trigger        = tegra30_i2s_trigger,
299         .set_tdm_slot   = tegra30_i2s_set_tdm,
300 };
301 
302 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
303         .probe = tegra30_i2s_probe,
304         .playback = {
305                 .stream_name = "Playback",
306                 .channels_min = 2,
307                 .channels_max = 2,
308                 .rates = SNDRV_PCM_RATE_8000_96000,
309                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
310         },
311         .capture = {
312                 .stream_name = "Capture",
313                 .channels_min = 2,
314                 .channels_max = 2,
315                 .rates = SNDRV_PCM_RATE_8000_96000,
316                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
317         },
318         .ops = &tegra30_i2s_dai_ops,
319         .symmetric_rates = 1,
320 };
321 
322 static const struct snd_soc_component_driver tegra30_i2s_component = {
323         .name           = DRV_NAME,
324 };
325 
326 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
327 {
328         switch (reg) {
329         case TEGRA30_I2S_CTRL:
330         case TEGRA30_I2S_TIMING:
331         case TEGRA30_I2S_OFFSET:
332         case TEGRA30_I2S_CH_CTRL:
333         case TEGRA30_I2S_SLOT_CTRL:
334         case TEGRA30_I2S_CIF_RX_CTRL:
335         case TEGRA30_I2S_CIF_TX_CTRL:
336         case TEGRA30_I2S_FLOWCTL:
337         case TEGRA30_I2S_TX_STEP:
338         case TEGRA30_I2S_FLOW_STATUS:
339         case TEGRA30_I2S_FLOW_TOTAL:
340         case TEGRA30_I2S_FLOW_OVER:
341         case TEGRA30_I2S_FLOW_UNDER:
342         case TEGRA30_I2S_LCOEF_1_4_0:
343         case TEGRA30_I2S_LCOEF_1_4_1:
344         case TEGRA30_I2S_LCOEF_1_4_2:
345         case TEGRA30_I2S_LCOEF_1_4_3:
346         case TEGRA30_I2S_LCOEF_1_4_4:
347         case TEGRA30_I2S_LCOEF_1_4_5:
348         case TEGRA30_I2S_LCOEF_2_4_0:
349         case TEGRA30_I2S_LCOEF_2_4_1:
350         case TEGRA30_I2S_LCOEF_2_4_2:
351                 return true;
352         default:
353                 return false;
354         }
355 }
356 
357 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
358 {
359         switch (reg) {
360         case TEGRA30_I2S_FLOW_STATUS:
361         case TEGRA30_I2S_FLOW_TOTAL:
362         case TEGRA30_I2S_FLOW_OVER:
363         case TEGRA30_I2S_FLOW_UNDER:
364                 return true;
365         default:
366                 return false;
367         }
368 }
369 
370 static const struct regmap_config tegra30_i2s_regmap_config = {
371         .reg_bits = 32,
372         .reg_stride = 4,
373         .val_bits = 32,
374         .max_register = TEGRA30_I2S_LCOEF_2_4_2,
375         .writeable_reg = tegra30_i2s_wr_rd_reg,
376         .readable_reg = tegra30_i2s_wr_rd_reg,
377         .volatile_reg = tegra30_i2s_volatile_reg,
378         .cache_type = REGCACHE_FLAT,
379 };
380 
381 static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
382         .set_audio_cif = tegra30_ahub_set_cif,
383 };
384 
385 static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
386         .set_audio_cif = tegra124_ahub_set_cif,
387 };
388 
389 static const struct of_device_id tegra30_i2s_of_match[] = {
390         { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
391         { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
392         {},
393 };
394 
395 static int tegra30_i2s_platform_probe(struct platform_device *pdev)
396 {
397         struct tegra30_i2s *i2s;
398         const struct of_device_id *match;
399         u32 cif_ids[2];
400         void __iomem *regs;
401         int ret;
402 
403         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
404         if (!i2s) {
405                 ret = -ENOMEM;
406                 goto err;
407         }
408         dev_set_drvdata(&pdev->dev, i2s);
409 
410         match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
411         if (!match) {
412                 dev_err(&pdev->dev, "Error: No device match found\n");
413                 ret = -ENODEV;
414                 goto err;
415         }
416         i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
417 
418         i2s->dai = tegra30_i2s_dai_template;
419         i2s->dai.name = dev_name(&pdev->dev);
420 
421         ret = of_property_read_u32_array(pdev->dev.of_node,
422                                          "nvidia,ahub-cif-ids", cif_ids,
423                                          ARRAY_SIZE(cif_ids));
424         if (ret < 0)
425                 goto err;
426 
427         i2s->playback_i2s_cif = cif_ids[0];
428         i2s->capture_i2s_cif = cif_ids[1];
429 
430         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
431         if (IS_ERR(i2s->clk_i2s)) {
432                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
433                 ret = PTR_ERR(i2s->clk_i2s);
434                 goto err;
435         }
436 
437         regs = devm_platform_ioremap_resource(pdev, 0);
438         if (IS_ERR(regs)) {
439                 ret = PTR_ERR(regs);
440                 goto err_clk_put;
441         }
442 
443         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
444                                             &tegra30_i2s_regmap_config);
445         if (IS_ERR(i2s->regmap)) {
446                 dev_err(&pdev->dev, "regmap init failed\n");
447                 ret = PTR_ERR(i2s->regmap);
448                 goto err_clk_put;
449         }
450         regcache_cache_only(i2s->regmap, true);
451 
452         pm_runtime_enable(&pdev->dev);
453         if (!pm_runtime_enabled(&pdev->dev)) {
454                 ret = tegra30_i2s_runtime_resume(&pdev->dev);
455                 if (ret)
456                         goto err_pm_disable;
457         }
458 
459         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
460         i2s->playback_dma_data.maxburst = 4;
461         ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
462                                             i2s->playback_dma_chan,
463                                             sizeof(i2s->playback_dma_chan),
464                                             &i2s->playback_dma_data.addr);
465         if (ret) {
466                 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
467                 goto err_suspend;
468         }
469         ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
470                                              i2s->playback_fifo_cif);
471         if (ret) {
472                 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
473                 goto err_free_tx_fifo;
474         }
475 
476         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
477         i2s->capture_dma_data.maxburst = 4;
478         ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
479                                             i2s->capture_dma_chan,
480                                             sizeof(i2s->capture_dma_chan),
481                                             &i2s->capture_dma_data.addr);
482         if (ret) {
483                 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
484                 goto err_unroute_tx_fifo;
485         }
486         ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
487                                              i2s->capture_i2s_cif);
488         if (ret) {
489                 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
490                 goto err_free_rx_fifo;
491         }
492 
493         ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
494                                    &i2s->dai, 1);
495         if (ret) {
496                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
497                 ret = -ENOMEM;
498                 goto err_unroute_rx_fifo;
499         }
500 
501         ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
502                                 &i2s->dma_config, i2s->playback_dma_chan,
503                                 i2s->capture_dma_chan);
504         if (ret) {
505                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
506                 goto err_unregister_component;
507         }
508 
509         return 0;
510 
511 err_unregister_component:
512         snd_soc_unregister_component(&pdev->dev);
513 err_unroute_rx_fifo:
514         tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
515 err_free_rx_fifo:
516         tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
517 err_unroute_tx_fifo:
518         tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
519 err_free_tx_fifo:
520         tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
521 err_suspend:
522         if (!pm_runtime_status_suspended(&pdev->dev))
523                 tegra30_i2s_runtime_suspend(&pdev->dev);
524 err_pm_disable:
525         pm_runtime_disable(&pdev->dev);
526 err_clk_put:
527         clk_put(i2s->clk_i2s);
528 err:
529         return ret;
530 }
531 
532 static int tegra30_i2s_platform_remove(struct platform_device *pdev)
533 {
534         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
535 
536         pm_runtime_disable(&pdev->dev);
537         if (!pm_runtime_status_suspended(&pdev->dev))
538                 tegra30_i2s_runtime_suspend(&pdev->dev);
539 
540         tegra_pcm_platform_unregister(&pdev->dev);
541         snd_soc_unregister_component(&pdev->dev);
542 
543         tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
544         tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
545 
546         tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
547         tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
548 
549         clk_put(i2s->clk_i2s);
550 
551         return 0;
552 }
553 
554 #ifdef CONFIG_PM_SLEEP
555 static int tegra30_i2s_suspend(struct device *dev)
556 {
557         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
558 
559         regcache_mark_dirty(i2s->regmap);
560 
561         return 0;
562 }
563 
564 static int tegra30_i2s_resume(struct device *dev)
565 {
566         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
567         int ret;
568 
569         ret = pm_runtime_get_sync(dev);
570         if (ret < 0)
571                 return ret;
572         ret = regcache_sync(i2s->regmap);
573         pm_runtime_put(dev);
574 
575         return ret;
576 }
577 #endif
578 
579 static const struct dev_pm_ops tegra30_i2s_pm_ops = {
580         SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
581                            tegra30_i2s_runtime_resume, NULL)
582         SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
583 };
584 
585 static struct platform_driver tegra30_i2s_driver = {
586         .driver = {
587                 .name = DRV_NAME,
588                 .of_match_table = tegra30_i2s_of_match,
589                 .pm = &tegra30_i2s_pm_ops,
590         },
591         .probe = tegra30_i2s_platform_probe,
592         .remove = tegra30_i2s_platform_remove,
593 };
594 module_platform_driver(tegra30_i2s_driver);
595 
596 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
597 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
598 MODULE_LICENSE("GPL");
599 MODULE_ALIAS("platform:" DRV_NAME);
600 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
601 

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