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Linux/sound/soc/ti/omap-dmic.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * omap-dmic.c  --  OMAP ASoC DMIC DAI driver
  4  *
  5  * Copyright (C) 2010 - 2011 Texas Instruments
  6  *
  7  * Author: David Lambert <dlambert@ti.com>
  8  *         Misael Lopez Cruz <misael.lopez@ti.com>
  9  *         Liam Girdwood <lrg@ti.com>
 10  *         Peter Ujfalusi <peter.ujfalusi@ti.com>
 11  */
 12 
 13 #include <linux/init.h>
 14 #include <linux/module.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/err.h>
 17 #include <linux/clk.h>
 18 #include <linux/io.h>
 19 #include <linux/slab.h>
 20 #include <linux/pm_runtime.h>
 21 #include <linux/of_device.h>
 22 
 23 #include <sound/core.h>
 24 #include <sound/pcm.h>
 25 #include <sound/pcm_params.h>
 26 #include <sound/initval.h>
 27 #include <sound/soc.h>
 28 #include <sound/dmaengine_pcm.h>
 29 
 30 #include "omap-dmic.h"
 31 #include "sdma-pcm.h"
 32 
 33 struct omap_dmic {
 34         struct device *dev;
 35         void __iomem *io_base;
 36         struct clk *fclk;
 37         struct pm_qos_request pm_qos_req;
 38         int latency;
 39         int fclk_freq;
 40         int out_freq;
 41         int clk_div;
 42         int sysclk;
 43         int threshold;
 44         u32 ch_enabled;
 45         bool active;
 46         struct mutex mutex;
 47 
 48         struct snd_dmaengine_dai_dma_data dma_data;
 49 };
 50 
 51 static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
 52 {
 53         writel_relaxed(val, dmic->io_base + reg);
 54 }
 55 
 56 static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
 57 {
 58         return readl_relaxed(dmic->io_base + reg);
 59 }
 60 
 61 static inline void omap_dmic_start(struct omap_dmic *dmic)
 62 {
 63         u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
 64 
 65         /* Configure DMA controller */
 66         omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
 67                         OMAP_DMIC_DMA_ENABLE);
 68 
 69         omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
 70 }
 71 
 72 static inline void omap_dmic_stop(struct omap_dmic *dmic)
 73 {
 74         u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
 75         omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
 76                         ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
 77 
 78         /* Disable DMA request generation */
 79         omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
 80                         OMAP_DMIC_DMA_ENABLE);
 81 
 82 }
 83 
 84 static inline int dmic_is_enabled(struct omap_dmic *dmic)
 85 {
 86         return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
 87                                                 OMAP_DMIC_UP_ENABLE_MASK;
 88 }
 89 
 90 static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
 91                                   struct snd_soc_dai *dai)
 92 {
 93         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
 94         int ret = 0;
 95 
 96         mutex_lock(&dmic->mutex);
 97 
 98         if (!dai->active)
 99                 dmic->active = 1;
100         else
101                 ret = -EBUSY;
102 
103         mutex_unlock(&dmic->mutex);
104 
105         return ret;
106 }
107 
108 static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
109                                     struct snd_soc_dai *dai)
110 {
111         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
112 
113         mutex_lock(&dmic->mutex);
114 
115         pm_qos_remove_request(&dmic->pm_qos_req);
116 
117         if (!dai->active)
118                 dmic->active = 0;
119 
120         mutex_unlock(&dmic->mutex);
121 }
122 
123 static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
124 {
125         int divider = -EINVAL;
126 
127         /*
128          * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
129          * configuration.
130          */
131         if (sample_rate == 192000) {
132                 if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
133                         divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
134                 else
135                         dev_err(dmic->dev,
136                                 "invalid clock configuration for 192KHz\n");
137 
138                 return divider;
139         }
140 
141         switch (dmic->out_freq) {
142         case 1536000:
143                 if (dmic->fclk_freq != 24576000)
144                         goto div_err;
145                 divider = 0x4; /* Divider: 16 */
146                 break;
147         case 2400000:
148                 switch (dmic->fclk_freq) {
149                 case 12000000:
150                         divider = 0x5; /* Divider: 5 */
151                         break;
152                 case 19200000:
153                         divider = 0x0; /* Divider: 8 */
154                         break;
155                 case 24000000:
156                         divider = 0x2; /* Divider: 10 */
157                         break;
158                 default:
159                         goto div_err;
160                 }
161                 break;
162         case 3072000:
163                 if (dmic->fclk_freq != 24576000)
164                         goto div_err;
165                 divider = 0x3; /* Divider: 8 */
166                 break;
167         case 3840000:
168                 if (dmic->fclk_freq != 19200000)
169                         goto div_err;
170                 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
171                 break;
172         default:
173                 dev_err(dmic->dev, "invalid out frequency: %dHz\n",
174                         dmic->out_freq);
175                 break;
176         }
177 
178         return divider;
179 
180 div_err:
181         dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
182                 dmic->out_freq, dmic->fclk_freq);
183         return -EINVAL;
184 }
185 
186 static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
187                                     struct snd_pcm_hw_params *params,
188                                     struct snd_soc_dai *dai)
189 {
190         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
191         struct snd_dmaengine_dai_dma_data *dma_data;
192         int channels;
193 
194         dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
195         if (dmic->clk_div < 0) {
196                 dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
197                         dmic->out_freq, dmic->fclk_freq);
198                 return -EINVAL;
199         }
200 
201         dmic->ch_enabled = 0;
202         channels = params_channels(params);
203         switch (channels) {
204         case 6:
205                 dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
206                 /* fall through */
207         case 4:
208                 dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
209                 /* fall through */
210         case 2:
211                 dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
212                 break;
213         default:
214                 dev_err(dmic->dev, "invalid number of legacy channels\n");
215                 return -EINVAL;
216         }
217 
218         /* packet size is threshold * channels */
219         dma_data = snd_soc_dai_get_dma_data(dai, substream);
220         dma_data->maxburst = dmic->threshold * channels;
221         dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
222                         params_rate(params);
223 
224         return 0;
225 }
226 
227 static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
228                                   struct snd_soc_dai *dai)
229 {
230         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
231         u32 ctrl;
232 
233         if (pm_qos_request_active(&dmic->pm_qos_req))
234                 pm_qos_update_request(&dmic->pm_qos_req, dmic->latency);
235 
236         /* Configure uplink threshold */
237         omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
238 
239         ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
240 
241         /* Set dmic out format */
242         ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
243         ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
244                  OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
245 
246         /* Configure dmic clock divider */
247         ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
248         ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
249 
250         omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
251 
252         omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
253                         ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
254                         OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
255 
256         return 0;
257 }
258 
259 static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
260                                   int cmd, struct snd_soc_dai *dai)
261 {
262         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
263 
264         switch (cmd) {
265         case SNDRV_PCM_TRIGGER_START:
266                 omap_dmic_start(dmic);
267                 break;
268         case SNDRV_PCM_TRIGGER_STOP:
269                 omap_dmic_stop(dmic);
270                 break;
271         default:
272                 break;
273         }
274 
275         return 0;
276 }
277 
278 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
279                                  unsigned int freq)
280 {
281         struct clk *parent_clk, *mux;
282         char *parent_clk_name;
283         int ret = 0;
284 
285         switch (freq) {
286         case 12000000:
287         case 19200000:
288         case 24000000:
289         case 24576000:
290                 break;
291         default:
292                 dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
293                 dmic->fclk_freq = 0;
294                 return -EINVAL;
295         }
296 
297         if (dmic->sysclk == clk_id) {
298                 dmic->fclk_freq = freq;
299                 return 0;
300         }
301 
302         /* re-parent not allowed if a stream is ongoing */
303         if (dmic->active && dmic_is_enabled(dmic)) {
304                 dev_err(dmic->dev, "can't re-parent when DMIC active\n");
305                 return -EBUSY;
306         }
307 
308         switch (clk_id) {
309         case OMAP_DMIC_SYSCLK_PAD_CLKS:
310                 parent_clk_name = "pad_clks_ck";
311                 break;
312         case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
313                 parent_clk_name = "slimbus_clk";
314                 break;
315         case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
316                 parent_clk_name = "dmic_sync_mux_ck";
317                 break;
318         default:
319                 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
320                 return -EINVAL;
321         }
322 
323         parent_clk = clk_get(dmic->dev, parent_clk_name);
324         if (IS_ERR(parent_clk)) {
325                 dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
326                 return -ENODEV;
327         }
328 
329         mux = clk_get_parent(dmic->fclk);
330         if (IS_ERR(mux)) {
331                 dev_err(dmic->dev, "can't get fck mux parent\n");
332                 clk_put(parent_clk);
333                 return -ENODEV;
334         }
335 
336         mutex_lock(&dmic->mutex);
337         if (dmic->active) {
338                 /* disable clock while reparenting */
339                 pm_runtime_put_sync(dmic->dev);
340                 ret = clk_set_parent(mux, parent_clk);
341                 pm_runtime_get_sync(dmic->dev);
342         } else {
343                 ret = clk_set_parent(mux, parent_clk);
344         }
345         mutex_unlock(&dmic->mutex);
346 
347         if (ret < 0) {
348                 dev_err(dmic->dev, "re-parent failed\n");
349                 goto err_busy;
350         }
351 
352         dmic->sysclk = clk_id;
353         dmic->fclk_freq = freq;
354 
355 err_busy:
356         clk_put(mux);
357         clk_put(parent_clk);
358 
359         return ret;
360 }
361 
362 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
363                                     unsigned int freq)
364 {
365         int ret = 0;
366 
367         if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
368                 dev_err(dmic->dev, "output clk_id (%d) not supported\n",
369                         clk_id);
370                 return -EINVAL;
371         }
372 
373         switch (freq) {
374         case 1536000:
375         case 2400000:
376         case 3072000:
377         case 3840000:
378                 dmic->out_freq = freq;
379                 break;
380         default:
381                 dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
382                 dmic->out_freq = 0;
383                 ret = -EINVAL;
384         }
385 
386         return ret;
387 }
388 
389 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
390                                     unsigned int freq, int dir)
391 {
392         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
393 
394         if (dir == SND_SOC_CLOCK_IN)
395                 return omap_dmic_select_fclk(dmic, clk_id, freq);
396         else if (dir == SND_SOC_CLOCK_OUT)
397                 return omap_dmic_select_outclk(dmic, clk_id, freq);
398 
399         dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
400         return -EINVAL;
401 }
402 
403 static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
404         .startup        = omap_dmic_dai_startup,
405         .shutdown       = omap_dmic_dai_shutdown,
406         .hw_params      = omap_dmic_dai_hw_params,
407         .prepare        = omap_dmic_dai_prepare,
408         .trigger        = omap_dmic_dai_trigger,
409         .set_sysclk     = omap_dmic_set_dai_sysclk,
410 };
411 
412 static int omap_dmic_probe(struct snd_soc_dai *dai)
413 {
414         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
415 
416         pm_runtime_enable(dmic->dev);
417 
418         /* Disable lines while request is ongoing */
419         pm_runtime_get_sync(dmic->dev);
420         omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
421         pm_runtime_put_sync(dmic->dev);
422 
423         /* Configure DMIC threshold value */
424         dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
425 
426         snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
427 
428         return 0;
429 }
430 
431 static int omap_dmic_remove(struct snd_soc_dai *dai)
432 {
433         struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
434 
435         pm_runtime_disable(dmic->dev);
436 
437         return 0;
438 }
439 
440 static struct snd_soc_dai_driver omap_dmic_dai = {
441         .name = "omap-dmic",
442         .probe = omap_dmic_probe,
443         .remove = omap_dmic_remove,
444         .capture = {
445                 .channels_min = 2,
446                 .channels_max = 6,
447                 .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
448                 .formats = SNDRV_PCM_FMTBIT_S32_LE,
449                 .sig_bits = 24,
450         },
451         .ops = &omap_dmic_dai_ops,
452 };
453 
454 static const struct snd_soc_component_driver omap_dmic_component = {
455         .name           = "omap-dmic",
456 };
457 
458 static int asoc_dmic_probe(struct platform_device *pdev)
459 {
460         struct omap_dmic *dmic;
461         struct resource *res;
462         int ret;
463 
464         dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
465         if (!dmic)
466                 return -ENOMEM;
467 
468         platform_set_drvdata(pdev, dmic);
469         dmic->dev = &pdev->dev;
470         dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
471 
472         mutex_init(&dmic->mutex);
473 
474         dmic->fclk = devm_clk_get(dmic->dev, "fck");
475         if (IS_ERR(dmic->fclk)) {
476                 dev_err(dmic->dev, "cant get fck\n");
477                 return -ENODEV;
478         }
479 
480         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
481         if (!res) {
482                 dev_err(dmic->dev, "invalid dma memory resource\n");
483                 return -ENODEV;
484         }
485         dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
486 
487         dmic->dma_data.filter_data = "up_link";
488 
489         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
490         dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
491         if (IS_ERR(dmic->io_base))
492                 return PTR_ERR(dmic->io_base);
493 
494 
495         ret = devm_snd_soc_register_component(&pdev->dev,
496                                               &omap_dmic_component,
497                                               &omap_dmic_dai, 1);
498         if (ret)
499                 return ret;
500 
501         ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
502         if (ret)
503                 return ret;
504 
505         return 0;
506 }
507 
508 static const struct of_device_id omap_dmic_of_match[] = {
509         { .compatible = "ti,omap4-dmic", },
510         { }
511 };
512 MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
513 
514 static struct platform_driver asoc_dmic_driver = {
515         .driver = {
516                 .name = "omap-dmic",
517                 .of_match_table = omap_dmic_of_match,
518         },
519         .probe = asoc_dmic_probe,
520 };
521 
522 module_platform_driver(asoc_dmic_driver);
523 
524 MODULE_ALIAS("platform:omap-dmic");
525 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
526 MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
527 MODULE_LICENSE("GPL");
528 

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