~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/xilinx/xlnx_formatter_pcm.c

Version: ~ [ linux-6.0-rc1 ] ~ [ linux-5.19.1 ] ~ [ linux-5.18.17 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.60 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.136 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.210 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.255 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.290 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.325 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 // SPDX-License-Identifier: GPL-2.0
  2 //
  3 // Xilinx ASoC audio formatter support
  4 //
  5 // Copyright (C) 2018 Xilinx, Inc.
  6 //
  7 // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
  8 
  9 #include <linux/clk.h>
 10 #include <linux/io.h>
 11 #include <linux/module.h>
 12 #include <linux/of_address.h>
 13 #include <linux/of_irq.h>
 14 #include <linux/sizes.h>
 15 
 16 #include <sound/asoundef.h>
 17 #include <sound/soc.h>
 18 #include <sound/pcm_params.h>
 19 
 20 #define DRV_NAME "xlnx_formatter_pcm"
 21 
 22 #define XLNX_S2MM_OFFSET        0
 23 #define XLNX_MM2S_OFFSET        0x100
 24 
 25 #define XLNX_AUD_CORE_CONFIG    0x4
 26 #define XLNX_AUD_CTRL           0x10
 27 #define XLNX_AUD_STS            0x14
 28 
 29 #define AUD_CTRL_RESET_MASK     BIT(1)
 30 #define AUD_CFG_MM2S_MASK       BIT(15)
 31 #define AUD_CFG_S2MM_MASK       BIT(31)
 32 
 33 #define XLNX_AUD_FS_MULTIPLIER  0x18
 34 #define XLNX_AUD_PERIOD_CONFIG  0x1C
 35 #define XLNX_AUD_BUFF_ADDR_LSB  0x20
 36 #define XLNX_AUD_BUFF_ADDR_MSB  0x24
 37 #define XLNX_AUD_XFER_COUNT     0x28
 38 #define XLNX_AUD_CH_STS_START   0x2C
 39 #define XLNX_BYTES_PER_CH       0x44
 40 
 41 #define AUD_STS_IOC_IRQ_MASK    BIT(31)
 42 #define AUD_STS_CH_STS_MASK     BIT(29)
 43 #define AUD_CTRL_IOC_IRQ_MASK   BIT(13)
 44 #define AUD_CTRL_TOUT_IRQ_MASK  BIT(14)
 45 #define AUD_CTRL_DMA_EN_MASK    BIT(0)
 46 
 47 #define CFG_MM2S_CH_MASK        GENMASK(11, 8)
 48 #define CFG_MM2S_CH_SHIFT       8
 49 #define CFG_MM2S_XFER_MASK      GENMASK(14, 13)
 50 #define CFG_MM2S_XFER_SHIFT     13
 51 #define CFG_MM2S_PKG_MASK       BIT(12)
 52 
 53 #define CFG_S2MM_CH_MASK        GENMASK(27, 24)
 54 #define CFG_S2MM_CH_SHIFT       24
 55 #define CFG_S2MM_XFER_MASK      GENMASK(30, 29)
 56 #define CFG_S2MM_XFER_SHIFT     29
 57 #define CFG_S2MM_PKG_MASK       BIT(28)
 58 
 59 #define AUD_CTRL_DATA_WIDTH_SHIFT       16
 60 #define AUD_CTRL_ACTIVE_CH_SHIFT        19
 61 #define PERIOD_CFG_PERIODS_SHIFT        16
 62 
 63 #define PERIODS_MIN             2
 64 #define PERIODS_MAX             6
 65 #define PERIOD_BYTES_MIN        192
 66 #define PERIOD_BYTES_MAX        (50 * 1024)
 67 #define XLNX_PARAM_UNKNOWN      0
 68 
 69 enum bit_depth {
 70         BIT_DEPTH_8,
 71         BIT_DEPTH_16,
 72         BIT_DEPTH_20,
 73         BIT_DEPTH_24,
 74         BIT_DEPTH_32,
 75 };
 76 
 77 struct xlnx_pcm_drv_data {
 78         void __iomem *mmio;
 79         bool s2mm_presence;
 80         bool mm2s_presence;
 81         int s2mm_irq;
 82         int mm2s_irq;
 83         struct snd_pcm_substream *play_stream;
 84         struct snd_pcm_substream *capture_stream;
 85         struct clk *axi_clk;
 86 };
 87 
 88 /*
 89  * struct xlnx_pcm_stream_param - stream configuration
 90  * @mmio: base address offset
 91  * @interleaved: audio channels arrangement in buffer
 92  * @xfer_mode: data formatting mode during transfer
 93  * @ch_limit: Maximum channels supported
 94  * @buffer_size: stream ring buffer size
 95  */
 96 struct xlnx_pcm_stream_param {
 97         void __iomem *mmio;
 98         bool interleaved;
 99         u32 xfer_mode;
100         u32 ch_limit;
101         u64 buffer_size;
102 };
103 
104 static const struct snd_pcm_hardware xlnx_pcm_hardware = {
105         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
106                 SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE |
107                 SNDRV_PCM_INFO_RESUME,
108         .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
109                    SNDRV_PCM_FMTBIT_S24_LE,
110         .channels_min = 2,
111         .channels_max = 2,
112         .rates = SNDRV_PCM_RATE_8000_192000,
113         .rate_min = 8000,
114         .rate_max = 192000,
115         .buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX,
116         .period_bytes_min = PERIOD_BYTES_MIN,
117         .period_bytes_max = PERIOD_BYTES_MAX,
118         .periods_min = PERIODS_MIN,
119         .periods_max = PERIODS_MAX,
120 };
121 
122 enum {
123         AES_TO_AES,
124         AES_TO_PCM,
125         PCM_TO_PCM,
126         PCM_TO_AES
127 };
128 
129 static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val,
130                                   struct device *dev)
131 {
132         u32 padded, srate, bit_depth, status[2];
133 
134         if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) {
135                 status[0] = chsts_reg1_val & 0xff;
136                 status[1] = (chsts_reg1_val >> 16) & 0xff;
137 
138                 switch (status[0] & IEC958_AES0_PRO_FS) {
139                 case IEC958_AES0_PRO_FS_44100:
140                         srate = 44100;
141                         break;
142                 case IEC958_AES0_PRO_FS_48000:
143                         srate = 48000;
144                         break;
145                 case IEC958_AES0_PRO_FS_32000:
146                         srate = 32000;
147                         break;
148                 case IEC958_AES0_PRO_FS_NOTID:
149                 default:
150                         srate = XLNX_PARAM_UNKNOWN;
151                         break;
152                 }
153 
154                 switch (status[1] & IEC958_AES2_PRO_SBITS) {
155                 case IEC958_AES2_PRO_WORDLEN_NOTID:
156                 case IEC958_AES2_PRO_SBITS_20:
157                         padded = 0;
158                         break;
159                 case IEC958_AES2_PRO_SBITS_24:
160                         padded = 4;
161                         break;
162                 default:
163                         bit_depth = XLNX_PARAM_UNKNOWN;
164                         goto log_params;
165                 }
166 
167                 switch (status[1] & IEC958_AES2_PRO_WORDLEN) {
168                 case IEC958_AES2_PRO_WORDLEN_20_16:
169                         bit_depth = 16 + padded;
170                         break;
171                 case IEC958_AES2_PRO_WORDLEN_22_18:
172                         bit_depth = 18 + padded;
173                         break;
174                 case IEC958_AES2_PRO_WORDLEN_23_19:
175                         bit_depth = 19 + padded;
176                         break;
177                 case IEC958_AES2_PRO_WORDLEN_24_20:
178                         bit_depth = 20 + padded;
179                         break;
180                 case IEC958_AES2_PRO_WORDLEN_NOTID:
181                 default:
182                         bit_depth = XLNX_PARAM_UNKNOWN;
183                         break;
184                 }
185 
186         } else {
187                 status[0] = (chsts_reg1_val >> 24) & 0xff;
188                 status[1] = chsts_reg2_val & 0xff;
189 
190                 switch (status[0] & IEC958_AES3_CON_FS) {
191                 case IEC958_AES3_CON_FS_44100:
192                         srate = 44100;
193                         break;
194                 case IEC958_AES3_CON_FS_48000:
195                         srate = 48000;
196                         break;
197                 case IEC958_AES3_CON_FS_32000:
198                         srate = 32000;
199                         break;
200                 default:
201                         srate = XLNX_PARAM_UNKNOWN;
202                         break;
203                 }
204 
205                 if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24)
206                         padded = 4;
207                 else
208                         padded = 0;
209 
210                 switch (status[1] & IEC958_AES4_CON_WORDLEN) {
211                 case IEC958_AES4_CON_WORDLEN_20_16:
212                         bit_depth = 16 + padded;
213                         break;
214                 case IEC958_AES4_CON_WORDLEN_22_18:
215                         bit_depth = 18 + padded;
216                         break;
217                 case IEC958_AES4_CON_WORDLEN_23_19:
218                         bit_depth = 19 + padded;
219                         break;
220                 case IEC958_AES4_CON_WORDLEN_24_20:
221                         bit_depth = 20 + padded;
222                         break;
223                 case IEC958_AES4_CON_WORDLEN_21_17:
224                         bit_depth = 17 + padded;
225                         break;
226                 case IEC958_AES4_CON_WORDLEN_NOTID:
227                 default:
228                         bit_depth = XLNX_PARAM_UNKNOWN;
229                         break;
230                 }
231         }
232 
233 log_params:
234         if (srate != XLNX_PARAM_UNKNOWN)
235                 dev_info(dev, "sample rate = %d\n", srate);
236         else
237                 dev_info(dev, "sample rate = unknown\n");
238 
239         if (bit_depth != XLNX_PARAM_UNKNOWN)
240                 dev_info(dev, "bit_depth = %d\n", bit_depth);
241         else
242                 dev_info(dev, "bit_depth = unknown\n");
243 }
244 
245 static int xlnx_formatter_pcm_reset(void __iomem *mmio_base)
246 {
247         u32 val, retries = 0;
248 
249         val = readl(mmio_base + XLNX_AUD_CTRL);
250         val |= AUD_CTRL_RESET_MASK;
251         writel(val, mmio_base + XLNX_AUD_CTRL);
252 
253         val = readl(mmio_base + XLNX_AUD_CTRL);
254         /* Poll for maximum timeout of approximately 100ms (1 * 100)*/
255         while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) {
256                 mdelay(1);
257                 retries++;
258                 val = readl(mmio_base + XLNX_AUD_CTRL);
259         }
260         if (val & AUD_CTRL_RESET_MASK)
261                 return -ENODEV;
262 
263         return 0;
264 }
265 
266 static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream)
267 {
268         u32 val;
269 
270         val = readl(mmio_base + XLNX_AUD_CTRL);
271         val &= ~AUD_CTRL_IOC_IRQ_MASK;
272         if (stream == SNDRV_PCM_STREAM_CAPTURE)
273                 val &= ~AUD_CTRL_TOUT_IRQ_MASK;
274 
275         writel(val, mmio_base + XLNX_AUD_CTRL);
276 }
277 
278 static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg)
279 {
280         u32 val;
281         void __iomem *reg;
282         struct device *dev = arg;
283         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
284 
285         reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS;
286         val = readl(reg);
287         if (val & AUD_STS_IOC_IRQ_MASK) {
288                 writel(val & AUD_STS_IOC_IRQ_MASK, reg);
289                 if (adata->play_stream)
290                         snd_pcm_period_elapsed(adata->play_stream);
291                 return IRQ_HANDLED;
292         }
293 
294         return IRQ_NONE;
295 }
296 
297 static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg)
298 {
299         u32 val;
300         void __iomem *reg;
301         struct device *dev = arg;
302         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
303 
304         reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS;
305         val = readl(reg);
306         if (val & AUD_STS_IOC_IRQ_MASK) {
307                 writel(val & AUD_STS_IOC_IRQ_MASK, reg);
308                 if (adata->capture_stream)
309                         snd_pcm_period_elapsed(adata->capture_stream);
310                 return IRQ_HANDLED;
311         }
312 
313         return IRQ_NONE;
314 }
315 
316 static int xlnx_formatter_pcm_open(struct snd_soc_component *component,
317                                    struct snd_pcm_substream *substream)
318 {
319         int err;
320         u32 val, data_format_mode;
321         u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift;
322         struct xlnx_pcm_stream_param *stream_data;
323         struct snd_pcm_runtime *runtime = substream->runtime;
324         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev);
325 
326         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
327             !adata->mm2s_presence)
328                 return -ENODEV;
329         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
330                  !adata->s2mm_presence)
331                 return -ENODEV;
332 
333         stream_data = kzalloc(sizeof(*stream_data), GFP_KERNEL);
334         if (!stream_data)
335                 return -ENOMEM;
336 
337         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
338                 ch_count_mask = CFG_MM2S_CH_MASK;
339                 ch_count_shift = CFG_MM2S_CH_SHIFT;
340                 data_xfer_mode = CFG_MM2S_XFER_MASK;
341                 data_xfer_shift = CFG_MM2S_XFER_SHIFT;
342                 data_format_mode = CFG_MM2S_PKG_MASK;
343                 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET;
344                 adata->play_stream = substream;
345 
346         } else {
347                 ch_count_mask = CFG_S2MM_CH_MASK;
348                 ch_count_shift = CFG_S2MM_CH_SHIFT;
349                 data_xfer_mode = CFG_S2MM_XFER_MASK;
350                 data_xfer_shift = CFG_S2MM_XFER_SHIFT;
351                 data_format_mode = CFG_S2MM_PKG_MASK;
352                 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET;
353                 adata->capture_stream = substream;
354         }
355 
356         val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG);
357 
358         if (!(val & data_format_mode))
359                 stream_data->interleaved = true;
360 
361         stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift;
362         stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift;
363         dev_info(component->dev,
364                  "stream %d : format = %d mode = %d ch_limit = %d\n",
365                  substream->stream, stream_data->interleaved,
366                  stream_data->xfer_mode, stream_data->ch_limit);
367 
368         snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware);
369         runtime->private_data = stream_data;
370 
371         /* Resize the period size divisible by 64 */
372         err = snd_pcm_hw_constraint_step(runtime, 0,
373                                          SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
374         if (err) {
375                 dev_err(component->dev,
376                         "unable to set constraint on period bytes\n");
377                 return err;
378         }
379 
380         /* enable DMA IOC irq */
381         val = readl(stream_data->mmio + XLNX_AUD_CTRL);
382         val |= AUD_CTRL_IOC_IRQ_MASK;
383         writel(val, stream_data->mmio + XLNX_AUD_CTRL);
384 
385         return 0;
386 }
387 
388 static int xlnx_formatter_pcm_close(struct snd_soc_component *component,
389                                     struct snd_pcm_substream *substream)
390 {
391         int ret;
392         struct xlnx_pcm_stream_param *stream_data =
393                         substream->runtime->private_data;
394 
395         ret = xlnx_formatter_pcm_reset(stream_data->mmio);
396         if (ret) {
397                 dev_err(component->dev, "audio formatter reset failed\n");
398                 goto err_reset;
399         }
400         xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream);
401 
402 err_reset:
403         kfree(stream_data);
404         return 0;
405 }
406 
407 static snd_pcm_uframes_t
408 xlnx_formatter_pcm_pointer(struct snd_soc_component *component,
409                            struct snd_pcm_substream *substream)
410 {
411         u32 pos;
412         struct snd_pcm_runtime *runtime = substream->runtime;
413         struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
414 
415         pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT);
416 
417         if (pos >= stream_data->buffer_size)
418                 pos = 0;
419 
420         return bytes_to_frames(runtime, pos);
421 }
422 
423 static int xlnx_formatter_pcm_hw_params(struct snd_soc_component *component,
424                                         struct snd_pcm_substream *substream,
425                                         struct snd_pcm_hw_params *params)
426 {
427         u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample;
428         u32 aes_reg1_val, aes_reg2_val;
429         int status;
430         u64 size;
431         struct snd_pcm_runtime *runtime = substream->runtime;
432         struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
433 
434         active_ch = params_channels(params);
435         if (active_ch > stream_data->ch_limit)
436                 return -EINVAL;
437 
438         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
439             stream_data->xfer_mode == AES_TO_PCM) {
440                 val = readl(stream_data->mmio + XLNX_AUD_STS);
441                 if (val & AUD_STS_CH_STS_MASK) {
442                         aes_reg1_val = readl(stream_data->mmio +
443                                              XLNX_AUD_CH_STS_START);
444                         aes_reg2_val = readl(stream_data->mmio +
445                                              XLNX_AUD_CH_STS_START + 0x4);
446 
447                         xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val,
448                                               component->dev);
449                 }
450         }
451 
452         size = params_buffer_bytes(params);
453         status = snd_pcm_lib_malloc_pages(substream, size);
454         if (status < 0)
455                 return status;
456 
457         stream_data->buffer_size = size;
458 
459         low = lower_32_bits(substream->dma_buffer.addr);
460         high = upper_32_bits(substream->dma_buffer.addr);
461         writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB);
462         writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB);
463 
464         val = readl(stream_data->mmio + XLNX_AUD_CTRL);
465         bits_per_sample = params_width(params);
466         switch (bits_per_sample) {
467         case 8:
468                 val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT);
469                 break;
470         case 16:
471                 val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT);
472                 break;
473         case 20:
474                 val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT);
475                 break;
476         case 24:
477                 val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT);
478                 break;
479         case 32:
480                 val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT);
481                 break;
482         default:
483                 return -EINVAL;
484         }
485 
486         val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT;
487         writel(val, stream_data->mmio + XLNX_AUD_CTRL);
488 
489         val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT)
490                 | params_period_bytes(params);
491         writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG);
492         bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch);
493         writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH);
494 
495         return 0;
496 }
497 
498 static int xlnx_formatter_pcm_hw_free(struct snd_soc_component *component,
499                                       struct snd_pcm_substream *substream)
500 {
501         return snd_pcm_lib_free_pages(substream);
502 }
503 
504 static int xlnx_formatter_pcm_trigger(struct snd_soc_component *component,
505                                       struct snd_pcm_substream *substream,
506                                       int cmd)
507 {
508         u32 val;
509         struct xlnx_pcm_stream_param *stream_data =
510                         substream->runtime->private_data;
511 
512         switch (cmd) {
513         case SNDRV_PCM_TRIGGER_START:
514         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
515         case SNDRV_PCM_TRIGGER_RESUME:
516                 val = readl(stream_data->mmio + XLNX_AUD_CTRL);
517                 val |= AUD_CTRL_DMA_EN_MASK;
518                 writel(val, stream_data->mmio + XLNX_AUD_CTRL);
519                 break;
520         case SNDRV_PCM_TRIGGER_STOP:
521         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
522         case SNDRV_PCM_TRIGGER_SUSPEND:
523                 val = readl(stream_data->mmio + XLNX_AUD_CTRL);
524                 val &= ~AUD_CTRL_DMA_EN_MASK;
525                 writel(val, stream_data->mmio + XLNX_AUD_CTRL);
526                 break;
527         }
528 
529         return 0;
530 }
531 
532 static int xlnx_formatter_pcm_new(struct snd_soc_component *component,
533                                   struct snd_soc_pcm_runtime *rtd)
534 {
535         snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
536                         SNDRV_DMA_TYPE_DEV, component->dev,
537                         xlnx_pcm_hardware.buffer_bytes_max,
538                         xlnx_pcm_hardware.buffer_bytes_max);
539         return 0;
540 }
541 
542 static const struct snd_soc_component_driver xlnx_asoc_component = {
543         .name           = DRV_NAME,
544         .open           = xlnx_formatter_pcm_open,
545         .close          = xlnx_formatter_pcm_close,
546         .ioctl          = snd_soc_pcm_lib_ioctl,
547         .hw_params      = xlnx_formatter_pcm_hw_params,
548         .hw_free        = xlnx_formatter_pcm_hw_free,
549         .trigger        = xlnx_formatter_pcm_trigger,
550         .pointer        = xlnx_formatter_pcm_pointer,
551         .pcm_construct  = xlnx_formatter_pcm_new,
552 };
553 
554 static int xlnx_formatter_pcm_probe(struct platform_device *pdev)
555 {
556         int ret;
557         u32 val;
558         struct xlnx_pcm_drv_data *aud_drv_data;
559         struct device *dev = &pdev->dev;
560 
561         aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL);
562         if (!aud_drv_data)
563                 return -ENOMEM;
564 
565         aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk");
566         if (IS_ERR(aud_drv_data->axi_clk)) {
567                 ret = PTR_ERR(aud_drv_data->axi_clk);
568                 dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret);
569                 return ret;
570         }
571         ret = clk_prepare_enable(aud_drv_data->axi_clk);
572         if (ret) {
573                 dev_err(dev,
574                         "failed to enable s_axi_lite_aclk(%d)\n", ret);
575                 return ret;
576         }
577 
578         aud_drv_data->mmio = devm_platform_ioremap_resource(pdev, 0);
579         if (IS_ERR(aud_drv_data->mmio)) {
580                 dev_err(dev, "audio formatter ioremap failed\n");
581                 ret = PTR_ERR(aud_drv_data->mmio);
582                 goto clk_err;
583         }
584 
585         val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG);
586         if (val & AUD_CFG_MM2S_MASK) {
587                 aud_drv_data->mm2s_presence = true;
588                 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
589                                                XLNX_MM2S_OFFSET);
590                 if (ret) {
591                         dev_err(dev, "audio formatter reset failed\n");
592                         goto clk_err;
593                 }
594                 xlnx_formatter_disable_irqs(aud_drv_data->mmio +
595                                             XLNX_MM2S_OFFSET,
596                                             SNDRV_PCM_STREAM_PLAYBACK);
597 
598                 aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev,
599                                                                  "irq_mm2s");
600                 if (aud_drv_data->mm2s_irq < 0) {
601                         ret = aud_drv_data->mm2s_irq;
602                         goto clk_err;
603                 }
604                 ret = devm_request_irq(dev, aud_drv_data->mm2s_irq,
605                                        xlnx_mm2s_irq_handler, 0,
606                                        "xlnx_formatter_pcm_mm2s_irq", dev);
607                 if (ret) {
608                         dev_err(dev, "xlnx audio mm2s irq request failed\n");
609                         goto clk_err;
610                 }
611         }
612         if (val & AUD_CFG_S2MM_MASK) {
613                 aud_drv_data->s2mm_presence = true;
614                 ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
615                                                XLNX_S2MM_OFFSET);
616                 if (ret) {
617                         dev_err(dev, "audio formatter reset failed\n");
618                         goto clk_err;
619                 }
620                 xlnx_formatter_disable_irqs(aud_drv_data->mmio +
621                                             XLNX_S2MM_OFFSET,
622                                             SNDRV_PCM_STREAM_CAPTURE);
623 
624                 aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev,
625                                                                  "irq_s2mm");
626                 if (aud_drv_data->s2mm_irq < 0) {
627                         ret = aud_drv_data->s2mm_irq;
628                         goto clk_err;
629                 }
630                 ret = devm_request_irq(dev, aud_drv_data->s2mm_irq,
631                                        xlnx_s2mm_irq_handler, 0,
632                                        "xlnx_formatter_pcm_s2mm_irq",
633                                        dev);
634                 if (ret) {
635                         dev_err(dev, "xlnx audio s2mm irq request failed\n");
636                         goto clk_err;
637                 }
638         }
639 
640         dev_set_drvdata(dev, aud_drv_data);
641 
642         ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component,
643                                               NULL, 0);
644         if (ret) {
645                 dev_err(dev, "pcm platform device register failed\n");
646                 goto clk_err;
647         }
648 
649         return 0;
650 
651 clk_err:
652         clk_disable_unprepare(aud_drv_data->axi_clk);
653         return ret;
654 }
655 
656 static int xlnx_formatter_pcm_remove(struct platform_device *pdev)
657 {
658         int ret = 0;
659         struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev);
660 
661         if (adata->s2mm_presence)
662                 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET);
663 
664         /* Try MM2S reset, even if S2MM  reset fails */
665         if (adata->mm2s_presence)
666                 ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET);
667 
668         if (ret)
669                 dev_err(&pdev->dev, "audio formatter reset failed\n");
670 
671         clk_disable_unprepare(adata->axi_clk);
672         return ret;
673 }
674 
675 static const struct of_device_id xlnx_formatter_pcm_of_match[] = {
676         { .compatible = "xlnx,audio-formatter-1.0"},
677         {},
678 };
679 MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match);
680 
681 static struct platform_driver xlnx_formatter_pcm_driver = {
682         .probe  = xlnx_formatter_pcm_probe,
683         .remove = xlnx_formatter_pcm_remove,
684         .driver = {
685                 .name   = DRV_NAME,
686                 .of_match_table = xlnx_formatter_pcm_of_match,
687         },
688 };
689 
690 module_platform_driver(xlnx_formatter_pcm_driver);
691 MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
692 MODULE_LICENSE("GPL v2");
693 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp