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TOMOYO Linux Cross Reference
Linux/sound/sparc/dbri.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * Driver for DBRI sound chip found on Sparcs.
  4  * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
  5  *
  6  * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
  7  *
  8  * Based entirely upon drivers/sbus/audio/dbri.c which is:
  9  * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
 10  * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
 11  *
 12  * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
 13  * on Sun SPARCStation 10, 20, LX and Voyager models.
 14  *
 15  * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
 16  *   data time multiplexer with ISDN support (aka T7259)
 17  *   Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
 18  *   CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
 19  *   Documentation:
 20  *   - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
 21  *     Sparc Technology Business (courtesy of Sun Support)
 22  *   - Data sheet of the T7903, a newer but very similar ISA bus equivalent
 23  *     available from the Lucent (formerly AT&T microelectronics) home
 24  *     page.
 25  *   - http://www.freesoft.org/Linux/DBRI/
 26  * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
 27  *   Interfaces: CHI, Audio In & Out, 2 bits parallel
 28  *   Documentation: from the Crystal Semiconductor home page.
 29  *
 30  * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
 31  * memory and a serial device (long pipes, no. 0-15) or between two serial
 32  * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
 33  * device (short pipes).
 34  * A timeslot defines the bit-offset and no. of bits read from a serial device.
 35  * The timeslots are linked to 6 circular lists, one for each direction for
 36  * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
 37  * (the second one is a monitor/tee pipe, valid only for serial input).
 38  *
 39  * The mmcodec is connected via the CHI bus and needs the data & some
 40  * parameters (volume, output selection) time multiplexed in 8 byte
 41  * chunks. It also has a control mode, which serves for audio format setting.
 42  *
 43  * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
 44  * the same CHI bus, so I thought perhaps it is possible to use the on-board
 45  * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
 46  * audio devices. But the SUN HW group decided against it, at least on my
 47  * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
 48  * connected.
 49  *
 50  * I've tried to stick to the following function naming conventions:
 51  * snd_*        ALSA stuff
 52  * cs4215_*     CS4215 codec specific stuff
 53  * dbri_*       DBRI high-level stuff
 54  * other        DBRI low-level stuff
 55  */
 56 
 57 #include <linux/interrupt.h>
 58 #include <linux/delay.h>
 59 #include <linux/irq.h>
 60 #include <linux/io.h>
 61 #include <linux/dma-mapping.h>
 62 #include <linux/gfp.h>
 63 
 64 #include <sound/core.h>
 65 #include <sound/pcm.h>
 66 #include <sound/pcm_params.h>
 67 #include <sound/info.h>
 68 #include <sound/control.h>
 69 #include <sound/initval.h>
 70 
 71 #include <linux/of.h>
 72 #include <linux/of_device.h>
 73 #include <linux/atomic.h>
 74 #include <linux/module.h>
 75 
 76 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
 77 MODULE_DESCRIPTION("Sun DBRI");
 78 MODULE_LICENSE("GPL");
 79 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
 80 
 81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 82 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 83 /* Enable this card */
 84 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 85 
 86 module_param_array(index, int, NULL, 0444);
 87 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
 88 module_param_array(id, charp, NULL, 0444);
 89 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
 90 module_param_array(enable, bool, NULL, 0444);
 91 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
 92 
 93 #undef DBRI_DEBUG
 94 
 95 #define D_INT   (1<<0)
 96 #define D_GEN   (1<<1)
 97 #define D_CMD   (1<<2)
 98 #define D_MM    (1<<3)
 99 #define D_USR   (1<<4)
100 #define D_DESC  (1<<5)
101 
102 static int dbri_debug;
103 module_param(dbri_debug, int, 0644);
104 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
105 
106 #ifdef DBRI_DEBUG
107 static char *cmds[] = {
108         "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
109         "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
110 };
111 
112 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
113 
114 #else
115 #define dprintk(a, x...) do { } while (0)
116 
117 #endif                          /* DBRI_DEBUG */
118 
119 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) |       \
120                                     (intr << 27) |      \
121                                     value)
122 
123 /***************************************************************************
124         CS4215 specific definitions and structures
125 ****************************************************************************/
126 
127 struct cs4215 {
128         __u8 data[4];           /* Data mode: Time slots 5-8 */
129         __u8 ctrl[4];           /* Ctrl mode: Time slots 1-4 */
130         __u8 onboard;
131         __u8 offset;            /* Bit offset from frame sync to time slot 1 */
132         volatile __u32 status;
133         volatile __u32 version;
134         __u8 precision;         /* In bits, either 8 or 16 */
135         __u8 channels;          /* 1 or 2 */
136 };
137 
138 /*
139  * Control mode first
140  */
141 
142 /* Time Slot 1, Status register */
143 #define CS4215_CLB      (1<<2)  /* Control Latch Bit */
144 #define CS4215_OLB      (1<<3)  /* 1: line: 2.0V, speaker 4V */
145                                 /* 0: line: 2.8V, speaker 8V */
146 #define CS4215_MLB      (1<<4)  /* 1: Microphone: 20dB gain disabled */
147 #define CS4215_RSRVD_1  (1<<5)
148 
149 /* Time Slot 2, Data Format Register */
150 #define CS4215_DFR_LINEAR16     0
151 #define CS4215_DFR_ULAW         1
152 #define CS4215_DFR_ALAW         2
153 #define CS4215_DFR_LINEAR8      3
154 #define CS4215_DFR_STEREO       (1<<2)
155 static struct {
156         unsigned short freq;
157         unsigned char xtal;
158         unsigned char csval;
159 } CS4215_FREQ[] = {
160         {  8000, (1 << 4), (0 << 3) },
161         { 16000, (1 << 4), (1 << 3) },
162         { 27429, (1 << 4), (2 << 3) },  /* Actually 24428.57 */
163         { 32000, (1 << 4), (3 << 3) },
164      /* {    NA, (1 << 4), (4 << 3) }, */
165      /* {    NA, (1 << 4), (5 << 3) }, */
166         { 48000, (1 << 4), (6 << 3) },
167         {  9600, (1 << 4), (7 << 3) },
168         {  5512, (2 << 4), (0 << 3) },  /* Actually 5512.5 */
169         { 11025, (2 << 4), (1 << 3) },
170         { 18900, (2 << 4), (2 << 3) },
171         { 22050, (2 << 4), (3 << 3) },
172         { 37800, (2 << 4), (4 << 3) },
173         { 44100, (2 << 4), (5 << 3) },
174         { 33075, (2 << 4), (6 << 3) },
175         {  6615, (2 << 4), (7 << 3) },
176         { 0, 0, 0}
177 };
178 
179 #define CS4215_HPF      (1<<7)  /* High Pass Filter, 1: Enabled */
180 
181 #define CS4215_12_MASK  0xfcbf  /* Mask off reserved bits in slot 1 & 2 */
182 
183 /* Time Slot 3, Serial Port Control register */
184 #define CS4215_XEN      (1<<0)  /* 0: Enable serial output */
185 #define CS4215_XCLK     (1<<1)  /* 1: Master mode: Generate SCLK */
186 #define CS4215_BSEL_64  (0<<2)  /* Bitrate: 64 bits per frame */
187 #define CS4215_BSEL_128 (1<<2)
188 #define CS4215_BSEL_256 (2<<2)
189 #define CS4215_MCK_MAST (0<<4)  /* Master clock */
190 #define CS4215_MCK_XTL1 (1<<4)  /* 24.576 MHz clock source */
191 #define CS4215_MCK_XTL2 (2<<4)  /* 16.9344 MHz clock source */
192 #define CS4215_MCK_CLK1 (3<<4)  /* Clockin, 256 x Fs */
193 #define CS4215_MCK_CLK2 (4<<4)  /* Clockin, see DFR */
194 
195 /* Time Slot 4, Test Register */
196 #define CS4215_DAD      (1<<0)  /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
197 #define CS4215_ENL      (1<<1)  /* Enable Loopback Testing */
198 
199 /* Time Slot 5, Parallel Port Register */
200 /* Read only here and the same as the in data mode */
201 
202 /* Time Slot 6, Reserved  */
203 
204 /* Time Slot 7, Version Register  */
205 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
206 
207 /* Time Slot 8, Reserved  */
208 
209 /*
210  * Data mode
211  */
212 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data  */
213 
214 /* Time Slot 5, Output Setting  */
215 #define CS4215_LO(v)    v       /* Left Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_LE       (1<<6)  /* Line Out Enable */
217 #define CS4215_HE       (1<<7)  /* Headphone Enable */
218 
219 /* Time Slot 6, Output Setting  */
220 #define CS4215_RO(v)    v       /* Right Output Attenuation 0x3f: -94.5 dB */
221 #define CS4215_SE       (1<<6)  /* Speaker Enable */
222 #define CS4215_ADI      (1<<7)  /* A/D Data Invalid: Busy in calibration */
223 
224 /* Time Slot 7, Input Setting */
225 #define CS4215_LG(v)    v       /* Left Gain Setting 0xf: 22.5 dB */
226 #define CS4215_IS       (1<<4)  /* Input Select: 1=Microphone, 0=Line */
227 #define CS4215_OVR      (1<<5)  /* 1: Over range condition occurred */
228 #define CS4215_PIO0     (1<<6)  /* Parallel I/O 0 */
229 #define CS4215_PIO1     (1<<7)
230 
231 /* Time Slot 8, Input Setting */
232 #define CS4215_RG(v)    v       /* Right Gain Setting 0xf: 22.5 dB */
233 #define CS4215_MA(v)    (v<<4)  /* Monitor Path Attenuation 0xf: mute */
234 
235 /***************************************************************************
236                 DBRI specific definitions and structures
237 ****************************************************************************/
238 
239 /* DBRI main registers */
240 #define REG0    0x00            /* Status and Control */
241 #define REG1    0x04            /* Mode and Interrupt */
242 #define REG2    0x08            /* Parallel IO */
243 #define REG3    0x0c            /* Test */
244 #define REG8    0x20            /* Command Queue Pointer */
245 #define REG9    0x24            /* Interrupt Queue Pointer */
246 
247 #define DBRI_NO_CMDS    64
248 #define DBRI_INT_BLK    64
249 #define DBRI_NO_DESCS   64
250 #define DBRI_NO_PIPES   32
251 #define DBRI_MAX_PIPE   (DBRI_NO_PIPES - 1)
252 
253 #define DBRI_REC        0
254 #define DBRI_PLAY       1
255 #define DBRI_NO_STREAMS 2
256 
257 /* One transmit/receive descriptor */
258 /* When ba != 0 descriptor is used */
259 struct dbri_mem {
260         volatile __u32 word1;
261         __u32 ba;       /* Transmit/Receive Buffer Address */
262         __u32 nda;      /* Next Descriptor Address */
263         volatile __u32 word4;
264 };
265 
266 /* This structure is in a DMA region where it can accessed by both
267  * the CPU and the DBRI
268  */
269 struct dbri_dma {
270         s32 cmd[DBRI_NO_CMDS];                  /* Place for commands */
271         volatile s32 intr[DBRI_INT_BLK];        /* Interrupt field  */
272         struct dbri_mem desc[DBRI_NO_DESCS];    /* Xmit/receive descriptors */
273 };
274 
275 #define dbri_dma_off(member, elem)      \
276         ((u32)(unsigned long)           \
277          (&(((struct dbri_dma *)0)->member[elem])))
278 
279 enum in_or_out { PIPEinput, PIPEoutput };
280 
281 struct dbri_pipe {
282         u32 sdp;                /* SDP command word */
283         int nextpipe;           /* Next pipe in linked list */
284         int length;             /* Length of timeslot (bits) */
285         int first_desc;         /* Index of first descriptor */
286         int desc;               /* Index of active descriptor */
287         volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
288 };
289 
290 /* Per stream (playback or record) information */
291 struct dbri_streaminfo {
292         struct snd_pcm_substream *substream;
293         u32 dvma_buffer;        /* Device view of ALSA DMA buffer */
294         int size;               /* Size of DMA buffer             */
295         size_t offset;          /* offset in user buffer          */
296         int pipe;               /* Data pipe used                 */
297         int left_gain;          /* mixer elements                 */
298         int right_gain;
299 };
300 
301 /* This structure holds the information for both chips (DBRI & CS4215) */
302 struct snd_dbri {
303         int regs_size, irq;     /* Needed for unload */
304         struct platform_device *op;     /* OF device info */
305         spinlock_t lock;
306 
307         struct dbri_dma *dma;   /* Pointer to our DMA block */
308         dma_addr_t dma_dvma;    /* DBRI visible DMA address */
309 
310         void __iomem *regs;     /* dbri HW regs */
311         int dbri_irqp;          /* intr queue pointer */
312 
313         struct dbri_pipe pipes[DBRI_NO_PIPES];  /* DBRI's 32 data pipes */
314         int next_desc[DBRI_NO_DESCS];           /* Index of next desc, or -1 */
315         spinlock_t cmdlock;     /* Protects cmd queue accesses */
316         s32 *cmdptr;            /* Pointer to the last queued cmd */
317 
318         int chi_bpf;
319 
320         struct cs4215 mm;       /* mmcodec special info */
321                                 /* per stream (playback/record) info */
322         struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
323 };
324 
325 #define DBRI_MAX_VOLUME         63      /* Output volume */
326 #define DBRI_MAX_GAIN           15      /* Input gain */
327 
328 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
329 #define D_P             (1<<15) /* Program command & queue pointer valid */
330 #define D_G             (1<<14) /* Allow 4-Word SBus Burst */
331 #define D_S             (1<<13) /* Allow 16-Word SBus Burst */
332 #define D_E             (1<<12) /* Allow 8-Word SBus Burst */
333 #define D_X             (1<<7)  /* Sanity Timer Disable */
334 #define D_T             (1<<6)  /* Permit activation of the TE interface */
335 #define D_N             (1<<5)  /* Permit activation of the NT interface */
336 #define D_C             (1<<4)  /* Permit activation of the CHI interface */
337 #define D_F             (1<<3)  /* Force Sanity Timer Time-Out */
338 #define D_D             (1<<2)  /* Disable Master Mode */
339 #define D_H             (1<<1)  /* Halt for Analysis */
340 #define D_R             (1<<0)  /* Soft Reset */
341 
342 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
343 #define D_LITTLE_END    (1<<8)  /* Byte Order */
344 #define D_BIG_END       (0<<8)  /* Byte Order */
345 #define D_MRR           (1<<4)  /* Multiple Error Ack on SBus (read only) */
346 #define D_MLE           (1<<3)  /* Multiple Late Error on SBus (read only) */
347 #define D_LBG           (1<<2)  /* Lost Bus Grant on SBus (read only) */
348 #define D_MBE           (1<<1)  /* Burst Error on SBus (read only) */
349 #define D_IR            (1<<0)  /* Interrupt Indicator (read only) */
350 
351 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
352 #define D_ENPIO3        (1<<7)  /* Enable Pin 3 */
353 #define D_ENPIO2        (1<<6)  /* Enable Pin 2 */
354 #define D_ENPIO1        (1<<5)  /* Enable Pin 1 */
355 #define D_ENPIO0        (1<<4)  /* Enable Pin 0 */
356 #define D_ENPIO         (0xf0)  /* Enable all the pins */
357 #define D_PIO3          (1<<3)  /* Pin 3: 1: Data mode, 0: Ctrl mode */
358 #define D_PIO2          (1<<2)  /* Pin 2: 1: Onboard PDN */
359 #define D_PIO1          (1<<1)  /* Pin 1: 0: Reset */
360 #define D_PIO0          (1<<0)  /* Pin 0: 1: Speakerbox PDN */
361 
362 /* DBRI Commands (Page 20) */
363 #define D_WAIT          0x0     /* Stop execution */
364 #define D_PAUSE         0x1     /* Flush long pipes */
365 #define D_JUMP          0x2     /* New command queue */
366 #define D_IIQ           0x3     /* Initialize Interrupt Queue */
367 #define D_REX           0x4     /* Report command execution via interrupt */
368 #define D_SDP           0x5     /* Setup Data Pipe */
369 #define D_CDP           0x6     /* Continue Data Pipe (reread NULL Pointer) */
370 #define D_DTS           0x7     /* Define Time Slot */
371 #define D_SSP           0x8     /* Set short Data Pipe */
372 #define D_CHI           0x9     /* Set CHI Global Mode */
373 #define D_NT            0xa     /* NT Command */
374 #define D_TE            0xb     /* TE Command */
375 #define D_CDEC          0xc     /* Codec setup */
376 #define D_TEST          0xd     /* No comment */
377 #define D_CDM           0xe     /* CHI Data mode command */
378 
379 /* Special bits for some commands */
380 #define D_PIPE(v)      ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
381 
382 /* Setup Data Pipe */
383 /* IRM */
384 #define D_SDP_2SAME     (1<<18) /* Report 2nd time in a row value received */
385 #define D_SDP_CHANGE    (2<<18) /* Report any changes */
386 #define D_SDP_EVERY     (3<<18) /* Report any changes */
387 #define D_SDP_EOL       (1<<17) /* EOL interrupt enable */
388 #define D_SDP_IDLE      (1<<16) /* HDLC idle interrupt enable */
389 
390 /* Pipe data MODE */
391 #define D_SDP_MEM       (0<<13) /* To/from memory */
392 #define D_SDP_HDLC      (2<<13)
393 #define D_SDP_HDLC_D    (3<<13) /* D Channel (prio control) */
394 #define D_SDP_SER       (4<<13) /* Serial to serial */
395 #define D_SDP_FIXED     (6<<13) /* Short only */
396 #define D_SDP_MODE(v)   ((v)&(7<<13))
397 
398 #define D_SDP_TO_SER    (1<<12) /* Direction */
399 #define D_SDP_FROM_SER  (0<<12) /* Direction */
400 #define D_SDP_MSB       (1<<11) /* Bit order within Byte */
401 #define D_SDP_LSB       (0<<11) /* Bit order within Byte */
402 #define D_SDP_P         (1<<10) /* Pointer Valid */
403 #define D_SDP_A         (1<<8)  /* Abort */
404 #define D_SDP_C         (1<<7)  /* Clear */
405 
406 /* Define Time Slot */
407 #define D_DTS_VI        (1<<17) /* Valid Input Time-Slot Descriptor */
408 #define D_DTS_VO        (1<<16) /* Valid Output Time-Slot Descriptor */
409 #define D_DTS_INS       (1<<15) /* Insert Time Slot */
410 #define D_DTS_DEL       (0<<15) /* Delete Time Slot */
411 #define D_DTS_PRVIN(v) ((v)<<10)        /* Previous In Pipe */
412 #define D_DTS_PRVOUT(v)        ((v)<<5) /* Previous Out Pipe */
413 
414 /* Time Slot defines */
415 #define D_TS_LEN(v)     ((v)<<24)       /* Number of bits in this time slot */
416 #define D_TS_CYCLE(v)   ((v)<<14)       /* Bit Count at start of TS */
417 #define D_TS_DI         (1<<13) /* Data Invert */
418 #define D_TS_1CHANNEL   (0<<10) /* Single Channel / Normal mode */
419 #define D_TS_MONITOR    (2<<10) /* Monitor pipe */
420 #define D_TS_NONCONTIG  (3<<10) /* Non contiguous mode */
421 #define D_TS_ANCHOR     (7<<10) /* Starting short pipes */
422 #define D_TS_MON(v)    ((v)<<5) /* Monitor Pipe */
423 #define D_TS_NEXT(v)   ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
424 
425 /* Concentration Highway Interface Modes */
426 #define D_CHI_CHICM(v)  ((v)<<16)       /* Clock mode */
427 #define D_CHI_IR        (1<<15) /* Immediate Interrupt Report */
428 #define D_CHI_EN        (1<<14) /* CHIL Interrupt enabled */
429 #define D_CHI_OD        (1<<13) /* Open Drain Enable */
430 #define D_CHI_FE        (1<<12) /* Sample CHIFS on Rising Frame Edge */
431 #define D_CHI_FD        (1<<11) /* Frame Drive */
432 #define D_CHI_BPF(v)    ((v)<<0)        /* Bits per Frame */
433 
434 /* NT: These are here for completeness */
435 #define D_NT_FBIT       (1<<17) /* Frame Bit */
436 #define D_NT_NBF        (1<<16) /* Number of bad frames to loose framing */
437 #define D_NT_IRM_IMM    (1<<15) /* Interrupt Report & Mask: Immediate */
438 #define D_NT_IRM_EN     (1<<14) /* Interrupt Report & Mask: Enable */
439 #define D_NT_ISNT       (1<<13) /* Configure interface as NT */
440 #define D_NT_FT         (1<<12) /* Fixed Timing */
441 #define D_NT_EZ         (1<<11) /* Echo Channel is Zeros */
442 #define D_NT_IFA        (1<<10) /* Inhibit Final Activation */
443 #define D_NT_ACT        (1<<9)  /* Activate Interface */
444 #define D_NT_MFE        (1<<8)  /* Multiframe Enable */
445 #define D_NT_RLB(v)     ((v)<<5)        /* Remote Loopback */
446 #define D_NT_LLB(v)     ((v)<<2)        /* Local Loopback */
447 #define D_NT_FACT       (1<<1)  /* Force Activation */
448 #define D_NT_ABV        (1<<0)  /* Activate Bipolar Violation */
449 
450 /* Codec Setup */
451 #define D_CDEC_CK(v)    ((v)<<24)       /* Clock Select */
452 #define D_CDEC_FED(v)   ((v)<<12)       /* FSCOD Falling Edge Delay */
453 #define D_CDEC_RED(v)   ((v)<<0)        /* FSCOD Rising Edge Delay */
454 
455 /* Test */
456 #define D_TEST_RAM(v)   ((v)<<16)       /* RAM Pointer */
457 #define D_TEST_SIZE(v)  ((v)<<11)       /* */
458 #define D_TEST_ROMONOFF 0x5     /* Toggle ROM opcode monitor on/off */
459 #define D_TEST_PROC     0x6     /* Microprocessor test */
460 #define D_TEST_SER      0x7     /* Serial-Controller test */
461 #define D_TEST_RAMREAD  0x8     /* Copy from Ram to system memory */
462 #define D_TEST_RAMWRITE 0x9     /* Copy into Ram from system memory */
463 #define D_TEST_RAMBIST  0xa     /* RAM Built-In Self Test */
464 #define D_TEST_MCBIST   0xb     /* Microcontroller Built-In Self Test */
465 #define D_TEST_DUMP     0xe     /* ROM Dump */
466 
467 /* CHI Data Mode */
468 #define D_CDM_THI       (1 << 8)        /* Transmit Data on CHIDR Pin */
469 #define D_CDM_RHI       (1 << 7)        /* Receive Data on CHIDX Pin */
470 #define D_CDM_RCE       (1 << 6)        /* Receive on Rising Edge of CHICK */
471 #define D_CDM_XCE       (1 << 2) /* Transmit Data on Rising Edge of CHICK */
472 #define D_CDM_XEN       (1 << 1)        /* Transmit Highway Enable */
473 #define D_CDM_REN       (1 << 0)        /* Receive Highway Enable */
474 
475 /* The Interrupts */
476 #define D_INTR_BRDY     1       /* Buffer Ready for processing */
477 #define D_INTR_MINT     2       /* Marked Interrupt in RD/TD */
478 #define D_INTR_IBEG     3       /* Flag to idle transition detected (HDLC) */
479 #define D_INTR_IEND     4       /* Idle to flag transition detected (HDLC) */
480 #define D_INTR_EOL      5       /* End of List */
481 #define D_INTR_CMDI     6       /* Command has bean read */
482 #define D_INTR_XCMP     8       /* Transmission of frame complete */
483 #define D_INTR_SBRI     9       /* BRI status change info */
484 #define D_INTR_FXDT     10      /* Fixed data change */
485 #define D_INTR_CHIL     11      /* CHI lost frame sync (channel 36 only) */
486 #define D_INTR_COLL     11      /* Unrecoverable D-Channel collision */
487 #define D_INTR_DBYT     12      /* Dropped by frame slip */
488 #define D_INTR_RBYT     13      /* Repeated by frame slip */
489 #define D_INTR_LINT     14      /* Lost Interrupt */
490 #define D_INTR_UNDR     15      /* DMA underrun */
491 
492 #define D_INTR_TE       32
493 #define D_INTR_NT       34
494 #define D_INTR_CHI      36
495 #define D_INTR_CMD      38
496 
497 #define D_INTR_GETCHAN(v)       (((v) >> 24) & 0x3f)
498 #define D_INTR_GETCODE(v)       (((v) >> 20) & 0xf)
499 #define D_INTR_GETCMD(v)        (((v) >> 16) & 0xf)
500 #define D_INTR_GETVAL(v)        ((v) & 0xffff)
501 #define D_INTR_GETRVAL(v)       ((v) & 0xfffff)
502 
503 #define D_P_0           0       /* TE receive anchor */
504 #define D_P_1           1       /* TE transmit anchor */
505 #define D_P_2           2       /* NT transmit anchor */
506 #define D_P_3           3       /* NT receive anchor */
507 #define D_P_4           4       /* CHI send data */
508 #define D_P_5           5       /* CHI receive data */
509 #define D_P_6           6       /* */
510 #define D_P_7           7       /* */
511 #define D_P_8           8       /* */
512 #define D_P_9           9       /* */
513 #define D_P_10          10      /* */
514 #define D_P_11          11      /* */
515 #define D_P_12          12      /* */
516 #define D_P_13          13      /* */
517 #define D_P_14          14      /* */
518 #define D_P_15          15      /* */
519 #define D_P_16          16      /* CHI anchor pipe */
520 #define D_P_17          17      /* CHI send */
521 #define D_P_18          18      /* CHI receive */
522 #define D_P_19          19      /* CHI receive */
523 #define D_P_20          20      /* CHI receive */
524 #define D_P_21          21      /* */
525 #define D_P_22          22      /* */
526 #define D_P_23          23      /* */
527 #define D_P_24          24      /* */
528 #define D_P_25          25      /* */
529 #define D_P_26          26      /* */
530 #define D_P_27          27      /* */
531 #define D_P_28          28      /* */
532 #define D_P_29          29      /* */
533 #define D_P_30          30      /* */
534 #define D_P_31          31      /* */
535 
536 /* Transmit descriptor defines */
537 #define DBRI_TD_F       (1 << 31)       /* End of Frame */
538 #define DBRI_TD_D       (1 << 30)       /* Do not append CRC */
539 #define DBRI_TD_CNT(v)  ((v) << 16) /* Number of valid bytes in the buffer */
540 #define DBRI_TD_B       (1 << 15)       /* Final interrupt */
541 #define DBRI_TD_M       (1 << 14)       /* Marker interrupt */
542 #define DBRI_TD_I       (1 << 13)       /* Transmit Idle Characters */
543 #define DBRI_TD_FCNT(v) (v)             /* Flag Count */
544 #define DBRI_TD_UNR     (1 << 3) /* Underrun: transmitter is out of data */
545 #define DBRI_TD_ABT     (1 << 2)        /* Abort: frame aborted */
546 #define DBRI_TD_TBC     (1 << 0)        /* Transmit buffer Complete */
547 #define DBRI_TD_STATUS(v)       ((v) & 0xff)    /* Transmit status */
548                         /* Maximum buffer size per TD: almost 8KB */
549 #define DBRI_TD_MAXCNT  ((1 << 13) - 4)
550 
551 /* Receive descriptor defines */
552 #define DBRI_RD_F       (1 << 31)       /* End of Frame */
553 #define DBRI_RD_C       (1 << 30)       /* Completed buffer */
554 #define DBRI_RD_B       (1 << 15)       /* Final interrupt */
555 #define DBRI_RD_M       (1 << 14)       /* Marker interrupt */
556 #define DBRI_RD_BCNT(v) (v)             /* Buffer size */
557 #define DBRI_RD_CRC     (1 << 7)        /* 0: CRC is correct */
558 #define DBRI_RD_BBC     (1 << 6)        /* 1: Bad Byte received */
559 #define DBRI_RD_ABT     (1 << 5)        /* Abort: frame aborted */
560 #define DBRI_RD_OVRN    (1 << 3)        /* Overrun: data lost */
561 #define DBRI_RD_STATUS(v)      ((v) & 0xff)     /* Receive status */
562 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff)   /* Valid bytes in the buffer */
563 
564 /* stream_info[] access */
565 /* Translate the ALSA direction into the array index */
566 #define DBRI_STREAMNO(substream)                                \
567                 (substream->stream ==                           \
568                  SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
569 
570 /* Return a pointer to dbri_streaminfo */
571 #define DBRI_STREAM(dbri, substream)    \
572                 &dbri->stream_info[DBRI_STREAMNO(substream)]
573 
574 /*
575  * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
576  * So we have to reverse the bits. Note: not all bit lengths are supported
577  */
578 static __u32 reverse_bytes(__u32 b, int len)
579 {
580         switch (len) {
581         case 32:
582                 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
583         case 16:
584                 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
585         case 8:
586                 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
587         case 4:
588                 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
589         case 2:
590                 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
591         case 1:
592         case 0:
593                 break;
594         default:
595                 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
596         }
597 
598         return b;
599 }
600 
601 /*
602 ****************************************************************************
603 ************** DBRI initialization and command synchronization *************
604 ****************************************************************************
605 
606 Commands are sent to the DBRI by building a list of them in memory,
607 then writing the address of the first list item to DBRI register 8.
608 The list is terminated with a WAIT command, which generates a
609 CPU interrupt to signal completion.
610 
611 Since the DBRI can run in parallel with the CPU, several means of
612 synchronization present themselves. The method implemented here uses
613 the dbri_cmdwait() to wait for execution of batch of sent commands.
614 
615 A circular command buffer is used here. A new command is being added
616 while another can be executed. The scheme works by adding two WAIT commands
617 after each sent batch of commands. When the next batch is prepared it is
618 added after the WAIT commands then the WAITs are replaced with single JUMP
619 command to the new batch. The the DBRI is forced to reread the last WAIT
620 command (replaced by the JUMP by then). If the DBRI is still executing
621 previous commands the request to reread the WAIT command is ignored.
622 
623 Every time a routine wants to write commands to the DBRI, it must
624 first call dbri_cmdlock() and get pointer to a free space in
625 dbri->dma->cmd buffer. After this, the commands can be written to
626 the buffer, and dbri_cmdsend() is called with the final pointer value
627 to send them to the DBRI.
628 
629 */
630 
631 #define MAXLOOPS 20
632 /*
633  * Wait for the current command string to execute
634  */
635 static void dbri_cmdwait(struct snd_dbri *dbri)
636 {
637         int maxloops = MAXLOOPS;
638         unsigned long flags;
639 
640         /* Delay if previous commands are still being processed */
641         spin_lock_irqsave(&dbri->lock, flags);
642         while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
643                 spin_unlock_irqrestore(&dbri->lock, flags);
644                 msleep_interruptible(1);
645                 spin_lock_irqsave(&dbri->lock, flags);
646         }
647         spin_unlock_irqrestore(&dbri->lock, flags);
648 
649         if (maxloops == 0)
650                 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
651         else
652                 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
653                         MAXLOOPS - maxloops - 1);
654 }
655 /*
656  * Lock the command queue and return pointer to space for len cmd words
657  * It locks the cmdlock spinlock.
658  */
659 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
660 {
661         u32 dvma_addr = (u32)dbri->dma_dvma;
662 
663         /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
664         len += 2;
665         spin_lock(&dbri->cmdlock);
666         if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
667                 return dbri->cmdptr + 2;
668         else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
669                 return dbri->dma->cmd;
670         else
671                 printk(KERN_ERR "DBRI: no space for commands.");
672 
673         return NULL;
674 }
675 
676 /*
677  * Send prepared cmd string. It works by writing a JUMP cmd into
678  * the last WAIT cmd and force DBRI to reread the cmd.
679  * The JUMP cmd points to the new cmd string.
680  * It also releases the cmdlock spinlock.
681  *
682  * Lock must be held before calling this.
683  */
684 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
685 {
686         u32 dvma_addr = (u32)dbri->dma_dvma;
687         s32 tmp, addr;
688         static int wait_id = 0;
689 
690         wait_id++;
691         wait_id &= 0xffff;      /* restrict it to a 16 bit counter. */
692         *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
693         *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
694 
695         /* Replace the last command with JUMP */
696         addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
697         *(dbri->cmdptr+1) = addr;
698         *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
699 
700 #ifdef DBRI_DEBUG
701         if (cmd > dbri->cmdptr) {
702                 s32 *ptr;
703 
704                 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
705                         dprintk(D_CMD, "cmd: %lx:%08x\n",
706                                 (unsigned long)ptr, *ptr);
707         } else {
708                 s32 *ptr = dbri->cmdptr;
709 
710                 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
711                 ptr++;
712                 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
713                 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
714                         dprintk(D_CMD, "cmd: %lx:%08x\n",
715                                 (unsigned long)ptr, *ptr);
716         }
717 #endif
718 
719         /* Reread the last command */
720         tmp = sbus_readl(dbri->regs + REG0);
721         tmp |= D_P;
722         sbus_writel(tmp, dbri->regs + REG0);
723 
724         dbri->cmdptr = cmd;
725         spin_unlock(&dbri->cmdlock);
726 }
727 
728 /* Lock must be held when calling this */
729 static void dbri_reset(struct snd_dbri *dbri)
730 {
731         int i;
732         u32 tmp;
733 
734         dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
735                 sbus_readl(dbri->regs + REG0),
736                 sbus_readl(dbri->regs + REG2),
737                 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
738 
739         sbus_writel(D_R, dbri->regs + REG0);    /* Soft Reset */
740         for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
741                 udelay(10);
742 
743         /* A brute approach - DBRI falls back to working burst size by itself
744          * On SS20 D_S does not work, so do not try so high. */
745         tmp = sbus_readl(dbri->regs + REG0);
746         tmp |= D_G | D_E;
747         tmp &= ~D_S;
748         sbus_writel(tmp, dbri->regs + REG0);
749 }
750 
751 /* Lock must not be held before calling this */
752 static void dbri_initialize(struct snd_dbri *dbri)
753 {
754         u32 dvma_addr = (u32)dbri->dma_dvma;
755         s32 *cmd;
756         u32 dma_addr;
757         unsigned long flags;
758         int n;
759 
760         spin_lock_irqsave(&dbri->lock, flags);
761 
762         dbri_reset(dbri);
763 
764         /* Initialize pipes */
765         for (n = 0; n < DBRI_NO_PIPES; n++)
766                 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
767 
768         spin_lock_init(&dbri->cmdlock);
769         /*
770          * Initialize the interrupt ring buffer.
771          */
772         dma_addr = dvma_addr + dbri_dma_off(intr, 0);
773         dbri->dma->intr[0] = dma_addr;
774         dbri->dbri_irqp = 1;
775         /*
776          * Set up the interrupt queue
777          */
778         spin_lock(&dbri->cmdlock);
779         cmd = dbri->cmdptr = dbri->dma->cmd;
780         *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
781         *(cmd++) = dma_addr;
782         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
783         dbri->cmdptr = cmd;
784         *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
785         *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
786         dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
787         sbus_writel(dma_addr, dbri->regs + REG8);
788         spin_unlock(&dbri->cmdlock);
789 
790         spin_unlock_irqrestore(&dbri->lock, flags);
791         dbri_cmdwait(dbri);
792 }
793 
794 /*
795 ****************************************************************************
796 ************************** DBRI data pipe management ***********************
797 ****************************************************************************
798 
799 While DBRI control functions use the command and interrupt buffers, the
800 main data path takes the form of data pipes, which can be short (command
801 and interrupt driven), or long (attached to DMA buffers).  These functions
802 provide a rudimentary means of setting up and managing the DBRI's pipes,
803 but the calling functions have to make sure they respect the pipes' linked
804 list ordering, among other things.  The transmit and receive functions
805 here interface closely with the transmit and receive interrupt code.
806 
807 */
808 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
809 {
810         return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
811 }
812 
813 /* reset_pipe(dbri, pipe)
814  *
815  * Called on an in-use pipe to clear anything being transmitted or received
816  * Lock must be held before calling this.
817  */
818 static void reset_pipe(struct snd_dbri *dbri, int pipe)
819 {
820         int sdp;
821         int desc;
822         s32 *cmd;
823 
824         if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
825                 printk(KERN_ERR "DBRI: reset_pipe called with "
826                         "illegal pipe number\n");
827                 return;
828         }
829 
830         sdp = dbri->pipes[pipe].sdp;
831         if (sdp == 0) {
832                 printk(KERN_ERR "DBRI: reset_pipe called "
833                         "on uninitialized pipe\n");
834                 return;
835         }
836 
837         cmd = dbri_cmdlock(dbri, 3);
838         *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
839         *(cmd++) = 0;
840         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
841         dbri_cmdsend(dbri, cmd, 3);
842 
843         desc = dbri->pipes[pipe].first_desc;
844         if (desc >= 0)
845                 do {
846                         dbri->dma->desc[desc].ba = 0;
847                         dbri->dma->desc[desc].nda = 0;
848                         desc = dbri->next_desc[desc];
849                 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
850 
851         dbri->pipes[pipe].desc = -1;
852         dbri->pipes[pipe].first_desc = -1;
853 }
854 
855 /*
856  * Lock must be held before calling this.
857  */
858 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
859 {
860         if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
861                 printk(KERN_ERR "DBRI: setup_pipe called "
862                         "with illegal pipe number\n");
863                 return;
864         }
865 
866         if ((sdp & 0xf800) != sdp) {
867                 printk(KERN_ERR "DBRI: setup_pipe called "
868                         "with strange SDP value\n");
869                 /* sdp &= 0xf800; */
870         }
871 
872         /* If this is a fixed receive pipe, arrange for an interrupt
873          * every time its data changes
874          */
875         if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
876                 sdp |= D_SDP_CHANGE;
877 
878         sdp |= D_PIPE(pipe);
879         dbri->pipes[pipe].sdp = sdp;
880         dbri->pipes[pipe].desc = -1;
881         dbri->pipes[pipe].first_desc = -1;
882 
883         reset_pipe(dbri, pipe);
884 }
885 
886 /*
887  * Lock must be held before calling this.
888  */
889 static void link_time_slot(struct snd_dbri *dbri, int pipe,
890                            int prevpipe, int nextpipe,
891                            int length, int cycle)
892 {
893         s32 *cmd;
894         int val;
895 
896         if (pipe < 0 || pipe > DBRI_MAX_PIPE
897                         || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
898                         || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
899                 printk(KERN_ERR
900                     "DBRI: link_time_slot called with illegal pipe number\n");
901                 return;
902         }
903 
904         if (dbri->pipes[pipe].sdp == 0
905                         || dbri->pipes[prevpipe].sdp == 0
906                         || dbri->pipes[nextpipe].sdp == 0) {
907                 printk(KERN_ERR "DBRI: link_time_slot called "
908                         "on uninitialized pipe\n");
909                 return;
910         }
911 
912         dbri->pipes[prevpipe].nextpipe = pipe;
913         dbri->pipes[pipe].nextpipe = nextpipe;
914         dbri->pipes[pipe].length = length;
915 
916         cmd = dbri_cmdlock(dbri, 4);
917 
918         if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
919                 /* Deal with CHI special case:
920                  * "If transmission on edges 0 or 1 is desired, then cycle n
921                  *  (where n = # of bit times per frame...) must be used."
922                  *                  - DBRI data sheet, page 11
923                  */
924                 if (prevpipe == 16 && cycle == 0)
925                         cycle = dbri->chi_bpf;
926 
927                 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
928                 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
929                 *(cmd++) = 0;
930                 *(cmd++) =
931                     D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
932         } else {
933                 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
934                 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
935                 *(cmd++) =
936                     D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
937                 *(cmd++) = 0;
938         }
939         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
940 
941         dbri_cmdsend(dbri, cmd, 4);
942 }
943 
944 #if 0
945 /*
946  * Lock must be held before calling this.
947  */
948 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
949                              enum in_or_out direction, int prevpipe,
950                              int nextpipe)
951 {
952         s32 *cmd;
953         int val;
954 
955         if (pipe < 0 || pipe > DBRI_MAX_PIPE
956                         || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
957                         || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
958                 printk(KERN_ERR
959                     "DBRI: unlink_time_slot called with illegal pipe number\n");
960                 return;
961         }
962 
963         cmd = dbri_cmdlock(dbri, 4);
964 
965         if (direction == PIPEinput) {
966                 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
967                 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
968                 *(cmd++) = D_TS_NEXT(nextpipe);
969                 *(cmd++) = 0;
970         } else {
971                 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
972                 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
973                 *(cmd++) = 0;
974                 *(cmd++) = D_TS_NEXT(nextpipe);
975         }
976         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
977 
978         dbri_cmdsend(dbri, cmd, 4);
979 }
980 #endif
981 
982 /* xmit_fixed() / recv_fixed()
983  *
984  * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
985  * expected to change much, and which we don't need to buffer.
986  * The DBRI only interrupts us when the data changes (receive pipes),
987  * or only changes the data when this function is called (transmit pipes).
988  * Only short pipes (numbers 16-31) can be used in fixed data mode.
989  *
990  * These function operate on a 32-bit field, no matter how large
991  * the actual time slot is.  The interrupt handler takes care of bit
992  * ordering and alignment.  An 8-bit time slot will always end up
993  * in the low-order 8 bits, filled either MSB-first or LSB-first,
994  * depending on the settings passed to setup_pipe().
995  *
996  * Lock must not be held before calling it.
997  */
998 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
999 {
1000         s32 *cmd;
1001         unsigned long flags;
1002 
1003         if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1004                 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1005                 return;
1006         }
1007 
1008         if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1009                 printk(KERN_ERR "DBRI: xmit_fixed: "
1010                         "Uninitialized pipe %d\n", pipe);
1011                 return;
1012         }
1013 
1014         if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1015                 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1016                 return;
1017         }
1018 
1019         if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1020                 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1021                         pipe);
1022                 return;
1023         }
1024 
1025         /* DBRI short pipes always transmit LSB first */
1026 
1027         if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1028                 data = reverse_bytes(data, dbri->pipes[pipe].length);
1029 
1030         cmd = dbri_cmdlock(dbri, 3);
1031 
1032         *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1033         *(cmd++) = data;
1034         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1035 
1036         spin_lock_irqsave(&dbri->lock, flags);
1037         dbri_cmdsend(dbri, cmd, 3);
1038         spin_unlock_irqrestore(&dbri->lock, flags);
1039         dbri_cmdwait(dbri);
1040 
1041 }
1042 
1043 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1044 {
1045         if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1046                 printk(KERN_ERR "DBRI: recv_fixed called with "
1047                         "illegal pipe number\n");
1048                 return;
1049         }
1050 
1051         if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1052                 printk(KERN_ERR "DBRI: recv_fixed called on "
1053                         "non-fixed pipe %d\n", pipe);
1054                 return;
1055         }
1056 
1057         if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1058                 printk(KERN_ERR "DBRI: recv_fixed called on "
1059                         "transmit pipe %d\n", pipe);
1060                 return;
1061         }
1062 
1063         dbri->pipes[pipe].recv_fixed_ptr = ptr;
1064 }
1065 
1066 /* setup_descs()
1067  *
1068  * Setup transmit/receive data on a "long" pipe - i.e, one associated
1069  * with a DMA buffer.
1070  *
1071  * Only pipe numbers 0-15 can be used in this mode.
1072  *
1073  * This function takes a stream number pointing to a data buffer,
1074  * and work by building chains of descriptors which identify the
1075  * data buffers.  Buffers too large for a single descriptor will
1076  * be spread across multiple descriptors.
1077  *
1078  * All descriptors create a ring buffer.
1079  *
1080  * Lock must be held before calling this.
1081  */
1082 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1083 {
1084         struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1085         u32 dvma_addr = (u32)dbri->dma_dvma;
1086         __u32 dvma_buffer;
1087         int desc;
1088         int len;
1089         int first_desc = -1;
1090         int last_desc = -1;
1091 
1092         if (info->pipe < 0 || info->pipe > 15) {
1093                 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1094                 return -2;
1095         }
1096 
1097         if (dbri->pipes[info->pipe].sdp == 0) {
1098                 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1099                        info->pipe);
1100                 return -2;
1101         }
1102 
1103         dvma_buffer = info->dvma_buffer;
1104         len = info->size;
1105 
1106         if (streamno == DBRI_PLAY) {
1107                 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1108                         printk(KERN_ERR "DBRI: setup_descs: "
1109                                 "Called on receive pipe %d\n", info->pipe);
1110                         return -2;
1111                 }
1112         } else {
1113                 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1114                         printk(KERN_ERR
1115                             "DBRI: setup_descs: Called on transmit pipe %d\n",
1116                              info->pipe);
1117                         return -2;
1118                 }
1119                 /* Should be able to queue multiple buffers
1120                  * to receive on a pipe
1121                  */
1122                 if (pipe_active(dbri, info->pipe)) {
1123                         printk(KERN_ERR "DBRI: recv_on_pipe: "
1124                                 "Called on active pipe %d\n", info->pipe);
1125                         return -2;
1126                 }
1127 
1128                 /* Make sure buffer size is multiple of four */
1129                 len &= ~3;
1130         }
1131 
1132         /* Free descriptors if pipe has any */
1133         desc = dbri->pipes[info->pipe].first_desc;
1134         if (desc >= 0)
1135                 do {
1136                         dbri->dma->desc[desc].ba = 0;
1137                         dbri->dma->desc[desc].nda = 0;
1138                         desc = dbri->next_desc[desc];
1139                 } while (desc != -1 &&
1140                          desc != dbri->pipes[info->pipe].first_desc);
1141 
1142         dbri->pipes[info->pipe].desc = -1;
1143         dbri->pipes[info->pipe].first_desc = -1;
1144 
1145         desc = 0;
1146         while (len > 0) {
1147                 int mylen;
1148 
1149                 for (; desc < DBRI_NO_DESCS; desc++) {
1150                         if (!dbri->dma->desc[desc].ba)
1151                                 break;
1152                 }
1153 
1154                 if (desc == DBRI_NO_DESCS) {
1155                         printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1156                         return -1;
1157                 }
1158 
1159                 if (len > DBRI_TD_MAXCNT)
1160                         mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1161                 else
1162                         mylen = len;
1163 
1164                 if (mylen > period)
1165                         mylen = period;
1166 
1167                 dbri->next_desc[desc] = -1;
1168                 dbri->dma->desc[desc].ba = dvma_buffer;
1169                 dbri->dma->desc[desc].nda = 0;
1170 
1171                 if (streamno == DBRI_PLAY) {
1172                         dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1173                         dbri->dma->desc[desc].word4 = 0;
1174                         dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1175                 } else {
1176                         dbri->dma->desc[desc].word1 = 0;
1177                         dbri->dma->desc[desc].word4 =
1178                             DBRI_RD_B | DBRI_RD_BCNT(mylen);
1179                 }
1180 
1181                 if (first_desc == -1)
1182                         first_desc = desc;
1183                 else {
1184                         dbri->next_desc[last_desc] = desc;
1185                         dbri->dma->desc[last_desc].nda =
1186                             dvma_addr + dbri_dma_off(desc, desc);
1187                 }
1188 
1189                 last_desc = desc;
1190                 dvma_buffer += mylen;
1191                 len -= mylen;
1192         }
1193 
1194         if (first_desc == -1 || last_desc == -1) {
1195                 printk(KERN_ERR "DBRI: setup_descs: "
1196                         " Not enough descriptors available\n");
1197                 return -1;
1198         }
1199 
1200         dbri->dma->desc[last_desc].nda =
1201             dvma_addr + dbri_dma_off(desc, first_desc);
1202         dbri->next_desc[last_desc] = first_desc;
1203         dbri->pipes[info->pipe].first_desc = first_desc;
1204         dbri->pipes[info->pipe].desc = first_desc;
1205 
1206 #ifdef DBRI_DEBUG
1207         for (desc = first_desc; desc != -1;) {
1208                 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1209                         desc,
1210                         dbri->dma->desc[desc].word1,
1211                         dbri->dma->desc[desc].ba,
1212                         dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1213                         desc = dbri->next_desc[desc];
1214                         if (desc == first_desc)
1215                                 break;
1216         }
1217 #endif
1218         return 0;
1219 }
1220 
1221 /*
1222 ****************************************************************************
1223 ************************** DBRI - CHI interface ****************************
1224 ****************************************************************************
1225 
1226 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1227 multiplexed serial interface which the DBRI can operate in either master
1228 (give clock/frame sync) or slave (take clock/frame sync) mode.
1229 
1230 */
1231 
1232 enum master_or_slave { CHImaster, CHIslave };
1233 
1234 /*
1235  * Lock must not be held before calling it.
1236  */
1237 static void reset_chi(struct snd_dbri *dbri,
1238                       enum master_or_slave master_or_slave,
1239                       int bits_per_frame)
1240 {
1241         s32 *cmd;
1242         int val;
1243 
1244         /* Set CHI Anchor: Pipe 16 */
1245 
1246         cmd = dbri_cmdlock(dbri, 4);
1247         val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1248                 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1249         *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1250         *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1251         *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1252         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1253         dbri_cmdsend(dbri, cmd, 4);
1254 
1255         dbri->pipes[16].sdp = 1;
1256         dbri->pipes[16].nextpipe = 16;
1257 
1258         cmd = dbri_cmdlock(dbri, 4);
1259 
1260         if (master_or_slave == CHIslave) {
1261                 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1262                  *
1263                  * CHICM  = 0 (slave mode, 8 kHz frame rate)
1264                  * IR     = give immediate CHI status interrupt
1265                  * EN     = give CHI status interrupt upon change
1266                  */
1267                 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1268         } else {
1269                 /* Setup DBRI for CHI Master - generate clock, FS
1270                  *
1271                  * BPF                          =  bits per 8 kHz frame
1272                  * 12.288 MHz / CHICM_divisor   = clock rate
1273                  * FD = 1 - drive CHIFS on rising edge of CHICK
1274                  */
1275                 int clockrate = bits_per_frame * 8;
1276                 int divisor = 12288 / clockrate;
1277 
1278                 if (divisor > 255 || divisor * clockrate != 12288)
1279                         printk(KERN_ERR "DBRI: illegal bits_per_frame "
1280                                 "in setup_chi\n");
1281 
1282                 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1283                                     | D_CHI_BPF(bits_per_frame));
1284         }
1285 
1286         dbri->chi_bpf = bits_per_frame;
1287 
1288         /* CHI Data Mode
1289          *
1290          * RCE   =  0 - receive on falling edge of CHICK
1291          * XCE   =  1 - transmit on rising edge of CHICK
1292          * XEN   =  1 - enable transmitter
1293          * REN   =  1 - enable receiver
1294          */
1295 
1296         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1297         *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1298         *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1299 
1300         dbri_cmdsend(dbri, cmd, 4);
1301 }
1302 
1303 /*
1304 ****************************************************************************
1305 *********************** CS4215 audio codec management **********************
1306 ****************************************************************************
1307 
1308 In the standard SPARC audio configuration, the CS4215 codec is attached
1309 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1310 
1311  * Lock must not be held before calling it.
1312 
1313 */
1314 static void cs4215_setup_pipes(struct snd_dbri *dbri)
1315 {
1316         unsigned long flags;
1317 
1318         spin_lock_irqsave(&dbri->lock, flags);
1319         /*
1320          * Data mode:
1321          * Pipe  4: Send timeslots 1-4 (audio data)
1322          * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1323          * Pipe  6: Receive timeslots 1-4 (audio data)
1324          * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1325          *          interrupt, and the rest of the data (slot 5 and 8) is
1326          *          not relevant for us (only for doublechecking).
1327          *
1328          * Control mode:
1329          * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1330          * Pipe 18: Receive timeslot 1 (clb).
1331          * Pipe 19: Receive timeslot 7 (version).
1332          */
1333 
1334         setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1335         setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1336         setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1337         setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1338 
1339         setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1340         setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1341         setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1342         spin_unlock_irqrestore(&dbri->lock, flags);
1343 
1344         dbri_cmdwait(dbri);
1345 }
1346 
1347 static int cs4215_init_data(struct cs4215 *mm)
1348 {
1349         /*
1350          * No action, memory resetting only.
1351          *
1352          * Data Time Slot 5-8
1353          * Speaker,Line and Headphone enable. Gain set to the half.
1354          * Input is mike.
1355          */
1356         mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1357         mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1358         mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1359         mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1360 
1361         /*
1362          * Control Time Slot 1-4
1363          * 0: Default I/O voltage scale
1364          * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1365          * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1366          * 3: Tests disabled
1367          */
1368         mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1369         mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1370         mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1371         mm->ctrl[3] = 0;
1372 
1373         mm->status = 0;
1374         mm->version = 0xff;
1375         mm->precision = 8;      /* For ULAW */
1376         mm->channels = 1;
1377 
1378         return 0;
1379 }
1380 
1381 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1382 {
1383         if (muted) {
1384                 dbri->mm.data[0] |= 63;
1385                 dbri->mm.data[1] |= 63;
1386                 dbri->mm.data[2] &= ~15;
1387                 dbri->mm.data[3] &= ~15;
1388         } else {
1389                 /* Start by setting the playback attenuation. */
1390                 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1391                 int left_gain = info->left_gain & 0x3f;
1392                 int right_gain = info->right_gain & 0x3f;
1393 
1394                 dbri->mm.data[0] &= ~0x3f;      /* Reset the volume bits */
1395                 dbri->mm.data[1] &= ~0x3f;
1396                 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1397                 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1398 
1399                 /* Now set the recording gain. */
1400                 info = &dbri->stream_info[DBRI_REC];
1401                 left_gain = info->left_gain & 0xf;
1402                 right_gain = info->right_gain & 0xf;
1403                 dbri->mm.data[2] |= CS4215_LG(left_gain);
1404                 dbri->mm.data[3] |= CS4215_RG(right_gain);
1405         }
1406 
1407         xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1408 }
1409 
1410 /*
1411  * Set the CS4215 to data mode.
1412  */
1413 static void cs4215_open(struct snd_dbri *dbri)
1414 {
1415         int data_width;
1416         u32 tmp;
1417         unsigned long flags;
1418 
1419         dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1420                 dbri->mm.channels, dbri->mm.precision);
1421 
1422         /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1423          * to make sure this takes.  This avoids clicking noises.
1424          */
1425 
1426         cs4215_setdata(dbri, 1);
1427         udelay(125);
1428 
1429         /*
1430          * Data mode:
1431          * Pipe  4: Send timeslots 1-4 (audio data)
1432          * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1433          * Pipe  6: Receive timeslots 1-4 (audio data)
1434          * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1435          *          interrupt, and the rest of the data (slot 5 and 8) is
1436          *          not relevant for us (only for doublechecking).
1437          *
1438          * Just like in control mode, the time slots are all offset by eight
1439          * bits.  The CS4215, it seems, observes TSIN (the delayed signal)
1440          * even if it's the CHI master.  Don't ask me...
1441          */
1442         spin_lock_irqsave(&dbri->lock, flags);
1443         tmp = sbus_readl(dbri->regs + REG0);
1444         tmp &= ~(D_C);          /* Disable CHI */
1445         sbus_writel(tmp, dbri->regs + REG0);
1446 
1447         /* Switch CS4215 to data mode - set PIO3 to 1 */
1448         sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1449                     (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1450 
1451         reset_chi(dbri, CHIslave, 128);
1452 
1453         /* Note: this next doesn't work for 8-bit stereo, because the two
1454          * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1455          * (See CS4215 datasheet Fig 15)
1456          *
1457          * DBRI non-contiguous mode would be required to make this work.
1458          */
1459         data_width = dbri->mm.channels * dbri->mm.precision;
1460 
1461         link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1462         link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1463         link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1464         link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1465 
1466         /* FIXME: enable CHI after _setdata? */
1467         tmp = sbus_readl(dbri->regs + REG0);
1468         tmp |= D_C;             /* Enable CHI */
1469         sbus_writel(tmp, dbri->regs + REG0);
1470         spin_unlock_irqrestore(&dbri->lock, flags);
1471 
1472         cs4215_setdata(dbri, 0);
1473 }
1474 
1475 /*
1476  * Send the control information (i.e. audio format)
1477  */
1478 static int cs4215_setctrl(struct snd_dbri *dbri)
1479 {
1480         int i, val;
1481         u32 tmp;
1482         unsigned long flags;
1483 
1484         /* FIXME - let the CPU do something useful during these delays */
1485 
1486         /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1487          * to make sure this takes.  This avoids clicking noises.
1488          */
1489         cs4215_setdata(dbri, 1);
1490         udelay(125);
1491 
1492         /*
1493          * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1494          * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1495          */
1496         val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1497         sbus_writel(val, dbri->regs + REG2);
1498         dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1499         udelay(34);
1500 
1501         /* In Control mode, the CS4215 is a slave device, so the DBRI must
1502          * operate as CHI master, supplying clocking and frame synchronization.
1503          *
1504          * In Data mode, however, the CS4215 must be CHI master to insure
1505          * that its data stream is synchronous with its codec.
1506          *
1507          * The upshot of all this?  We start by putting the DBRI into master
1508          * mode, program the CS4215 in Control mode, then switch the CS4215
1509          * into Data mode and put the DBRI into slave mode.  Various timing
1510          * requirements must be observed along the way.
1511          *
1512          * Oh, and one more thing, on a SPARCStation 20 (and maybe
1513          * others?), the addressing of the CS4215's time slots is
1514          * offset by eight bits, so we add eight to all the "cycle"
1515          * values in the Define Time Slot (DTS) commands.  This is
1516          * done in hardware by a TI 248 that delays the DBRI->4215
1517          * frame sync signal by eight clock cycles.  Anybody know why?
1518          */
1519         spin_lock_irqsave(&dbri->lock, flags);
1520         tmp = sbus_readl(dbri->regs + REG0);
1521         tmp &= ~D_C;            /* Disable CHI */
1522         sbus_writel(tmp, dbri->regs + REG0);
1523 
1524         reset_chi(dbri, CHImaster, 128);
1525 
1526         /*
1527          * Control mode:
1528          * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1529          * Pipe 18: Receive timeslot 1 (clb).
1530          * Pipe 19: Receive timeslot 7 (version).
1531          */
1532 
1533         link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1534         link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1535         link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1536         spin_unlock_irqrestore(&dbri->lock, flags);
1537 
1538         /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1539         dbri->mm.ctrl[0] &= ~CS4215_CLB;
1540         xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1541 
1542         spin_lock_irqsave(&dbri->lock, flags);
1543         tmp = sbus_readl(dbri->regs + REG0);
1544         tmp |= D_C;             /* Enable CHI */
1545         sbus_writel(tmp, dbri->regs + REG0);
1546         spin_unlock_irqrestore(&dbri->lock, flags);
1547 
1548         for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1549                 msleep_interruptible(1);
1550 
1551         if (i == 0) {
1552                 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1553                         dbri->mm.status);
1554                 return -1;
1555         }
1556 
1557         /* Disable changes to our copy of the version number, as we are about
1558          * to leave control mode.
1559          */
1560         recv_fixed(dbri, 19, NULL);
1561 
1562         /* Terminate CS4215 control mode - data sheet says
1563          * "Set CLB=1 and send two more frames of valid control info"
1564          */
1565         dbri->mm.ctrl[0] |= CS4215_CLB;
1566         xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1567 
1568         /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1569         udelay(250);
1570 
1571         cs4215_setdata(dbri, 0);
1572 
1573         return 0;
1574 }
1575 
1576 /*
1577  * Setup the codec with the sampling rate, audio format and number of
1578  * channels.
1579  * As part of the process we resend the settings for the data
1580  * timeslots as well.
1581  */
1582 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1583                           snd_pcm_format_t format, unsigned int channels)
1584 {
1585         int freq_idx;
1586         int ret = 0;
1587 
1588         /* Lookup index for this rate */
1589         for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1590                 if (CS4215_FREQ[freq_idx].freq == rate)
1591                         break;
1592         }
1593         if (CS4215_FREQ[freq_idx].freq != rate) {
1594                 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1595                 return -1;
1596         }
1597 
1598         switch (format) {
1599         case SNDRV_PCM_FORMAT_MU_LAW:
1600                 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1601                 dbri->mm.precision = 8;
1602                 break;
1603         case SNDRV_PCM_FORMAT_A_LAW:
1604                 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1605                 dbri->mm.precision = 8;
1606                 break;
1607         case SNDRV_PCM_FORMAT_U8:
1608                 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1609                 dbri->mm.precision = 8;
1610                 break;
1611         case SNDRV_PCM_FORMAT_S16_BE:
1612                 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1613                 dbri->mm.precision = 16;
1614                 break;
1615         default:
1616                 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1617                 return -1;
1618         }
1619 
1620         /* Add rate parameters */
1621         dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1622         dbri->mm.ctrl[2] = CS4215_XCLK |
1623             CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1624 
1625         dbri->mm.channels = channels;
1626         if (channels == 2)
1627                 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1628 
1629         ret = cs4215_setctrl(dbri);
1630         if (ret == 0)
1631                 cs4215_open(dbri);      /* set codec to data mode */
1632 
1633         return ret;
1634 }
1635 
1636 /*
1637  *
1638  */
1639 static int cs4215_init(struct snd_dbri *dbri)
1640 {
1641         u32 reg2 = sbus_readl(dbri->regs + REG2);
1642         dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1643 
1644         /* Look for the cs4215 chips */
1645         if (reg2 & D_PIO2) {
1646                 dprintk(D_MM, "Onboard CS4215 detected\n");
1647                 dbri->mm.onboard = 1;
1648         }
1649         if (reg2 & D_PIO0) {
1650                 dprintk(D_MM, "Speakerbox detected\n");
1651                 dbri->mm.onboard = 0;
1652 
1653                 if (reg2 & D_PIO2) {
1654                         printk(KERN_INFO "DBRI: Using speakerbox / "
1655                                "ignoring onboard mmcodec.\n");
1656                         sbus_writel(D_ENPIO2, dbri->regs + REG2);
1657                 }
1658         }
1659 
1660         if (!(reg2 & (D_PIO0 | D_PIO2))) {
1661                 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1662                 return -EIO;
1663         }
1664 
1665         cs4215_setup_pipes(dbri);
1666         cs4215_init_data(&dbri->mm);
1667 
1668         /* Enable capture of the status & version timeslots. */
1669         recv_fixed(dbri, 18, &dbri->mm.status);
1670         recv_fixed(dbri, 19, &dbri->mm.version);
1671 
1672         dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1673         if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1674                 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1675                         dbri->mm.offset);
1676                 return -EIO;
1677         }
1678         dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1679 
1680         return 0;
1681 }
1682 
1683 /*
1684 ****************************************************************************
1685 *************************** DBRI interrupt handler *************************
1686 ****************************************************************************
1687 
1688 The DBRI communicates with the CPU mainly via a circular interrupt
1689 buffer.  When an interrupt is signaled, the CPU walks through the
1690 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1691 Complicated interrupts are handled by dedicated functions (which
1692 appear first in this file).  Any pending interrupts can be serviced by
1693 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1694 interrupts are disabled.
1695 
1696 */
1697 
1698 /* xmit_descs()
1699  *
1700  * Starts transmitting the current TD's for recording/playing.
1701  * For playback, ALSA has filled the DMA memory with new data (we hope).
1702  */
1703 static void xmit_descs(struct snd_dbri *dbri)
1704 {
1705         struct dbri_streaminfo *info;
1706         u32 dvma_addr;
1707         s32 *cmd;
1708         unsigned long flags;
1709         int first_td;
1710 
1711         if (dbri == NULL)
1712                 return;         /* Disabled */
1713 
1714         dvma_addr = (u32)dbri->dma_dvma;
1715         info = &dbri->stream_info[DBRI_REC];
1716         spin_lock_irqsave(&dbri->lock, flags);
1717 
1718         if (info->pipe >= 0) {
1719                 first_td = dbri->pipes[info->pipe].first_desc;
1720 
1721                 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1722 
1723                 /* Stream could be closed by the time we run. */
1724                 if (first_td >= 0) {
1725                         cmd = dbri_cmdlock(dbri, 2);
1726                         *(cmd++) = DBRI_CMD(D_SDP, 0,
1727                                             dbri->pipes[info->pipe].sdp
1728                                             | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1729                         *(cmd++) = dvma_addr +
1730                                    dbri_dma_off(desc, first_td);
1731                         dbri_cmdsend(dbri, cmd, 2);
1732 
1733                         /* Reset our admin of the pipe. */
1734                         dbri->pipes[info->pipe].desc = first_td;
1735                 }
1736         }
1737 
1738         info = &dbri->stream_info[DBRI_PLAY];
1739 
1740         if (info->pipe >= 0) {
1741                 first_td = dbri->pipes[info->pipe].first_desc;
1742 
1743                 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1744 
1745                 /* Stream could be closed by the time we run. */
1746                 if (first_td >= 0) {
1747                         cmd = dbri_cmdlock(dbri, 2);
1748                         *(cmd++) = DBRI_CMD(D_SDP, 0,
1749                                             dbri->pipes[info->pipe].sdp
1750                                             | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1751                         *(cmd++) = dvma_addr +
1752                                    dbri_dma_off(desc, first_td);
1753                         dbri_cmdsend(dbri, cmd, 2);
1754 
1755                         /* Reset our admin of the pipe. */
1756                         dbri->pipes[info->pipe].desc = first_td;
1757                 }
1758         }
1759 
1760         spin_unlock_irqrestore(&dbri->lock, flags);
1761 }
1762 
1763 /* transmission_complete_intr()
1764  *
1765  * Called by main interrupt handler when DBRI signals transmission complete
1766  * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1767  *
1768  * Walks through the pipe's list of transmit buffer descriptors and marks
1769  * them as available. Stops when the first descriptor is found without
1770  * TBC (Transmit Buffer Complete) set, or we've run through them all.
1771  *
1772  * The DMA buffers are not released. They form a ring buffer and
1773  * they are filled by ALSA while others are transmitted by DMA.
1774  *
1775  */
1776 
1777 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1778 {
1779         struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1780         int td = dbri->pipes[pipe].desc;
1781         int status;
1782 
1783         while (td >= 0) {
1784                 if (td >= DBRI_NO_DESCS) {
1785                         printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1786                         return;
1787                 }
1788 
1789                 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1790                 if (!(status & DBRI_TD_TBC))
1791                         break;
1792 
1793                 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1794 
1795                 dbri->dma->desc[td].word4 = 0;  /* Reset it for next time. */
1796                 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1797 
1798                 td = dbri->next_desc[td];
1799                 dbri->pipes[pipe].desc = td;
1800         }
1801 
1802         /* Notify ALSA */
1803         spin_unlock(&dbri->lock);
1804         snd_pcm_period_elapsed(info->substream);
1805         spin_lock(&dbri->lock);
1806 }
1807 
1808 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1809 {
1810         struct dbri_streaminfo *info;
1811         int rd = dbri->pipes[pipe].desc;
1812         s32 status;
1813 
1814         if (rd < 0 || rd >= DBRI_NO_DESCS) {
1815                 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1816                 return;
1817         }
1818 
1819         dbri->pipes[pipe].desc = dbri->next_desc[rd];
1820         status = dbri->dma->desc[rd].word1;
1821         dbri->dma->desc[rd].word1 = 0;  /* Reset it for next time. */
1822 
1823         info = &dbri->stream_info[DBRI_REC];
1824         info->offset += DBRI_RD_CNT(status);
1825 
1826         /* FIXME: Check status */
1827 
1828         dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1829                 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1830 
1831         /* Notify ALSA */
1832         spin_unlock(&dbri->lock);
1833         snd_pcm_period_elapsed(info->substream);
1834         spin_lock(&dbri->lock);
1835 }
1836 
1837 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1838 {
1839         int val = D_INTR_GETVAL(x);
1840         int channel = D_INTR_GETCHAN(x);
1841         int command = D_INTR_GETCMD(x);
1842         int code = D_INTR_GETCODE(x);
1843 #ifdef DBRI_DEBUG
1844         int rval = D_INTR_GETRVAL(x);
1845 #endif
1846 
1847         if (channel == D_INTR_CMD) {
1848                 dprintk(D_CMD, "INTR: Command: %-5s  Value:%d\n",
1849                         cmds[command], val);
1850         } else {
1851                 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1852                         channel, code, rval);
1853         }
1854 
1855         switch (code) {
1856         case D_INTR_CMDI:
1857                 if (command != D_WAIT)
1858                         printk(KERN_ERR "DBRI: Command read interrupt\n");
1859                 break;
1860         case D_INTR_BRDY:
1861                 reception_complete_intr(dbri, channel);
1862                 break;
1863         case D_INTR_XCMP:
1864         case D_INTR_MINT:
1865                 transmission_complete_intr(dbri, channel);
1866                 break;
1867         case D_INTR_UNDR:
1868                 /* UNDR - Transmission underrun
1869                  * resend SDP command with clear pipe bit (C) set
1870                  */
1871                 {
1872         /* FIXME: do something useful in case of underrun */
1873                         printk(KERN_ERR "DBRI: Underrun error\n");
1874 #if 0
1875                         s32 *cmd;
1876                         int pipe = channel;
1877                         int td = dbri->pipes[pipe].desc;
1878 
1879                         dbri->dma->desc[td].word4 = 0;
1880                         cmd = dbri_cmdlock(dbri, NoGetLock);
1881                         *(cmd++) = DBRI_CMD(D_SDP, 0,
1882                                             dbri->pipes[pipe].sdp
1883                                             | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1884                         *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1885                         dbri_cmdsend(dbri, cmd);
1886 #endif
1887                 }
1888                 break;
1889         case D_INTR_FXDT:
1890                 /* FXDT - Fixed data change */
1891                 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1892                         val = reverse_bytes(val, dbri->pipes[channel].length);
1893 
1894                 if (dbri->pipes[channel].recv_fixed_ptr)
1895                         *(dbri->pipes[channel].recv_fixed_ptr) = val;
1896                 break;
1897         default:
1898                 if (channel != D_INTR_CMD)
1899                         printk(KERN_WARNING
1900                                "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1901         }
1902 }
1903 
1904 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1905  * buffer until it finds a zero word (indicating nothing more to do
1906  * right now).  Non-zero words require processing and are handed off
1907  * to dbri_process_one_interrupt AFTER advancing the pointer.
1908  */
1909 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1910 {
1911         s32 x;
1912 
1913         while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1914                 dbri->dma->intr[dbri->dbri_irqp] = 0;
1915                 dbri->dbri_irqp++;
1916                 if (dbri->dbri_irqp == DBRI_INT_BLK)
1917                         dbri->dbri_irqp = 1;
1918 
1919                 dbri_process_one_interrupt(dbri, x);
1920         }
1921 }
1922 
1923 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1924 {
1925         struct snd_dbri *dbri = dev_id;
1926         static int errcnt = 0;
1927         int x;
1928 
1929         if (dbri == NULL)
1930                 return IRQ_NONE;
1931         spin_lock(&dbri->lock);
1932 
1933         /*
1934          * Read it, so the interrupt goes away.
1935          */
1936         x = sbus_readl(dbri->regs + REG1);
1937 
1938         if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1939                 u32 tmp;
1940 
1941                 if (x & D_MRR)
1942                         printk(KERN_ERR
1943                                "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1944                                x);
1945                 if (x & D_MLE)
1946                         printk(KERN_ERR
1947                                "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1948                                x);
1949                 if (x & D_LBG)
1950                         printk(KERN_ERR
1951                                "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1952                 if (x & D_MBE)
1953                         printk(KERN_ERR
1954                                "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1955 
1956                 /* Some of these SBus errors cause the chip's SBus circuitry
1957                  * to be disabled, so just re-enable and try to keep going.
1958                  *
1959                  * The only one I've seen is MRR, which will be triggered
1960                  * if you let a transmit pipe underrun, then try to CDP it.
1961                  *
1962                  * If these things persist, we reset the chip.
1963                  */
1964                 if ((++errcnt) % 10 == 0) {
1965                         dprintk(D_INT, "Interrupt errors exceeded.\n");
1966                         dbri_reset(dbri);
1967                 } else {
1968                         tmp = sbus_readl(dbri->regs + REG0);
1969                         tmp &= ~(D_D);
1970                         sbus_writel(tmp, dbri->regs + REG0);
1971                 }
1972         }
1973 
1974         dbri_process_interrupt_buffer(dbri);
1975 
1976         spin_unlock(&dbri->lock);
1977 
1978         return IRQ_HANDLED;
1979 }
1980 
1981 /****************************************************************************
1982                 PCM Interface
1983 ****************************************************************************/
1984 static const struct snd_pcm_hardware snd_dbri_pcm_hw = {
1985         .info           = SNDRV_PCM_INFO_MMAP |
1986                           SNDRV_PCM_INFO_INTERLEAVED |
1987                           SNDRV_PCM_INFO_BLOCK_TRANSFER |
1988                           SNDRV_PCM_INFO_MMAP_VALID |
1989                           SNDRV_PCM_INFO_BATCH,
1990         .formats        = SNDRV_PCM_FMTBIT_MU_LAW |
1991                           SNDRV_PCM_FMTBIT_A_LAW |
1992                           SNDRV_PCM_FMTBIT_U8 |
1993                           SNDRV_PCM_FMTBIT_S16_BE,
1994         .rates          = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1995         .rate_min               = 5512,
1996         .rate_max               = 48000,
1997         .channels_min           = 1,
1998         .channels_max           = 2,
1999         .buffer_bytes_max       = 64 * 1024,
2000         .period_bytes_min       = 1,
2001         .period_bytes_max       = DBRI_TD_MAXCNT,
2002         .periods_min            = 1,
2003         .periods_max            = 1024,
2004 };
2005 
2006 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2007                               struct snd_pcm_hw_rule *rule)
2008 {
2009         struct snd_interval *c = hw_param_interval(params,
2010                                 SNDRV_PCM_HW_PARAM_CHANNELS);
2011         struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2012         struct snd_mask fmt;
2013 
2014         snd_mask_any(&fmt);
2015         if (c->min > 1) {
2016                 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2017                 return snd_mask_refine(f, &fmt);
2018         }
2019         return 0;
2020 }
2021 
2022 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2023                                 struct snd_pcm_hw_rule *rule)
2024 {
2025         struct snd_interval *c = hw_param_interval(params,
2026                                 SNDRV_PCM_HW_PARAM_CHANNELS);
2027         struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2028         struct snd_interval ch;
2029 
2030         snd_interval_any(&ch);
2031         if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2032                 ch.min = 1;
2033                 ch.max = 1;
2034                 ch.integer = 1;
2035                 return snd_interval_refine(c, &ch);
2036         }
2037         return 0;
2038 }
2039 
2040 static int snd_dbri_open(struct snd_pcm_substream *substream)
2041 {
2042         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2043         struct snd_pcm_runtime *runtime = substream->runtime;
2044         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2045         unsigned long flags;
2046 
2047         dprintk(D_USR, "open audio output.\n");
2048         runtime->hw = snd_dbri_pcm_hw;
2049 
2050         spin_lock_irqsave(&dbri->lock, flags);
2051         info->substream = substream;
2052         info->offset = 0;
2053         info->dvma_buffer = 0;
2054         info->pipe = -1;
2055         spin_unlock_irqrestore(&dbri->lock, flags);
2056 
2057         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2058                             snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2059                             -1);
2060         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2061                             snd_hw_rule_channels, NULL,
2062                             SNDRV_PCM_HW_PARAM_CHANNELS,
2063                             -1);
2064 
2065         cs4215_open(dbri);
2066 
2067         return 0;
2068 }
2069 
2070 static int snd_dbri_close(struct snd_pcm_substream *substream)
2071 {
2072         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2073         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2074 
2075         dprintk(D_USR, "close audio output.\n");
2076         info->substream = NULL;
2077         info->offset = 0;
2078 
2079         return 0;
2080 }
2081 
2082 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2083                               struct snd_pcm_hw_params *hw_params)
2084 {
2085         struct snd_pcm_runtime *runtime = substream->runtime;
2086         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2087         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2088         int direction;
2089         int ret;
2090 
2091         /* set sampling rate, audio format and number of channels */
2092         ret = cs4215_prepare(dbri, params_rate(hw_params),
2093                              params_format(hw_params),
2094                              params_channels(hw_params));
2095         if (ret != 0)
2096                 return ret;
2097 
2098         if ((ret = snd_pcm_lib_malloc_pages(substream,
2099                                 params_buffer_bytes(hw_params))) < 0) {
2100                 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2101                 return ret;
2102         }
2103 
2104         /* hw_params can get called multiple times. Only map the DMA once.
2105          */
2106         if (info->dvma_buffer == 0) {
2107                 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2108                         direction = DMA_TO_DEVICE;
2109                 else
2110                         direction = DMA_FROM_DEVICE;
2111 
2112                 info->dvma_buffer =
2113                         dma_map_single(&dbri->op->dev,
2114                                        runtime->dma_area,
2115                                        params_buffer_bytes(hw_params),
2116                                        direction);
2117         }
2118 
2119         direction = params_buffer_bytes(hw_params);
2120         dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2121                 direction, info->dvma_buffer);
2122         return 0;
2123 }
2124 
2125 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2126 {
2127         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2128         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2129         int direction;
2130 
2131         dprintk(D_USR, "hw_free.\n");
2132 
2133         /* hw_free can get called multiple times. Only unmap the DMA once.
2134          */
2135         if (info->dvma_buffer) {
2136                 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2137                         direction = DMA_TO_DEVICE;
2138                 else
2139                         direction = DMA_FROM_DEVICE;
2140 
2141                 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2142                                  substream->runtime->buffer_size, direction);
2143                 info->dvma_buffer = 0;
2144         }
2145         if (info->pipe != -1) {
2146                 reset_pipe(dbri, info->pipe);
2147                 info->pipe = -1;
2148         }
2149 
2150         return snd_pcm_lib_free_pages(substream);
2151 }
2152 
2153 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2154 {
2155         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2156         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2157         int ret;
2158 
2159         info->size = snd_pcm_lib_buffer_bytes(substream);
2160         if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2161                 info->pipe = 4; /* Send pipe */
2162         else
2163                 info->pipe = 6; /* Receive pipe */
2164 
2165         spin_lock_irq(&dbri->lock);
2166         info->offset = 0;
2167 
2168         /* Setup the all the transmit/receive descriptors to cover the
2169          * whole DMA buffer.
2170          */
2171         ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2172                           snd_pcm_lib_period_bytes(substream));
2173 
2174         spin_unlock_irq(&dbri->lock);
2175 
2176         dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2177         return ret;
2178 }
2179 
2180 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2181 {
2182         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2183         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2184         int ret = 0;
2185 
2186         switch (cmd) {
2187         case SNDRV_PCM_TRIGGER_START:
2188                 dprintk(D_USR, "start audio, period is %d bytes\n",
2189                         (int)snd_pcm_lib_period_bytes(substream));
2190                 /* Re-submit the TDs. */
2191                 xmit_descs(dbri);
2192                 break;
2193         case SNDRV_PCM_TRIGGER_STOP:
2194                 dprintk(D_USR, "stop audio.\n");
2195                 reset_pipe(dbri, info->pipe);
2196                 break;
2197         default:
2198                 ret = -EINVAL;
2199         }
2200 
2201         return ret;
2202 }
2203 
2204 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2205 {
2206         struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2207         struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2208         snd_pcm_uframes_t ret;
2209 
2210         ret = bytes_to_frames(substream->runtime, info->offset)
2211                 % substream->runtime->buffer_size;
2212         dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2213                 ret, substream->runtime->buffer_size);
2214         return ret;
2215 }
2216 
2217 static const struct snd_pcm_ops snd_dbri_ops = {
2218         .open = snd_dbri_open,
2219         .close = snd_dbri_close,
2220         .ioctl = snd_pcm_lib_ioctl,
2221         .hw_params = snd_dbri_hw_params,
2222         .hw_free = snd_dbri_hw_free,
2223         .prepare = snd_dbri_prepare,
2224         .trigger = snd_dbri_trigger,
2225         .pointer = snd_dbri_pointer,
2226 };
2227 
2228 static int snd_dbri_pcm(struct snd_card *card)
2229 {
2230         struct snd_pcm *pcm;
2231         int err;
2232 
2233         if ((err = snd_pcm_new(card,
2234                                /* ID */             "sun_dbri",
2235                                /* device */         0,
2236                                /* playback count */ 1,
2237                                /* capture count */  1, &pcm)) < 0)
2238                 return err;
2239 
2240         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2241         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2242 
2243         pcm->private_data = card->private_data;
2244         pcm->info_flags = 0;
2245         strcpy(pcm->name, card->shortname);
2246 
2247         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
2248                                               snd_dma_continuous_data(GFP_KERNEL),
2249                                               64 * 1024, 64 * 1024);
2250         return 0;
2251 }
2252 
2253 /*****************************************************************************
2254                         Mixer interface
2255 *****************************************************************************/
2256 
2257 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2258                                   struct snd_ctl_elem_info *uinfo)
2259 {
2260         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2261         uinfo->count = 2;
2262         uinfo->value.integer.min = 0;
2263         if (kcontrol->private_value == DBRI_PLAY)
2264                 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2265         else
2266                 uinfo->value.integer.max = DBRI_MAX_GAIN;
2267         return 0;
2268 }
2269 
2270 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2271                                  struct snd_ctl_elem_value *ucontrol)
2272 {
2273         struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2274         struct dbri_streaminfo *info;
2275 
2276         if (snd_BUG_ON(!dbri))
2277                 return -EINVAL;
2278         info = &dbri->stream_info[kcontrol->private_value];
2279 
2280         ucontrol->value.integer.value[0] = info->left_gain;
2281         ucontrol->value.integer.value[1] = info->right_gain;
2282         return 0;
2283 }
2284 
2285 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2286                                  struct snd_ctl_elem_value *ucontrol)
2287 {
2288         struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2289         struct dbri_streaminfo *info =
2290                                 &dbri->stream_info[kcontrol->private_value];
2291         unsigned int vol[2];
2292         int changed = 0;
2293 
2294         vol[0] = ucontrol->value.integer.value[0];
2295         vol[1] = ucontrol->value.integer.value[1];
2296         if (kcontrol->private_value == DBRI_PLAY) {
2297                 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2298                         return -EINVAL;
2299         } else {
2300                 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2301                         return -EINVAL;
2302         }
2303 
2304         if (info->left_gain != vol[0]) {
2305                 info->left_gain = vol[0];
2306                 changed = 1;
2307         }
2308         if (info->right_gain != vol[1]) {
2309                 info->right_gain = vol[1];
2310                 changed = 1;
2311         }
2312         if (changed) {
2313                 /* First mute outputs, and wait 1/8000 sec (125 us)
2314                  * to make sure this takes.  This avoids clicking noises.
2315                  */
2316                 cs4215_setdata(dbri, 1);
2317                 udelay(125);
2318                 cs4215_setdata(dbri, 0);
2319         }
2320         return changed;
2321 }
2322 
2323 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2324                                   struct snd_ctl_elem_info *uinfo)
2325 {
2326         int mask = (kcontrol->private_value >> 16) & 0xff;
2327 
2328         uinfo->type = (mask == 1) ?
2329             SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2330         uinfo->count = 1;
2331         uinfo->value.integer.min = 0;
2332         uinfo->value.integer.max = mask;
2333         return 0;
2334 }
2335 
2336 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2337                                  struct snd_ctl_elem_value *ucontrol)
2338 {
2339         struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2340         int elem = kcontrol->private_value & 0xff;
2341         int shift = (kcontrol->private_value >> 8) & 0xff;
2342         int mask = (kcontrol->private_value >> 16) & 0xff;
2343         int invert = (kcontrol->private_value >> 24) & 1;
2344 
2345         if (snd_BUG_ON(!dbri))
2346                 return -EINVAL;
2347 
2348         if (elem < 4)
2349                 ucontrol->value.integer.value[0] =
2350                     (dbri->mm.data[elem] >> shift) & mask;
2351         else
2352                 ucontrol->value.integer.value[0] =
2353                     (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2354 
2355         if (invert == 1)
2356                 ucontrol->value.integer.value[0] =
2357                     mask - ucontrol->value.integer.value[0];
2358         return 0;
2359 }
2360 
2361 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2362                                  struct snd_ctl_elem_value *ucontrol)
2363 {
2364         struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2365         int elem = kcontrol->private_value & 0xff;
2366         int shift = (kcontrol->private_value >> 8) & 0xff;
2367         int mask = (kcontrol->private_value >> 16) & 0xff;
2368         int invert = (kcontrol->private_value >> 24) & 1;
2369         int changed = 0;
2370         unsigned short val;
2371 
2372         if (snd_BUG_ON(!dbri))
2373                 return -EINVAL;
2374 
2375         val = (ucontrol->value.integer.value[0] & mask);
2376         if (invert == 1)
2377                 val = mask - val;
2378         val <<= shift;
2379 
2380         if (elem < 4) {
2381                 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2382                                        ~(mask << shift)) | val;
2383                 changed = (val != dbri->mm.data[elem]);
2384         } else {
2385                 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2386                                            ~(mask << shift)) | val;
2387                 changed = (val != dbri->mm.ctrl[elem - 4]);
2388         }
2389 
2390         dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2391                 "mixer-value=%ld, mm-value=0x%x\n",
2392                 mask, changed, ucontrol->value.integer.value[0],
2393                 dbri->mm.data[elem & 3]);
2394 
2395         if (changed) {
2396                 /* First mute outputs, and wait 1/8000 sec (125 us)
2397                  * to make sure this takes.  This avoids clicking noises.
2398                  */
2399                 cs4215_setdata(dbri, 1);
2400                 udelay(125);
2401                 cs4215_setdata(dbri, 0);
2402         }
2403         return changed;
2404 }
2405 
2406 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2407    timeslots. Shift is the bit offset in the timeslot, mask defines the
2408    number of bits. invert is a boolean for use with attenuation.
2409  */
2410 #define CS4215_SINGLE(xname, entry, shift, mask, invert)        \
2411 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),         \
2412   .info = snd_cs4215_info_single,                               \
2413   .get = snd_cs4215_get_single, .put = snd_cs4215_put_single,   \
2414   .private_value = (entry) | ((shift) << 8) | ((mask) << 16) |  \
2415                         ((invert) << 24) },
2416 
2417 static struct snd_kcontrol_new dbri_controls[] = {
2418         {
2419          .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2420          .name  = "Playback Volume",
2421          .info  = snd_cs4215_info_volume,
2422          .get   = snd_cs4215_get_volume,
2423          .put   = snd_cs4215_put_volume,
2424          .private_value = DBRI_PLAY,
2425          },
2426         CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2427         CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2428         CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2429         {
2430          .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2431          .name  = "Capture Volume",
2432          .info  = snd_cs4215_info_volume,
2433          .get   = snd_cs4215_get_volume,
2434          .put   = snd_cs4215_put_volume,
2435          .private_value = DBRI_REC,
2436          },
2437         /* FIXME: mic/line switch */
2438         CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2439         CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2440         CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2441         CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2442 };
2443 
2444 static int snd_dbri_mixer(struct snd_card *card)
2445 {
2446         int idx, err;
2447         struct snd_dbri *dbri;
2448 
2449         if (snd_BUG_ON(!card || !card->private_data))
2450                 return -EINVAL;
2451         dbri = card->private_data;
2452 
2453         strcpy(card->mixername, card->shortname);
2454 
2455         for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2456                 err = snd_ctl_add(card,
2457                                 snd_ctl_new1(&dbri_controls[idx], dbri));
2458                 if (err < 0)
2459                         return err;
2460         }
2461 
2462         for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2463                 dbri->stream_info[idx].left_gain = 0;
2464                 dbri->stream_info[idx].right_gain = 0;
2465         }
2466 
2467         return 0;
2468 }
2469 
2470 /****************************************************************************
2471                         /proc interface
2472 ****************************************************************************/
2473 static void dbri_regs_read(struct snd_info_entry *entry,
2474                            struct snd_info_buffer *buffer)
2475 {
2476         struct snd_dbri *dbri = entry->private_data;
2477 
2478         snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2479         snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2480         snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2481         snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2482 }
2483 
2484 #ifdef DBRI_DEBUG
2485 static void dbri_debug_read(struct snd_info_entry *entry,
2486                             struct snd_info_buffer *buffer)
2487 {
2488         struct snd_dbri *dbri = entry->private_data;
2489         int pipe;
2490         snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2491 
2492         for (pipe = 0; pipe < 32; pipe++) {
2493                 if (pipe_active(dbri, pipe)) {
2494                         struct dbri_pipe *pptr = &dbri->pipes[pipe];
2495                         snd_iprintf(buffer,
2496                                     "Pipe %d: %s SDP=0x%x desc=%d, "
2497                                     "len=%d next %d\n",
2498                                     pipe,
2499                                    (pptr->sdp & D_SDP_TO_SER) ? "output" :
2500                                                                  "input",
2501                                     pptr->sdp, pptr->desc,
2502                                     pptr->length, pptr->nextpipe);
2503                 }
2504         }
2505 }
2506 #endif
2507 
2508 static void snd_dbri_proc(struct snd_card *card)
2509 {
2510         struct snd_dbri *dbri = card->private_data;
2511 
2512         snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
2513 #ifdef DBRI_DEBUG
2514         snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
2515 #endif
2516 }
2517 
2518 /*
2519 ****************************************************************************
2520 **************************** Initialization ********************************
2521 ****************************************************************************
2522 */
2523 static void snd_dbri_free(struct snd_dbri *dbri);
2524 
2525 static int snd_dbri_create(struct snd_card *card,
2526                            struct platform_device *op,
2527                            int irq, int dev)
2528 {
2529         struct snd_dbri *dbri = card->private_data;
2530         int err;
2531 
2532         spin_lock_init(&dbri->lock);
2533         dbri->op = op;
2534         dbri->irq = irq;
2535 
2536         dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2537                                        &dbri->dma_dvma, GFP_KERNEL);
2538         if (!dbri->dma)
2539                 return -ENOMEM;
2540 
2541         dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n",
2542                 dbri->dma, dbri->dma_dvma);
2543 
2544         /* Map the registers into memory. */
2545         dbri->regs_size = resource_size(&op->resource[0]);
2546         dbri->regs = of_ioremap(&op->resource[0], 0,
2547                                 dbri->regs_size, "DBRI Registers");
2548         if (!dbri->regs) {
2549                 printk(KERN_ERR "DBRI: could not allocate registers\n");
2550                 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2551                                   (void *)dbri->dma, dbri->dma_dvma);
2552                 return -EIO;
2553         }
2554 
2555         err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2556                           "DBRI audio", dbri);
2557         if (err) {
2558                 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2559                 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2560                 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2561                                   (void *)dbri->dma, dbri->dma_dvma);
2562                 return err;
2563         }
2564 
2565         /* Do low level initialization of the DBRI and CS4215 chips */
2566         dbri_initialize(dbri);
2567         err = cs4215_init(dbri);
2568         if (err) {
2569                 snd_dbri_free(dbri);
2570                 return err;
2571         }
2572 
2573         return 0;
2574 }
2575 
2576 static void snd_dbri_free(struct snd_dbri *dbri)
2577 {
2578         dprintk(D_GEN, "snd_dbri_free\n");
2579         dbri_reset(dbri);
2580 
2581         if (dbri->irq)
2582                 free_irq(dbri->irq, dbri);
2583 
2584         if (dbri->regs)
2585                 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2586 
2587         if (dbri->dma)
2588                 dma_free_coherent(&dbri->op->dev,
2589                                   sizeof(struct dbri_dma),
2590                                   (void *)dbri->dma, dbri->dma_dvma);
2591 }
2592 
2593 static int dbri_probe(struct platform_device *op)
2594 {
2595         struct snd_dbri *dbri;
2596         struct resource *rp;
2597         struct snd_card *card;
2598         static int dev = 0;
2599         int irq;
2600         int err;
2601 
2602         if (dev >= SNDRV_CARDS)
2603                 return -ENODEV;
2604         if (!enable[dev]) {
2605                 dev++;
2606                 return -ENOENT;
2607         }
2608 
2609         irq = op->archdata.irqs[0];
2610         if (irq <= 0) {
2611                 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2612                 return -ENODEV;
2613         }
2614 
2615         err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2616                            sizeof(struct snd_dbri), &card);
2617         if (err < 0)
2618                 return err;
2619 
2620         strcpy(card->driver, "DBRI");
2621         strcpy(card->shortname, "Sun DBRI");
2622         rp = &op->resource[0];
2623         sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2624                 card->shortname,
2625                 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2626 
2627         err = snd_dbri_create(card, op, irq, dev);
2628         if (err < 0) {
2629                 snd_card_free(card);
2630                 return err;
2631         }
2632 
2633         dbri = card->private_data;
2634         err = snd_dbri_pcm(card);
2635         if (err < 0)
2636                 goto _err;
2637 
2638         err = snd_dbri_mixer(card);
2639         if (err < 0)
2640                 goto _err;
2641 
2642         /* /proc file handling */
2643         snd_dbri_proc(card);
2644         dev_set_drvdata(&op->dev, card);
2645 
2646         err = snd_card_register(card);
2647         if (err < 0)
2648                 goto _err;
2649 
2650         printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2651                dev, dbri->regs,
2652                dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2653         dev++;
2654 
2655         return 0;
2656 
2657 _err:
2658         snd_dbri_free(dbri);
2659         snd_card_free(card);
2660         return err;
2661 }
2662 
2663 static int dbri_remove(struct platform_device *op)
2664 {
2665         struct snd_card *card = dev_get_drvdata(&op->dev);
2666 
2667         snd_dbri_free(card->private_data);
2668         snd_card_free(card);
2669 
2670         return 0;
2671 }
2672 
2673 static const struct of_device_id dbri_match[] = {
2674         {
2675                 .name = "SUNW,DBRIe",
2676         },
2677         {
2678                 .name = "SUNW,DBRIf",
2679         },
2680         {},
2681 };
2682 
2683 MODULE_DEVICE_TABLE(of, dbri_match);
2684 
2685 static struct platform_driver dbri_sbus_driver = {
2686         .driver = {
2687                 .name = "dbri",
2688                 .of_match_table = dbri_match,
2689         },
2690         .probe          = dbri_probe,
2691         .remove         = dbri_remove,
2692 };
2693 
2694 module_platform_driver(dbri_sbus_driver);
2695 

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