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Linux/sound/x86/intel_hdmi_audio.c

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  1 /*
  2  *   intel_hdmi_audio.c - Intel HDMI audio driver
  3  *
  4  *  Copyright (C) 2016 Intel Corp
  5  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
  6  *              Ramesh Babu K V <ramesh.babu@intel.com>
  7  *              Vaibhav Agarwal <vaibhav.agarwal@intel.com>
  8  *              Jerome Anand <jerome.anand@intel.com>
  9  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 10  *
 11  *  This program is free software; you can redistribute it and/or modify
 12  *  it under the terms of the GNU General Public License as published by
 13  *  the Free Software Foundation; version 2 of the License.
 14  *
 15  *  This program is distributed in the hope that it will be useful, but
 16  *  WITHOUT ANY WARRANTY; without even the implied warranty of
 17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 18  *  General Public License for more details.
 19  *
 20  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 21  * ALSA driver for Intel HDMI audio
 22  */
 23 
 24 #include <linux/types.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/io.h>
 27 #include <linux/slab.h>
 28 #include <linux/module.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/dma-mapping.h>
 32 #include <linux/delay.h>
 33 #include <sound/core.h>
 34 #include <sound/asoundef.h>
 35 #include <sound/pcm.h>
 36 #include <sound/pcm_params.h>
 37 #include <sound/initval.h>
 38 #include <sound/control.h>
 39 #include <sound/jack.h>
 40 #include <drm/drm_edid.h>
 41 #include <drm/intel_lpe_audio.h>
 42 #include "intel_hdmi_audio.h"
 43 
 44 #define for_each_pipe(card_ctx, pipe) \
 45         for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
 46 #define for_each_port(card_ctx, port) \
 47         for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
 48 
 49 /*standard module options for ALSA. This module supports only one card*/
 50 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
 51 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
 52 static bool single_port;
 53 
 54 module_param_named(index, hdmi_card_index, int, 0444);
 55 MODULE_PARM_DESC(index,
 56                 "Index value for INTEL Intel HDMI Audio controller.");
 57 module_param_named(id, hdmi_card_id, charp, 0444);
 58 MODULE_PARM_DESC(id,
 59                 "ID string for INTEL Intel HDMI Audio controller.");
 60 module_param(single_port, bool, 0444);
 61 MODULE_PARM_DESC(single_port,
 62                 "Single-port mode (for compatibility)");
 63 
 64 /*
 65  * ELD SA bits in the CEA Speaker Allocation data block
 66  */
 67 static const int eld_speaker_allocation_bits[] = {
 68         [0] = FL | FR,
 69         [1] = LFE,
 70         [2] = FC,
 71         [3] = RL | RR,
 72         [4] = RC,
 73         [5] = FLC | FRC,
 74         [6] = RLC | RRC,
 75         /* the following are not defined in ELD yet */
 76         [7] = 0,
 77 };
 78 
 79 /*
 80  * This is an ordered list!
 81  *
 82  * The preceding ones have better chances to be selected by
 83  * hdmi_channel_allocation().
 84  */
 85 static struct cea_channel_speaker_allocation channel_allocations[] = {
 86 /*                        channel:   7     6    5    4    3     2    1    0  */
 87 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
 88                                 /* 2.1 */
 89 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
 90                                 /* Dolby Surround */
 91 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
 92                                 /* surround40 */
 93 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
 94                                 /* surround41 */
 95 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
 96                                 /* surround50 */
 97 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 98                                 /* surround51 */
 99 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
100                                 /* 6.1 */
101 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
102                                 /* surround71 */
103 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
104 
105 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
106 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
107 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
108 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
109 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
110 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
111 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
112 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
113 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
114 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
115 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
116 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
117 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
118 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
119 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
120 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
121 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
122 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
123 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
124 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
125 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
126 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
127 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
128 };
129 
130 static const struct channel_map_table map_tables[] = {
131         { SNDRV_CHMAP_FL,       0x00,   FL },
132         { SNDRV_CHMAP_FR,       0x01,   FR },
133         { SNDRV_CHMAP_RL,       0x04,   RL },
134         { SNDRV_CHMAP_RR,       0x05,   RR },
135         { SNDRV_CHMAP_LFE,      0x02,   LFE },
136         { SNDRV_CHMAP_FC,       0x03,   FC },
137         { SNDRV_CHMAP_RLC,      0x06,   RLC },
138         { SNDRV_CHMAP_RRC,      0x07,   RRC },
139         {} /* terminator */
140 };
141 
142 /* hardware capability structure */
143 static const struct snd_pcm_hardware had_pcm_hardware = {
144         .info = (SNDRV_PCM_INFO_INTERLEAVED |
145                 SNDRV_PCM_INFO_MMAP |
146                 SNDRV_PCM_INFO_MMAP_VALID |
147                 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
148         .formats = (SNDRV_PCM_FMTBIT_S16_LE |
149                     SNDRV_PCM_FMTBIT_S24_LE |
150                     SNDRV_PCM_FMTBIT_S32_LE),
151         .rates = SNDRV_PCM_RATE_32000 |
152                 SNDRV_PCM_RATE_44100 |
153                 SNDRV_PCM_RATE_48000 |
154                 SNDRV_PCM_RATE_88200 |
155                 SNDRV_PCM_RATE_96000 |
156                 SNDRV_PCM_RATE_176400 |
157                 SNDRV_PCM_RATE_192000,
158         .rate_min = HAD_MIN_RATE,
159         .rate_max = HAD_MAX_RATE,
160         .channels_min = HAD_MIN_CHANNEL,
161         .channels_max = HAD_MAX_CHANNEL,
162         .buffer_bytes_max = HAD_MAX_BUFFER,
163         .period_bytes_min = HAD_MIN_PERIOD_BYTES,
164         .period_bytes_max = HAD_MAX_PERIOD_BYTES,
165         .periods_min = HAD_MIN_PERIODS,
166         .periods_max = HAD_MAX_PERIODS,
167         .fifo_size = HAD_FIFO_SIZE,
168 };
169 
170 /* Get the active PCM substream;
171  * Call had_substream_put() for unreferecing.
172  * Don't call this inside had_spinlock, as it takes by itself
173  */
174 static struct snd_pcm_substream *
175 had_substream_get(struct snd_intelhad *intelhaddata)
176 {
177         struct snd_pcm_substream *substream;
178         unsigned long flags;
179 
180         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
181         substream = intelhaddata->stream_info.substream;
182         if (substream)
183                 intelhaddata->stream_info.substream_refcount++;
184         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
185         return substream;
186 }
187 
188 /* Unref the active PCM substream;
189  * Don't call this inside had_spinlock, as it takes by itself
190  */
191 static void had_substream_put(struct snd_intelhad *intelhaddata)
192 {
193         unsigned long flags;
194 
195         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
196         intelhaddata->stream_info.substream_refcount--;
197         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
198 }
199 
200 static u32 had_config_offset(int pipe)
201 {
202         switch (pipe) {
203         default:
204         case 0:
205                 return AUDIO_HDMI_CONFIG_A;
206         case 1:
207                 return AUDIO_HDMI_CONFIG_B;
208         case 2:
209                 return AUDIO_HDMI_CONFIG_C;
210         }
211 }
212 
213 /* Register access functions */
214 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
215                                  int pipe, u32 reg)
216 {
217         return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
218 }
219 
220 static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
221                                    int pipe, u32 reg, u32 val)
222 {
223         iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
224 }
225 
226 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
227 {
228         if (!ctx->connected)
229                 *val = 0;
230         else
231                 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
232 }
233 
234 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
235 {
236         if (ctx->connected)
237                 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
238 }
239 
240 /*
241  * enable / disable audio configuration
242  *
243  * The normal read/modify should not directly be used on VLV2 for
244  * updating AUD_CONFIG register.
245  * This is because:
246  * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
247  * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
248  * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
249  * register. This field should be 1xy binary for configuration with 6 or
250  * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
251  * causes the "channels" field to be updated as 0xy binary resulting in
252  * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
253  * appropriate value when doing read-modify of AUD_CONFIG register.
254  */
255 static void had_enable_audio(struct snd_intelhad *intelhaddata,
256                              bool enable)
257 {
258         /* update the cached value */
259         intelhaddata->aud_config.regx.aud_en = enable;
260         had_write_register(intelhaddata, AUD_CONFIG,
261                            intelhaddata->aud_config.regval);
262 }
263 
264 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
265 static void had_ack_irqs(struct snd_intelhad *ctx)
266 {
267         u32 status_reg;
268 
269         if (!ctx->connected)
270                 return;
271         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
272         status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
273         had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
274         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
275 }
276 
277 /* Reset buffer pointers */
278 static void had_reset_audio(struct snd_intelhad *intelhaddata)
279 {
280         had_write_register(intelhaddata, AUD_HDMI_STATUS,
281                            AUD_HDMI_STATUSG_MASK_FUNCRST);
282         had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
283 }
284 
285 /*
286  * initialize audio channel status registers
287  * This function is called in the prepare callback
288  */
289 static int had_prog_status_reg(struct snd_pcm_substream *substream,
290                         struct snd_intelhad *intelhaddata)
291 {
292         union aud_ch_status_0 ch_stat0 = {.regval = 0};
293         union aud_ch_status_1 ch_stat1 = {.regval = 0};
294 
295         ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
296                                           IEC958_AES0_NONAUDIO) >> 1;
297         ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
298                                           IEC958_AES3_CON_CLOCK) >> 4;
299 
300         switch (substream->runtime->rate) {
301         case AUD_SAMPLE_RATE_32:
302                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
303                 break;
304 
305         case AUD_SAMPLE_RATE_44_1:
306                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
307                 break;
308         case AUD_SAMPLE_RATE_48:
309                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
310                 break;
311         case AUD_SAMPLE_RATE_88_2:
312                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
313                 break;
314         case AUD_SAMPLE_RATE_96:
315                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
316                 break;
317         case AUD_SAMPLE_RATE_176_4:
318                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
319                 break;
320         case AUD_SAMPLE_RATE_192:
321                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
322                 break;
323 
324         default:
325                 /* control should never come here */
326                 return -EINVAL;
327         }
328 
329         had_write_register(intelhaddata,
330                            AUD_CH_STATUS_0, ch_stat0.regval);
331 
332         switch (substream->runtime->format) {
333         case SNDRV_PCM_FORMAT_S16_LE:
334                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
335                 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
336                 break;
337         case SNDRV_PCM_FORMAT_S24_LE:
338         case SNDRV_PCM_FORMAT_S32_LE:
339                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
340                 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
341                 break;
342         default:
343                 return -EINVAL;
344         }
345 
346         had_write_register(intelhaddata,
347                            AUD_CH_STATUS_1, ch_stat1.regval);
348         return 0;
349 }
350 
351 /*
352  * function to initialize audio
353  * registers and buffer confgiuration registers
354  * This function is called in the prepare callback
355  */
356 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
357                                struct snd_intelhad *intelhaddata)
358 {
359         union aud_cfg cfg_val = {.regval = 0};
360         union aud_buf_config buf_cfg = {.regval = 0};
361         u8 channels;
362 
363         had_prog_status_reg(substream, intelhaddata);
364 
365         buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
366         buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
367         buf_cfg.regx.aud_delay = 0;
368         had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
369 
370         channels = substream->runtime->channels;
371         cfg_val.regx.num_ch = channels - 2;
372         if (channels <= 2)
373                 cfg_val.regx.layout = LAYOUT0;
374         else
375                 cfg_val.regx.layout = LAYOUT1;
376 
377         if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
378                 cfg_val.regx.packet_mode = 1;
379 
380         if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
381                 cfg_val.regx.left_align = 1;
382 
383         cfg_val.regx.val_bit = 1;
384 
385         /* fix up the DP bits */
386         if (intelhaddata->dp_output) {
387                 cfg_val.regx.dp_modei = 1;
388                 cfg_val.regx.set = 1;
389         }
390 
391         had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
392         intelhaddata->aud_config = cfg_val;
393         return 0;
394 }
395 
396 /*
397  * Compute derived values in channel_allocations[].
398  */
399 static void init_channel_allocations(void)
400 {
401         int i, j;
402         struct cea_channel_speaker_allocation *p;
403 
404         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
405                 p = channel_allocations + i;
406                 p->channels = 0;
407                 p->spk_mask = 0;
408                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
409                         if (p->speakers[j]) {
410                                 p->channels++;
411                                 p->spk_mask |= p->speakers[j];
412                         }
413         }
414 }
415 
416 /*
417  * The transformation takes two steps:
418  *
419  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
420  *            spk_mask => (channel_allocations[])         => ai->CA
421  *
422  * TODO: it could select the wrong CA from multiple candidates.
423  */
424 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
425                                   int channels)
426 {
427         int i;
428         int ca = 0;
429         int spk_mask = 0;
430 
431         /*
432          * CA defaults to 0 for basic stereo audio
433          */
434         if (channels <= 2)
435                 return 0;
436 
437         /*
438          * expand ELD's speaker allocation mask
439          *
440          * ELD tells the speaker mask in a compact(paired) form,
441          * expand ELD's notions to match the ones used by Audio InfoFrame.
442          */
443 
444         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
445                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
446                         spk_mask |= eld_speaker_allocation_bits[i];
447         }
448 
449         /* search for the first working match in the CA table */
450         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
451                 if (channels == channel_allocations[i].channels &&
452                 (spk_mask & channel_allocations[i].spk_mask) ==
453                                 channel_allocations[i].spk_mask) {
454                         ca = channel_allocations[i].ca_index;
455                         break;
456                 }
457         }
458 
459         dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
460 
461         return ca;
462 }
463 
464 /* from speaker bit mask to ALSA API channel position */
465 static int spk_to_chmap(int spk)
466 {
467         const struct channel_map_table *t = map_tables;
468 
469         for (; t->map; t++) {
470                 if (t->spk_mask == spk)
471                         return t->map;
472         }
473         return 0;
474 }
475 
476 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
477 {
478         int i, c;
479         int spk_mask = 0;
480         struct snd_pcm_chmap_elem *chmap;
481         u8 eld_high, eld_high_mask = 0xF0;
482         u8 high_msb;
483 
484         kfree(intelhaddata->chmap->chmap);
485         intelhaddata->chmap->chmap = NULL;
486 
487         chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
488         if (!chmap)
489                 return;
490 
491         dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
492                 intelhaddata->eld[DRM_ELD_SPEAKER]);
493 
494         /* WA: Fix the max channel supported to 8 */
495 
496         /*
497          * Sink may support more than 8 channels, if eld_high has more than
498          * one bit set. SOC supports max 8 channels.
499          * Refer eld_speaker_allocation_bits, for sink speaker allocation
500          */
501 
502         /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
503         eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
504         if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
505                 /* eld_high & (eld_high-1): if more than 1 bit set */
506                 /* 0x1F: 7 channels */
507                 for (i = 1; i < 4; i++) {
508                         high_msb = eld_high & (0x80 >> i);
509                         if (high_msb) {
510                                 intelhaddata->eld[DRM_ELD_SPEAKER] &=
511                                         high_msb | 0xF;
512                                 break;
513                         }
514                 }
515         }
516 
517         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
518                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
519                         spk_mask |= eld_speaker_allocation_bits[i];
520         }
521 
522         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
523                 if (spk_mask == channel_allocations[i].spk_mask) {
524                         for (c = 0; c < channel_allocations[i].channels; c++) {
525                                 chmap->map[c] = spk_to_chmap(
526                                         channel_allocations[i].speakers[
527                                                 (MAX_SPEAKERS - 1) - c]);
528                         }
529                         chmap->channels = channel_allocations[i].channels;
530                         intelhaddata->chmap->chmap = chmap;
531                         break;
532                 }
533         }
534         if (i >= ARRAY_SIZE(channel_allocations))
535                 kfree(chmap);
536 }
537 
538 /*
539  * ALSA API channel-map control callbacks
540  */
541 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
542                                 struct snd_ctl_elem_info *uinfo)
543 {
544         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
545         uinfo->count = HAD_MAX_CHANNEL;
546         uinfo->value.integer.min = 0;
547         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
548         return 0;
549 }
550 
551 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
552                                 struct snd_ctl_elem_value *ucontrol)
553 {
554         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
555         struct snd_intelhad *intelhaddata = info->private_data;
556         int i;
557         const struct snd_pcm_chmap_elem *chmap;
558 
559         memset(ucontrol->value.integer.value, 0,
560                sizeof(long) * HAD_MAX_CHANNEL);
561         mutex_lock(&intelhaddata->mutex);
562         if (!intelhaddata->chmap->chmap) {
563                 mutex_unlock(&intelhaddata->mutex);
564                 return 0;
565         }
566 
567         chmap = intelhaddata->chmap->chmap;
568         for (i = 0; i < chmap->channels; i++)
569                 ucontrol->value.integer.value[i] = chmap->map[i];
570         mutex_unlock(&intelhaddata->mutex);
571 
572         return 0;
573 }
574 
575 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
576                                                 struct snd_pcm *pcm)
577 {
578         int err;
579 
580         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
581                         NULL, 0, (unsigned long)intelhaddata,
582                         &intelhaddata->chmap);
583         if (err < 0)
584                 return err;
585 
586         intelhaddata->chmap->private_data = intelhaddata;
587         intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
588         intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
589         intelhaddata->chmap->chmap = NULL;
590         return 0;
591 }
592 
593 /*
594  * Initialize Data Island Packets registers
595  * This function is called in the prepare callback
596  */
597 static void had_prog_dip(struct snd_pcm_substream *substream,
598                          struct snd_intelhad *intelhaddata)
599 {
600         int i;
601         union aud_ctrl_st ctrl_state = {.regval = 0};
602         union aud_info_frame2 frame2 = {.regval = 0};
603         union aud_info_frame3 frame3 = {.regval = 0};
604         u8 checksum = 0;
605         u32 info_frame;
606         int channels;
607         int ca;
608 
609         channels = substream->runtime->channels;
610 
611         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
612 
613         ca = had_channel_allocation(intelhaddata, channels);
614         if (intelhaddata->dp_output) {
615                 info_frame = DP_INFO_FRAME_WORD1;
616                 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
617         } else {
618                 info_frame = HDMI_INFO_FRAME_WORD1;
619                 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
620                 frame3.regx.chnl_alloc = ca;
621 
622                 /* Calculte the byte wide checksum for all valid DIP words */
623                 for (i = 0; i < BYTES_PER_WORD; i++)
624                         checksum += (info_frame >> (i * 8)) & 0xff;
625                 for (i = 0; i < BYTES_PER_WORD; i++)
626                         checksum += (frame2.regval >> (i * 8)) & 0xff;
627                 for (i = 0; i < BYTES_PER_WORD; i++)
628                         checksum += (frame3.regval >> (i * 8)) & 0xff;
629 
630                 frame2.regx.chksum = -(checksum);
631         }
632 
633         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
634         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
635         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
636 
637         /* program remaining DIP words with zero */
638         for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
639                 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
640 
641         ctrl_state.regx.dip_freq = 1;
642         ctrl_state.regx.dip_en_sta = 1;
643         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
644 }
645 
646 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
647 {
648         u32 maud_val;
649 
650         /* Select maud according to DP 1.2 spec */
651         if (link_rate == DP_2_7_GHZ) {
652                 switch (aud_samp_freq) {
653                 case AUD_SAMPLE_RATE_32:
654                         maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
655                         break;
656 
657                 case AUD_SAMPLE_RATE_44_1:
658                         maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
659                         break;
660 
661                 case AUD_SAMPLE_RATE_48:
662                         maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
663                         break;
664 
665                 case AUD_SAMPLE_RATE_88_2:
666                         maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
667                         break;
668 
669                 case AUD_SAMPLE_RATE_96:
670                         maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
671                         break;
672 
673                 case AUD_SAMPLE_RATE_176_4:
674                         maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
675                         break;
676 
677                 case HAD_MAX_RATE:
678                         maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
679                         break;
680 
681                 default:
682                         maud_val = -EINVAL;
683                         break;
684                 }
685         } else if (link_rate == DP_1_62_GHZ) {
686                 switch (aud_samp_freq) {
687                 case AUD_SAMPLE_RATE_32:
688                         maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
689                         break;
690 
691                 case AUD_SAMPLE_RATE_44_1:
692                         maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
693                         break;
694 
695                 case AUD_SAMPLE_RATE_48:
696                         maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
697                         break;
698 
699                 case AUD_SAMPLE_RATE_88_2:
700                         maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
701                         break;
702 
703                 case AUD_SAMPLE_RATE_96:
704                         maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
705                         break;
706 
707                 case AUD_SAMPLE_RATE_176_4:
708                         maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
709                         break;
710 
711                 case HAD_MAX_RATE:
712                         maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
713                         break;
714 
715                 default:
716                         maud_val = -EINVAL;
717                         break;
718                 }
719         } else
720                 maud_val = -EINVAL;
721 
722         return maud_val;
723 }
724 
725 /*
726  * Program HDMI audio CTS value
727  *
728  * @aud_samp_freq: sampling frequency of audio data
729  * @tmds: sampling frequency of the display data
730  * @link_rate: DP link rate
731  * @n_param: N value, depends on aud_samp_freq
732  * @intelhaddata: substream private data
733  *
734  * Program CTS register based on the audio and display sampling frequency
735  */
736 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
737                          u32 n_param, struct snd_intelhad *intelhaddata)
738 {
739         u32 cts_val;
740         u64 dividend, divisor;
741 
742         if (intelhaddata->dp_output) {
743                 /* Substitute cts_val with Maud according to DP 1.2 spec*/
744                 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
745         } else {
746                 /* Calculate CTS according to HDMI 1.3a spec*/
747                 dividend = (u64)tmds * n_param*1000;
748                 divisor = 128 * aud_samp_freq;
749                 cts_val = div64_u64(dividend, divisor);
750         }
751         dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
752                  tmds, n_param, cts_val);
753         had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
754 }
755 
756 static int had_calculate_n_value(u32 aud_samp_freq)
757 {
758         int n_val;
759 
760         /* Select N according to HDMI 1.3a spec*/
761         switch (aud_samp_freq) {
762         case AUD_SAMPLE_RATE_32:
763                 n_val = 4096;
764                 break;
765 
766         case AUD_SAMPLE_RATE_44_1:
767                 n_val = 6272;
768                 break;
769 
770         case AUD_SAMPLE_RATE_48:
771                 n_val = 6144;
772                 break;
773 
774         case AUD_SAMPLE_RATE_88_2:
775                 n_val = 12544;
776                 break;
777 
778         case AUD_SAMPLE_RATE_96:
779                 n_val = 12288;
780                 break;
781 
782         case AUD_SAMPLE_RATE_176_4:
783                 n_val = 25088;
784                 break;
785 
786         case HAD_MAX_RATE:
787                 n_val = 24576;
788                 break;
789 
790         default:
791                 n_val = -EINVAL;
792                 break;
793         }
794         return n_val;
795 }
796 
797 /*
798  * Program HDMI audio N value
799  *
800  * @aud_samp_freq: sampling frequency of audio data
801  * @n_param: N value, depends on aud_samp_freq
802  * @intelhaddata: substream private data
803  *
804  * This function is called in the prepare callback.
805  * It programs based on the audio and display sampling frequency
806  */
807 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
808                       struct snd_intelhad *intelhaddata)
809 {
810         int n_val;
811 
812         if (intelhaddata->dp_output) {
813                 /*
814                  * According to DP specs, Maud and Naud values hold
815                  * a relationship, which is stated as:
816                  * Maud/Naud = 512 * fs / f_LS_Clk
817                  * where, fs is the sampling frequency of the audio stream
818                  * and Naud is 32768 for Async clock.
819                  */
820 
821                 n_val = DP_NAUD_VAL;
822         } else
823                 n_val = had_calculate_n_value(aud_samp_freq);
824 
825         if (n_val < 0)
826                 return n_val;
827 
828         had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
829         *n_param = n_val;
830         return 0;
831 }
832 
833 /*
834  * PCM ring buffer handling
835  *
836  * The hardware provides a ring buffer with the fixed 4 buffer descriptors
837  * (BDs).  The driver maps these 4 BDs onto the PCM ring buffer.  The mapping
838  * moves at each period elapsed.  The below illustrates how it works:
839  *
840  * At time=0
841  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
842  *  BD  | 0 | 1 | 2 | 3 |
843  *
844  * At time=1 (period elapsed)
845  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
846  *  BD      | 1 | 2 | 3 | 0 |
847  *
848  * At time=2 (second period elapsed)
849  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
850  *  BD          | 2 | 3 | 0 | 1 |
851  *
852  * The bd_head field points to the index of the BD to be read.  It's also the
853  * position to be filled at next.  The pcm_head and the pcm_filled fields
854  * point to the indices of the current position and of the next position to
855  * be filled, respectively.  For PCM buffer there are both _head and _filled
856  * because they may be difference when nperiods > 4.  For example, in the
857  * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
858  *
859  * pcm_head (=1) --v               v-- pcm_filled (=5)
860  *       PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
861  *       BD      | 1 | 2 | 3 | 0 |
862  *  bd_head (=1) --^               ^-- next to fill (= bd_head)
863  *
864  * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
865  * the hardware skips those BDs in the loop.
866  *
867  * An exceptional setup is the case with nperiods=1.  Since we have to update
868  * BDs after finishing one BD processing, we'd need at least two BDs, where
869  * both BDs point to the same content, the same address, the same size of the
870  * whole PCM buffer.
871  */
872 
873 #define AUD_BUF_ADDR(x)         (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
874 #define AUD_BUF_LEN(x)          (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
875 
876 /* Set up a buffer descriptor at the "filled" position */
877 static void had_prog_bd(struct snd_pcm_substream *substream,
878                         struct snd_intelhad *intelhaddata)
879 {
880         int idx = intelhaddata->bd_head;
881         int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
882         u32 addr = substream->runtime->dma_addr + ofs;
883 
884         addr |= AUD_BUF_VALID;
885         if (!substream->runtime->no_period_wakeup)
886                 addr |= AUD_BUF_INTR_EN;
887         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
888         had_write_register(intelhaddata, AUD_BUF_LEN(idx),
889                            intelhaddata->period_bytes);
890 
891         /* advance the indices to the next */
892         intelhaddata->bd_head++;
893         intelhaddata->bd_head %= intelhaddata->num_bds;
894         intelhaddata->pcmbuf_filled++;
895         intelhaddata->pcmbuf_filled %= substream->runtime->periods;
896 }
897 
898 /* invalidate a buffer descriptor with the given index */
899 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
900                               int idx)
901 {
902         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
903         had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
904 }
905 
906 /* Initial programming of ring buffer */
907 static void had_init_ringbuf(struct snd_pcm_substream *substream,
908                              struct snd_intelhad *intelhaddata)
909 {
910         struct snd_pcm_runtime *runtime = substream->runtime;
911         int i, num_periods;
912 
913         num_periods = runtime->periods;
914         intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
915         /* set the minimum 2 BDs for num_periods=1 */
916         intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
917         intelhaddata->period_bytes =
918                 frames_to_bytes(runtime, runtime->period_size);
919         WARN_ON(intelhaddata->period_bytes & 0x3f);
920 
921         intelhaddata->bd_head = 0;
922         intelhaddata->pcmbuf_head = 0;
923         intelhaddata->pcmbuf_filled = 0;
924 
925         for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
926                 if (i < intelhaddata->num_bds)
927                         had_prog_bd(substream, intelhaddata);
928                 else /* invalidate the rest */
929                         had_invalidate_bd(intelhaddata, i);
930         }
931 
932         intelhaddata->bd_head = 0; /* reset at head again before starting */
933 }
934 
935 /* process a bd, advance to the next */
936 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
937                                 struct snd_intelhad *intelhaddata)
938 {
939         int num_periods = substream->runtime->periods;
940 
941         /* reprogram the next buffer */
942         had_prog_bd(substream, intelhaddata);
943 
944         /* proceed to next */
945         intelhaddata->pcmbuf_head++;
946         intelhaddata->pcmbuf_head %= num_periods;
947 }
948 
949 /* process the current BD(s);
950  * returns the current PCM buffer byte position, or -EPIPE for underrun.
951  */
952 static int had_process_ringbuf(struct snd_pcm_substream *substream,
953                                struct snd_intelhad *intelhaddata)
954 {
955         int len, processed;
956         unsigned long flags;
957 
958         processed = 0;
959         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
960         for (;;) {
961                 /* get the remaining bytes on the buffer */
962                 had_read_register(intelhaddata,
963                                   AUD_BUF_LEN(intelhaddata->bd_head),
964                                   &len);
965                 if (len < 0 || len > intelhaddata->period_bytes) {
966                         dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
967                                 len);
968                         len = -EPIPE;
969                         goto out;
970                 }
971 
972                 if (len > 0) /* OK, this is the current buffer */
973                         break;
974 
975                 /* len=0 => already empty, check the next buffer */
976                 if (++processed >= intelhaddata->num_bds) {
977                         len = -EPIPE; /* all empty? - report underrun */
978                         goto out;
979                 }
980                 had_advance_ringbuf(substream, intelhaddata);
981         }
982 
983         len = intelhaddata->period_bytes - len;
984         len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
985  out:
986         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
987         return len;
988 }
989 
990 /* called from irq handler */
991 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
992 {
993         struct snd_pcm_substream *substream;
994 
995         substream = had_substream_get(intelhaddata);
996         if (!substream)
997                 return; /* no stream? - bail out */
998 
999         if (!intelhaddata->connected) {
1000                 snd_pcm_stop_xrun(substream);
1001                 goto out; /* disconnected? - bail out */
1002         }
1003 
1004         /* process or stop the stream */
1005         if (had_process_ringbuf(substream, intelhaddata) < 0)
1006                 snd_pcm_stop_xrun(substream);
1007         else
1008                 snd_pcm_period_elapsed(substream);
1009 
1010  out:
1011         had_substream_put(intelhaddata);
1012 }
1013 
1014 /*
1015  * The interrupt status 'sticky' bits might not be cleared by
1016  * setting '1' to that bit once...
1017  */
1018 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1019 {
1020         int i;
1021         u32 val;
1022 
1023         for (i = 0; i < 100; i++) {
1024                 /* clear bit30, 31 AUD_HDMI_STATUS */
1025                 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1026                 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1027                         return;
1028                 udelay(100);
1029                 cond_resched();
1030                 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1031         }
1032         dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1033 }
1034 
1035 /* Perform some reset procedure but only when need_reset is set;
1036  * this is called from prepare or hw_free callbacks once after trigger STOP
1037  * or underrun has been processed in order to settle down the h/w state.
1038  */
1039 static void had_do_reset(struct snd_intelhad *intelhaddata)
1040 {
1041         if (!intelhaddata->need_reset || !intelhaddata->connected)
1042                 return;
1043 
1044         /* Reset buffer pointers */
1045         had_reset_audio(intelhaddata);
1046         wait_clear_underrun_bit(intelhaddata);
1047         intelhaddata->need_reset = false;
1048 }
1049 
1050 /* called from irq handler */
1051 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1052 {
1053         struct snd_pcm_substream *substream;
1054 
1055         /* Report UNDERRUN error to above layers */
1056         substream = had_substream_get(intelhaddata);
1057         if (substream) {
1058                 snd_pcm_stop_xrun(substream);
1059                 had_substream_put(intelhaddata);
1060         }
1061         intelhaddata->need_reset = true;
1062 }
1063 
1064 /*
1065  * ALSA PCM open callback
1066  */
1067 static int had_pcm_open(struct snd_pcm_substream *substream)
1068 {
1069         struct snd_intelhad *intelhaddata;
1070         struct snd_pcm_runtime *runtime;
1071         int retval;
1072 
1073         intelhaddata = snd_pcm_substream_chip(substream);
1074         runtime = substream->runtime;
1075 
1076         pm_runtime_get_sync(intelhaddata->dev);
1077 
1078         /* set the runtime hw parameter with local snd_pcm_hardware struct */
1079         runtime->hw = had_pcm_hardware;
1080 
1081         retval = snd_pcm_hw_constraint_integer(runtime,
1082                          SNDRV_PCM_HW_PARAM_PERIODS);
1083         if (retval < 0)
1084                 goto error;
1085 
1086         /* Make sure, that the period size is always aligned
1087          * 64byte boundary
1088          */
1089         retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1090                         SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1091         if (retval < 0)
1092                 goto error;
1093 
1094         retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1095         if (retval < 0)
1096                 goto error;
1097 
1098         /* expose PCM substream */
1099         spin_lock_irq(&intelhaddata->had_spinlock);
1100         intelhaddata->stream_info.substream = substream;
1101         intelhaddata->stream_info.substream_refcount++;
1102         spin_unlock_irq(&intelhaddata->had_spinlock);
1103 
1104         return retval;
1105  error:
1106         pm_runtime_mark_last_busy(intelhaddata->dev);
1107         pm_runtime_put_autosuspend(intelhaddata->dev);
1108         return retval;
1109 }
1110 
1111 /*
1112  * ALSA PCM close callback
1113  */
1114 static int had_pcm_close(struct snd_pcm_substream *substream)
1115 {
1116         struct snd_intelhad *intelhaddata;
1117 
1118         intelhaddata = snd_pcm_substream_chip(substream);
1119 
1120         /* unreference and sync with the pending PCM accesses */
1121         spin_lock_irq(&intelhaddata->had_spinlock);
1122         intelhaddata->stream_info.substream = NULL;
1123         intelhaddata->stream_info.substream_refcount--;
1124         while (intelhaddata->stream_info.substream_refcount > 0) {
1125                 spin_unlock_irq(&intelhaddata->had_spinlock);
1126                 cpu_relax();
1127                 spin_lock_irq(&intelhaddata->had_spinlock);
1128         }
1129         spin_unlock_irq(&intelhaddata->had_spinlock);
1130 
1131         pm_runtime_mark_last_busy(intelhaddata->dev);
1132         pm_runtime_put_autosuspend(intelhaddata->dev);
1133         return 0;
1134 }
1135 
1136 /*
1137  * ALSA PCM hw_params callback
1138  */
1139 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1140                              struct snd_pcm_hw_params *hw_params)
1141 {
1142         struct snd_intelhad *intelhaddata;
1143         int buf_size, retval;
1144 
1145         intelhaddata = snd_pcm_substream_chip(substream);
1146         buf_size = params_buffer_bytes(hw_params);
1147         retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1148         if (retval < 0)
1149                 return retval;
1150         dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1151                 __func__, buf_size);
1152         return retval;
1153 }
1154 
1155 /*
1156  * ALSA PCM hw_free callback
1157  */
1158 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1159 {
1160         struct snd_intelhad *intelhaddata;
1161 
1162         intelhaddata = snd_pcm_substream_chip(substream);
1163         had_do_reset(intelhaddata);
1164 
1165         return snd_pcm_lib_free_pages(substream);
1166 }
1167 
1168 /*
1169  * ALSA PCM trigger callback
1170  */
1171 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1172 {
1173         int retval = 0;
1174         struct snd_intelhad *intelhaddata;
1175 
1176         intelhaddata = snd_pcm_substream_chip(substream);
1177 
1178         spin_lock(&intelhaddata->had_spinlock);
1179         switch (cmd) {
1180         case SNDRV_PCM_TRIGGER_START:
1181         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1182         case SNDRV_PCM_TRIGGER_RESUME:
1183                 /* Enable Audio */
1184                 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1185                 had_enable_audio(intelhaddata, true);
1186                 break;
1187 
1188         case SNDRV_PCM_TRIGGER_STOP:
1189         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1190                 /* Disable Audio */
1191                 had_enable_audio(intelhaddata, false);
1192                 intelhaddata->need_reset = true;
1193                 break;
1194 
1195         default:
1196                 retval = -EINVAL;
1197         }
1198         spin_unlock(&intelhaddata->had_spinlock);
1199         return retval;
1200 }
1201 
1202 /*
1203  * ALSA PCM prepare callback
1204  */
1205 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1206 {
1207         int retval;
1208         u32 disp_samp_freq, n_param;
1209         u32 link_rate = 0;
1210         struct snd_intelhad *intelhaddata;
1211         struct snd_pcm_runtime *runtime;
1212 
1213         intelhaddata = snd_pcm_substream_chip(substream);
1214         runtime = substream->runtime;
1215 
1216         dev_dbg(intelhaddata->dev, "period_size=%d\n",
1217                 (int)frames_to_bytes(runtime, runtime->period_size));
1218         dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1219         dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1220                 (int)snd_pcm_lib_buffer_bytes(substream));
1221         dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1222         dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1223 
1224         had_do_reset(intelhaddata);
1225 
1226         /* Get N value in KHz */
1227         disp_samp_freq = intelhaddata->tmds_clock_speed;
1228 
1229         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1230         if (retval) {
1231                 dev_err(intelhaddata->dev,
1232                         "programming N value failed %#x\n", retval);
1233                 goto prep_end;
1234         }
1235 
1236         if (intelhaddata->dp_output)
1237                 link_rate = intelhaddata->link_rate;
1238 
1239         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1240                      n_param, intelhaddata);
1241 
1242         had_prog_dip(substream, intelhaddata);
1243 
1244         retval = had_init_audio_ctrl(substream, intelhaddata);
1245 
1246         /* Prog buffer address */
1247         had_init_ringbuf(substream, intelhaddata);
1248 
1249         /*
1250          * Program channel mapping in following order:
1251          * FL, FR, C, LFE, RL, RR
1252          */
1253 
1254         had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1255 
1256 prep_end:
1257         return retval;
1258 }
1259 
1260 /*
1261  * ALSA PCM pointer callback
1262  */
1263 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1264 {
1265         struct snd_intelhad *intelhaddata;
1266         int len;
1267 
1268         intelhaddata = snd_pcm_substream_chip(substream);
1269 
1270         if (!intelhaddata->connected)
1271                 return SNDRV_PCM_POS_XRUN;
1272 
1273         len = had_process_ringbuf(substream, intelhaddata);
1274         if (len < 0)
1275                 return SNDRV_PCM_POS_XRUN;
1276         len = bytes_to_frames(substream->runtime, len);
1277         /* wrapping may happen when periods=1 */
1278         len %= substream->runtime->buffer_size;
1279         return len;
1280 }
1281 
1282 /*
1283  * ALSA PCM mmap callback
1284  */
1285 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1286                         struct vm_area_struct *vma)
1287 {
1288         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1289         return remap_pfn_range(vma, vma->vm_start,
1290                         substream->dma_buffer.addr >> PAGE_SHIFT,
1291                         vma->vm_end - vma->vm_start, vma->vm_page_prot);
1292 }
1293 
1294 /*
1295  * ALSA PCM ops
1296  */
1297 static const struct snd_pcm_ops had_pcm_ops = {
1298         .open =         had_pcm_open,
1299         .close =        had_pcm_close,
1300         .ioctl =        snd_pcm_lib_ioctl,
1301         .hw_params =    had_pcm_hw_params,
1302         .hw_free =      had_pcm_hw_free,
1303         .prepare =      had_pcm_prepare,
1304         .trigger =      had_pcm_trigger,
1305         .pointer =      had_pcm_pointer,
1306         .mmap =         had_pcm_mmap,
1307 };
1308 
1309 /* process mode change of the running stream; called in mutex */
1310 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1311 {
1312         struct snd_pcm_substream *substream;
1313         int retval = 0;
1314         u32 disp_samp_freq, n_param;
1315         u32 link_rate = 0;
1316 
1317         substream = had_substream_get(intelhaddata);
1318         if (!substream)
1319                 return 0;
1320 
1321         /* Disable Audio */
1322         had_enable_audio(intelhaddata, false);
1323 
1324         /* Update CTS value */
1325         disp_samp_freq = intelhaddata->tmds_clock_speed;
1326 
1327         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1328         if (retval) {
1329                 dev_err(intelhaddata->dev,
1330                         "programming N value failed %#x\n", retval);
1331                 goto out;
1332         }
1333 
1334         if (intelhaddata->dp_output)
1335                 link_rate = intelhaddata->link_rate;
1336 
1337         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1338                      n_param, intelhaddata);
1339 
1340         /* Enable Audio */
1341         had_enable_audio(intelhaddata, true);
1342 
1343 out:
1344         had_substream_put(intelhaddata);
1345         return retval;
1346 }
1347 
1348 /* process hot plug, called from wq with mutex locked */
1349 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1350 {
1351         struct snd_pcm_substream *substream;
1352 
1353         spin_lock_irq(&intelhaddata->had_spinlock);
1354         if (intelhaddata->connected) {
1355                 dev_dbg(intelhaddata->dev, "Device already connected\n");
1356                 spin_unlock_irq(&intelhaddata->had_spinlock);
1357                 return;
1358         }
1359 
1360         /* Disable Audio */
1361         had_enable_audio(intelhaddata, false);
1362 
1363         intelhaddata->connected = true;
1364         dev_dbg(intelhaddata->dev,
1365                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1366                         __func__, __LINE__);
1367         spin_unlock_irq(&intelhaddata->had_spinlock);
1368 
1369         had_build_channel_allocation_map(intelhaddata);
1370 
1371         /* Report to above ALSA layer */
1372         substream = had_substream_get(intelhaddata);
1373         if (substream) {
1374                 snd_pcm_stop_xrun(substream);
1375                 had_substream_put(intelhaddata);
1376         }
1377 
1378         snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1379 }
1380 
1381 /* process hot unplug, called from wq with mutex locked */
1382 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1383 {
1384         struct snd_pcm_substream *substream;
1385 
1386         spin_lock_irq(&intelhaddata->had_spinlock);
1387         if (!intelhaddata->connected) {
1388                 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1389                 spin_unlock_irq(&intelhaddata->had_spinlock);
1390                 return;
1391 
1392         }
1393 
1394         /* Disable Audio */
1395         had_enable_audio(intelhaddata, false);
1396 
1397         intelhaddata->connected = false;
1398         dev_dbg(intelhaddata->dev,
1399                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1400                         __func__, __LINE__);
1401         spin_unlock_irq(&intelhaddata->had_spinlock);
1402 
1403         kfree(intelhaddata->chmap->chmap);
1404         intelhaddata->chmap->chmap = NULL;
1405 
1406         /* Report to above ALSA layer */
1407         substream = had_substream_get(intelhaddata);
1408         if (substream) {
1409                 snd_pcm_stop_xrun(substream);
1410                 had_substream_put(intelhaddata);
1411         }
1412 
1413         snd_jack_report(intelhaddata->jack, 0);
1414 }
1415 
1416 /*
1417  * ALSA iec958 and ELD controls
1418  */
1419 
1420 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1421                                 struct snd_ctl_elem_info *uinfo)
1422 {
1423         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1424         uinfo->count = 1;
1425         return 0;
1426 }
1427 
1428 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1429                                 struct snd_ctl_elem_value *ucontrol)
1430 {
1431         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1432 
1433         mutex_lock(&intelhaddata->mutex);
1434         ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1435         ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1436         ucontrol->value.iec958.status[2] =
1437                                         (intelhaddata->aes_bits >> 16) & 0xff;
1438         ucontrol->value.iec958.status[3] =
1439                                         (intelhaddata->aes_bits >> 24) & 0xff;
1440         mutex_unlock(&intelhaddata->mutex);
1441         return 0;
1442 }
1443 
1444 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1445                                 struct snd_ctl_elem_value *ucontrol)
1446 {
1447         ucontrol->value.iec958.status[0] = 0xff;
1448         ucontrol->value.iec958.status[1] = 0xff;
1449         ucontrol->value.iec958.status[2] = 0xff;
1450         ucontrol->value.iec958.status[3] = 0xff;
1451         return 0;
1452 }
1453 
1454 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1455                                 struct snd_ctl_elem_value *ucontrol)
1456 {
1457         unsigned int val;
1458         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1459         int changed = 0;
1460 
1461         val = (ucontrol->value.iec958.status[0] << 0) |
1462                 (ucontrol->value.iec958.status[1] << 8) |
1463                 (ucontrol->value.iec958.status[2] << 16) |
1464                 (ucontrol->value.iec958.status[3] << 24);
1465         mutex_lock(&intelhaddata->mutex);
1466         if (intelhaddata->aes_bits != val) {
1467                 intelhaddata->aes_bits = val;
1468                 changed = 1;
1469         }
1470         mutex_unlock(&intelhaddata->mutex);
1471         return changed;
1472 }
1473 
1474 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1475                             struct snd_ctl_elem_info *uinfo)
1476 {
1477         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1478         uinfo->count = HDMI_MAX_ELD_BYTES;
1479         return 0;
1480 }
1481 
1482 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1483                            struct snd_ctl_elem_value *ucontrol)
1484 {
1485         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1486 
1487         mutex_lock(&intelhaddata->mutex);
1488         memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1489                HDMI_MAX_ELD_BYTES);
1490         mutex_unlock(&intelhaddata->mutex);
1491         return 0;
1492 }
1493 
1494 static const struct snd_kcontrol_new had_controls[] = {
1495         {
1496                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1497                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1498                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1499                 .info = had_iec958_info, /* shared */
1500                 .get = had_iec958_mask_get,
1501         },
1502         {
1503                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1504                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1505                 .info = had_iec958_info,
1506                 .get = had_iec958_get,
1507                 .put = had_iec958_put,
1508         },
1509         {
1510                 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1511                            SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1512                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1513                 .name = "ELD",
1514                 .info = had_ctl_eld_info,
1515                 .get = had_ctl_eld_get,
1516         },
1517 };
1518 
1519 /*
1520  * audio interrupt handler
1521  */
1522 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1523 {
1524         struct snd_intelhad_card *card_ctx = dev_id;
1525         u32 audio_stat[3] = {};
1526         int pipe, port;
1527 
1528         for_each_pipe(card_ctx, pipe) {
1529                 /* use raw register access to ack IRQs even while disconnected */
1530                 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1531                                                          AUD_HDMI_STATUS) &
1532                         (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1533 
1534                 if (audio_stat[pipe])
1535                         had_write_register_raw(card_ctx, pipe,
1536                                                AUD_HDMI_STATUS, audio_stat[pipe]);
1537         }
1538 
1539         for_each_port(card_ctx, port) {
1540                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1541                 int pipe = ctx->pipe;
1542 
1543                 if (pipe < 0)
1544                         continue;
1545 
1546                 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1547                         had_process_buffer_done(ctx);
1548                 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1549                         had_process_buffer_underrun(ctx);
1550         }
1551 
1552         return IRQ_HANDLED;
1553 }
1554 
1555 /*
1556  * monitor plug/unplug notification from i915; just kick off the work
1557  */
1558 static void notify_audio_lpe(struct platform_device *pdev, int port)
1559 {
1560         struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1561         struct snd_intelhad *ctx;
1562 
1563         ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1564         if (single_port)
1565                 ctx->port = port;
1566 
1567         schedule_work(&ctx->hdmi_audio_wq);
1568 }
1569 
1570 /* the work to handle monitor hot plug/unplug */
1571 static void had_audio_wq(struct work_struct *work)
1572 {
1573         struct snd_intelhad *ctx =
1574                 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1575         struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1576         struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1577 
1578         pm_runtime_get_sync(ctx->dev);
1579         mutex_lock(&ctx->mutex);
1580         if (ppdata->pipe < 0) {
1581                 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1582                         __func__, ctx->port);
1583 
1584                 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1585 
1586                 ctx->dp_output = false;
1587                 ctx->tmds_clock_speed = 0;
1588                 ctx->link_rate = 0;
1589 
1590                 /* Shut down the stream */
1591                 had_process_hot_unplug(ctx);
1592 
1593                 ctx->pipe = -1;
1594         } else {
1595                 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1596                         __func__, ctx->port, ppdata->ls_clock);
1597 
1598                 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1599 
1600                 ctx->dp_output = ppdata->dp_output;
1601                 if (ctx->dp_output) {
1602                         ctx->tmds_clock_speed = 0;
1603                         ctx->link_rate = ppdata->ls_clock;
1604                 } else {
1605                         ctx->tmds_clock_speed = ppdata->ls_clock;
1606                         ctx->link_rate = 0;
1607                 }
1608 
1609                 /*
1610                  * Shut down the stream before we change
1611                  * the pipe assignment for this pcm device
1612                  */
1613                 had_process_hot_plug(ctx);
1614 
1615                 ctx->pipe = ppdata->pipe;
1616 
1617                 /* Restart the stream if necessary */
1618                 had_process_mode_change(ctx);
1619         }
1620 
1621         mutex_unlock(&ctx->mutex);
1622         pm_runtime_mark_last_busy(ctx->dev);
1623         pm_runtime_put_autosuspend(ctx->dev);
1624 }
1625 
1626 /*
1627  * Jack interface
1628  */
1629 static int had_create_jack(struct snd_intelhad *ctx,
1630                            struct snd_pcm *pcm)
1631 {
1632         char hdmi_str[32];
1633         int err;
1634 
1635         snprintf(hdmi_str, sizeof(hdmi_str),
1636                  "HDMI/DP,pcm=%d", pcm->device);
1637 
1638         err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1639                            SND_JACK_AVOUT, &ctx->jack,
1640                            true, false);
1641         if (err < 0)
1642                 return err;
1643         ctx->jack->private_data = ctx;
1644         return 0;
1645 }
1646 
1647 /*
1648  * PM callbacks
1649  */
1650 
1651 static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1652 {
1653         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1654         int port;
1655 
1656         for_each_port(card_ctx, port) {
1657                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1658                 struct snd_pcm_substream *substream;
1659 
1660                 substream = had_substream_get(ctx);
1661                 if (substream) {
1662                         snd_pcm_suspend(substream);
1663                         had_substream_put(ctx);
1664                 }
1665         }
1666 
1667         return 0;
1668 }
1669 
1670 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1671 {
1672         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1673         int err;
1674 
1675         err = hdmi_lpe_audio_runtime_suspend(dev);
1676         if (!err)
1677                 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1678         return err;
1679 }
1680 
1681 static int hdmi_lpe_audio_runtime_resume(struct device *dev)
1682 {
1683         pm_runtime_mark_last_busy(dev);
1684         return 0;
1685 }
1686 
1687 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1688 {
1689         struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1690 
1691         hdmi_lpe_audio_runtime_resume(dev);
1692         snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1693         return 0;
1694 }
1695 
1696 /* release resources */
1697 static void hdmi_lpe_audio_free(struct snd_card *card)
1698 {
1699         struct snd_intelhad_card *card_ctx = card->private_data;
1700         struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1701         int port;
1702 
1703         spin_lock_irq(&pdata->lpe_audio_slock);
1704         pdata->notify_audio_lpe = NULL;
1705         spin_unlock_irq(&pdata->lpe_audio_slock);
1706 
1707         for_each_port(card_ctx, port) {
1708                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1709 
1710                 cancel_work_sync(&ctx->hdmi_audio_wq);
1711         }
1712 
1713         if (card_ctx->mmio_start)
1714                 iounmap(card_ctx->mmio_start);
1715         if (card_ctx->irq >= 0)
1716                 free_irq(card_ctx->irq, card_ctx);
1717 }
1718 
1719 /*
1720  * hdmi_lpe_audio_probe - start bridge with i915
1721  *
1722  * This function is called when the i915 driver creates the
1723  * hdmi-lpe-audio platform device.
1724  */
1725 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1726 {
1727         struct snd_card *card;
1728         struct snd_intelhad_card *card_ctx;
1729         struct snd_intelhad *ctx;
1730         struct snd_pcm *pcm;
1731         struct intel_hdmi_lpe_audio_pdata *pdata;
1732         int irq;
1733         struct resource *res_mmio;
1734         int port, ret;
1735 
1736         pdata = pdev->dev.platform_data;
1737         if (!pdata) {
1738                 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1739                 return -EINVAL;
1740         }
1741 
1742         /* get resources */
1743         irq = platform_get_irq(pdev, 0);
1744         if (irq < 0) {
1745                 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq);
1746                 return irq;
1747         }
1748 
1749         res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1750         if (!res_mmio) {
1751                 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1752                 return -ENXIO;
1753         }
1754 
1755         /* create a card instance with ALSA framework */
1756         ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1757                            THIS_MODULE, sizeof(*card_ctx), &card);
1758         if (ret)
1759                 return ret;
1760 
1761         card_ctx = card->private_data;
1762         card_ctx->dev = &pdev->dev;
1763         card_ctx->card = card;
1764         strcpy(card->driver, INTEL_HAD);
1765         strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1766         strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1767 
1768         card_ctx->irq = -1;
1769 
1770         card->private_free = hdmi_lpe_audio_free;
1771 
1772         platform_set_drvdata(pdev, card_ctx);
1773 
1774         card_ctx->num_pipes = pdata->num_pipes;
1775         card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1776 
1777         for_each_port(card_ctx, port) {
1778                 ctx = &card_ctx->pcm_ctx[port];
1779                 ctx->card_ctx = card_ctx;
1780                 ctx->dev = card_ctx->dev;
1781                 ctx->port = single_port ? -1 : port;
1782                 ctx->pipe = -1;
1783 
1784                 spin_lock_init(&ctx->had_spinlock);
1785                 mutex_init(&ctx->mutex);
1786                 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1787         }
1788 
1789         dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1790                 __func__, (unsigned int)res_mmio->start,
1791                 (unsigned int)res_mmio->end);
1792 
1793         card_ctx->mmio_start = ioremap_nocache(res_mmio->start,
1794                                                (size_t)(resource_size(res_mmio)));
1795         if (!card_ctx->mmio_start) {
1796                 dev_err(&pdev->dev, "Could not get ioremap\n");
1797                 ret = -EACCES;
1798                 goto err;
1799         }
1800 
1801         /* setup interrupt handler */
1802         ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1803                           pdev->name, card_ctx);
1804         if (ret < 0) {
1805                 dev_err(&pdev->dev, "request_irq failed\n");
1806                 goto err;
1807         }
1808 
1809         card_ctx->irq = irq;
1810 
1811         /* only 32bit addressable */
1812         dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1813         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1814 
1815         init_channel_allocations();
1816 
1817         card_ctx->num_pipes = pdata->num_pipes;
1818         card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1819 
1820         for_each_port(card_ctx, port) {
1821                 int i;
1822 
1823                 ctx = &card_ctx->pcm_ctx[port];
1824                 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1825                                   MAX_CAP_STREAMS, &pcm);
1826                 if (ret)
1827                         goto err;
1828 
1829                 /* setup private data which can be retrieved when required */
1830                 pcm->private_data = ctx;
1831                 pcm->info_flags = 0;
1832                 strlcpy(pcm->name, card->shortname, strlen(card->shortname));
1833                 /* setup the ops for playabck */
1834                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1835 
1836                 /* allocate dma pages;
1837                  * try to allocate 600k buffer as default which is large enough
1838                  */
1839                 snd_pcm_lib_preallocate_pages_for_all(pcm,
1840                                                       SNDRV_DMA_TYPE_DEV_UC, NULL,
1841                                                       HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1842 
1843                 /* create controls */
1844                 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1845                         struct snd_kcontrol *kctl;
1846 
1847                         kctl = snd_ctl_new1(&had_controls[i], ctx);
1848                         if (!kctl) {
1849                                 ret = -ENOMEM;
1850                                 goto err;
1851                         }
1852 
1853                         kctl->id.device = pcm->device;
1854 
1855                         ret = snd_ctl_add(card, kctl);
1856                         if (ret < 0)
1857                                 goto err;
1858                 }
1859 
1860                 /* Register channel map controls */
1861                 ret = had_register_chmap_ctls(ctx, pcm);
1862                 if (ret < 0)
1863                         goto err;
1864 
1865                 ret = had_create_jack(ctx, pcm);
1866                 if (ret < 0)
1867                         goto err;
1868         }
1869 
1870         ret = snd_card_register(card);
1871         if (ret)
1872                 goto err;
1873 
1874         spin_lock_irq(&pdata->lpe_audio_slock);
1875         pdata->notify_audio_lpe = notify_audio_lpe;
1876         spin_unlock_irq(&pdata->lpe_audio_slock);
1877 
1878         pm_runtime_use_autosuspend(&pdev->dev);
1879         pm_runtime_mark_last_busy(&pdev->dev);
1880         pm_runtime_set_active(&pdev->dev);
1881 
1882         dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1883         for_each_port(card_ctx, port) {
1884                 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1885 
1886                 schedule_work(&ctx->hdmi_audio_wq);
1887         }
1888 
1889         return 0;
1890 
1891 err:
1892         snd_card_free(card);
1893         return ret;
1894 }
1895 
1896 /*
1897  * hdmi_lpe_audio_remove - stop bridge with i915
1898  *
1899  * This function is called when the platform device is destroyed.
1900  */
1901 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1902 {
1903         struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1904 
1905         snd_card_free(card_ctx->card);
1906         return 0;
1907 }
1908 
1909 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1910         SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1911         SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend,
1912                            hdmi_lpe_audio_runtime_resume, NULL)
1913 };
1914 
1915 static struct platform_driver hdmi_lpe_audio_driver = {
1916         .driver         = {
1917                 .name  = "hdmi-lpe-audio",
1918                 .pm = &hdmi_lpe_audio_pm,
1919         },
1920         .probe          = hdmi_lpe_audio_probe,
1921         .remove         = hdmi_lpe_audio_remove,
1922 };
1923 
1924 module_platform_driver(hdmi_lpe_audio_driver);
1925 MODULE_ALIAS("platform:hdmi_lpe_audio");
1926 
1927 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1928 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1929 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1930 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1931 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1932 MODULE_LICENSE("GPL v2");
1933 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
1934 

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