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TOMOYO Linux Cross Reference
Linux/tools/include/uapi/drm/i915_drm.h

Version: ~ [ linux-4.18 ] ~ [ linux-4.17.14 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.62 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.119 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.147 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.118 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.57 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.27.62 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~ [ linux-next-20180810 ] ~ [ linux-next-20180813 ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  3  * All Rights Reserved.
  4  *
  5  * Permission is hereby granted, free of charge, to any person obtaining a
  6  * copy of this software and associated documentation files (the
  7  * "Software"), to deal in the Software without restriction, including
  8  * without limitation the rights to use, copy, modify, merge, publish,
  9  * distribute, sub license, and/or sell copies of the Software, and to
 10  * permit persons to whom the Software is furnished to do so, subject to
 11  * the following conditions:
 12  *
 13  * The above copyright notice and this permission notice (including the
 14  * next paragraph) shall be included in all copies or substantial portions
 15  * of the Software.
 16  *
 17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 24  *
 25  */
 26 
 27 #ifndef _UAPI_I915_DRM_H_
 28 #define _UAPI_I915_DRM_H_
 29 
 30 #include "drm.h"
 31 
 32 #if defined(__cplusplus)
 33 extern "C" {
 34 #endif
 35 
 36 /* Please note that modifications to all structs defined here are
 37  * subject to backwards-compatibility constraints.
 38  */
 39 
 40 /**
 41  * DOC: uevents generated by i915 on it's device node
 42  *
 43  * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
 44  *      event from the gpu l3 cache. Additional information supplied is ROW,
 45  *      BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
 46  *      track of these events and if a specific cache-line seems to have a
 47  *      persistent error remap it with the l3 remapping tool supplied in
 48  *      intel-gpu-tools.  The value supplied with the event is always 1.
 49  *
 50  * I915_ERROR_UEVENT - Generated upon error detection, currently only via
 51  *      hangcheck. The error detection event is a good indicator of when things
 52  *      began to go badly. The value supplied with the event is a 1 upon error
 53  *      detection, and a 0 upon reset completion, signifying no more error
 54  *      exists. NOTE: Disabling hangcheck or reset via module parameter will
 55  *      cause the related events to not be seen.
 56  *
 57  * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
 58  *      the GPU. The value supplied with the event is always 1. NOTE: Disable
 59  *      reset via module parameter will cause this event to not be seen.
 60  */
 61 #define I915_L3_PARITY_UEVENT           "L3_PARITY_ERROR"
 62 #define I915_ERROR_UEVENT               "ERROR"
 63 #define I915_RESET_UEVENT               "RESET"
 64 
 65 /*
 66  * MOCS indexes used for GPU surfaces, defining the cacheability of the
 67  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
 68  */
 69 enum i915_mocs_table_index {
 70         /*
 71          * Not cached anywhere, coherency between CPU and GPU accesses is
 72          * guaranteed.
 73          */
 74         I915_MOCS_UNCACHED,
 75         /*
 76          * Cacheability and coherency controlled by the kernel automatically
 77          * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
 78          * usage of the surface (used for display scanout or not).
 79          */
 80         I915_MOCS_PTE,
 81         /*
 82          * Cached in all GPU caches available on the platform.
 83          * Coherency between CPU and GPU accesses to the surface is not
 84          * guaranteed without extra synchronization.
 85          */
 86         I915_MOCS_CACHED,
 87 };
 88 
 89 /*
 90  * Different engines serve different roles, and there may be more than one
 91  * engine serving each role. enum drm_i915_gem_engine_class provides a
 92  * classification of the role of the engine, which may be used when requesting
 93  * operations to be performed on a certain subset of engines, or for providing
 94  * information about that group.
 95  */
 96 enum drm_i915_gem_engine_class {
 97         I915_ENGINE_CLASS_RENDER        = 0,
 98         I915_ENGINE_CLASS_COPY          = 1,
 99         I915_ENGINE_CLASS_VIDEO         = 2,
100         I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
101 
102         I915_ENGINE_CLASS_INVALID       = -1
103 };
104 
105 /**
106  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
107  *
108  */
109 
110 enum drm_i915_pmu_engine_sample {
111         I915_SAMPLE_BUSY = 0,
112         I915_SAMPLE_WAIT = 1,
113         I915_SAMPLE_SEMA = 2
114 };
115 
116 #define I915_PMU_SAMPLE_BITS (4)
117 #define I915_PMU_SAMPLE_MASK (0xf)
118 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
119 #define I915_PMU_CLASS_SHIFT \
120         (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
121 
122 #define __I915_PMU_ENGINE(class, instance, sample) \
123         ((class) << I915_PMU_CLASS_SHIFT | \
124         (instance) << I915_PMU_SAMPLE_BITS | \
125         (sample))
126 
127 #define I915_PMU_ENGINE_BUSY(class, instance) \
128         __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
129 
130 #define I915_PMU_ENGINE_WAIT(class, instance) \
131         __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
132 
133 #define I915_PMU_ENGINE_SEMA(class, instance) \
134         __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
135 
136 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
137 
138 #define I915_PMU_ACTUAL_FREQUENCY       __I915_PMU_OTHER(0)
139 #define I915_PMU_REQUESTED_FREQUENCY    __I915_PMU_OTHER(1)
140 #define I915_PMU_INTERRUPTS             __I915_PMU_OTHER(2)
141 #define I915_PMU_RC6_RESIDENCY          __I915_PMU_OTHER(3)
142 
143 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
144 
145 /* Each region is a minimum of 16k, and there are at most 255 of them.
146  */
147 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
148                                  * of chars for next/prev indices */
149 #define I915_LOG_MIN_TEX_REGION_SIZE 14
150 
151 typedef struct _drm_i915_init {
152         enum {
153                 I915_INIT_DMA = 0x01,
154                 I915_CLEANUP_DMA = 0x02,
155                 I915_RESUME_DMA = 0x03
156         } func;
157         unsigned int mmio_offset;
158         int sarea_priv_offset;
159         unsigned int ring_start;
160         unsigned int ring_end;
161         unsigned int ring_size;
162         unsigned int front_offset;
163         unsigned int back_offset;
164         unsigned int depth_offset;
165         unsigned int w;
166         unsigned int h;
167         unsigned int pitch;
168         unsigned int pitch_bits;
169         unsigned int back_pitch;
170         unsigned int depth_pitch;
171         unsigned int cpp;
172         unsigned int chipset;
173 } drm_i915_init_t;
174 
175 typedef struct _drm_i915_sarea {
176         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
177         int last_upload;        /* last time texture was uploaded */
178         int last_enqueue;       /* last time a buffer was enqueued */
179         int last_dispatch;      /* age of the most recently dispatched buffer */
180         int ctxOwner;           /* last context to upload state */
181         int texAge;
182         int pf_enabled;         /* is pageflipping allowed? */
183         int pf_active;
184         int pf_current_page;    /* which buffer is being displayed? */
185         int perf_boxes;         /* performance boxes to be displayed */
186         int width, height;      /* screen size in pixels */
187 
188         drm_handle_t front_handle;
189         int front_offset;
190         int front_size;
191 
192         drm_handle_t back_handle;
193         int back_offset;
194         int back_size;
195 
196         drm_handle_t depth_handle;
197         int depth_offset;
198         int depth_size;
199 
200         drm_handle_t tex_handle;
201         int tex_offset;
202         int tex_size;
203         int log_tex_granularity;
204         int pitch;
205         int rotation;           /* 0, 90, 180 or 270 */
206         int rotated_offset;
207         int rotated_size;
208         int rotated_pitch;
209         int virtualX, virtualY;
210 
211         unsigned int front_tiled;
212         unsigned int back_tiled;
213         unsigned int depth_tiled;
214         unsigned int rotated_tiled;
215         unsigned int rotated2_tiled;
216 
217         int pipeA_x;
218         int pipeA_y;
219         int pipeA_w;
220         int pipeA_h;
221         int pipeB_x;
222         int pipeB_y;
223         int pipeB_w;
224         int pipeB_h;
225 
226         /* fill out some space for old userspace triple buffer */
227         drm_handle_t unused_handle;
228         __u32 unused1, unused2, unused3;
229 
230         /* buffer object handles for static buffers. May change
231          * over the lifetime of the client.
232          */
233         __u32 front_bo_handle;
234         __u32 back_bo_handle;
235         __u32 unused_bo_handle;
236         __u32 depth_bo_handle;
237 
238 } drm_i915_sarea_t;
239 
240 /* due to userspace building against these headers we need some compat here */
241 #define planeA_x pipeA_x
242 #define planeA_y pipeA_y
243 #define planeA_w pipeA_w
244 #define planeA_h pipeA_h
245 #define planeB_x pipeB_x
246 #define planeB_y pipeB_y
247 #define planeB_w pipeB_w
248 #define planeB_h pipeB_h
249 
250 /* Flags for perf_boxes
251  */
252 #define I915_BOX_RING_EMPTY    0x1
253 #define I915_BOX_FLIP          0x2
254 #define I915_BOX_WAIT          0x4
255 #define I915_BOX_TEXTURE_LOAD  0x8
256 #define I915_BOX_LOST_CONTEXT  0x10
257 
258 /*
259  * i915 specific ioctls.
260  *
261  * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
262  * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
263  * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
264  */
265 #define DRM_I915_INIT           0x00
266 #define DRM_I915_FLUSH          0x01
267 #define DRM_I915_FLIP           0x02
268 #define DRM_I915_BATCHBUFFER    0x03
269 #define DRM_I915_IRQ_EMIT       0x04
270 #define DRM_I915_IRQ_WAIT       0x05
271 #define DRM_I915_GETPARAM       0x06
272 #define DRM_I915_SETPARAM       0x07
273 #define DRM_I915_ALLOC          0x08
274 #define DRM_I915_FREE           0x09
275 #define DRM_I915_INIT_HEAP      0x0a
276 #define DRM_I915_CMDBUFFER      0x0b
277 #define DRM_I915_DESTROY_HEAP   0x0c
278 #define DRM_I915_SET_VBLANK_PIPE        0x0d
279 #define DRM_I915_GET_VBLANK_PIPE        0x0e
280 #define DRM_I915_VBLANK_SWAP    0x0f
281 #define DRM_I915_HWS_ADDR       0x11
282 #define DRM_I915_GEM_INIT       0x13
283 #define DRM_I915_GEM_EXECBUFFER 0x14
284 #define DRM_I915_GEM_PIN        0x15
285 #define DRM_I915_GEM_UNPIN      0x16
286 #define DRM_I915_GEM_BUSY       0x17
287 #define DRM_I915_GEM_THROTTLE   0x18
288 #define DRM_I915_GEM_ENTERVT    0x19
289 #define DRM_I915_GEM_LEAVEVT    0x1a
290 #define DRM_I915_GEM_CREATE     0x1b
291 #define DRM_I915_GEM_PREAD      0x1c
292 #define DRM_I915_GEM_PWRITE     0x1d
293 #define DRM_I915_GEM_MMAP       0x1e
294 #define DRM_I915_GEM_SET_DOMAIN 0x1f
295 #define DRM_I915_GEM_SW_FINISH  0x20
296 #define DRM_I915_GEM_SET_TILING 0x21
297 #define DRM_I915_GEM_GET_TILING 0x22
298 #define DRM_I915_GEM_GET_APERTURE 0x23
299 #define DRM_I915_GEM_MMAP_GTT   0x24
300 #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
301 #define DRM_I915_GEM_MADVISE    0x26
302 #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
303 #define DRM_I915_OVERLAY_ATTRS  0x28
304 #define DRM_I915_GEM_EXECBUFFER2        0x29
305 #define DRM_I915_GEM_EXECBUFFER2_WR     DRM_I915_GEM_EXECBUFFER2
306 #define DRM_I915_GET_SPRITE_COLORKEY    0x2a
307 #define DRM_I915_SET_SPRITE_COLORKEY    0x2b
308 #define DRM_I915_GEM_WAIT       0x2c
309 #define DRM_I915_GEM_CONTEXT_CREATE     0x2d
310 #define DRM_I915_GEM_CONTEXT_DESTROY    0x2e
311 #define DRM_I915_GEM_SET_CACHING        0x2f
312 #define DRM_I915_GEM_GET_CACHING        0x30
313 #define DRM_I915_REG_READ               0x31
314 #define DRM_I915_GET_RESET_STATS        0x32
315 #define DRM_I915_GEM_USERPTR            0x33
316 #define DRM_I915_GEM_CONTEXT_GETPARAM   0x34
317 #define DRM_I915_GEM_CONTEXT_SETPARAM   0x35
318 #define DRM_I915_PERF_OPEN              0x36
319 #define DRM_I915_PERF_ADD_CONFIG        0x37
320 #define DRM_I915_PERF_REMOVE_CONFIG     0x38
321 #define DRM_I915_QUERY                  0x39
322 
323 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
324 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
325 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
326 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
327 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
328 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
329 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
330 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
331 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
332 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
333 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
334 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
335 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
336 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
337 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
338 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
339 #define DRM_IOCTL_I915_HWS_ADDR         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
340 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
341 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
342 #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
343 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
344 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
345 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
346 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
347 #define DRM_IOCTL_I915_GEM_SET_CACHING          DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
348 #define DRM_IOCTL_I915_GEM_GET_CACHING          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
349 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
350 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
351 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
352 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
353 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
354 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
355 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
356 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
357 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
358 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
359 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
360 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
361 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
362 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
363 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
364 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
365 #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
366 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
367 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
368 #define DRM_IOCTL_I915_GEM_WAIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
369 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE       DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
370 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY      DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
371 #define DRM_IOCTL_I915_REG_READ                 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
372 #define DRM_IOCTL_I915_GET_RESET_STATS          DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
373 #define DRM_IOCTL_I915_GEM_USERPTR                      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
374 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
375 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
376 #define DRM_IOCTL_I915_PERF_OPEN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
377 #define DRM_IOCTL_I915_PERF_ADD_CONFIG  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
378 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG       DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
379 #define DRM_IOCTL_I915_QUERY                    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
380 
381 /* Allow drivers to submit batchbuffers directly to hardware, relying
382  * on the security mechanisms provided by hardware.
383  */
384 typedef struct drm_i915_batchbuffer {
385         int start;              /* agp offset */
386         int used;               /* nr bytes in use */
387         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
388         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
389         int num_cliprects;      /* mulitpass with multiple cliprects? */
390         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
391 } drm_i915_batchbuffer_t;
392 
393 /* As above, but pass a pointer to userspace buffer which can be
394  * validated by the kernel prior to sending to hardware.
395  */
396 typedef struct _drm_i915_cmdbuffer {
397         char __user *buf;       /* pointer to userspace command buffer */
398         int sz;                 /* nr bytes in buf */
399         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
400         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
401         int num_cliprects;      /* mulitpass with multiple cliprects? */
402         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
403 } drm_i915_cmdbuffer_t;
404 
405 /* Userspace can request & wait on irq's:
406  */
407 typedef struct drm_i915_irq_emit {
408         int __user *irq_seq;
409 } drm_i915_irq_emit_t;
410 
411 typedef struct drm_i915_irq_wait {
412         int irq_seq;
413 } drm_i915_irq_wait_t;
414 
415 /* Ioctl to query kernel params:
416  */
417 #define I915_PARAM_IRQ_ACTIVE            1
418 #define I915_PARAM_ALLOW_BATCHBUFFER     2
419 #define I915_PARAM_LAST_DISPATCH         3
420 #define I915_PARAM_CHIPSET_ID            4
421 #define I915_PARAM_HAS_GEM               5
422 #define I915_PARAM_NUM_FENCES_AVAIL      6
423 #define I915_PARAM_HAS_OVERLAY           7
424 #define I915_PARAM_HAS_PAGEFLIPPING      8
425 #define I915_PARAM_HAS_EXECBUF2          9
426 #define I915_PARAM_HAS_BSD               10
427 #define I915_PARAM_HAS_BLT               11
428 #define I915_PARAM_HAS_RELAXED_FENCING   12
429 #define I915_PARAM_HAS_COHERENT_RINGS    13
430 #define I915_PARAM_HAS_EXEC_CONSTANTS    14
431 #define I915_PARAM_HAS_RELAXED_DELTA     15
432 #define I915_PARAM_HAS_GEN7_SOL_RESET    16
433 #define I915_PARAM_HAS_LLC               17
434 #define I915_PARAM_HAS_ALIASING_PPGTT    18
435 #define I915_PARAM_HAS_WAIT_TIMEOUT      19
436 #define I915_PARAM_HAS_SEMAPHORES        20
437 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH  21
438 #define I915_PARAM_HAS_VEBOX             22
439 #define I915_PARAM_HAS_SECURE_BATCHES    23
440 #define I915_PARAM_HAS_PINNED_BATCHES    24
441 #define I915_PARAM_HAS_EXEC_NO_RELOC     25
442 #define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
443 #define I915_PARAM_HAS_WT                27
444 #define I915_PARAM_CMD_PARSER_VERSION    28
445 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
446 #define I915_PARAM_MMAP_VERSION          30
447 #define I915_PARAM_HAS_BSD2              31
448 #define I915_PARAM_REVISION              32
449 #define I915_PARAM_SUBSLICE_TOTAL        33
450 #define I915_PARAM_EU_TOTAL              34
451 #define I915_PARAM_HAS_GPU_RESET         35
452 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
453 #define I915_PARAM_HAS_EXEC_SOFTPIN      37
454 #define I915_PARAM_HAS_POOLED_EU         38
455 #define I915_PARAM_MIN_EU_IN_POOL        39
456 #define I915_PARAM_MMAP_GTT_VERSION      40
457 
458 /*
459  * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
460  * priorities and the driver will attempt to execute batches in priority order.
461  * The param returns a capability bitmask, nonzero implies that the scheduler
462  * is enabled, with different features present according to the mask.
463  *
464  * The initial priority for each batch is supplied by the context and is
465  * controlled via I915_CONTEXT_PARAM_PRIORITY.
466  */
467 #define I915_PARAM_HAS_SCHEDULER         41
468 #define   I915_SCHEDULER_CAP_ENABLED    (1ul << 0)
469 #define   I915_SCHEDULER_CAP_PRIORITY   (1ul << 1)
470 #define   I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
471 
472 #define I915_PARAM_HUC_STATUS            42
473 
474 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
475  * synchronisation with implicit fencing on individual objects.
476  * See EXEC_OBJECT_ASYNC.
477  */
478 #define I915_PARAM_HAS_EXEC_ASYNC        43
479 
480 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
481  * both being able to pass in a sync_file fd to wait upon before executing,
482  * and being able to return a new sync_file fd that is signaled when the
483  * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
484  */
485 #define I915_PARAM_HAS_EXEC_FENCE        44
486 
487 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
488  * user specified bufffers for post-mortem debugging of GPU hangs. See
489  * EXEC_OBJECT_CAPTURE.
490  */
491 #define I915_PARAM_HAS_EXEC_CAPTURE      45
492 
493 #define I915_PARAM_SLICE_MASK            46
494 
495 /* Assuming it's uniform for each slice, this queries the mask of subslices
496  * per-slice for this system.
497  */
498 #define I915_PARAM_SUBSLICE_MASK         47
499 
500 /*
501  * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
502  * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
503  */
504 #define I915_PARAM_HAS_EXEC_BATCH_FIRST  48
505 
506 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
507  * drm_i915_gem_exec_fence structures.  See I915_EXEC_FENCE_ARRAY.
508  */
509 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
510 
511 /*
512  * Query whether every context (both per-file default and user created) is
513  * isolated (insofar as HW supports). If this parameter is not true, then
514  * freshly created contexts may inherit values from an existing context,
515  * rather than default HW values. If true, it also ensures (insofar as HW
516  * supports) that all state set by this context will not leak to any other
517  * context.
518  *
519  * As not every engine across every gen support contexts, the returned
520  * value reports the support of context isolation for individual engines by
521  * returning a bitmask of each engine class set to true if that class supports
522  * isolation.
523  */
524 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
525 
526 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
527  * registers. This used to be fixed per platform but from CNL onwards, this
528  * might vary depending on the parts.
529  */
530 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
531 
532 typedef struct drm_i915_getparam {
533         __s32 param;
534         /*
535          * WARNING: Using pointers instead of fixed-size u64 means we need to write
536          * compat32 code. Don't repeat this mistake.
537          */
538         int __user *value;
539 } drm_i915_getparam_t;
540 
541 /* Ioctl to set kernel params:
542  */
543 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
544 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
545 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
546 #define I915_SETPARAM_NUM_USED_FENCES                     4
547 
548 typedef struct drm_i915_setparam {
549         int param;
550         int value;
551 } drm_i915_setparam_t;
552 
553 /* A memory manager for regions of shared memory:
554  */
555 #define I915_MEM_REGION_AGP 1
556 
557 typedef struct drm_i915_mem_alloc {
558         int region;
559         int alignment;
560         int size;
561         int __user *region_offset;      /* offset from start of fb or agp */
562 } drm_i915_mem_alloc_t;
563 
564 typedef struct drm_i915_mem_free {
565         int region;
566         int region_offset;
567 } drm_i915_mem_free_t;
568 
569 typedef struct drm_i915_mem_init_heap {
570         int region;
571         int size;
572         int start;
573 } drm_i915_mem_init_heap_t;
574 
575 /* Allow memory manager to be torn down and re-initialized (eg on
576  * rotate):
577  */
578 typedef struct drm_i915_mem_destroy_heap {
579         int region;
580 } drm_i915_mem_destroy_heap_t;
581 
582 /* Allow X server to configure which pipes to monitor for vblank signals
583  */
584 #define DRM_I915_VBLANK_PIPE_A  1
585 #define DRM_I915_VBLANK_PIPE_B  2
586 
587 typedef struct drm_i915_vblank_pipe {
588         int pipe;
589 } drm_i915_vblank_pipe_t;
590 
591 /* Schedule buffer swap at given vertical blank:
592  */
593 typedef struct drm_i915_vblank_swap {
594         drm_drawable_t drawable;
595         enum drm_vblank_seq_type seqtype;
596         unsigned int sequence;
597 } drm_i915_vblank_swap_t;
598 
599 typedef struct drm_i915_hws_addr {
600         __u64 addr;
601 } drm_i915_hws_addr_t;
602 
603 struct drm_i915_gem_init {
604         /**
605          * Beginning offset in the GTT to be managed by the DRM memory
606          * manager.
607          */
608         __u64 gtt_start;
609         /**
610          * Ending offset in the GTT to be managed by the DRM memory
611          * manager.
612          */
613         __u64 gtt_end;
614 };
615 
616 struct drm_i915_gem_create {
617         /**
618          * Requested size for the object.
619          *
620          * The (page-aligned) allocated size for the object will be returned.
621          */
622         __u64 size;
623         /**
624          * Returned handle for the object.
625          *
626          * Object handles are nonzero.
627          */
628         __u32 handle;
629         __u32 pad;
630 };
631 
632 struct drm_i915_gem_pread {
633         /** Handle for the object being read. */
634         __u32 handle;
635         __u32 pad;
636         /** Offset into the object to read from */
637         __u64 offset;
638         /** Length of data to read */
639         __u64 size;
640         /**
641          * Pointer to write the data into.
642          *
643          * This is a fixed-size type for 32/64 compatibility.
644          */
645         __u64 data_ptr;
646 };
647 
648 struct drm_i915_gem_pwrite {
649         /** Handle for the object being written to. */
650         __u32 handle;
651         __u32 pad;
652         /** Offset into the object to write to */
653         __u64 offset;
654         /** Length of data to write */
655         __u64 size;
656         /**
657          * Pointer to read the data from.
658          *
659          * This is a fixed-size type for 32/64 compatibility.
660          */
661         __u64 data_ptr;
662 };
663 
664 struct drm_i915_gem_mmap {
665         /** Handle for the object being mapped. */
666         __u32 handle;
667         __u32 pad;
668         /** Offset in the object to map. */
669         __u64 offset;
670         /**
671          * Length of data to map.
672          *
673          * The value will be page-aligned.
674          */
675         __u64 size;
676         /**
677          * Returned pointer the data was mapped at.
678          *
679          * This is a fixed-size type for 32/64 compatibility.
680          */
681         __u64 addr_ptr;
682 
683         /**
684          * Flags for extended behaviour.
685          *
686          * Added in version 2.
687          */
688         __u64 flags;
689 #define I915_MMAP_WC 0x1
690 };
691 
692 struct drm_i915_gem_mmap_gtt {
693         /** Handle for the object being mapped. */
694         __u32 handle;
695         __u32 pad;
696         /**
697          * Fake offset to use for subsequent mmap call
698          *
699          * This is a fixed-size type for 32/64 compatibility.
700          */
701         __u64 offset;
702 };
703 
704 struct drm_i915_gem_set_domain {
705         /** Handle for the object */
706         __u32 handle;
707 
708         /** New read domains */
709         __u32 read_domains;
710 
711         /** New write domain */
712         __u32 write_domain;
713 };
714 
715 struct drm_i915_gem_sw_finish {
716         /** Handle for the object */
717         __u32 handle;
718 };
719 
720 struct drm_i915_gem_relocation_entry {
721         /**
722          * Handle of the buffer being pointed to by this relocation entry.
723          *
724          * It's appealing to make this be an index into the mm_validate_entry
725          * list to refer to the buffer, but this allows the driver to create
726          * a relocation list for state buffers and not re-write it per
727          * exec using the buffer.
728          */
729         __u32 target_handle;
730 
731         /**
732          * Value to be added to the offset of the target buffer to make up
733          * the relocation entry.
734          */
735         __u32 delta;
736 
737         /** Offset in the buffer the relocation entry will be written into */
738         __u64 offset;
739 
740         /**
741          * Offset value of the target buffer that the relocation entry was last
742          * written as.
743          *
744          * If the buffer has the same offset as last time, we can skip syncing
745          * and writing the relocation.  This value is written back out by
746          * the execbuffer ioctl when the relocation is written.
747          */
748         __u64 presumed_offset;
749 
750         /**
751          * Target memory domains read by this operation.
752          */
753         __u32 read_domains;
754 
755         /**
756          * Target memory domains written by this operation.
757          *
758          * Note that only one domain may be written by the whole
759          * execbuffer operation, so that where there are conflicts,
760          * the application will get -EINVAL back.
761          */
762         __u32 write_domain;
763 };
764 
765 /** @{
766  * Intel memory domains
767  *
768  * Most of these just align with the various caches in
769  * the system and are used to flush and invalidate as
770  * objects end up cached in different domains.
771  */
772 /** CPU cache */
773 #define I915_GEM_DOMAIN_CPU             0x00000001
774 /** Render cache, used by 2D and 3D drawing */
775 #define I915_GEM_DOMAIN_RENDER          0x00000002
776 /** Sampler cache, used by texture engine */
777 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
778 /** Command queue, used to load batch buffers */
779 #define I915_GEM_DOMAIN_COMMAND         0x00000008
780 /** Instruction cache, used by shader programs */
781 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
782 /** Vertex address cache */
783 #define I915_GEM_DOMAIN_VERTEX          0x00000020
784 /** GTT domain - aperture and scanout */
785 #define I915_GEM_DOMAIN_GTT             0x00000040
786 /** WC domain - uncached access */
787 #define I915_GEM_DOMAIN_WC              0x00000080
788 /** @} */
789 
790 struct drm_i915_gem_exec_object {
791         /**
792          * User's handle for a buffer to be bound into the GTT for this
793          * operation.
794          */
795         __u32 handle;
796 
797         /** Number of relocations to be performed on this buffer */
798         __u32 relocation_count;
799         /**
800          * Pointer to array of struct drm_i915_gem_relocation_entry containing
801          * the relocations to be performed in this buffer.
802          */
803         __u64 relocs_ptr;
804 
805         /** Required alignment in graphics aperture */
806         __u64 alignment;
807 
808         /**
809          * Returned value of the updated offset of the object, for future
810          * presumed_offset writes.
811          */
812         __u64 offset;
813 };
814 
815 struct drm_i915_gem_execbuffer {
816         /**
817          * List of buffers to be validated with their relocations to be
818          * performend on them.
819          *
820          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
821          *
822          * These buffers must be listed in an order such that all relocations
823          * a buffer is performing refer to buffers that have already appeared
824          * in the validate list.
825          */
826         __u64 buffers_ptr;
827         __u32 buffer_count;
828 
829         /** Offset in the batchbuffer to start execution from. */
830         __u32 batch_start_offset;
831         /** Bytes used in batchbuffer from batch_start_offset */
832         __u32 batch_len;
833         __u32 DR1;
834         __u32 DR4;
835         __u32 num_cliprects;
836         /** This is a struct drm_clip_rect *cliprects */
837         __u64 cliprects_ptr;
838 };
839 
840 struct drm_i915_gem_exec_object2 {
841         /**
842          * User's handle for a buffer to be bound into the GTT for this
843          * operation.
844          */
845         __u32 handle;
846 
847         /** Number of relocations to be performed on this buffer */
848         __u32 relocation_count;
849         /**
850          * Pointer to array of struct drm_i915_gem_relocation_entry containing
851          * the relocations to be performed in this buffer.
852          */
853         __u64 relocs_ptr;
854 
855         /** Required alignment in graphics aperture */
856         __u64 alignment;
857 
858         /**
859          * When the EXEC_OBJECT_PINNED flag is specified this is populated by
860          * the user with the GTT offset at which this object will be pinned.
861          * When the I915_EXEC_NO_RELOC flag is specified this must contain the
862          * presumed_offset of the object.
863          * During execbuffer2 the kernel populates it with the value of the
864          * current GTT offset of the object, for future presumed_offset writes.
865          */
866         __u64 offset;
867 
868 #define EXEC_OBJECT_NEEDS_FENCE          (1<<0)
869 #define EXEC_OBJECT_NEEDS_GTT            (1<<1)
870 #define EXEC_OBJECT_WRITE                (1<<2)
871 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
872 #define EXEC_OBJECT_PINNED               (1<<4)
873 #define EXEC_OBJECT_PAD_TO_SIZE          (1<<5)
874 /* The kernel implicitly tracks GPU activity on all GEM objects, and
875  * synchronises operations with outstanding rendering. This includes
876  * rendering on other devices if exported via dma-buf. However, sometimes
877  * this tracking is too coarse and the user knows better. For example,
878  * if the object is split into non-overlapping ranges shared between different
879  * clients or engines (i.e. suballocating objects), the implicit tracking
880  * by kernel assumes that each operation affects the whole object rather
881  * than an individual range, causing needless synchronisation between clients.
882  * The kernel will also forgo any CPU cache flushes prior to rendering from
883  * the object as the client is expected to be also handling such domain
884  * tracking.
885  *
886  * The kernel maintains the implicit tracking in order to manage resources
887  * used by the GPU - this flag only disables the synchronisation prior to
888  * rendering with this object in this execbuf.
889  *
890  * Opting out of implicit synhronisation requires the user to do its own
891  * explicit tracking to avoid rendering corruption. See, for example,
892  * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
893  */
894 #define EXEC_OBJECT_ASYNC               (1<<6)
895 /* Request that the contents of this execobject be copied into the error
896  * state upon a GPU hang involving this batch for post-mortem debugging.
897  * These buffers are recorded in no particular order as "user" in
898  * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
899  * if the kernel supports this flag.
900  */
901 #define EXEC_OBJECT_CAPTURE             (1<<7)
902 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
903 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
904         __u64 flags;
905 
906         union {
907                 __u64 rsvd1;
908                 __u64 pad_to_size;
909         };
910         __u64 rsvd2;
911 };
912 
913 struct drm_i915_gem_exec_fence {
914         /**
915          * User's handle for a drm_syncobj to wait on or signal.
916          */
917         __u32 handle;
918 
919 #define I915_EXEC_FENCE_WAIT            (1<<0)
920 #define I915_EXEC_FENCE_SIGNAL          (1<<1)
921 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
922         __u32 flags;
923 };
924 
925 struct drm_i915_gem_execbuffer2 {
926         /**
927          * List of gem_exec_object2 structs
928          */
929         __u64 buffers_ptr;
930         __u32 buffer_count;
931 
932         /** Offset in the batchbuffer to start execution from. */
933         __u32 batch_start_offset;
934         /** Bytes used in batchbuffer from batch_start_offset */
935         __u32 batch_len;
936         __u32 DR1;
937         __u32 DR4;
938         __u32 num_cliprects;
939         /**
940          * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
941          * is not set.  If I915_EXEC_FENCE_ARRAY is set, then this is a
942          * struct drm_i915_gem_exec_fence *fences.
943          */
944         __u64 cliprects_ptr;
945 #define I915_EXEC_RING_MASK              (7<<0)
946 #define I915_EXEC_DEFAULT                (0<<0)
947 #define I915_EXEC_RENDER                 (1<<0)
948 #define I915_EXEC_BSD                    (2<<0)
949 #define I915_EXEC_BLT                    (3<<0)
950 #define I915_EXEC_VEBOX                  (4<<0)
951 
952 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
953  * Gen6+ only supports relative addressing to dynamic state (default) and
954  * absolute addressing.
955  *
956  * These flags are ignored for the BSD and BLT rings.
957  */
958 #define I915_EXEC_CONSTANTS_MASK        (3<<6)
959 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
960 #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
961 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
962         __u64 flags;
963         __u64 rsvd1; /* now used for context info */
964         __u64 rsvd2;
965 };
966 
967 /** Resets the SO write offset registers for transform feedback on gen7. */
968 #define I915_EXEC_GEN7_SOL_RESET        (1<<8)
969 
970 /** Request a privileged ("secure") batch buffer. Note only available for
971  * DRM_ROOT_ONLY | DRM_MASTER processes.
972  */
973 #define I915_EXEC_SECURE                (1<<9)
974 
975 /** Inform the kernel that the batch is and will always be pinned. This
976  * negates the requirement for a workaround to be performed to avoid
977  * an incoherent CS (such as can be found on 830/845). If this flag is
978  * not passed, the kernel will endeavour to make sure the batch is
979  * coherent with the CS before execution. If this flag is passed,
980  * userspace assumes the responsibility for ensuring the same.
981  */
982 #define I915_EXEC_IS_PINNED             (1<<10)
983 
984 /** Provide a hint to the kernel that the command stream and auxiliary
985  * state buffers already holds the correct presumed addresses and so the
986  * relocation process may be skipped if no buffers need to be moved in
987  * preparation for the execbuffer.
988  */
989 #define I915_EXEC_NO_RELOC              (1<<11)
990 
991 /** Use the reloc.handle as an index into the exec object array rather
992  * than as the per-file handle.
993  */
994 #define I915_EXEC_HANDLE_LUT            (1<<12)
995 
996 /** Used for switching BSD rings on the platforms with two BSD rings */
997 #define I915_EXEC_BSD_SHIFT      (13)
998 #define I915_EXEC_BSD_MASK       (3 << I915_EXEC_BSD_SHIFT)
999 /* default ping-pong mode */
1000 #define I915_EXEC_BSD_DEFAULT    (0 << I915_EXEC_BSD_SHIFT)
1001 #define I915_EXEC_BSD_RING1      (1 << I915_EXEC_BSD_SHIFT)
1002 #define I915_EXEC_BSD_RING2      (2 << I915_EXEC_BSD_SHIFT)
1003 
1004 /** Tell the kernel that the batchbuffer is processed by
1005  *  the resource streamer.
1006  */
1007 #define I915_EXEC_RESOURCE_STREAMER     (1<<15)
1008 
1009 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1010  * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1011  * the batch.
1012  *
1013  * Returns -EINVAL if the sync_file fd cannot be found.
1014  */
1015 #define I915_EXEC_FENCE_IN              (1<<16)
1016 
1017 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1018  * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1019  * to the caller, and it should be close() after use. (The fd is a regular
1020  * file descriptor and will be cleaned up on process termination. It holds
1021  * a reference to the request, but nothing else.)
1022  *
1023  * The sync_file fd can be combined with other sync_file and passed either
1024  * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1025  * will only occur after this request completes), or to other devices.
1026  *
1027  * Using I915_EXEC_FENCE_OUT requires use of
1028  * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1029  * back to userspace. Failure to do so will cause the out-fence to always
1030  * be reported as zero, and the real fence fd to be leaked.
1031  */
1032 #define I915_EXEC_FENCE_OUT             (1<<17)
1033 
1034 /*
1035  * Traditionally the execbuf ioctl has only considered the final element in
1036  * the execobject[] to be the executable batch. Often though, the client
1037  * will known the batch object prior to construction and being able to place
1038  * it into the execobject[] array first can simplify the relocation tracking.
1039  * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1040  * execobject[] as the * batch instead (the default is to use the last
1041  * element).
1042  */
1043 #define I915_EXEC_BATCH_FIRST           (1<<18)
1044 
1045 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1046  * define an array of i915_gem_exec_fence structures which specify a set of
1047  * dma fences to wait upon or signal.
1048  */
1049 #define I915_EXEC_FENCE_ARRAY   (1<<19)
1050 
1051 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
1052 
1053 #define I915_EXEC_CONTEXT_ID_MASK       (0xffffffff)
1054 #define i915_execbuffer2_set_context_id(eb2, context) \
1055         (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1056 #define i915_execbuffer2_get_context_id(eb2) \
1057         ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1058 
1059 struct drm_i915_gem_pin {
1060         /** Handle of the buffer to be pinned. */
1061         __u32 handle;
1062         __u32 pad;
1063 
1064         /** alignment required within the aperture */
1065         __u64 alignment;
1066 
1067         /** Returned GTT offset of the buffer. */
1068         __u64 offset;
1069 };
1070 
1071 struct drm_i915_gem_unpin {
1072         /** Handle of the buffer to be unpinned. */
1073         __u32 handle;
1074         __u32 pad;
1075 };
1076 
1077 struct drm_i915_gem_busy {
1078         /** Handle of the buffer to check for busy */
1079         __u32 handle;
1080 
1081         /** Return busy status
1082          *
1083          * A return of 0 implies that the object is idle (after
1084          * having flushed any pending activity), and a non-zero return that
1085          * the object is still in-flight on the GPU. (The GPU has not yet
1086          * signaled completion for all pending requests that reference the
1087          * object.) An object is guaranteed to become idle eventually (so
1088          * long as no new GPU commands are executed upon it). Due to the
1089          * asynchronous nature of the hardware, an object reported
1090          * as busy may become idle before the ioctl is completed.
1091          *
1092          * Furthermore, if the object is busy, which engine is busy is only
1093          * provided as a guide. There are race conditions which prevent the
1094          * report of which engines are busy from being always accurate.
1095          * However, the converse is not true. If the object is idle, the
1096          * result of the ioctl, that all engines are idle, is accurate.
1097          *
1098          * The returned dword is split into two fields to indicate both
1099          * the engines on which the object is being read, and the
1100          * engine on which it is currently being written (if any).
1101          *
1102          * The low word (bits 0:15) indicate if the object is being written
1103          * to by any engine (there can only be one, as the GEM implicit
1104          * synchronisation rules force writes to be serialised). Only the
1105          * engine for the last write is reported.
1106          *
1107          * The high word (bits 16:31) are a bitmask of which engines are
1108          * currently reading from the object. Multiple engines may be
1109          * reading from the object simultaneously.
1110          *
1111          * The value of each engine is the same as specified in the
1112          * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
1113          * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
1114          * the I915_EXEC_RENDER engine for execution, and so it is never
1115          * reported as active itself. Some hardware may have parallel
1116          * execution engines, e.g. multiple media engines, which are
1117          * mapped to the same identifier in the EXECBUFFER2 ioctl and
1118          * so are not separately reported for busyness.
1119          *
1120          * Caveat emptor:
1121          * Only the boolean result of this query is reliable; that is whether
1122          * the object is idle or busy. The report of which engines are busy
1123          * should be only used as a heuristic.
1124          */
1125         __u32 busy;
1126 };
1127 
1128 /**
1129  * I915_CACHING_NONE
1130  *
1131  * GPU access is not coherent with cpu caches. Default for machines without an
1132  * LLC.
1133  */
1134 #define I915_CACHING_NONE               0
1135 /**
1136  * I915_CACHING_CACHED
1137  *
1138  * GPU access is coherent with cpu caches and furthermore the data is cached in
1139  * last-level caches shared between cpu cores and the gpu GT. Default on
1140  * machines with HAS_LLC.
1141  */
1142 #define I915_CACHING_CACHED             1
1143 /**
1144  * I915_CACHING_DISPLAY
1145  *
1146  * Special GPU caching mode which is coherent with the scanout engines.
1147  * Transparently falls back to I915_CACHING_NONE on platforms where no special
1148  * cache mode (like write-through or gfdt flushing) is available. The kernel
1149  * automatically sets this mode when using a buffer as a scanout target.
1150  * Userspace can manually set this mode to avoid a costly stall and clflush in
1151  * the hotpath of drawing the first frame.
1152  */
1153 #define I915_CACHING_DISPLAY            2
1154 
1155 struct drm_i915_gem_caching {
1156         /**
1157          * Handle of the buffer to set/get the caching level of. */
1158         __u32 handle;
1159 
1160         /**
1161          * Cacheing level to apply or return value
1162          *
1163          * bits0-15 are for generic caching control (i.e. the above defined
1164          * values). bits16-31 are reserved for platform-specific variations
1165          * (e.g. l3$ caching on gen7). */
1166         __u32 caching;
1167 };
1168 
1169 #define I915_TILING_NONE        0
1170 #define I915_TILING_X           1
1171 #define I915_TILING_Y           2
1172 #define I915_TILING_LAST        I915_TILING_Y
1173 
1174 #define I915_BIT_6_SWIZZLE_NONE         0
1175 #define I915_BIT_6_SWIZZLE_9            1
1176 #define I915_BIT_6_SWIZZLE_9_10         2
1177 #define I915_BIT_6_SWIZZLE_9_11         3
1178 #define I915_BIT_6_SWIZZLE_9_10_11      4
1179 /* Not seen by userland */
1180 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
1181 /* Seen by userland. */
1182 #define I915_BIT_6_SWIZZLE_9_17         6
1183 #define I915_BIT_6_SWIZZLE_9_10_17      7
1184 
1185 struct drm_i915_gem_set_tiling {
1186         /** Handle of the buffer to have its tiling state updated */
1187         __u32 handle;
1188 
1189         /**
1190          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1191          * I915_TILING_Y).
1192          *
1193          * This value is to be set on request, and will be updated by the
1194          * kernel on successful return with the actual chosen tiling layout.
1195          *
1196          * The tiling mode may be demoted to I915_TILING_NONE when the system
1197          * has bit 6 swizzling that can't be managed correctly by GEM.
1198          *
1199          * Buffer contents become undefined when changing tiling_mode.
1200          */
1201         __u32 tiling_mode;
1202 
1203         /**
1204          * Stride in bytes for the object when in I915_TILING_X or
1205          * I915_TILING_Y.
1206          */
1207         __u32 stride;
1208 
1209         /**
1210          * Returned address bit 6 swizzling required for CPU access through
1211          * mmap mapping.
1212          */
1213         __u32 swizzle_mode;
1214 };
1215 
1216 struct drm_i915_gem_get_tiling {
1217         /** Handle of the buffer to get tiling state for. */
1218         __u32 handle;
1219 
1220         /**
1221          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1222          * I915_TILING_Y).
1223          */
1224         __u32 tiling_mode;
1225 
1226         /**
1227          * Returned address bit 6 swizzling required for CPU access through
1228          * mmap mapping.
1229          */
1230         __u32 swizzle_mode;
1231 
1232         /**
1233          * Returned address bit 6 swizzling required for CPU access through
1234          * mmap mapping whilst bound.
1235          */
1236         __u32 phys_swizzle_mode;
1237 };
1238 
1239 struct drm_i915_gem_get_aperture {
1240         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1241         __u64 aper_size;
1242 
1243         /**
1244          * Available space in the aperture used by i915_gem_execbuffer, in
1245          * bytes
1246          */
1247         __u64 aper_available_size;
1248 };
1249 
1250 struct drm_i915_get_pipe_from_crtc_id {
1251         /** ID of CRTC being requested **/
1252         __u32 crtc_id;
1253 
1254         /** pipe of requested CRTC **/
1255         __u32 pipe;
1256 };
1257 
1258 #define I915_MADV_WILLNEED 0
1259 #define I915_MADV_DONTNEED 1
1260 #define __I915_MADV_PURGED 2 /* internal state */
1261 
1262 struct drm_i915_gem_madvise {
1263         /** Handle of the buffer to change the backing store advice */
1264         __u32 handle;
1265 
1266         /* Advice: either the buffer will be needed again in the near future,
1267          *         or wont be and could be discarded under memory pressure.
1268          */
1269         __u32 madv;
1270 
1271         /** Whether the backing store still exists. */
1272         __u32 retained;
1273 };
1274 
1275 /* flags */
1276 #define I915_OVERLAY_TYPE_MASK          0xff
1277 #define I915_OVERLAY_YUV_PLANAR         0x01
1278 #define I915_OVERLAY_YUV_PACKED         0x02
1279 #define I915_OVERLAY_RGB                0x03
1280 
1281 #define I915_OVERLAY_DEPTH_MASK         0xff00
1282 #define I915_OVERLAY_RGB24              0x1000
1283 #define I915_OVERLAY_RGB16              0x2000
1284 #define I915_OVERLAY_RGB15              0x3000
1285 #define I915_OVERLAY_YUV422             0x0100
1286 #define I915_OVERLAY_YUV411             0x0200
1287 #define I915_OVERLAY_YUV420             0x0300
1288 #define I915_OVERLAY_YUV410             0x0400
1289 
1290 #define I915_OVERLAY_SWAP_MASK          0xff0000
1291 #define I915_OVERLAY_NO_SWAP            0x000000
1292 #define I915_OVERLAY_UV_SWAP            0x010000
1293 #define I915_OVERLAY_Y_SWAP             0x020000
1294 #define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
1295 
1296 #define I915_OVERLAY_FLAGS_MASK         0xff000000
1297 #define I915_OVERLAY_ENABLE             0x01000000
1298 
1299 struct drm_intel_overlay_put_image {
1300         /* various flags and src format description */
1301         __u32 flags;
1302         /* source picture description */
1303         __u32 bo_handle;
1304         /* stride values and offsets are in bytes, buffer relative */
1305         __u16 stride_Y; /* stride for packed formats */
1306         __u16 stride_UV;
1307         __u32 offset_Y; /* offset for packet formats */
1308         __u32 offset_U;
1309         __u32 offset_V;
1310         /* in pixels */
1311         __u16 src_width;
1312         __u16 src_height;
1313         /* to compensate the scaling factors for partially covered surfaces */
1314         __u16 src_scan_width;
1315         __u16 src_scan_height;
1316         /* output crtc description */
1317         __u32 crtc_id;
1318         __u16 dst_x;
1319         __u16 dst_y;
1320         __u16 dst_width;
1321         __u16 dst_height;
1322 };
1323 
1324 /* flags */
1325 #define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
1326 #define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
1327 #define I915_OVERLAY_DISABLE_DEST_COLORKEY      (1<<2)
1328 struct drm_intel_overlay_attrs {
1329         __u32 flags;
1330         __u32 color_key;
1331         __s32 brightness;
1332         __u32 contrast;
1333         __u32 saturation;
1334         __u32 gamma0;
1335         __u32 gamma1;
1336         __u32 gamma2;
1337         __u32 gamma3;
1338         __u32 gamma4;
1339         __u32 gamma5;
1340 };
1341 
1342 /*
1343  * Intel sprite handling
1344  *
1345  * Color keying works with a min/mask/max tuple.  Both source and destination
1346  * color keying is allowed.
1347  *
1348  * Source keying:
1349  * Sprite pixels within the min & max values, masked against the color channels
1350  * specified in the mask field, will be transparent.  All other pixels will
1351  * be displayed on top of the primary plane.  For RGB surfaces, only the min
1352  * and mask fields will be used; ranged compares are not allowed.
1353  *
1354  * Destination keying:
1355  * Primary plane pixels that match the min value, masked against the color
1356  * channels specified in the mask field, will be replaced by corresponding
1357  * pixels from the sprite plane.
1358  *
1359  * Note that source & destination keying are exclusive; only one can be
1360  * active on a given plane.
1361  */
1362 
1363 #define I915_SET_COLORKEY_NONE          (1<<0) /* Deprecated. Instead set
1364                                                 * flags==0 to disable colorkeying.
1365                                                 */
1366 #define I915_SET_COLORKEY_DESTINATION   (1<<1)
1367 #define I915_SET_COLORKEY_SOURCE        (1<<2)
1368 struct drm_intel_sprite_colorkey {
1369         __u32 plane_id;
1370         __u32 min_value;
1371         __u32 channel_mask;
1372         __u32 max_value;
1373         __u32 flags;
1374 };
1375 
1376 struct drm_i915_gem_wait {
1377         /** Handle of BO we shall wait on */
1378         __u32 bo_handle;
1379         __u32 flags;
1380         /** Number of nanoseconds to wait, Returns time remaining. */
1381         __s64 timeout_ns;
1382 };
1383 
1384 struct drm_i915_gem_context_create {
1385         /*  output: id of new context*/
1386         __u32 ctx_id;
1387         __u32 pad;
1388 };
1389 
1390 struct drm_i915_gem_context_destroy {
1391         __u32 ctx_id;
1392         __u32 pad;
1393 };
1394 
1395 struct drm_i915_reg_read {
1396         /*
1397          * Register offset.
1398          * For 64bit wide registers where the upper 32bits don't immediately
1399          * follow the lower 32bits, the offset of the lower 32bits must
1400          * be specified
1401          */
1402         __u64 offset;
1403 #define I915_REG_READ_8B_WA (1ul << 0)
1404 
1405         __u64 val; /* Return value */
1406 };
1407 /* Known registers:
1408  *
1409  * Render engine timestamp - 0x2358 + 64bit - gen7+
1410  * - Note this register returns an invalid value if using the default
1411  *   single instruction 8byte read, in order to workaround that pass
1412  *   flag I915_REG_READ_8B_WA in offset field.
1413  *
1414  */
1415 
1416 struct drm_i915_reset_stats {
1417         __u32 ctx_id;
1418         __u32 flags;
1419 
1420         /* All resets since boot/module reload, for all contexts */
1421         __u32 reset_count;
1422 
1423         /* Number of batches lost when active in GPU, for this context */
1424         __u32 batch_active;
1425 
1426         /* Number of batches lost pending for execution, for this context */
1427         __u32 batch_pending;
1428 
1429         __u32 pad;
1430 };
1431 
1432 struct drm_i915_gem_userptr {
1433         __u64 user_ptr;
1434         __u64 user_size;
1435         __u32 flags;
1436 #define I915_USERPTR_READ_ONLY 0x1
1437 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1438         /**
1439          * Returned handle for the object.
1440          *
1441          * Object handles are nonzero.
1442          */
1443         __u32 handle;
1444 };
1445 
1446 struct drm_i915_gem_context_param {
1447         __u32 ctx_id;
1448         __u32 size;
1449         __u64 param;
1450 #define I915_CONTEXT_PARAM_BAN_PERIOD   0x1
1451 #define I915_CONTEXT_PARAM_NO_ZEROMAP   0x2
1452 #define I915_CONTEXT_PARAM_GTT_SIZE     0x3
1453 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE     0x4
1454 #define I915_CONTEXT_PARAM_BANNABLE     0x5
1455 #define I915_CONTEXT_PARAM_PRIORITY     0x6
1456 #define   I915_CONTEXT_MAX_USER_PRIORITY        1023 /* inclusive */
1457 #define   I915_CONTEXT_DEFAULT_PRIORITY         0
1458 #define   I915_CONTEXT_MIN_USER_PRIORITY        -1023 /* inclusive */
1459         __u64 value;
1460 };
1461 
1462 enum drm_i915_oa_format {
1463         I915_OA_FORMAT_A13 = 1,     /* HSW only */
1464         I915_OA_FORMAT_A29,         /* HSW only */
1465         I915_OA_FORMAT_A13_B8_C8,   /* HSW only */
1466         I915_OA_FORMAT_B4_C8,       /* HSW only */
1467         I915_OA_FORMAT_A45_B8_C8,   /* HSW only */
1468         I915_OA_FORMAT_B4_C8_A16,   /* HSW only */
1469         I915_OA_FORMAT_C4_B8,       /* HSW+ */
1470 
1471         /* Gen8+ */
1472         I915_OA_FORMAT_A12,
1473         I915_OA_FORMAT_A12_B8_C8,
1474         I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1475 
1476         I915_OA_FORMAT_MAX          /* non-ABI */
1477 };
1478 
1479 enum drm_i915_perf_property_id {
1480         /**
1481          * Open the stream for a specific context handle (as used with
1482          * execbuffer2). A stream opened for a specific context this way
1483          * won't typically require root privileges.
1484          */
1485         DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1486 
1487         /**
1488          * A value of 1 requests the inclusion of raw OA unit reports as
1489          * part of stream samples.
1490          */
1491         DRM_I915_PERF_PROP_SAMPLE_OA,
1492 
1493         /**
1494          * The value specifies which set of OA unit metrics should be
1495          * be configured, defining the contents of any OA unit reports.
1496          */
1497         DRM_I915_PERF_PROP_OA_METRICS_SET,
1498 
1499         /**
1500          * The value specifies the size and layout of OA unit reports.
1501          */
1502         DRM_I915_PERF_PROP_OA_FORMAT,
1503 
1504         /**
1505          * Specifying this property implicitly requests periodic OA unit
1506          * sampling and (at least on Haswell) the sampling frequency is derived
1507          * from this exponent as follows:
1508          *
1509          *   80ns * 2^(period_exponent + 1)
1510          */
1511         DRM_I915_PERF_PROP_OA_EXPONENT,
1512 
1513         DRM_I915_PERF_PROP_MAX /* non-ABI */
1514 };
1515 
1516 struct drm_i915_perf_open_param {
1517         __u32 flags;
1518 #define I915_PERF_FLAG_FD_CLOEXEC       (1<<0)
1519 #define I915_PERF_FLAG_FD_NONBLOCK      (1<<1)
1520 #define I915_PERF_FLAG_DISABLED         (1<<2)
1521 
1522         /** The number of u64 (id, value) pairs */
1523         __u32 num_properties;
1524 
1525         /**
1526          * Pointer to array of u64 (id, value) pairs configuring the stream
1527          * to open.
1528          */
1529         __u64 properties_ptr;
1530 };
1531 
1532 /**
1533  * Enable data capture for a stream that was either opened in a disabled state
1534  * via I915_PERF_FLAG_DISABLED or was later disabled via
1535  * I915_PERF_IOCTL_DISABLE.
1536  *
1537  * It is intended to be cheaper to disable and enable a stream than it may be
1538  * to close and re-open a stream with the same configuration.
1539  *
1540  * It's undefined whether any pending data for the stream will be lost.
1541  */
1542 #define I915_PERF_IOCTL_ENABLE  _IO('i', 0x0)
1543 
1544 /**
1545  * Disable data capture for a stream.
1546  *
1547  * It is an error to try and read a stream that is disabled.
1548  */
1549 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1550 
1551 /**
1552  * Common to all i915 perf records
1553  */
1554 struct drm_i915_perf_record_header {
1555         __u32 type;
1556         __u16 pad;
1557         __u16 size;
1558 };
1559 
1560 enum drm_i915_perf_record_type {
1561 
1562         /**
1563          * Samples are the work horse record type whose contents are extensible
1564          * and defined when opening an i915 perf stream based on the given
1565          * properties.
1566          *
1567          * Boolean properties following the naming convention
1568          * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1569          * every sample.
1570          *
1571          * The order of these sample properties given by userspace has no
1572          * affect on the ordering of data within a sample. The order is
1573          * documented here.
1574          *
1575          * struct {
1576          *     struct drm_i915_perf_record_header header;
1577          *
1578          *     { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1579          * };
1580          */
1581         DRM_I915_PERF_RECORD_SAMPLE = 1,
1582 
1583         /*
1584          * Indicates that one or more OA reports were not written by the
1585          * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1586          * command collides with periodic sampling - which would be more likely
1587          * at higher sampling frequencies.
1588          */
1589         DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1590 
1591         /**
1592          * An error occurred that resulted in all pending OA reports being lost.
1593          */
1594         DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1595 
1596         DRM_I915_PERF_RECORD_MAX /* non-ABI */
1597 };
1598 
1599 /**
1600  * Structure to upload perf dynamic configuration into the kernel.
1601  */
1602 struct drm_i915_perf_oa_config {
1603         /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
1604         char uuid[36];
1605 
1606         __u32 n_mux_regs;
1607         __u32 n_boolean_regs;
1608         __u32 n_flex_regs;
1609 
1610         /*
1611          * These fields are pointers to tuples of u32 values (register address,
1612          * value). For example the expected length of the buffer pointed by
1613          * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
1614          */
1615         __u64 mux_regs_ptr;
1616         __u64 boolean_regs_ptr;
1617         __u64 flex_regs_ptr;
1618 };
1619 
1620 struct drm_i915_query_item {
1621         __u64 query_id;
1622 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
1623 
1624         /*
1625          * When set to zero by userspace, this is filled with the size of the
1626          * data to be written at the data_ptr pointer. The kernel sets this
1627          * value to a negative value to signal an error on a particular query
1628          * item.
1629          */
1630         __s32 length;
1631 
1632         /*
1633          * Unused for now. Must be cleared to zero.
1634          */
1635         __u32 flags;
1636 
1637         /*
1638          * Data will be written at the location pointed by data_ptr when the
1639          * value of length matches the length of the data to be written by the
1640          * kernel.
1641          */
1642         __u64 data_ptr;
1643 };
1644 
1645 struct drm_i915_query {
1646         __u32 num_items;
1647 
1648         /*
1649          * Unused for now. Must be cleared to zero.
1650          */
1651         __u32 flags;
1652 
1653         /*
1654          * This points to an array of num_items drm_i915_query_item structures.
1655          */
1656         __u64 items_ptr;
1657 };
1658 
1659 /*
1660  * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
1661  *
1662  * data: contains the 3 pieces of information :
1663  *
1664  * - the slice mask with one bit per slice telling whether a slice is
1665  *   available. The availability of slice X can be queried with the following
1666  *   formula :
1667  *
1668  *           (data[X / 8] >> (X % 8)) & 1
1669  *
1670  * - the subslice mask for each slice with one bit per subslice telling
1671  *   whether a subslice is available. The availability of subslice Y in slice
1672  *   X can be queried with the following formula :
1673  *
1674  *           (data[subslice_offset +
1675  *                 X * subslice_stride +
1676  *                 Y / 8] >> (Y % 8)) & 1
1677  *
1678  * - the EU mask for each subslice in each slice with one bit per EU telling
1679  *   whether an EU is available. The availability of EU Z in subslice Y in
1680  *   slice X can be queried with the following formula :
1681  *
1682  *           (data[eu_offset +
1683  *                 (X * max_subslices + Y) * eu_stride +
1684  *                 Z / 8] >> (Z % 8)) & 1
1685  */
1686 struct drm_i915_query_topology_info {
1687         /*
1688          * Unused for now. Must be cleared to zero.
1689          */
1690         __u16 flags;
1691 
1692         __u16 max_slices;
1693         __u16 max_subslices;
1694         __u16 max_eus_per_subslice;
1695 
1696         /*
1697          * Offset in data[] at which the subslice masks are stored.
1698          */
1699         __u16 subslice_offset;
1700 
1701         /*
1702          * Stride at which each of the subslice masks for each slice are
1703          * stored.
1704          */
1705         __u16 subslice_stride;
1706 
1707         /*
1708          * Offset in data[] at which the EU masks are stored.
1709          */
1710         __u16 eu_offset;
1711 
1712         /*
1713          * Stride at which each of the EU masks for each subslice are stored.
1714          */
1715         __u16 eu_stride;
1716 
1717         __u8 data[];
1718 };
1719 
1720 #if defined(__cplusplus)
1721 }
1722 #endif
1723 
1724 #endif /* _UAPI_I915_DRM_H_ */
1725 

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