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TOMOYO Linux Cross Reference
Linux/tools/testing/nvdimm/test/nfit.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
  4  */
  5 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  6 #include <linux/platform_device.h>
  7 #include <linux/dma-mapping.h>
  8 #include <linux/workqueue.h>
  9 #include <linux/libnvdimm.h>
 10 #include <linux/genalloc.h>
 11 #include <linux/vmalloc.h>
 12 #include <linux/device.h>
 13 #include <linux/module.h>
 14 #include <linux/mutex.h>
 15 #include <linux/ndctl.h>
 16 #include <linux/sizes.h>
 17 #include <linux/list.h>
 18 #include <linux/slab.h>
 19 #include <nd-core.h>
 20 #include <intel.h>
 21 #include <nfit.h>
 22 #include <nd.h>
 23 #include "nfit_test.h"
 24 #include "../watermark.h"
 25 
 26 #include <asm/mcsafe_test.h>
 27 
 28 /*
 29  * Generate an NFIT table to describe the following topology:
 30  *
 31  * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
 32  *
 33  *                     (a)                       (b)            DIMM   BLK-REGION
 34  *           +----------+--------------+----------+---------+
 35  * +------+  |  blk2.0  |     pm0.0    |  blk2.1  |  pm1.0  |    0      region2
 36  * | imc0 +--+- - - - - region0 - - - -+----------+         +
 37  * +--+---+  |  blk3.0  |     pm0.0    |  blk3.1  |  pm1.0  |    1      region3
 38  *    |      +----------+--------------v----------v         v
 39  * +--+---+                            |                    |
 40  * | cpu0 |                                    region1
 41  * +--+---+                            |                    |
 42  *    |      +-------------------------^----------^         ^
 43  * +--+---+  |                 blk4.0             |  pm1.0  |    2      region4
 44  * | imc1 +--+-------------------------+----------+         +
 45  * +------+  |                 blk5.0             |  pm1.0  |    3      region5
 46  *           +-------------------------+----------+-+-------+
 47  *
 48  * +--+---+
 49  * | cpu1 |
 50  * +--+---+                   (Hotplug DIMM)
 51  *    |      +----------------------------------------------+
 52  * +--+---+  |                 blk6.0/pm7.0                 |    4      region6/7
 53  * | imc0 +--+----------------------------------------------+
 54  * +------+
 55  *
 56  *
 57  * *) In this layout we have four dimms and two memory controllers in one
 58  *    socket.  Each unique interface (BLK or PMEM) to DPA space
 59  *    is identified by a region device with a dynamically assigned id.
 60  *
 61  * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
 62  *    A single PMEM namespace "pm0.0" is created using half of the
 63  *    REGION0 SPA-range.  REGION0 spans dimm0 and dimm1.  PMEM namespace
 64  *    allocate from from the bottom of a region.  The unallocated
 65  *    portion of REGION0 aliases with REGION2 and REGION3.  That
 66  *    unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
 67  *    "blk3.0") starting at the base of each DIMM to offset (a) in those
 68  *    DIMMs.  "pm0.0", "blk2.0" and "blk3.0" are free-form readable
 69  *    names that can be assigned to a namespace.
 70  *
 71  * *) In the last portion of dimm0 and dimm1 we have an interleaved
 72  *    SPA range, REGION1, that spans those two dimms as well as dimm2
 73  *    and dimm3.  Some of REGION1 allocated to a PMEM namespace named
 74  *    "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
 75  *    dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
 76  *    "blk5.0".
 77  *
 78  * *) The portion of dimm2 and dimm3 that do not participate in the
 79  *    REGION1 interleaved SPA range (i.e. the DPA address below offset
 80  *    (b) are also included in the "blk4.0" and "blk5.0" namespaces.
 81  *    Note, that BLK namespaces need not be contiguous in DPA-space, and
 82  *    can consume aliased capacity from multiple interleave sets.
 83  *
 84  * BUS1: Legacy NVDIMM (single contiguous range)
 85  *
 86  *  region2
 87  * +---------------------+
 88  * |---------------------|
 89  * ||       pm2.0       ||
 90  * |---------------------|
 91  * +---------------------+
 92  *
 93  * *) A NFIT-table may describe a simple system-physical-address range
 94  *    with no BLK aliasing.  This type of region may optionally
 95  *    reference an NVDIMM.
 96  */
 97 enum {
 98         NUM_PM  = 3,
 99         NUM_DCR = 5,
100         NUM_HINTS = 8,
101         NUM_BDW = NUM_DCR,
102         NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
103         NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
104                 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
105         DIMM_SIZE = SZ_32M,
106         LABEL_SIZE = SZ_128K,
107         SPA_VCD_SIZE = SZ_4M,
108         SPA0_SIZE = DIMM_SIZE,
109         SPA1_SIZE = DIMM_SIZE*2,
110         SPA2_SIZE = DIMM_SIZE,
111         BDW_SIZE = 64 << 8,
112         DCR_SIZE = 12,
113         NUM_NFITS = 2, /* permit testing multiple NFITs per system */
114 };
115 
116 struct nfit_test_dcr {
117         __le64 bdw_addr;
118         __le32 bdw_status;
119         __u8 aperature[BDW_SIZE];
120 };
121 
122 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
123         (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
124          | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
125 
126 static u32 handle[] = {
127         [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
128         [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
129         [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
130         [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
131         [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
132         [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
133         [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
134 };
135 
136 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)];
137 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)];
138 struct nfit_test_sec {
139         u8 state;
140         u8 ext_state;
141         u8 old_state;
142         u8 passphrase[32];
143         u8 master_passphrase[32];
144         u64 overwrite_end_time;
145 } dimm_sec_info[NUM_DCR];
146 
147 static const struct nd_intel_smart smart_def = {
148         .flags = ND_INTEL_SMART_HEALTH_VALID
149                 | ND_INTEL_SMART_SPARES_VALID
150                 | ND_INTEL_SMART_ALARM_VALID
151                 | ND_INTEL_SMART_USED_VALID
152                 | ND_INTEL_SMART_SHUTDOWN_VALID
153                 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID
154                 | ND_INTEL_SMART_MTEMP_VALID
155                 | ND_INTEL_SMART_CTEMP_VALID,
156         .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
157         .media_temperature = 23 * 16,
158         .ctrl_temperature = 25 * 16,
159         .pmic_temperature = 40 * 16,
160         .spares = 75,
161         .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
162                 | ND_INTEL_SMART_TEMP_TRIP,
163         .ait_status = 1,
164         .life_used = 5,
165         .shutdown_state = 0,
166         .shutdown_count = 42,
167         .vendor_size = 0,
168 };
169 
170 struct nfit_test_fw {
171         enum intel_fw_update_state state;
172         u32 context;
173         u64 version;
174         u32 size_received;
175         u64 end_time;
176 };
177 
178 struct nfit_test {
179         struct acpi_nfit_desc acpi_desc;
180         struct platform_device pdev;
181         struct list_head resources;
182         void *nfit_buf;
183         dma_addr_t nfit_dma;
184         size_t nfit_size;
185         size_t nfit_filled;
186         int dcr_idx;
187         int num_dcr;
188         int num_pm;
189         void **dimm;
190         dma_addr_t *dimm_dma;
191         void **flush;
192         dma_addr_t *flush_dma;
193         void **label;
194         dma_addr_t *label_dma;
195         void **spa_set;
196         dma_addr_t *spa_set_dma;
197         struct nfit_test_dcr **dcr;
198         dma_addr_t *dcr_dma;
199         int (*alloc)(struct nfit_test *t);
200         void (*setup)(struct nfit_test *t);
201         int setup_hotplug;
202         union acpi_object **_fit;
203         dma_addr_t _fit_dma;
204         struct ars_state {
205                 struct nd_cmd_ars_status *ars_status;
206                 unsigned long deadline;
207                 spinlock_t lock;
208         } ars_state;
209         struct device *dimm_dev[ARRAY_SIZE(handle)];
210         struct nd_intel_smart *smart;
211         struct nd_intel_smart_threshold *smart_threshold;
212         struct badrange badrange;
213         struct work_struct work;
214         struct nfit_test_fw *fw;
215 };
216 
217 static struct workqueue_struct *nfit_wq;
218 
219 static struct gen_pool *nfit_pool;
220 
221 static const char zero_key[NVDIMM_PASSPHRASE_LEN];
222 
223 static struct nfit_test *to_nfit_test(struct device *dev)
224 {
225         struct platform_device *pdev = to_platform_device(dev);
226 
227         return container_of(pdev, struct nfit_test, pdev);
228 }
229 
230 static int nd_intel_test_get_fw_info(struct nfit_test *t,
231                 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
232                 int idx)
233 {
234         struct device *dev = &t->pdev.dev;
235         struct nfit_test_fw *fw = &t->fw[idx];
236 
237         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
238                         __func__, t, nd_cmd, buf_len, idx);
239 
240         if (buf_len < sizeof(*nd_cmd))
241                 return -EINVAL;
242 
243         nd_cmd->status = 0;
244         nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
245         nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
246         nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
247         nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
248         nd_cmd->update_cap = 0;
249         nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
250         nd_cmd->run_version = 0;
251         nd_cmd->updated_version = fw->version;
252 
253         return 0;
254 }
255 
256 static int nd_intel_test_start_update(struct nfit_test *t,
257                 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
258                 int idx)
259 {
260         struct device *dev = &t->pdev.dev;
261         struct nfit_test_fw *fw = &t->fw[idx];
262 
263         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
264                         __func__, t, nd_cmd, buf_len, idx);
265 
266         if (buf_len < sizeof(*nd_cmd))
267                 return -EINVAL;
268 
269         if (fw->state != FW_STATE_NEW) {
270                 /* extended status, FW update in progress */
271                 nd_cmd->status = 0x10007;
272                 return 0;
273         }
274 
275         fw->state = FW_STATE_IN_PROGRESS;
276         fw->context++;
277         fw->size_received = 0;
278         nd_cmd->status = 0;
279         nd_cmd->context = fw->context;
280 
281         dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
282 
283         return 0;
284 }
285 
286 static int nd_intel_test_send_data(struct nfit_test *t,
287                 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
288                 int idx)
289 {
290         struct device *dev = &t->pdev.dev;
291         struct nfit_test_fw *fw = &t->fw[idx];
292         u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
293 
294         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
295                         __func__, t, nd_cmd, buf_len, idx);
296 
297         if (buf_len < sizeof(*nd_cmd))
298                 return -EINVAL;
299 
300 
301         dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
302         dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
303         dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
304                         nd_cmd->data[nd_cmd->length-1]);
305 
306         if (fw->state != FW_STATE_IN_PROGRESS) {
307                 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
308                 *status = 0x5;
309                 return 0;
310         }
311 
312         if (nd_cmd->context != fw->context) {
313                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
314                                 __func__, nd_cmd->context, fw->context);
315                 *status = 0x10007;
316                 return 0;
317         }
318 
319         /*
320          * check offset + len > size of fw storage
321          * check length is > max send length
322          */
323         if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
324                         nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
325                 *status = 0x3;
326                 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
327                 return 0;
328         }
329 
330         fw->size_received += nd_cmd->length;
331         dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
332                         __func__, nd_cmd->length, fw->size_received);
333         *status = 0;
334         return 0;
335 }
336 
337 static int nd_intel_test_finish_fw(struct nfit_test *t,
338                 struct nd_intel_fw_finish_update *nd_cmd,
339                 unsigned int buf_len, int idx)
340 {
341         struct device *dev = &t->pdev.dev;
342         struct nfit_test_fw *fw = &t->fw[idx];
343 
344         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
345                         __func__, t, nd_cmd, buf_len, idx);
346 
347         if (fw->state == FW_STATE_UPDATED) {
348                 /* update already done, need cold boot */
349                 nd_cmd->status = 0x20007;
350                 return 0;
351         }
352 
353         dev_dbg(dev, "%s: context: %#x  ctrl_flags: %#x\n",
354                         __func__, nd_cmd->context, nd_cmd->ctrl_flags);
355 
356         switch (nd_cmd->ctrl_flags) {
357         case 0: /* finish */
358                 if (nd_cmd->context != fw->context) {
359                         dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
360                                         __func__, nd_cmd->context,
361                                         fw->context);
362                         nd_cmd->status = 0x10007;
363                         return 0;
364                 }
365                 nd_cmd->status = 0;
366                 fw->state = FW_STATE_VERIFY;
367                 /* set 1 second of time for firmware "update" */
368                 fw->end_time = jiffies + HZ;
369                 break;
370 
371         case 1: /* abort */
372                 fw->size_received = 0;
373                 /* successfully aborted status */
374                 nd_cmd->status = 0x40007;
375                 fw->state = FW_STATE_NEW;
376                 dev_dbg(dev, "%s: abort successful\n", __func__);
377                 break;
378 
379         default: /* bad control flag */
380                 dev_warn(dev, "%s: unknown control flag: %#x\n",
381                                 __func__, nd_cmd->ctrl_flags);
382                 return -EINVAL;
383         }
384 
385         return 0;
386 }
387 
388 static int nd_intel_test_finish_query(struct nfit_test *t,
389                 struct nd_intel_fw_finish_query *nd_cmd,
390                 unsigned int buf_len, int idx)
391 {
392         struct device *dev = &t->pdev.dev;
393         struct nfit_test_fw *fw = &t->fw[idx];
394 
395         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
396                         __func__, t, nd_cmd, buf_len, idx);
397 
398         if (buf_len < sizeof(*nd_cmd))
399                 return -EINVAL;
400 
401         if (nd_cmd->context != fw->context) {
402                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
403                                 __func__, nd_cmd->context, fw->context);
404                 nd_cmd->status = 0x10007;
405                 return 0;
406         }
407 
408         dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
409 
410         switch (fw->state) {
411         case FW_STATE_NEW:
412                 nd_cmd->updated_fw_rev = 0;
413                 nd_cmd->status = 0;
414                 dev_dbg(dev, "%s: new state\n", __func__);
415                 break;
416 
417         case FW_STATE_IN_PROGRESS:
418                 /* sequencing error */
419                 nd_cmd->status = 0x40007;
420                 nd_cmd->updated_fw_rev = 0;
421                 dev_dbg(dev, "%s: sequence error\n", __func__);
422                 break;
423 
424         case FW_STATE_VERIFY:
425                 if (time_is_after_jiffies64(fw->end_time)) {
426                         nd_cmd->updated_fw_rev = 0;
427                         nd_cmd->status = 0x20007;
428                         dev_dbg(dev, "%s: still verifying\n", __func__);
429                         break;
430                 }
431 
432                 dev_dbg(dev, "%s: transition out verify\n", __func__);
433                 fw->state = FW_STATE_UPDATED;
434                 /* we are going to fall through if it's "done" */
435         case FW_STATE_UPDATED:
436                 nd_cmd->status = 0;
437                 /* bogus test version */
438                 fw->version = nd_cmd->updated_fw_rev =
439                         INTEL_FW_FAKE_VERSION;
440                 dev_dbg(dev, "%s: updated\n", __func__);
441                 break;
442 
443         default: /* we should never get here */
444                 return -EINVAL;
445         }
446 
447         return 0;
448 }
449 
450 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
451                 unsigned int buf_len)
452 {
453         if (buf_len < sizeof(*nd_cmd))
454                 return -EINVAL;
455 
456         nd_cmd->status = 0;
457         nd_cmd->config_size = LABEL_SIZE;
458         nd_cmd->max_xfer = SZ_4K;
459 
460         return 0;
461 }
462 
463 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
464                 *nd_cmd, unsigned int buf_len, void *label)
465 {
466         unsigned int len, offset = nd_cmd->in_offset;
467         int rc;
468 
469         if (buf_len < sizeof(*nd_cmd))
470                 return -EINVAL;
471         if (offset >= LABEL_SIZE)
472                 return -EINVAL;
473         if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
474                 return -EINVAL;
475 
476         nd_cmd->status = 0;
477         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
478         memcpy(nd_cmd->out_buf, label + offset, len);
479         rc = buf_len - sizeof(*nd_cmd) - len;
480 
481         return rc;
482 }
483 
484 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
485                 unsigned int buf_len, void *label)
486 {
487         unsigned int len, offset = nd_cmd->in_offset;
488         u32 *status;
489         int rc;
490 
491         if (buf_len < sizeof(*nd_cmd))
492                 return -EINVAL;
493         if (offset >= LABEL_SIZE)
494                 return -EINVAL;
495         if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
496                 return -EINVAL;
497 
498         status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
499         *status = 0;
500         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
501         memcpy(label + offset, nd_cmd->in_buf, len);
502         rc = buf_len - sizeof(*nd_cmd) - (len + 4);
503 
504         return rc;
505 }
506 
507 #define NFIT_TEST_CLEAR_ERR_UNIT 256
508 
509 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
510                 unsigned int buf_len)
511 {
512         int ars_recs;
513 
514         if (buf_len < sizeof(*nd_cmd))
515                 return -EINVAL;
516 
517         /* for testing, only store up to n records that fit within 4k */
518         ars_recs = SZ_4K / sizeof(struct nd_ars_record);
519 
520         nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
521                 + ars_recs * sizeof(struct nd_ars_record);
522         nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
523         nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
524 
525         return 0;
526 }
527 
528 static void post_ars_status(struct ars_state *ars_state,
529                 struct badrange *badrange, u64 addr, u64 len)
530 {
531         struct nd_cmd_ars_status *ars_status;
532         struct nd_ars_record *ars_record;
533         struct badrange_entry *be;
534         u64 end = addr + len - 1;
535         int i = 0;
536 
537         ars_state->deadline = jiffies + 1*HZ;
538         ars_status = ars_state->ars_status;
539         ars_status->status = 0;
540         ars_status->address = addr;
541         ars_status->length = len;
542         ars_status->type = ND_ARS_PERSISTENT;
543 
544         spin_lock(&badrange->lock);
545         list_for_each_entry(be, &badrange->list, list) {
546                 u64 be_end = be->start + be->length - 1;
547                 u64 rstart, rend;
548 
549                 /* skip entries outside the range */
550                 if (be_end < addr || be->start > end)
551                         continue;
552 
553                 rstart = (be->start < addr) ? addr : be->start;
554                 rend = (be_end < end) ? be_end : end;
555                 ars_record = &ars_status->records[i];
556                 ars_record->handle = 0;
557                 ars_record->err_address = rstart;
558                 ars_record->length = rend - rstart + 1;
559                 i++;
560         }
561         spin_unlock(&badrange->lock);
562         ars_status->num_records = i;
563         ars_status->out_length = sizeof(struct nd_cmd_ars_status)
564                 + i * sizeof(struct nd_ars_record);
565 }
566 
567 static int nfit_test_cmd_ars_start(struct nfit_test *t,
568                 struct ars_state *ars_state,
569                 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
570                 int *cmd_rc)
571 {
572         if (buf_len < sizeof(*ars_start))
573                 return -EINVAL;
574 
575         spin_lock(&ars_state->lock);
576         if (time_before(jiffies, ars_state->deadline)) {
577                 ars_start->status = NFIT_ARS_START_BUSY;
578                 *cmd_rc = -EBUSY;
579         } else {
580                 ars_start->status = 0;
581                 ars_start->scrub_time = 1;
582                 post_ars_status(ars_state, &t->badrange, ars_start->address,
583                                 ars_start->length);
584                 *cmd_rc = 0;
585         }
586         spin_unlock(&ars_state->lock);
587 
588         return 0;
589 }
590 
591 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
592                 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
593                 int *cmd_rc)
594 {
595         if (buf_len < ars_state->ars_status->out_length)
596                 return -EINVAL;
597 
598         spin_lock(&ars_state->lock);
599         if (time_before(jiffies, ars_state->deadline)) {
600                 memset(ars_status, 0, buf_len);
601                 ars_status->status = NFIT_ARS_STATUS_BUSY;
602                 ars_status->out_length = sizeof(*ars_status);
603                 *cmd_rc = -EBUSY;
604         } else {
605                 memcpy(ars_status, ars_state->ars_status,
606                                 ars_state->ars_status->out_length);
607                 *cmd_rc = 0;
608         }
609         spin_unlock(&ars_state->lock);
610         return 0;
611 }
612 
613 static int nfit_test_cmd_clear_error(struct nfit_test *t,
614                 struct nd_cmd_clear_error *clear_err,
615                 unsigned int buf_len, int *cmd_rc)
616 {
617         const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
618         if (buf_len < sizeof(*clear_err))
619                 return -EINVAL;
620 
621         if ((clear_err->address & mask) || (clear_err->length & mask))
622                 return -EINVAL;
623 
624         badrange_forget(&t->badrange, clear_err->address, clear_err->length);
625         clear_err->status = 0;
626         clear_err->cleared = clear_err->length;
627         *cmd_rc = 0;
628         return 0;
629 }
630 
631 struct region_search_spa {
632         u64 addr;
633         struct nd_region *region;
634 };
635 
636 static int is_region_device(struct device *dev)
637 {
638         return !strncmp(dev->kobj.name, "region", 6);
639 }
640 
641 static int nfit_test_search_region_spa(struct device *dev, void *data)
642 {
643         struct region_search_spa *ctx = data;
644         struct nd_region *nd_region;
645         resource_size_t ndr_end;
646 
647         if (!is_region_device(dev))
648                 return 0;
649 
650         nd_region = to_nd_region(dev);
651         ndr_end = nd_region->ndr_start + nd_region->ndr_size;
652 
653         if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
654                 ctx->region = nd_region;
655                 return 1;
656         }
657 
658         return 0;
659 }
660 
661 static int nfit_test_search_spa(struct nvdimm_bus *bus,
662                 struct nd_cmd_translate_spa *spa)
663 {
664         int ret;
665         struct nd_region *nd_region = NULL;
666         struct nvdimm *nvdimm = NULL;
667         struct nd_mapping *nd_mapping = NULL;
668         struct region_search_spa ctx = {
669                 .addr = spa->spa,
670                 .region = NULL,
671         };
672         u64 dpa;
673 
674         ret = device_for_each_child(&bus->dev, &ctx,
675                                 nfit_test_search_region_spa);
676 
677         if (!ret)
678                 return -ENODEV;
679 
680         nd_region = ctx.region;
681 
682         dpa = ctx.addr - nd_region->ndr_start;
683 
684         /*
685          * last dimm is selected for test
686          */
687         nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
688         nvdimm = nd_mapping->nvdimm;
689 
690         spa->devices[0].nfit_device_handle = handle[nvdimm->id];
691         spa->num_nvdimms = 1;
692         spa->devices[0].dpa = dpa;
693 
694         return 0;
695 }
696 
697 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
698                 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
699 {
700         if (buf_len < spa->translate_length)
701                 return -EINVAL;
702 
703         if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
704                 spa->status = 2;
705 
706         return 0;
707 }
708 
709 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
710                 struct nd_intel_smart *smart_data)
711 {
712         if (buf_len < sizeof(*smart))
713                 return -EINVAL;
714         memcpy(smart, smart_data, sizeof(*smart));
715         return 0;
716 }
717 
718 static int nfit_test_cmd_smart_threshold(
719                 struct nd_intel_smart_threshold *out,
720                 unsigned int buf_len,
721                 struct nd_intel_smart_threshold *smart_t)
722 {
723         if (buf_len < sizeof(*smart_t))
724                 return -EINVAL;
725         memcpy(out, smart_t, sizeof(*smart_t));
726         return 0;
727 }
728 
729 static void smart_notify(struct device *bus_dev,
730                 struct device *dimm_dev, struct nd_intel_smart *smart,
731                 struct nd_intel_smart_threshold *thresh)
732 {
733         dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
734                         __func__, thresh->alarm_control, thresh->spares,
735                         smart->spares, thresh->media_temperature,
736                         smart->media_temperature, thresh->ctrl_temperature,
737                         smart->ctrl_temperature);
738         if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
739                                 && smart->spares
740                                 <= thresh->spares)
741                         || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
742                                 && smart->media_temperature
743                                 >= thresh->media_temperature)
744                         || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
745                                 && smart->ctrl_temperature
746                                 >= thresh->ctrl_temperature)
747                         || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
748                         || (smart->shutdown_state != 0)) {
749                 device_lock(bus_dev);
750                 __acpi_nvdimm_notify(dimm_dev, 0x81);
751                 device_unlock(bus_dev);
752         }
753 }
754 
755 static int nfit_test_cmd_smart_set_threshold(
756                 struct nd_intel_smart_set_threshold *in,
757                 unsigned int buf_len,
758                 struct nd_intel_smart_threshold *thresh,
759                 struct nd_intel_smart *smart,
760                 struct device *bus_dev, struct device *dimm_dev)
761 {
762         unsigned int size;
763 
764         size = sizeof(*in) - 4;
765         if (buf_len < size)
766                 return -EINVAL;
767         memcpy(thresh->data, in, size);
768         in->status = 0;
769         smart_notify(bus_dev, dimm_dev, smart, thresh);
770 
771         return 0;
772 }
773 
774 static int nfit_test_cmd_smart_inject(
775                 struct nd_intel_smart_inject *inj,
776                 unsigned int buf_len,
777                 struct nd_intel_smart_threshold *thresh,
778                 struct nd_intel_smart *smart,
779                 struct device *bus_dev, struct device *dimm_dev)
780 {
781         if (buf_len != sizeof(*inj))
782                 return -EINVAL;
783 
784         if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) {
785                 if (inj->mtemp_enable)
786                         smart->media_temperature = inj->media_temperature;
787                 else
788                         smart->media_temperature = smart_def.media_temperature;
789         }
790         if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) {
791                 if (inj->spare_enable)
792                         smart->spares = inj->spares;
793                 else
794                         smart->spares = smart_def.spares;
795         }
796         if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) {
797                 if (inj->fatal_enable)
798                         smart->health = ND_INTEL_SMART_FATAL_HEALTH;
799                 else
800                         smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH;
801         }
802         if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) {
803                 if (inj->unsafe_shutdown_enable) {
804                         smart->shutdown_state = 1;
805                         smart->shutdown_count++;
806                 } else
807                         smart->shutdown_state = 0;
808         }
809         inj->status = 0;
810         smart_notify(bus_dev, dimm_dev, smart, thresh);
811 
812         return 0;
813 }
814 
815 static void uc_error_notify(struct work_struct *work)
816 {
817         struct nfit_test *t = container_of(work, typeof(*t), work);
818 
819         __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
820 }
821 
822 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
823                 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
824 {
825         int rc;
826 
827         if (buf_len != sizeof(*err_inj)) {
828                 rc = -EINVAL;
829                 goto err;
830         }
831 
832         if (err_inj->err_inj_spa_range_length <= 0) {
833                 rc = -EINVAL;
834                 goto err;
835         }
836 
837         rc =  badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
838                         err_inj->err_inj_spa_range_length);
839         if (rc < 0)
840                 goto err;
841 
842         if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
843                 queue_work(nfit_wq, &t->work);
844 
845         err_inj->status = 0;
846         return 0;
847 
848 err:
849         err_inj->status = NFIT_ARS_INJECT_INVALID;
850         return rc;
851 }
852 
853 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
854                 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
855 {
856         int rc;
857 
858         if (buf_len != sizeof(*err_clr)) {
859                 rc = -EINVAL;
860                 goto err;
861         }
862 
863         if (err_clr->err_inj_clr_spa_range_length <= 0) {
864                 rc = -EINVAL;
865                 goto err;
866         }
867 
868         badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
869                         err_clr->err_inj_clr_spa_range_length);
870 
871         err_clr->status = 0;
872         return 0;
873 
874 err:
875         err_clr->status = NFIT_ARS_INJECT_INVALID;
876         return rc;
877 }
878 
879 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
880                 struct nd_cmd_ars_err_inj_stat *err_stat,
881                 unsigned int buf_len)
882 {
883         struct badrange_entry *be;
884         int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
885         int i = 0;
886 
887         err_stat->status = 0;
888         spin_lock(&t->badrange.lock);
889         list_for_each_entry(be, &t->badrange.list, list) {
890                 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
891                 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
892                 i++;
893                 if (i > max)
894                         break;
895         }
896         spin_unlock(&t->badrange.lock);
897         err_stat->inj_err_rec_count = i;
898 
899         return 0;
900 }
901 
902 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
903                 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
904 {
905         struct device *dev = &t->pdev.dev;
906 
907         if (buf_len < sizeof(*nd_cmd))
908                 return -EINVAL;
909 
910         switch (nd_cmd->enable) {
911         case 0:
912                 nd_cmd->status = 0;
913                 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
914                                 __func__);
915                 break;
916         case 1:
917                 nd_cmd->status = 0;
918                 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
919                                 __func__);
920                 break;
921         default:
922                 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
923                 nd_cmd->status = 0x3;
924                 break;
925         }
926 
927 
928         return 0;
929 }
930 
931 static int override_return_code(int dimm, unsigned int func, int rc)
932 {
933         if ((1 << func) & dimm_fail_cmd_flags[dimm]) {
934                 if (dimm_fail_cmd_code[dimm])
935                         return dimm_fail_cmd_code[dimm];
936                 return -EIO;
937         }
938         return rc;
939 }
940 
941 static int nd_intel_test_cmd_security_status(struct nfit_test *t,
942                 struct nd_intel_get_security_state *nd_cmd,
943                 unsigned int buf_len, int dimm)
944 {
945         struct device *dev = &t->pdev.dev;
946         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
947 
948         nd_cmd->status = 0;
949         nd_cmd->state = sec->state;
950         nd_cmd->extended_state = sec->ext_state;
951         dev_dbg(dev, "security state (%#x) returned\n", nd_cmd->state);
952 
953         return 0;
954 }
955 
956 static int nd_intel_test_cmd_unlock_unit(struct nfit_test *t,
957                 struct nd_intel_unlock_unit *nd_cmd,
958                 unsigned int buf_len, int dimm)
959 {
960         struct device *dev = &t->pdev.dev;
961         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
962 
963         if (!(sec->state & ND_INTEL_SEC_STATE_LOCKED) ||
964                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
965                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
966                 dev_dbg(dev, "unlock unit: invalid state: %#x\n",
967                                 sec->state);
968         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
969                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
970                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
971                 dev_dbg(dev, "unlock unit: invalid passphrase\n");
972         } else {
973                 nd_cmd->status = 0;
974                 sec->state = ND_INTEL_SEC_STATE_ENABLED;
975                 dev_dbg(dev, "Unit unlocked\n");
976         }
977 
978         dev_dbg(dev, "unlocking status returned: %#x\n", nd_cmd->status);
979         return 0;
980 }
981 
982 static int nd_intel_test_cmd_set_pass(struct nfit_test *t,
983                 struct nd_intel_set_passphrase *nd_cmd,
984                 unsigned int buf_len, int dimm)
985 {
986         struct device *dev = &t->pdev.dev;
987         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
988 
989         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
990                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
991                 dev_dbg(dev, "set passphrase: wrong security state\n");
992         } else if (memcmp(nd_cmd->old_pass, sec->passphrase,
993                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
994                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
995                 dev_dbg(dev, "set passphrase: wrong passphrase\n");
996         } else {
997                 memcpy(sec->passphrase, nd_cmd->new_pass,
998                                 ND_INTEL_PASSPHRASE_SIZE);
999                 sec->state |= ND_INTEL_SEC_STATE_ENABLED;
1000                 nd_cmd->status = 0;
1001                 dev_dbg(dev, "passphrase updated\n");
1002         }
1003 
1004         return 0;
1005 }
1006 
1007 static int nd_intel_test_cmd_freeze_lock(struct nfit_test *t,
1008                 struct nd_intel_freeze_lock *nd_cmd,
1009                 unsigned int buf_len, int dimm)
1010 {
1011         struct device *dev = &t->pdev.dev;
1012         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1013 
1014         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)) {
1015                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1016                 dev_dbg(dev, "freeze lock: wrong security state\n");
1017         } else {
1018                 sec->state |= ND_INTEL_SEC_STATE_FROZEN;
1019                 nd_cmd->status = 0;
1020                 dev_dbg(dev, "security frozen\n");
1021         }
1022 
1023         return 0;
1024 }
1025 
1026 static int nd_intel_test_cmd_disable_pass(struct nfit_test *t,
1027                 struct nd_intel_disable_passphrase *nd_cmd,
1028                 unsigned int buf_len, int dimm)
1029 {
1030         struct device *dev = &t->pdev.dev;
1031         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1032 
1033         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) ||
1034                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
1035                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1036                 dev_dbg(dev, "disable passphrase: wrong security state\n");
1037         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1038                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1039                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1040                 dev_dbg(dev, "disable passphrase: wrong passphrase\n");
1041         } else {
1042                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1043                 sec->state = 0;
1044                 dev_dbg(dev, "disable passphrase: done\n");
1045         }
1046 
1047         return 0;
1048 }
1049 
1050 static int nd_intel_test_cmd_secure_erase(struct nfit_test *t,
1051                 struct nd_intel_secure_erase *nd_cmd,
1052                 unsigned int buf_len, int dimm)
1053 {
1054         struct device *dev = &t->pdev.dev;
1055         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1056 
1057         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
1058                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1059                 dev_dbg(dev, "secure erase: wrong security state\n");
1060         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1061                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1062                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1063                 dev_dbg(dev, "secure erase: wrong passphrase\n");
1064         } else {
1065                 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)
1066                                 && (memcmp(nd_cmd->passphrase, zero_key,
1067                                         ND_INTEL_PASSPHRASE_SIZE) != 0)) {
1068                         dev_dbg(dev, "invalid zero key\n");
1069                         return 0;
1070                 }
1071                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1072                 memset(sec->master_passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1073                 sec->state = 0;
1074                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1075                 dev_dbg(dev, "secure erase: done\n");
1076         }
1077 
1078         return 0;
1079 }
1080 
1081 static int nd_intel_test_cmd_overwrite(struct nfit_test *t,
1082                 struct nd_intel_overwrite *nd_cmd,
1083                 unsigned int buf_len, int dimm)
1084 {
1085         struct device *dev = &t->pdev.dev;
1086         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1087 
1088         if ((sec->state & ND_INTEL_SEC_STATE_ENABLED) &&
1089                         memcmp(nd_cmd->passphrase, sec->passphrase,
1090                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1091                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1092                 dev_dbg(dev, "overwrite: wrong passphrase\n");
1093                 return 0;
1094         }
1095 
1096         sec->old_state = sec->state;
1097         sec->state = ND_INTEL_SEC_STATE_OVERWRITE;
1098         dev_dbg(dev, "overwrite progressing.\n");
1099         sec->overwrite_end_time = get_jiffies_64() + 5 * HZ;
1100 
1101         return 0;
1102 }
1103 
1104 static int nd_intel_test_cmd_query_overwrite(struct nfit_test *t,
1105                 struct nd_intel_query_overwrite *nd_cmd,
1106                 unsigned int buf_len, int dimm)
1107 {
1108         struct device *dev = &t->pdev.dev;
1109         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1110 
1111         if (!(sec->state & ND_INTEL_SEC_STATE_OVERWRITE)) {
1112                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR;
1113                 return 0;
1114         }
1115 
1116         if (time_is_before_jiffies64(sec->overwrite_end_time)) {
1117                 sec->overwrite_end_time = 0;
1118                 sec->state = sec->old_state;
1119                 sec->old_state = 0;
1120                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1121                 dev_dbg(dev, "overwrite is complete\n");
1122         } else
1123                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_INPROGRESS;
1124         return 0;
1125 }
1126 
1127 static int nd_intel_test_cmd_master_set_pass(struct nfit_test *t,
1128                 struct nd_intel_set_master_passphrase *nd_cmd,
1129                 unsigned int buf_len, int dimm)
1130 {
1131         struct device *dev = &t->pdev.dev;
1132         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1133 
1134         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1135                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1136                 dev_dbg(dev, "master set passphrase: in wrong state\n");
1137         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1138                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1139                 dev_dbg(dev, "master set passphrase: in wrong security state\n");
1140         } else if (memcmp(nd_cmd->old_pass, sec->master_passphrase,
1141                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1142                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1143                 dev_dbg(dev, "master set passphrase: wrong passphrase\n");
1144         } else {
1145                 memcpy(sec->master_passphrase, nd_cmd->new_pass,
1146                                 ND_INTEL_PASSPHRASE_SIZE);
1147                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1148                 dev_dbg(dev, "master passphrase: updated\n");
1149         }
1150 
1151         return 0;
1152 }
1153 
1154 static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t,
1155                 struct nd_intel_master_secure_erase *nd_cmd,
1156                 unsigned int buf_len, int dimm)
1157 {
1158         struct device *dev = &t->pdev.dev;
1159         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1160 
1161         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1162                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1163                 dev_dbg(dev, "master secure erase: in wrong state\n");
1164         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1165                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1166                 dev_dbg(dev, "master secure erase: in wrong security state\n");
1167         } else if (memcmp(nd_cmd->passphrase, sec->master_passphrase,
1168                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1169                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1170                 dev_dbg(dev, "master secure erase: wrong passphrase\n");
1171         } else {
1172                 /* we do not erase master state passphrase ever */
1173                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1174                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1175                 sec->state = 0;
1176                 dev_dbg(dev, "master secure erase: done\n");
1177         }
1178 
1179         return 0;
1180 }
1181 
1182 
1183 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
1184 {
1185         int i;
1186 
1187         /* lookup per-dimm data */
1188         for (i = 0; i < ARRAY_SIZE(handle); i++)
1189                 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
1190                         break;
1191         if (i >= ARRAY_SIZE(handle))
1192                 return -ENXIO;
1193         return i;
1194 }
1195 
1196 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
1197                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1198                 unsigned int buf_len, int *cmd_rc)
1199 {
1200         struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1201         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1202         unsigned int func = cmd;
1203         int i, rc = 0, __cmd_rc;
1204 
1205         if (!cmd_rc)
1206                 cmd_rc = &__cmd_rc;
1207         *cmd_rc = 0;
1208 
1209         if (nvdimm) {
1210                 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
1211                 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
1212 
1213                 if (!nfit_mem)
1214                         return -ENOTTY;
1215 
1216                 if (cmd == ND_CMD_CALL) {
1217                         struct nd_cmd_pkg *call_pkg = buf;
1218 
1219                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1220                         buf = (void *) call_pkg->nd_payload;
1221                         func = call_pkg->nd_command;
1222                         if (call_pkg->nd_family != nfit_mem->family)
1223                                 return -ENOTTY;
1224 
1225                         i = get_dimm(nfit_mem, func);
1226                         if (i < 0)
1227                                 return i;
1228 
1229                         switch (func) {
1230                         case NVDIMM_INTEL_GET_SECURITY_STATE:
1231                                 rc = nd_intel_test_cmd_security_status(t,
1232                                                 buf, buf_len, i);
1233                                 break;
1234                         case NVDIMM_INTEL_UNLOCK_UNIT:
1235                                 rc = nd_intel_test_cmd_unlock_unit(t,
1236                                                 buf, buf_len, i);
1237                                 break;
1238                         case NVDIMM_INTEL_SET_PASSPHRASE:
1239                                 rc = nd_intel_test_cmd_set_pass(t,
1240                                                 buf, buf_len, i);
1241                                 break;
1242                         case NVDIMM_INTEL_DISABLE_PASSPHRASE:
1243                                 rc = nd_intel_test_cmd_disable_pass(t,
1244                                                 buf, buf_len, i);
1245                                 break;
1246                         case NVDIMM_INTEL_FREEZE_LOCK:
1247                                 rc = nd_intel_test_cmd_freeze_lock(t,
1248                                                 buf, buf_len, i);
1249                                 break;
1250                         case NVDIMM_INTEL_SECURE_ERASE:
1251                                 rc = nd_intel_test_cmd_secure_erase(t,
1252                                                 buf, buf_len, i);
1253                                 break;
1254                         case NVDIMM_INTEL_OVERWRITE:
1255                                 rc = nd_intel_test_cmd_overwrite(t,
1256                                                 buf, buf_len, i - t->dcr_idx);
1257                                 break;
1258                         case NVDIMM_INTEL_QUERY_OVERWRITE:
1259                                 rc = nd_intel_test_cmd_query_overwrite(t,
1260                                                 buf, buf_len, i - t->dcr_idx);
1261                                 break;
1262                         case NVDIMM_INTEL_SET_MASTER_PASSPHRASE:
1263                                 rc = nd_intel_test_cmd_master_set_pass(t,
1264                                                 buf, buf_len, i);
1265                                 break;
1266                         case NVDIMM_INTEL_MASTER_SECURE_ERASE:
1267                                 rc = nd_intel_test_cmd_master_secure_erase(t,
1268                                                 buf, buf_len, i);
1269                                 break;
1270                         case ND_INTEL_ENABLE_LSS_STATUS:
1271                                 rc = nd_intel_test_cmd_set_lss_status(t,
1272                                                 buf, buf_len);
1273                                 break;
1274                         case ND_INTEL_FW_GET_INFO:
1275                                 rc = nd_intel_test_get_fw_info(t, buf,
1276                                                 buf_len, i - t->dcr_idx);
1277                                 break;
1278                         case ND_INTEL_FW_START_UPDATE:
1279                                 rc = nd_intel_test_start_update(t, buf,
1280                                                 buf_len, i - t->dcr_idx);
1281                                 break;
1282                         case ND_INTEL_FW_SEND_DATA:
1283                                 rc = nd_intel_test_send_data(t, buf,
1284                                                 buf_len, i - t->dcr_idx);
1285                                 break;
1286                         case ND_INTEL_FW_FINISH_UPDATE:
1287                                 rc = nd_intel_test_finish_fw(t, buf,
1288                                                 buf_len, i - t->dcr_idx);
1289                                 break;
1290                         case ND_INTEL_FW_FINISH_QUERY:
1291                                 rc = nd_intel_test_finish_query(t, buf,
1292                                                 buf_len, i - t->dcr_idx);
1293                                 break;
1294                         case ND_INTEL_SMART:
1295                                 rc = nfit_test_cmd_smart(buf, buf_len,
1296                                                 &t->smart[i - t->dcr_idx]);
1297                                 break;
1298                         case ND_INTEL_SMART_THRESHOLD:
1299                                 rc = nfit_test_cmd_smart_threshold(buf,
1300                                                 buf_len,
1301                                                 &t->smart_threshold[i -
1302                                                         t->dcr_idx]);
1303                                 break;
1304                         case ND_INTEL_SMART_SET_THRESHOLD:
1305                                 rc = nfit_test_cmd_smart_set_threshold(buf,
1306                                                 buf_len,
1307                                                 &t->smart_threshold[i -
1308                                                         t->dcr_idx],
1309                                                 &t->smart[i - t->dcr_idx],
1310                                                 &t->pdev.dev, t->dimm_dev[i]);
1311                                 break;
1312                         case ND_INTEL_SMART_INJECT:
1313                                 rc = nfit_test_cmd_smart_inject(buf,
1314                                                 buf_len,
1315                                                 &t->smart_threshold[i -
1316                                                         t->dcr_idx],
1317                                                 &t->smart[i - t->dcr_idx],
1318                                                 &t->pdev.dev, t->dimm_dev[i]);
1319                                 break;
1320                         default:
1321                                 return -ENOTTY;
1322                         }
1323                         return override_return_code(i, func, rc);
1324                 }
1325 
1326                 if (!test_bit(cmd, &cmd_mask)
1327                                 || !test_bit(func, &nfit_mem->dsm_mask))
1328                         return -ENOTTY;
1329 
1330                 i = get_dimm(nfit_mem, func);
1331                 if (i < 0)
1332                         return i;
1333 
1334                 switch (func) {
1335                 case ND_CMD_GET_CONFIG_SIZE:
1336                         rc = nfit_test_cmd_get_config_size(buf, buf_len);
1337                         break;
1338                 case ND_CMD_GET_CONFIG_DATA:
1339                         rc = nfit_test_cmd_get_config_data(buf, buf_len,
1340                                 t->label[i - t->dcr_idx]);
1341                         break;
1342                 case ND_CMD_SET_CONFIG_DATA:
1343                         rc = nfit_test_cmd_set_config_data(buf, buf_len,
1344                                 t->label[i - t->dcr_idx]);
1345                         break;
1346                 default:
1347                         return -ENOTTY;
1348                 }
1349                 return override_return_code(i, func, rc);
1350         } else {
1351                 struct ars_state *ars_state = &t->ars_state;
1352                 struct nd_cmd_pkg *call_pkg = buf;
1353 
1354                 if (!nd_desc)
1355                         return -ENOTTY;
1356 
1357                 if (cmd == ND_CMD_CALL) {
1358                         func = call_pkg->nd_command;
1359 
1360                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1361                         buf = (void *) call_pkg->nd_payload;
1362 
1363                         switch (func) {
1364                         case NFIT_CMD_TRANSLATE_SPA:
1365                                 rc = nfit_test_cmd_translate_spa(
1366                                         acpi_desc->nvdimm_bus, buf, buf_len);
1367                                 return rc;
1368                         case NFIT_CMD_ARS_INJECT_SET:
1369                                 rc = nfit_test_cmd_ars_error_inject(t, buf,
1370                                         buf_len);
1371                                 return rc;
1372                         case NFIT_CMD_ARS_INJECT_CLEAR:
1373                                 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1374                                         buf_len);
1375                                 return rc;
1376                         case NFIT_CMD_ARS_INJECT_GET:
1377                                 rc = nfit_test_cmd_ars_inject_status(t, buf,
1378                                         buf_len);
1379                                 return rc;
1380                         default:
1381                                 return -ENOTTY;
1382                         }
1383                 }
1384 
1385                 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1386                         return -ENOTTY;
1387 
1388                 switch (func) {
1389                 case ND_CMD_ARS_CAP:
1390                         rc = nfit_test_cmd_ars_cap(buf, buf_len);
1391                         break;
1392                 case ND_CMD_ARS_START:
1393                         rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1394                                         buf_len, cmd_rc);
1395                         break;
1396                 case ND_CMD_ARS_STATUS:
1397                         rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1398                                         cmd_rc);
1399                         break;
1400                 case ND_CMD_CLEAR_ERROR:
1401                         rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1402                         break;
1403                 default:
1404                         return -ENOTTY;
1405                 }
1406         }
1407 
1408         return rc;
1409 }
1410 
1411 static DEFINE_SPINLOCK(nfit_test_lock);
1412 static struct nfit_test *instances[NUM_NFITS];
1413 
1414 static void release_nfit_res(void *data)
1415 {
1416         struct nfit_test_resource *nfit_res = data;
1417 
1418         spin_lock(&nfit_test_lock);
1419         list_del(&nfit_res->list);
1420         spin_unlock(&nfit_test_lock);
1421 
1422         if (resource_size(&nfit_res->res) >= DIMM_SIZE)
1423                 gen_pool_free(nfit_pool, nfit_res->res.start,
1424                                 resource_size(&nfit_res->res));
1425         vfree(nfit_res->buf);
1426         kfree(nfit_res);
1427 }
1428 
1429 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1430                 void *buf)
1431 {
1432         struct device *dev = &t->pdev.dev;
1433         struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1434                         GFP_KERNEL);
1435         int rc;
1436 
1437         if (!buf || !nfit_res || !*dma)
1438                 goto err;
1439         rc = devm_add_action(dev, release_nfit_res, nfit_res);
1440         if (rc)
1441                 goto err;
1442         INIT_LIST_HEAD(&nfit_res->list);
1443         memset(buf, 0, size);
1444         nfit_res->dev = dev;
1445         nfit_res->buf = buf;
1446         nfit_res->res.start = *dma;
1447         nfit_res->res.end = *dma + size - 1;
1448         nfit_res->res.name = "NFIT";
1449         spin_lock_init(&nfit_res->lock);
1450         INIT_LIST_HEAD(&nfit_res->requests);
1451         spin_lock(&nfit_test_lock);
1452         list_add(&nfit_res->list, &t->resources);
1453         spin_unlock(&nfit_test_lock);
1454 
1455         return nfit_res->buf;
1456  err:
1457         if (*dma && size >= DIMM_SIZE)
1458                 gen_pool_free(nfit_pool, *dma, size);
1459         if (buf)
1460                 vfree(buf);
1461         kfree(nfit_res);
1462         return NULL;
1463 }
1464 
1465 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1466 {
1467         struct genpool_data_align data = {
1468                 .align = SZ_128M,
1469         };
1470         void *buf = vmalloc(size);
1471 
1472         if (size >= DIMM_SIZE)
1473                 *dma = gen_pool_alloc_algo(nfit_pool, size,
1474                                 gen_pool_first_fit_align, &data);
1475         else
1476                 *dma = (unsigned long) buf;
1477         return __test_alloc(t, size, dma, buf);
1478 }
1479 
1480 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1481 {
1482         int i;
1483 
1484         for (i = 0; i < ARRAY_SIZE(instances); i++) {
1485                 struct nfit_test_resource *n, *nfit_res = NULL;
1486                 struct nfit_test *t = instances[i];
1487 
1488                 if (!t)
1489                         continue;
1490                 spin_lock(&nfit_test_lock);
1491                 list_for_each_entry(n, &t->resources, list) {
1492                         if (addr >= n->res.start && (addr < n->res.start
1493                                                 + resource_size(&n->res))) {
1494                                 nfit_res = n;
1495                                 break;
1496                         } else if (addr >= (unsigned long) n->buf
1497                                         && (addr < (unsigned long) n->buf
1498                                                 + resource_size(&n->res))) {
1499                                 nfit_res = n;
1500                                 break;
1501                         }
1502                 }
1503                 spin_unlock(&nfit_test_lock);
1504                 if (nfit_res)
1505                         return nfit_res;
1506         }
1507 
1508         return NULL;
1509 }
1510 
1511 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1512 {
1513         /* for testing, only store up to n records that fit within 4k */
1514         ars_state->ars_status = devm_kzalloc(dev,
1515                         sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1516         if (!ars_state->ars_status)
1517                 return -ENOMEM;
1518         spin_lock_init(&ars_state->lock);
1519         return 0;
1520 }
1521 
1522 static void put_dimms(void *data)
1523 {
1524         struct nfit_test *t = data;
1525         int i;
1526 
1527         for (i = 0; i < t->num_dcr; i++)
1528                 if (t->dimm_dev[i])
1529                         device_unregister(t->dimm_dev[i]);
1530 }
1531 
1532 static struct class *nfit_test_dimm;
1533 
1534 static int dimm_name_to_id(struct device *dev)
1535 {
1536         int dimm;
1537 
1538         if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1539                 return -ENXIO;
1540         return dimm;
1541 }
1542 
1543 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1544                 char *buf)
1545 {
1546         int dimm = dimm_name_to_id(dev);
1547 
1548         if (dimm < 0)
1549                 return dimm;
1550 
1551         return sprintf(buf, "%#x\n", handle[dimm]);
1552 }
1553 DEVICE_ATTR_RO(handle);
1554 
1555 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1556                 char *buf)
1557 {
1558         int dimm = dimm_name_to_id(dev);
1559 
1560         if (dimm < 0)
1561                 return dimm;
1562 
1563         return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1564 }
1565 
1566 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1567                 const char *buf, size_t size)
1568 {
1569         int dimm = dimm_name_to_id(dev);
1570         unsigned long val;
1571         ssize_t rc;
1572 
1573         if (dimm < 0)
1574                 return dimm;
1575 
1576         rc = kstrtol(buf, 0, &val);
1577         if (rc)
1578                 return rc;
1579 
1580         dimm_fail_cmd_flags[dimm] = val;
1581         return size;
1582 }
1583 static DEVICE_ATTR_RW(fail_cmd);
1584 
1585 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1586                 char *buf)
1587 {
1588         int dimm = dimm_name_to_id(dev);
1589 
1590         if (dimm < 0)
1591                 return dimm;
1592 
1593         return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1594 }
1595 
1596 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1597                 const char *buf, size_t size)
1598 {
1599         int dimm = dimm_name_to_id(dev);
1600         unsigned long val;
1601         ssize_t rc;
1602 
1603         if (dimm < 0)
1604                 return dimm;
1605 
1606         rc = kstrtol(buf, 0, &val);
1607         if (rc)
1608                 return rc;
1609 
1610         dimm_fail_cmd_code[dimm] = val;
1611         return size;
1612 }
1613 static DEVICE_ATTR_RW(fail_cmd_code);
1614 
1615 static ssize_t lock_dimm_store(struct device *dev,
1616                 struct device_attribute *attr, const char *buf, size_t size)
1617 {
1618         int dimm = dimm_name_to_id(dev);
1619         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1620 
1621         sec->state = ND_INTEL_SEC_STATE_ENABLED | ND_INTEL_SEC_STATE_LOCKED;
1622         return size;
1623 }
1624 static DEVICE_ATTR_WO(lock_dimm);
1625 
1626 static struct attribute *nfit_test_dimm_attributes[] = {
1627         &dev_attr_fail_cmd.attr,
1628         &dev_attr_fail_cmd_code.attr,
1629         &dev_attr_handle.attr,
1630         &dev_attr_lock_dimm.attr,
1631         NULL,
1632 };
1633 
1634 static struct attribute_group nfit_test_dimm_attribute_group = {
1635         .attrs = nfit_test_dimm_attributes,
1636 };
1637 
1638 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1639         &nfit_test_dimm_attribute_group,
1640         NULL,
1641 };
1642 
1643 static int nfit_test_dimm_init(struct nfit_test *t)
1644 {
1645         int i;
1646 
1647         if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1648                 return -ENOMEM;
1649         for (i = 0; i < t->num_dcr; i++) {
1650                 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1651                                 &t->pdev.dev, 0, NULL,
1652                                 nfit_test_dimm_attribute_groups,
1653                                 "test_dimm%d", i + t->dcr_idx);
1654                 if (!t->dimm_dev[i])
1655                         return -ENOMEM;
1656         }
1657         return 0;
1658 }
1659 
1660 static void security_init(struct nfit_test *t)
1661 {
1662         int i;
1663 
1664         for (i = 0; i < t->num_dcr; i++) {
1665                 struct nfit_test_sec *sec = &dimm_sec_info[i];
1666 
1667                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1668         }
1669 }
1670 
1671 static void smart_init(struct nfit_test *t)
1672 {
1673         int i;
1674         const struct nd_intel_smart_threshold smart_t_data = {
1675                 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1676                         | ND_INTEL_SMART_TEMP_TRIP,
1677                 .media_temperature = 40 * 16,
1678                 .ctrl_temperature = 30 * 16,
1679                 .spares = 5,
1680         };
1681 
1682         for (i = 0; i < t->num_dcr; i++) {
1683                 memcpy(&t->smart[i], &smart_def, sizeof(smart_def));
1684                 memcpy(&t->smart_threshold[i], &smart_t_data,
1685                                 sizeof(smart_t_data));
1686         }
1687 }
1688 
1689 static int nfit_test0_alloc(struct nfit_test *t)
1690 {
1691         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
1692                         + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1693                         + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1694                         + offsetof(struct acpi_nfit_control_region,
1695                                         window_size) * NUM_DCR
1696                         + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1697                         + (sizeof(struct acpi_nfit_flush_address)
1698                                         + sizeof(u64) * NUM_HINTS) * NUM_DCR
1699                         + sizeof(struct acpi_nfit_capabilities);
1700         int i;
1701 
1702         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1703         if (!t->nfit_buf)
1704                 return -ENOMEM;
1705         t->nfit_size = nfit_size;
1706 
1707         t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1708         if (!t->spa_set[0])
1709                 return -ENOMEM;
1710 
1711         t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1712         if (!t->spa_set[1])
1713                 return -ENOMEM;
1714 
1715         t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1716         if (!t->spa_set[2])
1717                 return -ENOMEM;
1718 
1719         for (i = 0; i < t->num_dcr; i++) {
1720                 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1721                 if (!t->dimm[i])
1722                         return -ENOMEM;
1723 
1724                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1725                 if (!t->label[i])
1726                         return -ENOMEM;
1727                 sprintf(t->label[i], "label%d", i);
1728 
1729                 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1730                                         sizeof(u64) * NUM_HINTS),
1731                                 &t->flush_dma[i]);
1732                 if (!t->flush[i])
1733                         return -ENOMEM;
1734         }
1735 
1736         for (i = 0; i < t->num_dcr; i++) {
1737                 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1738                 if (!t->dcr[i])
1739                         return -ENOMEM;
1740         }
1741 
1742         t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1743         if (!t->_fit)
1744                 return -ENOMEM;
1745 
1746         if (nfit_test_dimm_init(t))
1747                 return -ENOMEM;
1748         smart_init(t);
1749         security_init(t);
1750         return ars_state_init(&t->pdev.dev, &t->ars_state);
1751 }
1752 
1753 static int nfit_test1_alloc(struct nfit_test *t)
1754 {
1755         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
1756                 + sizeof(struct acpi_nfit_memory_map) * 2
1757                 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1758         int i;
1759 
1760         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1761         if (!t->nfit_buf)
1762                 return -ENOMEM;
1763         t->nfit_size = nfit_size;
1764 
1765         t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1766         if (!t->spa_set[0])
1767                 return -ENOMEM;
1768 
1769         for (i = 0; i < t->num_dcr; i++) {
1770                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1771                 if (!t->label[i])
1772                         return -ENOMEM;
1773                 sprintf(t->label[i], "label%d", i);
1774         }
1775 
1776         t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1777         if (!t->spa_set[1])
1778                 return -ENOMEM;
1779 
1780         if (nfit_test_dimm_init(t))
1781                 return -ENOMEM;
1782         smart_init(t);
1783         return ars_state_init(&t->pdev.dev, &t->ars_state);
1784 }
1785 
1786 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1787 {
1788         dcr->vendor_id = 0xabcd;
1789         dcr->device_id = 0;
1790         dcr->revision_id = 1;
1791         dcr->valid_fields = 1;
1792         dcr->manufacturing_location = 0xa;
1793         dcr->manufacturing_date = cpu_to_be16(2016);
1794 }
1795 
1796 static void nfit_test0_setup(struct nfit_test *t)
1797 {
1798         const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1799                 + (sizeof(u64) * NUM_HINTS);
1800         struct acpi_nfit_desc *acpi_desc;
1801         struct acpi_nfit_memory_map *memdev;
1802         void *nfit_buf = t->nfit_buf;
1803         struct acpi_nfit_system_address *spa;
1804         struct acpi_nfit_control_region *dcr;
1805         struct acpi_nfit_data_region *bdw;
1806         struct acpi_nfit_flush_address *flush;
1807         struct acpi_nfit_capabilities *pcap;
1808         unsigned int offset = 0, i;
1809 
1810         /*
1811          * spa0 (interleave first half of dimm0 and dimm1, note storage
1812          * does not actually alias the related block-data-window
1813          * regions)
1814          */
1815         spa = nfit_buf;
1816         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1817         spa->header.length = sizeof(*spa);
1818         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1819         spa->range_index = 0+1;
1820         spa->address = t->spa_set_dma[0];
1821         spa->length = SPA0_SIZE;
1822         offset += spa->header.length;
1823 
1824         /*
1825          * spa1 (interleave last half of the 4 DIMMS, note storage
1826          * does not actually alias the related block-data-window
1827          * regions)
1828          */
1829         spa = nfit_buf + offset;
1830         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1831         spa->header.length = sizeof(*spa);
1832         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1833         spa->range_index = 1+1;
1834         spa->address = t->spa_set_dma[1];
1835         spa->length = SPA1_SIZE;
1836         offset += spa->header.length;
1837 
1838         /* spa2 (dcr0) dimm0 */
1839         spa = nfit_buf + offset;
1840         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1841         spa->header.length = sizeof(*spa);
1842         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1843         spa->range_index = 2+1;
1844         spa->address = t->dcr_dma[0];
1845         spa->length = DCR_SIZE;
1846         offset += spa->header.length;
1847 
1848         /* spa3 (dcr1) dimm1 */
1849         spa = nfit_buf + offset;
1850         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1851         spa->header.length = sizeof(*spa);
1852         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1853         spa->range_index = 3+1;
1854         spa->address = t->dcr_dma[1];
1855         spa->length = DCR_SIZE;
1856         offset += spa->header.length;
1857 
1858         /* spa4 (dcr2) dimm2 */
1859         spa = nfit_buf + offset;
1860         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1861         spa->header.length = sizeof(*spa);
1862         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1863         spa->range_index = 4+1;
1864         spa->address = t->dcr_dma[2];
1865         spa->length = DCR_SIZE;
1866         offset += spa->header.length;
1867 
1868         /* spa5 (dcr3) dimm3 */
1869         spa = nfit_buf + offset;
1870         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1871         spa->header.length = sizeof(*spa);
1872         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1873         spa->range_index = 5+1;
1874         spa->address = t->dcr_dma[3];
1875         spa->length = DCR_SIZE;
1876         offset += spa->header.length;
1877 
1878         /* spa6 (bdw for dcr0) dimm0 */
1879         spa = nfit_buf + offset;
1880         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1881         spa->header.length = sizeof(*spa);
1882         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1883         spa->range_index = 6+1;
1884         spa->address = t->dimm_dma[0];
1885         spa->length = DIMM_SIZE;
1886         offset += spa->header.length;
1887 
1888         /* spa7 (bdw for dcr1) dimm1 */
1889         spa = nfit_buf + offset;
1890         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1891         spa->header.length = sizeof(*spa);
1892         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1893         spa->range_index = 7+1;
1894         spa->address = t->dimm_dma[1];
1895         spa->length = DIMM_SIZE;
1896         offset += spa->header.length;
1897 
1898         /* spa8 (bdw for dcr2) dimm2 */
1899         spa = nfit_buf + offset;
1900         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1901         spa->header.length = sizeof(*spa);
1902         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1903         spa->range_index = 8+1;
1904         spa->address = t->dimm_dma[2];
1905         spa->length = DIMM_SIZE;
1906         offset += spa->header.length;
1907 
1908         /* spa9 (bdw for dcr3) dimm3 */
1909         spa = nfit_buf + offset;
1910         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1911         spa->header.length = sizeof(*spa);
1912         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1913         spa->range_index = 9+1;
1914         spa->address = t->dimm_dma[3];
1915         spa->length = DIMM_SIZE;
1916         offset += spa->header.length;
1917 
1918         /* mem-region0 (spa0, dimm0) */
1919         memdev = nfit_buf + offset;
1920         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1921         memdev->header.length = sizeof(*memdev);
1922         memdev->device_handle = handle[0];
1923         memdev->physical_id = 0;
1924         memdev->region_id = 0;
1925         memdev->range_index = 0+1;
1926         memdev->region_index = 4+1;
1927         memdev->region_size = SPA0_SIZE/2;
1928         memdev->region_offset = 1;
1929         memdev->address = 0;
1930         memdev->interleave_index = 0;
1931         memdev->interleave_ways = 2;
1932         offset += memdev->header.length;
1933 
1934         /* mem-region1 (spa0, dimm1) */
1935         memdev = nfit_buf + offset;
1936         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1937         memdev->header.length = sizeof(*memdev);
1938         memdev->device_handle = handle[1];
1939         memdev->physical_id = 1;
1940         memdev->region_id = 0;
1941         memdev->range_index = 0+1;
1942         memdev->region_index = 5+1;
1943         memdev->region_size = SPA0_SIZE/2;
1944         memdev->region_offset = (1 << 8);
1945         memdev->address = 0;
1946         memdev->interleave_index = 0;
1947         memdev->interleave_ways = 2;
1948         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1949         offset += memdev->header.length;
1950 
1951         /* mem-region2 (spa1, dimm0) */
1952         memdev = nfit_buf + offset;
1953         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1954         memdev->header.length = sizeof(*memdev);
1955         memdev->device_handle = handle[0];
1956         memdev->physical_id = 0;
1957         memdev->region_id = 1;
1958         memdev->range_index = 1+1;
1959         memdev->region_index = 4+1;
1960         memdev->region_size = SPA1_SIZE/4;
1961         memdev->region_offset = (1 << 16);
1962         memdev->address = SPA0_SIZE/2;
1963         memdev->interleave_index = 0;
1964         memdev->interleave_ways = 4;
1965         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1966         offset += memdev->header.length;
1967 
1968         /* mem-region3 (spa1, dimm1) */
1969         memdev = nfit_buf + offset;
1970         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1971         memdev->header.length = sizeof(*memdev);
1972         memdev->device_handle = handle[1];
1973         memdev->physical_id = 1;
1974         memdev->region_id = 1;
1975         memdev->range_index = 1+1;
1976         memdev->region_index = 5+1;
1977         memdev->region_size = SPA1_SIZE/4;
1978         memdev->region_offset = (1 << 24);
1979         memdev->address = SPA0_SIZE/2;
1980         memdev->interleave_index = 0;
1981         memdev->interleave_ways = 4;
1982         offset += memdev->header.length;
1983 
1984         /* mem-region4 (spa1, dimm2) */
1985         memdev = nfit_buf + offset;
1986         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1987         memdev->header.length = sizeof(*memdev);
1988         memdev->device_handle = handle[2];
1989         memdev->physical_id = 2;
1990         memdev->region_id = 0;
1991         memdev->range_index = 1+1;
1992         memdev->region_index = 6+1;
1993         memdev->region_size = SPA1_SIZE/4;
1994         memdev->region_offset = (1ULL << 32);
1995         memdev->address = SPA0_SIZE/2;
1996         memdev->interleave_index = 0;
1997         memdev->interleave_ways = 4;
1998         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1999         offset += memdev->header.length;
2000 
2001         /* mem-region5 (spa1, dimm3) */
2002         memdev = nfit_buf + offset;
2003         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2004         memdev->header.length = sizeof(*memdev);
2005         memdev->device_handle = handle[3];
2006         memdev->physical_id = 3;
2007         memdev->region_id = 0;
2008         memdev->range_index = 1+1;
2009         memdev->region_index = 7+1;
2010         memdev->region_size = SPA1_SIZE/4;
2011         memdev->region_offset = (1ULL << 40);
2012         memdev->address = SPA0_SIZE/2;
2013         memdev->interleave_index = 0;
2014         memdev->interleave_ways = 4;
2015         offset += memdev->header.length;
2016 
2017         /* mem-region6 (spa/dcr0, dimm0) */
2018         memdev = nfit_buf + offset;
2019         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2020         memdev->header.length = sizeof(*memdev);
2021         memdev->device_handle = handle[0];
2022         memdev->physical_id = 0;
2023         memdev->region_id = 0;
2024         memdev->range_index = 2+1;
2025         memdev->region_index = 0+1;
2026         memdev->region_size = 0;
2027         memdev->region_offset = 0;
2028         memdev->address = 0;
2029         memdev->interleave_index = 0;
2030         memdev->interleave_ways = 1;
2031         offset += memdev->header.length;
2032 
2033         /* mem-region7 (spa/dcr1, dimm1) */
2034         memdev = nfit_buf + offset;
2035         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2036         memdev->header.length = sizeof(*memdev);
2037         memdev->device_handle = handle[1];
2038         memdev->physical_id = 1;
2039         memdev->region_id = 0;
2040         memdev->range_index = 3+1;
2041         memdev->region_index = 1+1;
2042         memdev->region_size = 0;
2043         memdev->region_offset = 0;
2044         memdev->address = 0;
2045         memdev->interleave_index = 0;
2046         memdev->interleave_ways = 1;
2047         offset += memdev->header.length;
2048 
2049         /* mem-region8 (spa/dcr2, dimm2) */
2050         memdev = nfit_buf + offset;
2051         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2052         memdev->header.length = sizeof(*memdev);
2053         memdev->device_handle = handle[2];
2054         memdev->physical_id = 2;
2055         memdev->region_id = 0;
2056         memdev->range_index = 4+1;
2057         memdev->region_index = 2+1;
2058         memdev->region_size = 0;
2059         memdev->region_offset = 0;
2060         memdev->address = 0;
2061         memdev->interleave_index = 0;
2062         memdev->interleave_ways = 1;
2063         offset += memdev->header.length;
2064 
2065         /* mem-region9 (spa/dcr3, dimm3) */
2066         memdev = nfit_buf + offset;
2067         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2068         memdev->header.length = sizeof(*memdev);
2069         memdev->device_handle = handle[3];
2070         memdev->physical_id = 3;
2071         memdev->region_id = 0;
2072         memdev->range_index = 5+1;
2073         memdev->region_index = 3+1;
2074         memdev->region_size = 0;
2075         memdev->region_offset = 0;
2076         memdev->address = 0;
2077         memdev->interleave_index = 0;
2078         memdev->interleave_ways = 1;
2079         offset += memdev->header.length;
2080 
2081         /* mem-region10 (spa/bdw0, dimm0) */
2082         memdev = nfit_buf + offset;
2083         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2084         memdev->header.length = sizeof(*memdev);
2085         memdev->device_handle = handle[0];
2086         memdev->physical_id = 0;
2087         memdev->region_id = 0;
2088         memdev->range_index = 6+1;
2089         memdev->region_index = 0+1;
2090         memdev->region_size = 0;
2091         memdev->region_offset = 0;
2092         memdev->address = 0;
2093         memdev->interleave_index = 0;
2094         memdev->interleave_ways = 1;
2095         offset += memdev->header.length;
2096 
2097         /* mem-region11 (spa/bdw1, dimm1) */
2098         memdev = nfit_buf + offset;
2099         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2100         memdev->header.length = sizeof(*memdev);
2101         memdev->device_handle = handle[1];
2102         memdev->physical_id = 1;
2103         memdev->region_id = 0;
2104         memdev->range_index = 7+1;
2105         memdev->region_index = 1+1;
2106         memdev->region_size = 0;
2107         memdev->region_offset = 0;
2108         memdev->address = 0;
2109         memdev->interleave_index = 0;
2110         memdev->interleave_ways = 1;
2111         offset += memdev->header.length;
2112 
2113         /* mem-region12 (spa/bdw2, dimm2) */
2114         memdev = nfit_buf + offset;
2115         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2116         memdev->header.length = sizeof(*memdev);
2117         memdev->device_handle = handle[2];
2118         memdev->physical_id = 2;
2119         memdev->region_id = 0;
2120         memdev->range_index = 8+1;
2121         memdev->region_index = 2+1;
2122         memdev->region_size = 0;
2123         memdev->region_offset = 0;
2124         memdev->address = 0;
2125         memdev->interleave_index = 0;
2126         memdev->interleave_ways = 1;
2127         offset += memdev->header.length;
2128 
2129         /* mem-region13 (spa/dcr3, dimm3) */
2130         memdev = nfit_buf + offset;
2131         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2132         memdev->header.length = sizeof(*memdev);
2133         memdev->device_handle = handle[3];
2134         memdev->physical_id = 3;
2135         memdev->region_id = 0;
2136         memdev->range_index = 9+1;
2137         memdev->region_index = 3+1;
2138         memdev->region_size = 0;
2139         memdev->region_offset = 0;
2140         memdev->address = 0;
2141         memdev->interleave_index = 0;
2142         memdev->interleave_ways = 1;
2143         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2144         offset += memdev->header.length;
2145 
2146         /* dcr-descriptor0: blk */
2147         dcr = nfit_buf + offset;
2148         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2149         dcr->header.length = sizeof(*dcr);
2150         dcr->region_index = 0+1;
2151         dcr_common_init(dcr);
2152         dcr->serial_number = ~handle[0];
2153         dcr->code = NFIT_FIC_BLK;
2154         dcr->windows = 1;
2155         dcr->window_size = DCR_SIZE;
2156         dcr->command_offset = 0;
2157         dcr->command_size = 8;
2158         dcr->status_offset = 8;
2159         dcr->status_size = 4;
2160         offset += dcr->header.length;
2161 
2162         /* dcr-descriptor1: blk */
2163         dcr = nfit_buf + offset;
2164         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2165         dcr->header.length = sizeof(*dcr);
2166         dcr->region_index = 1+1;
2167         dcr_common_init(dcr);
2168         dcr->serial_number = ~handle[1];
2169         dcr->code = NFIT_FIC_BLK;
2170         dcr->windows = 1;
2171         dcr->window_size = DCR_SIZE;
2172         dcr->command_offset = 0;
2173         dcr->command_size = 8;
2174         dcr->status_offset = 8;
2175         dcr->status_size = 4;
2176         offset += dcr->header.length;
2177 
2178         /* dcr-descriptor2: blk */
2179         dcr = nfit_buf + offset;
2180         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2181         dcr->header.length = sizeof(*dcr);
2182         dcr->region_index = 2+1;
2183         dcr_common_init(dcr);
2184         dcr->serial_number = ~handle[2];
2185         dcr->code = NFIT_FIC_BLK;
2186         dcr->windows = 1;
2187         dcr->window_size = DCR_SIZE;
2188         dcr->command_offset = 0;
2189         dcr->command_size = 8;
2190         dcr->status_offset = 8;
2191         dcr->status_size = 4;
2192         offset += dcr->header.length;
2193 
2194         /* dcr-descriptor3: blk */
2195         dcr = nfit_buf + offset;
2196         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2197         dcr->header.length = sizeof(*dcr);
2198         dcr->region_index = 3+1;
2199         dcr_common_init(dcr);
2200         dcr->serial_number = ~handle[3];
2201         dcr->code = NFIT_FIC_BLK;
2202         dcr->windows = 1;
2203         dcr->window_size = DCR_SIZE;
2204         dcr->command_offset = 0;
2205         dcr->command_size = 8;
2206         dcr->status_offset = 8;
2207         dcr->status_size = 4;
2208         offset += dcr->header.length;
2209 
2210         /* dcr-descriptor0: pmem */
2211         dcr = nfit_buf + offset;
2212         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2213         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2214                         window_size);
2215         dcr->region_index = 4+1;
2216         dcr_common_init(dcr);
2217         dcr->serial_number = ~handle[0];
2218         dcr->code = NFIT_FIC_BYTEN;
2219         dcr->windows = 0;
2220         offset += dcr->header.length;
2221 
2222         /* dcr-descriptor1: pmem */
2223         dcr = nfit_buf + offset;
2224         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2225         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2226                         window_size);
2227         dcr->region_index = 5+1;
2228         dcr_common_init(dcr);
2229         dcr->serial_number = ~handle[1];
2230         dcr->code = NFIT_FIC_BYTEN;
2231         dcr->windows = 0;
2232         offset += dcr->header.length;
2233 
2234         /* dcr-descriptor2: pmem */
2235         dcr = nfit_buf + offset;
2236         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2237         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2238                         window_size);
2239         dcr->region_index = 6+1;
2240         dcr_common_init(dcr);
2241         dcr->serial_number = ~handle[2];
2242         dcr->code = NFIT_FIC_BYTEN;
2243         dcr->windows = 0;
2244         offset += dcr->header.length;
2245 
2246         /* dcr-descriptor3: pmem */
2247         dcr = nfit_buf + offset;
2248         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2249         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2250                         window_size);
2251         dcr->region_index = 7+1;
2252         dcr_common_init(dcr);
2253         dcr->serial_number = ~handle[3];
2254         dcr->code = NFIT_FIC_BYTEN;
2255         dcr->windows = 0;
2256         offset += dcr->header.length;
2257 
2258         /* bdw0 (spa/dcr0, dimm0) */
2259         bdw = nfit_buf + offset;
2260         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2261         bdw->header.length = sizeof(*bdw);
2262         bdw->region_index = 0+1;
2263         bdw->windows = 1;
2264         bdw->offset = 0;
2265         bdw->size = BDW_SIZE;
2266         bdw->capacity = DIMM_SIZE;
2267         bdw->start_address = 0;
2268         offset += bdw->header.length;
2269 
2270         /* bdw1 (spa/dcr1, dimm1) */
2271         bdw = nfit_buf + offset;
2272         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2273         bdw->header.length = sizeof(*bdw);
2274         bdw->region_index = 1+1;
2275         bdw->windows = 1;
2276         bdw->offset = 0;
2277         bdw->size = BDW_SIZE;
2278         bdw->capacity = DIMM_SIZE;
2279         bdw->start_address = 0;
2280         offset += bdw->header.length;
2281 
2282         /* bdw2 (spa/dcr2, dimm2) */
2283         bdw = nfit_buf + offset;
2284         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2285         bdw->header.length = sizeof(*bdw);
2286         bdw->region_index = 2+1;
2287         bdw->windows = 1;
2288         bdw->offset = 0;
2289         bdw->size = BDW_SIZE;
2290         bdw->capacity = DIMM_SIZE;
2291         bdw->start_address = 0;
2292         offset += bdw->header.length;
2293 
2294         /* bdw3 (spa/dcr3, dimm3) */
2295         bdw = nfit_buf + offset;
2296         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2297         bdw->header.length = sizeof(*bdw);
2298         bdw->region_index = 3+1;
2299         bdw->windows = 1;
2300         bdw->offset = 0;
2301         bdw->size = BDW_SIZE;
2302         bdw->capacity = DIMM_SIZE;
2303         bdw->start_address = 0;
2304         offset += bdw->header.length;
2305 
2306         /* flush0 (dimm0) */
2307         flush = nfit_buf + offset;
2308         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2309         flush->header.length = flush_hint_size;
2310         flush->device_handle = handle[0];
2311         flush->hint_count = NUM_HINTS;
2312         for (i = 0; i < NUM_HINTS; i++)
2313                 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
2314         offset += flush->header.length;
2315 
2316         /* flush1 (dimm1) */
2317         flush = nfit_buf + offset;
2318         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2319         flush->header.length = flush_hint_size;
2320         flush->device_handle = handle[1];
2321         flush->hint_count = NUM_HINTS;
2322         for (i = 0; i < NUM_HINTS; i++)
2323                 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
2324         offset += flush->header.length;
2325 
2326         /* flush2 (dimm2) */
2327         flush = nfit_buf + offset;
2328         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2329         flush->header.length = flush_hint_size;
2330         flush->device_handle = handle[2];
2331         flush->hint_count = NUM_HINTS;
2332         for (i = 0; i < NUM_HINTS; i++)
2333                 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
2334         offset += flush->header.length;
2335 
2336         /* flush3 (dimm3) */
2337         flush = nfit_buf + offset;
2338         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2339         flush->header.length = flush_hint_size;
2340         flush->device_handle = handle[3];
2341         flush->hint_count = NUM_HINTS;
2342         for (i = 0; i < NUM_HINTS; i++)
2343                 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
2344         offset += flush->header.length;
2345 
2346         /* platform capabilities */
2347         pcap = nfit_buf + offset;
2348         pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
2349         pcap->header.length = sizeof(*pcap);
2350         pcap->highest_capability = 1;
2351         pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
2352         offset += pcap->header.length;
2353 
2354         if (t->setup_hotplug) {
2355                 /* dcr-descriptor4: blk */
2356                 dcr = nfit_buf + offset;
2357                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2358                 dcr->header.length = sizeof(*dcr);
2359                 dcr->region_index = 8+1;
2360                 dcr_common_init(dcr);
2361                 dcr->serial_number = ~handle[4];
2362                 dcr->code = NFIT_FIC_BLK;
2363                 dcr->windows = 1;
2364                 dcr->window_size = DCR_SIZE;
2365                 dcr->command_offset = 0;
2366                 dcr->command_size = 8;
2367                 dcr->status_offset = 8;
2368                 dcr->status_size = 4;
2369                 offset += dcr->header.length;
2370 
2371                 /* dcr-descriptor4: pmem */
2372                 dcr = nfit_buf + offset;
2373                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2374                 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2375                                 window_size);
2376                 dcr->region_index = 9+1;
2377                 dcr_common_init(dcr);
2378                 dcr->serial_number = ~handle[4];
2379                 dcr->code = NFIT_FIC_BYTEN;
2380                 dcr->windows = 0;
2381                 offset += dcr->header.length;
2382 
2383                 /* bdw4 (spa/dcr4, dimm4) */
2384                 bdw = nfit_buf + offset;
2385                 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2386                 bdw->header.length = sizeof(*bdw);
2387                 bdw->region_index = 8+1;
2388                 bdw->windows = 1;
2389                 bdw->offset = 0;
2390                 bdw->size = BDW_SIZE;
2391                 bdw->capacity = DIMM_SIZE;
2392                 bdw->start_address = 0;
2393                 offset += bdw->header.length;
2394 
2395                 /* spa10 (dcr4) dimm4 */
2396                 spa = nfit_buf + offset;
2397                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2398                 spa->header.length = sizeof(*spa);
2399                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2400                 spa->range_index = 10+1;
2401                 spa->address = t->dcr_dma[4];
2402                 spa->length = DCR_SIZE;
2403                 offset += spa->header.length;
2404 
2405                 /*
2406                  * spa11 (single-dimm interleave for hotplug, note storage
2407                  * does not actually alias the related block-data-window
2408                  * regions)
2409                  */
2410                 spa = nfit_buf + offset;
2411                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2412                 spa->header.length = sizeof(*spa);
2413                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2414                 spa->range_index = 11+1;
2415                 spa->address = t->spa_set_dma[2];
2416                 spa->length = SPA0_SIZE;
2417                 offset += spa->header.length;
2418 
2419                 /* spa12 (bdw for dcr4) dimm4 */
2420                 spa = nfit_buf + offset;
2421                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2422                 spa->header.length = sizeof(*spa);
2423                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2424                 spa->range_index = 12+1;
2425                 spa->address = t->dimm_dma[4];
2426                 spa->length = DIMM_SIZE;
2427                 offset += spa->header.length;
2428 
2429                 /* mem-region14 (spa/dcr4, dimm4) */
2430                 memdev = nfit_buf + offset;
2431                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2432                 memdev->header.length = sizeof(*memdev);
2433                 memdev->device_handle = handle[4];
2434                 memdev->physical_id = 4;
2435                 memdev->region_id = 0;
2436                 memdev->range_index = 10+1;
2437                 memdev->region_index = 8+1;
2438                 memdev->region_size = 0;
2439                 memdev->region_offset = 0;
2440                 memdev->address = 0;
2441                 memdev->interleave_index = 0;
2442                 memdev->interleave_ways = 1;
2443                 offset += memdev->header.length;
2444 
2445                 /* mem-region15 (spa11, dimm4) */
2446                 memdev = nfit_buf + offset;
2447                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2448                 memdev->header.length = sizeof(*memdev);
2449                 memdev->device_handle = handle[4];
2450                 memdev->physical_id = 4;
2451                 memdev->region_id = 0;
2452                 memdev->range_index = 11+1;
2453                 memdev->region_index = 9+1;
2454                 memdev->region_size = SPA0_SIZE;
2455                 memdev->region_offset = (1ULL << 48);
2456                 memdev->address = 0;
2457                 memdev->interleave_index = 0;
2458                 memdev->interleave_ways = 1;
2459                 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2460                 offset += memdev->header.length;
2461 
2462                 /* mem-region16 (spa/bdw4, dimm4) */
2463                 memdev = nfit_buf + offset;
2464                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2465                 memdev->header.length = sizeof(*memdev);
2466                 memdev->device_handle = handle[4];
2467                 memdev->physical_id = 4;
2468                 memdev->region_id = 0;
2469                 memdev->range_index = 12+1;
2470                 memdev->region_index = 8+1;
2471                 memdev->region_size = 0;
2472                 memdev->region_offset = 0;
2473                 memdev->address = 0;
2474                 memdev->interleave_index = 0;
2475                 memdev->interleave_ways = 1;
2476                 offset += memdev->header.length;
2477 
2478                 /* flush3 (dimm4) */
2479                 flush = nfit_buf + offset;
2480                 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2481                 flush->header.length = flush_hint_size;
2482                 flush->device_handle = handle[4];
2483                 flush->hint_count = NUM_HINTS;
2484                 for (i = 0; i < NUM_HINTS; i++)
2485                         flush->hint_address[i] = t->flush_dma[4]
2486                                 + i * sizeof(u64);
2487                 offset += flush->header.length;
2488 
2489                 /* sanity check to make sure we've filled the buffer */
2490                 WARN_ON(offset != t->nfit_size);
2491         }
2492 
2493         t->nfit_filled = offset;
2494 
2495         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2496                         SPA0_SIZE);
2497 
2498         acpi_desc = &t->acpi_desc;
2499         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2500         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2501         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2502         set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2503         set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2504         set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2505         set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2506         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2507         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2508         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2509         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2510         set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2511         set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en);
2512         set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en);
2513         set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en);
2514         set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en);
2515         set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2516         set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2517         set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2518         set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2519         set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2520         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2521         set_bit(NVDIMM_INTEL_GET_SECURITY_STATE,
2522                         &acpi_desc->dimm_cmd_force_en);
2523         set_bit(NVDIMM_INTEL_SET_PASSPHRASE, &acpi_desc->dimm_cmd_force_en);
2524         set_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE,
2525                         &acpi_desc->dimm_cmd_force_en);
2526         set_bit(NVDIMM_INTEL_UNLOCK_UNIT, &acpi_desc->dimm_cmd_force_en);
2527         set_bit(NVDIMM_INTEL_FREEZE_LOCK, &acpi_desc->dimm_cmd_force_en);
2528         set_bit(NVDIMM_INTEL_SECURE_ERASE, &acpi_desc->dimm_cmd_force_en);
2529         set_bit(NVDIMM_INTEL_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2530         set_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2531         set_bit(NVDIMM_INTEL_SET_MASTER_PASSPHRASE,
2532                         &acpi_desc->dimm_cmd_force_en);
2533         set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE,
2534                         &acpi_desc->dimm_cmd_force_en);
2535 }
2536 
2537 static void nfit_test1_setup(struct nfit_test *t)
2538 {
2539         size_t offset;
2540         void *nfit_buf = t->nfit_buf;
2541         struct acpi_nfit_memory_map *memdev;
2542         struct acpi_nfit_control_region *dcr;
2543         struct acpi_nfit_system_address *spa;
2544         struct acpi_nfit_desc *acpi_desc;
2545 
2546         offset = 0;
2547         /* spa0 (flat range with no bdw aliasing) */
2548         spa = nfit_buf + offset;
2549         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2550         spa->header.length = sizeof(*spa);
2551         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2552         spa->range_index = 0+1;
2553         spa->address = t->spa_set_dma[0];
2554         spa->length = SPA2_SIZE;
2555         offset += spa->header.length;
2556 
2557         /* virtual cd region */
2558         spa = nfit_buf + offset;
2559         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2560         spa->header.length = sizeof(*spa);
2561         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2562         spa->range_index = 0;
2563         spa->address = t->spa_set_dma[1];
2564         spa->length = SPA_VCD_SIZE;
2565         offset += spa->header.length;
2566 
2567         /* mem-region0 (spa0, dimm0) */
2568         memdev = nfit_buf + offset;
2569         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2570         memdev->header.length = sizeof(*memdev);
2571         memdev->device_handle = handle[5];
2572         memdev->physical_id = 0;
2573         memdev->region_id = 0;
2574         memdev->range_index = 0+1;
2575         memdev->region_index = 0+1;
2576         memdev->region_size = SPA2_SIZE;
2577         memdev->region_offset = 0;
2578         memdev->address = 0;
2579         memdev->interleave_index = 0;
2580         memdev->interleave_ways = 1;
2581         memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2582                 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2583                 | ACPI_NFIT_MEM_NOT_ARMED;
2584         offset += memdev->header.length;
2585 
2586         /* dcr-descriptor0 */
2587         dcr = nfit_buf + offset;
2588         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2589         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2590                         window_size);
2591         dcr->region_index = 0+1;
2592         dcr_common_init(dcr);
2593         dcr->serial_number = ~handle[5];
2594         dcr->code = NFIT_FIC_BYTE;
2595         dcr->windows = 0;
2596         offset += dcr->header.length;
2597 
2598         memdev = nfit_buf + offset;
2599         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2600         memdev->header.length = sizeof(*memdev);
2601         memdev->device_handle = handle[6];
2602         memdev->physical_id = 0;
2603         memdev->region_id = 0;
2604         memdev->range_index = 0;
2605         memdev->region_index = 0+2;
2606         memdev->region_size = SPA2_SIZE;
2607         memdev->region_offset = 0;
2608         memdev->address = 0;
2609         memdev->interleave_index = 0;
2610         memdev->interleave_ways = 1;
2611         memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2612         offset += memdev->header.length;
2613 
2614         /* dcr-descriptor1 */
2615         dcr = nfit_buf + offset;
2616         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2617         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2618                         window_size);
2619         dcr->region_index = 0+2;
2620         dcr_common_init(dcr);
2621         dcr->serial_number = ~handle[6];
2622         dcr->code = NFIT_FIC_BYTE;
2623         dcr->windows = 0;
2624         offset += dcr->header.length;
2625 
2626         /* sanity check to make sure we've filled the buffer */
2627         WARN_ON(offset != t->nfit_size);
2628 
2629         t->nfit_filled = offset;
2630 
2631         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2632                         SPA2_SIZE);
2633 
2634         acpi_desc = &t->acpi_desc;
2635         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2636         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2637         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2638         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2639         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2640         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2641         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2642         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2643 }
2644 
2645 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2646                 void *iobuf, u64 len, int rw)
2647 {
2648         struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2649         struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2650         struct nd_region *nd_region = &ndbr->nd_region;
2651         unsigned int lane;
2652 
2653         lane = nd_region_acquire_lane(nd_region);
2654         if (rw)
2655                 memcpy(mmio->addr.base + dpa, iobuf, len);
2656         else {
2657                 memcpy(iobuf, mmio->addr.base + dpa, len);
2658 
2659                 /* give us some some coverage of the arch_invalidate_pmem() API */
2660                 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2661         }
2662         nd_region_release_lane(nd_region, lane);
2663 
2664         return 0;
2665 }
2666 
2667 static unsigned long nfit_ctl_handle;
2668 
2669 union acpi_object *result;
2670 
2671 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2672                 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2673 {
2674         if (handle != &nfit_ctl_handle)
2675                 return ERR_PTR(-ENXIO);
2676 
2677         return result;
2678 }
2679 
2680 static int setup_result(void *buf, size_t size)
2681 {
2682         result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2683         if (!result)
2684                 return -ENOMEM;
2685         result->package.type = ACPI_TYPE_BUFFER,
2686         result->buffer.pointer = (void *) (result + 1);
2687         result->buffer.length = size;
2688         memcpy(result->buffer.pointer, buf, size);
2689         memset(buf, 0, size);
2690         return 0;
2691 }
2692 
2693 static int nfit_ctl_test(struct device *dev)
2694 {
2695         int rc, cmd_rc;
2696         struct nvdimm *nvdimm;
2697         struct acpi_device *adev;
2698         struct nfit_mem *nfit_mem;
2699         struct nd_ars_record *record;
2700         struct acpi_nfit_desc *acpi_desc;
2701         const u64 test_val = 0x0123456789abcdefULL;
2702         unsigned long mask, cmd_size, offset;
2703         union {
2704                 struct nd_cmd_get_config_size cfg_size;
2705                 struct nd_cmd_clear_error clear_err;
2706                 struct nd_cmd_ars_status ars_stat;
2707                 struct nd_cmd_ars_cap ars_cap;
2708                 char buf[sizeof(struct nd_cmd_ars_status)
2709                         + sizeof(struct nd_ars_record)];
2710         } cmds;
2711 
2712         adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2713         if (!adev)
2714                 return -ENOMEM;
2715         *adev = (struct acpi_device) {
2716                 .handle = &nfit_ctl_handle,
2717                 .dev = {
2718                         .init_name = "test-adev",
2719                 },
2720         };
2721 
2722         acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2723         if (!acpi_desc)
2724                 return -ENOMEM;
2725         *acpi_desc = (struct acpi_nfit_desc) {
2726                 .nd_desc = {
2727                         .cmd_mask = 1UL << ND_CMD_ARS_CAP
2728                                 | 1UL << ND_CMD_ARS_START
2729                                 | 1UL << ND_CMD_ARS_STATUS
2730                                 | 1UL << ND_CMD_CLEAR_ERROR
2731                                 | 1UL << ND_CMD_CALL,
2732                         .module = THIS_MODULE,
2733                         .provider_name = "ACPI.NFIT",
2734                         .ndctl = acpi_nfit_ctl,
2735                         .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2736                                 | 1UL << NFIT_CMD_ARS_INJECT_SET
2737                                 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2738                                 | 1UL << NFIT_CMD_ARS_INJECT_GET,
2739                 },
2740                 .dev = &adev->dev,
2741         };
2742 
2743         nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2744         if (!nfit_mem)
2745                 return -ENOMEM;
2746 
2747         mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2748                 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2749                 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2750                 | 1UL << ND_CMD_VENDOR;
2751         *nfit_mem = (struct nfit_mem) {
2752                 .adev = adev,
2753                 .family = NVDIMM_FAMILY_INTEL,
2754                 .dsm_mask = mask,
2755         };
2756 
2757         nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2758         if (!nvdimm)
2759                 return -ENOMEM;
2760         *nvdimm = (struct nvdimm) {
2761                 .provider_data = nfit_mem,
2762                 .cmd_mask = mask,
2763                 .dev = {
2764                         .init_name = "test-dimm",
2765                 },
2766         };
2767 
2768 
2769         /* basic checkout of a typical 'get config size' command */
2770         cmd_size = sizeof(cmds.cfg_size);
2771         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2772                 .status = 0,
2773                 .config_size = SZ_128K,
2774                 .max_xfer = SZ_4K,
2775         };
2776         rc = setup_result(cmds.buf, cmd_size);
2777         if (rc)
2778                 return rc;
2779         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2780                         cmds.buf, cmd_size, &cmd_rc);
2781 
2782         if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0
2783                         || cmds.cfg_size.config_size != SZ_128K
2784                         || cmds.cfg_size.max_xfer != SZ_4K) {
2785                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2786                                 __func__, __LINE__, rc, cmd_rc);
2787                 return -EIO;
2788         }
2789 
2790 
2791         /* test ars_status with zero output */
2792         cmd_size = offsetof(struct nd_cmd_ars_status, address);
2793         cmds.ars_stat = (struct nd_cmd_ars_status) {
2794                 .out_length = 0,
2795         };
2796         rc = setup_result(cmds.buf, cmd_size);
2797         if (rc)
2798                 return rc;
2799         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2800                         cmds.buf, cmd_size, &cmd_rc);
2801 
2802         if (rc < 0 || cmd_rc) {
2803                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2804                                 __func__, __LINE__, rc, cmd_rc);
2805                 return -EIO;
2806         }
2807 
2808 
2809         /* test ars_cap with benign extended status */
2810         cmd_size = sizeof(cmds.ars_cap);
2811         cmds.ars_cap = (struct nd_cmd_ars_cap) {
2812                 .status = ND_ARS_PERSISTENT << 16,
2813         };
2814         offset = offsetof(struct nd_cmd_ars_cap, status);
2815         rc = setup_result(cmds.buf + offset, cmd_size - offset);
2816         if (rc)
2817                 return rc;
2818         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
2819                         cmds.buf, cmd_size, &cmd_rc);
2820 
2821         if (rc < 0 || cmd_rc) {
2822                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2823                                 __func__, __LINE__, rc, cmd_rc);
2824                 return -EIO;
2825         }
2826 
2827 
2828         /* test ars_status with 'status' trimmed from 'out_length' */
2829         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2830         cmds.ars_stat = (struct nd_cmd_ars_status) {
2831                 .out_length = cmd_size - 4,
2832         };
2833         record = &cmds.ars_stat.records[0];
2834         *record = (struct nd_ars_record) {
2835                 .length = test_val,
2836         };
2837         rc = setup_result(cmds.buf, cmd_size);
2838         if (rc)
2839                 return rc;
2840         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2841                         cmds.buf, cmd_size, &cmd_rc);
2842 
2843         if (rc < 0 || cmd_rc || record->length != test_val) {
2844                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2845                                 __func__, __LINE__, rc, cmd_rc);
2846                 return -EIO;
2847         }
2848 
2849 
2850         /* test ars_status with 'Output (Size)' including 'status' */
2851         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2852         cmds.ars_stat = (struct nd_cmd_ars_status) {
2853                 .out_length = cmd_size,
2854         };
2855         record = &cmds.ars_stat.records[0];
2856         *record = (struct nd_ars_record) {
2857                 .length = test_val,
2858         };
2859         rc = setup_result(cmds.buf, cmd_size);
2860         if (rc)
2861                 return rc;
2862         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2863                         cmds.buf, cmd_size, &cmd_rc);
2864 
2865         if (rc < 0 || cmd_rc || record->length != test_val) {
2866                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2867                                 __func__, __LINE__, rc, cmd_rc);
2868                 return -EIO;
2869         }
2870 
2871 
2872         /* test extended status for get_config_size results in failure */
2873         cmd_size = sizeof(cmds.cfg_size);
2874         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2875                 .status = 1 << 16,
2876         };
2877         rc = setup_result(cmds.buf, cmd_size);
2878         if (rc)
2879                 return rc;
2880         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2881                         cmds.buf, cmd_size, &cmd_rc);
2882 
2883         if (rc < 0 || cmd_rc >= 0) {
2884                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2885                                 __func__, __LINE__, rc, cmd_rc);
2886                 return -EIO;
2887         }
2888 
2889         /* test clear error */
2890         cmd_size = sizeof(cmds.clear_err);
2891         cmds.clear_err = (struct nd_cmd_clear_error) {
2892                 .length = 512,
2893                 .cleared = 512,
2894         };
2895         rc = setup_result(cmds.buf, cmd_size);
2896         if (rc)
2897                 return rc;
2898         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
2899                         cmds.buf, cmd_size, &cmd_rc);
2900         if (rc < 0 || cmd_rc) {
2901                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2902                                 __func__, __LINE__, rc, cmd_rc);
2903                 return -EIO;
2904         }
2905 
2906         return 0;
2907 }
2908 
2909 static int nfit_test_probe(struct platform_device *pdev)
2910 {
2911         struct nvdimm_bus_descriptor *nd_desc;
2912         struct acpi_nfit_desc *acpi_desc;
2913         struct device *dev = &pdev->dev;
2914         struct nfit_test *nfit_test;
2915         struct nfit_mem *nfit_mem;
2916         union acpi_object *obj;
2917         int rc;
2918 
2919         if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
2920                 rc = nfit_ctl_test(&pdev->dev);
2921                 if (rc)
2922                         return rc;
2923         }
2924 
2925         nfit_test = to_nfit_test(&pdev->dev);
2926 
2927         /* common alloc */
2928         if (nfit_test->num_dcr) {
2929                 int num = nfit_test->num_dcr;
2930 
2931                 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
2932                                 GFP_KERNEL);
2933                 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2934                                 GFP_KERNEL);
2935                 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
2936                                 GFP_KERNEL);
2937                 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2938                                 GFP_KERNEL);
2939                 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
2940                                 GFP_KERNEL);
2941                 nfit_test->label_dma = devm_kcalloc(dev, num,
2942                                 sizeof(dma_addr_t), GFP_KERNEL);
2943                 nfit_test->dcr = devm_kcalloc(dev, num,
2944                                 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
2945                 nfit_test->dcr_dma = devm_kcalloc(dev, num,
2946                                 sizeof(dma_addr_t), GFP_KERNEL);
2947                 nfit_test->smart = devm_kcalloc(dev, num,
2948                                 sizeof(struct nd_intel_smart), GFP_KERNEL);
2949                 nfit_test->smart_threshold = devm_kcalloc(dev, num,
2950                                 sizeof(struct nd_intel_smart_threshold),
2951                                 GFP_KERNEL);
2952                 nfit_test->fw = devm_kcalloc(dev, num,
2953                                 sizeof(struct nfit_test_fw), GFP_KERNEL);
2954                 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
2955                                 && nfit_test->label_dma && nfit_test->dcr
2956                                 && nfit_test->dcr_dma && nfit_test->flush
2957                                 && nfit_test->flush_dma
2958                                 && nfit_test->fw)
2959                         /* pass */;
2960                 else
2961                         return -ENOMEM;
2962         }
2963 
2964         if (nfit_test->num_pm) {
2965                 int num = nfit_test->num_pm;
2966 
2967                 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
2968                                 GFP_KERNEL);
2969                 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
2970                                 sizeof(dma_addr_t), GFP_KERNEL);
2971                 if (nfit_test->spa_set && nfit_test->spa_set_dma)
2972                         /* pass */;
2973                 else
2974                         return -ENOMEM;
2975         }
2976 
2977         /* per-nfit specific alloc */
2978         if (nfit_test->alloc(nfit_test))
2979                 return -ENOMEM;
2980 
2981         nfit_test->setup(nfit_test);
2982         acpi_desc = &nfit_test->acpi_desc;
2983         acpi_nfit_desc_init(acpi_desc, &pdev->dev);
2984         acpi_desc->blk_do_io = nfit_test_blk_do_io;
2985         nd_desc = &acpi_desc->nd_desc;
2986         nd_desc->provider_name = NULL;
2987         nd_desc->module = THIS_MODULE;
2988         nd_desc->ndctl = nfit_test_ctl;
2989 
2990         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
2991                         nfit_test->nfit_filled);
2992         if (rc)
2993                 return rc;
2994 
2995         rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
2996         if (rc)
2997                 return rc;
2998 
2999         if (nfit_test->setup != nfit_test0_setup)
3000                 return 0;
3001 
3002         nfit_test->setup_hotplug = 1;
3003         nfit_test->setup(nfit_test);
3004 
3005         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3006         if (!obj)
3007                 return -ENOMEM;
3008         obj->type = ACPI_TYPE_BUFFER;
3009         obj->buffer.length = nfit_test->nfit_size;
3010         obj->buffer.pointer = nfit_test->nfit_buf;
3011         *(nfit_test->_fit) = obj;
3012         __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
3013 
3014         /* associate dimm devices with nfit_mem data for notification testing */
3015         mutex_lock(&acpi_desc->init_mutex);
3016         list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
3017                 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
3018                 int i;
3019 
3020                 for (i = 0; i < ARRAY_SIZE(handle); i++)
3021                         if (nfit_handle == handle[i])
3022                                 dev_set_drvdata(nfit_test->dimm_dev[i],
3023                                                 nfit_mem);
3024         }
3025         mutex_unlock(&acpi_desc->init_mutex);
3026 
3027         return 0;
3028 }
3029 
3030 static int nfit_test_remove(struct platform_device *pdev)
3031 {
3032         return 0;
3033 }
3034 
3035 static void nfit_test_release(struct device *dev)
3036 {
3037         struct nfit_test *nfit_test = to_nfit_test(dev);
3038 
3039         kfree(nfit_test);
3040 }
3041 
3042 static const struct platform_device_id nfit_test_id[] = {
3043         { KBUILD_MODNAME },
3044         { },
3045 };
3046 
3047 static struct platform_driver nfit_test_driver = {
3048         .probe = nfit_test_probe,
3049         .remove = nfit_test_remove,
3050         .driver = {
3051                 .name = KBUILD_MODNAME,
3052         },
3053         .id_table = nfit_test_id,
3054 };
3055 
3056 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE)));
3057 
3058 enum INJECT {
3059         INJECT_NONE,
3060         INJECT_SRC,
3061         INJECT_DST,
3062 };
3063 
3064 static void mcsafe_test_init(char *dst, char *src, size_t size)
3065 {
3066         size_t i;
3067 
3068         memset(dst, 0xff, size);
3069         for (i = 0; i < size; i++)
3070                 src[i] = (char) i;
3071 }
3072 
3073 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src,
3074                 size_t size, unsigned long rem)
3075 {
3076         size_t i;
3077 
3078         for (i = 0; i < size - rem; i++)
3079                 if (dst[i] != (unsigned char) i) {
3080                         pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n",
3081                                         __func__, __LINE__, i, dst[i],
3082                                         (unsigned char) i);
3083                         return false;
3084                 }
3085         for (i = size - rem; i < size; i++)
3086                 if (dst[i] != 0xffU) {
3087                         pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n",
3088                                         __func__, __LINE__, i, dst[i]);
3089                         return false;
3090                 }
3091         return true;
3092 }
3093 
3094 void mcsafe_test(void)
3095 {
3096         char *inject_desc[] = { "none", "source", "destination" };
3097         enum INJECT inj;
3098 
3099         if (IS_ENABLED(CONFIG_MCSAFE_TEST)) {
3100                 pr_info("%s: run...\n", __func__);
3101         } else {
3102                 pr_info("%s: disabled, skip.\n", __func__);
3103                 return;
3104         }
3105 
3106         for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) {
3107                 int i;
3108 
3109                 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]);
3110                 for (i = 0; i < 512; i++) {
3111                         unsigned long expect, rem;
3112                         void *src, *dst;
3113                         bool valid;
3114 
3115                         switch (inj) {
3116                         case INJECT_NONE:
3117                                 mcsafe_inject_src(NULL);
3118                                 mcsafe_inject_dst(NULL);
3119                                 dst = &mcsafe_buf[2048];
3120                                 src = &mcsafe_buf[1024 - i];
3121                                 expect = 0;
3122                                 break;
3123                         case INJECT_SRC:
3124                                 mcsafe_inject_src(&mcsafe_buf[1024]);
3125                                 mcsafe_inject_dst(NULL);
3126                                 dst = &mcsafe_buf[2048];
3127                                 src = &mcsafe_buf[1024 - i];
3128                                 expect = 512 - i;
3129                                 break;
3130                         case INJECT_DST:
3131                                 mcsafe_inject_src(NULL);
3132                                 mcsafe_inject_dst(&mcsafe_buf[2048]);
3133                                 dst = &mcsafe_buf[2048 - i];
3134                                 src = &mcsafe_buf[1024];
3135                                 expect = 512 - i;
3136                                 break;
3137                         }
3138 
3139                         mcsafe_test_init(dst, src, 512);
3140                         rem = __memcpy_mcsafe(dst, src, 512);
3141                         valid = mcsafe_test_validate(dst, src, 512, expect);
3142                         if (rem == expect && valid)
3143                                 continue;
3144                         pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n",
3145                                         __func__,
3146                                         ((unsigned long) dst) & ~PAGE_MASK,
3147                                         ((unsigned long ) src) & ~PAGE_MASK,
3148                                         512, i, rem, valid ? "valid" : "bad",
3149                                         expect);
3150                 }
3151         }
3152 
3153         mcsafe_inject_src(NULL);
3154         mcsafe_inject_dst(NULL);
3155 }
3156 
3157 static __init int nfit_test_init(void)
3158 {
3159         int rc, i;
3160 
3161         pmem_test();
3162         libnvdimm_test();
3163         acpi_nfit_test();
3164         device_dax_test();
3165         mcsafe_test();
3166         dax_pmem_test();
3167         dax_pmem_core_test();
3168         dax_pmem_compat_test();
3169 
3170         nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
3171 
3172         nfit_wq = create_singlethread_workqueue("nfit");
3173         if (!nfit_wq)
3174                 return -ENOMEM;
3175 
3176         nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
3177         if (IS_ERR(nfit_test_dimm)) {
3178                 rc = PTR_ERR(nfit_test_dimm);
3179                 goto err_register;
3180         }
3181 
3182         nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE);
3183         if (!nfit_pool) {
3184                 rc = -ENOMEM;
3185                 goto err_register;
3186         }
3187 
3188         if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) {
3189                 rc = -ENOMEM;
3190                 goto err_register;
3191         }
3192 
3193         for (i = 0; i < NUM_NFITS; i++) {
3194                 struct nfit_test *nfit_test;
3195                 struct platform_device *pdev;
3196 
3197                 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
3198                 if (!nfit_test) {
3199                         rc = -ENOMEM;
3200                         goto err_register;
3201                 }
3202                 INIT_LIST_HEAD(&nfit_test->resources);
3203                 badrange_init(&nfit_test->badrange);
3204                 switch (i) {
3205                 case 0:
3206                         nfit_test->num_pm = NUM_PM;
3207                         nfit_test->dcr_idx = 0;
3208                         nfit_test->num_dcr = NUM_DCR;
3209                         nfit_test->alloc = nfit_test0_alloc;
3210                         nfit_test->setup = nfit_test0_setup;
3211                         break;
3212                 case 1:
3213                         nfit_test->num_pm = 2;
3214                         nfit_test->dcr_idx = NUM_DCR;
3215                         nfit_test->num_dcr = 2;
3216                         nfit_test->alloc = nfit_test1_alloc;
3217                         nfit_test->setup = nfit_test1_setup;
3218                         break;
3219                 default:
3220                         rc = -EINVAL;
3221                         goto err_register;
3222                 }
3223                 pdev = &nfit_test->pdev;
3224                 pdev->name = KBUILD_MODNAME;
3225                 pdev->id = i;
3226                 pdev->dev.release = nfit_test_release;
3227                 rc = platform_device_register(pdev);
3228                 if (rc) {
3229                         put_device(&pdev->dev);
3230                         goto err_register;
3231                 }
3232                 get_device(&pdev->dev);
3233 
3234                 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3235                 if (rc)
3236                         goto err_register;
3237 
3238                 instances[i] = nfit_test;
3239                 INIT_WORK(&nfit_test->work, uc_error_notify);
3240         }
3241 
3242         rc = platform_driver_register(&nfit_test_driver);
3243         if (rc)
3244                 goto err_register;
3245         return 0;
3246 
3247  err_register:
3248         if (nfit_pool)
3249                 gen_pool_destroy(nfit_pool);
3250 
3251         destroy_workqueue(nfit_wq);
3252         for (i = 0; i < NUM_NFITS; i++)
3253                 if (instances[i])
3254                         platform_device_unregister(&instances[i]->pdev);
3255         nfit_test_teardown();
3256         for (i = 0; i < NUM_NFITS; i++)
3257                 if (instances[i])
3258                         put_device(&instances[i]->pdev.dev);
3259 
3260         return rc;
3261 }
3262 
3263 static __exit void nfit_test_exit(void)
3264 {
3265         int i;
3266 
3267         flush_workqueue(nfit_wq);
3268         destroy_workqueue(nfit_wq);
3269         for (i = 0; i < NUM_NFITS; i++)
3270                 platform_device_unregister(&instances[i]->pdev);
3271         platform_driver_unregister(&nfit_test_driver);
3272         nfit_test_teardown();
3273 
3274         gen_pool_destroy(nfit_pool);
3275 
3276         for (i = 0; i < NUM_NFITS; i++)
3277                 put_device(&instances[i]->pdev.dev);
3278         class_destroy(nfit_test_dimm);
3279 }
3280 
3281 module_init(nfit_test_init);
3282 module_exit(nfit_test_exit);
3283 MODULE_LICENSE("GPL v2");
3284 MODULE_AUTHOR("Intel Corporation");
3285 

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