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Linux/virt/kvm/arm/vgic-v3.c

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  1 /*
  2  * Copyright (C) 2013 ARM Limited, All Rights Reserved.
  3  * Author: Marc Zyngier <marc.zyngier@arm.com>
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License version 2 as
  7  * published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 16  */
 17 
 18 #include <linux/cpu.h>
 19 #include <linux/kvm.h>
 20 #include <linux/kvm_host.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/io.h>
 23 #include <linux/of.h>
 24 #include <linux/of_address.h>
 25 #include <linux/of_irq.h>
 26 
 27 #include <linux/irqchip/arm-gic-v3.h>
 28 
 29 #include <asm/kvm_emulate.h>
 30 #include <asm/kvm_arm.h>
 31 #include <asm/kvm_mmu.h>
 32 
 33 /* These are for GICv2 emulation only */
 34 #define GICH_LR_VIRTUALID               (0x3ffUL << 0)
 35 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
 36 #define GICH_LR_PHYSID_CPUID            (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
 37 #define ICH_LR_VIRTUALID_MASK           (BIT_ULL(32) - 1)
 38 
 39 /*
 40  * LRs are stored in reverse order in memory. make sure we index them
 41  * correctly.
 42  */
 43 #define LR_INDEX(lr)                    (VGIC_V3_MAX_LRS - 1 - lr)
 44 
 45 static u32 ich_vtr_el2;
 46 
 47 static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
 48 {
 49         struct vgic_lr lr_desc;
 50         u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)];
 51 
 52         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 53                 lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
 54         else
 55                 lr_desc.irq = val & GICH_LR_VIRTUALID;
 56 
 57         lr_desc.source = 0;
 58         if (lr_desc.irq <= 15 &&
 59             vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
 60                 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
 61 
 62         lr_desc.state = 0;
 63 
 64         if (val & ICH_LR_PENDING_BIT)
 65                 lr_desc.state |= LR_STATE_PENDING;
 66         if (val & ICH_LR_ACTIVE_BIT)
 67                 lr_desc.state |= LR_STATE_ACTIVE;
 68         if (val & ICH_LR_EOI)
 69                 lr_desc.state |= LR_EOI_INT;
 70         if (val & ICH_LR_HW) {
 71                 lr_desc.state |= LR_HW;
 72                 lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
 73         }
 74 
 75         return lr_desc;
 76 }
 77 
 78 static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
 79                            struct vgic_lr lr_desc)
 80 {
 81         u64 lr_val;
 82 
 83         lr_val = lr_desc.irq;
 84 
 85         /*
 86          * Currently all guest IRQs are Group1, as Group0 would result
 87          * in a FIQ in the guest, which it wouldn't expect.
 88          * Eventually we want to make this configurable, so we may revisit
 89          * this in the future.
 90          */
 91         switch (vcpu->kvm->arch.vgic.vgic_model) {
 92         case KVM_DEV_TYPE_ARM_VGIC_V3:
 93                 lr_val |= ICH_LR_GROUP;
 94                 break;
 95         case  KVM_DEV_TYPE_ARM_VGIC_V2:
 96                 if (lr_desc.irq < VGIC_NR_SGIS)
 97                         lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
 98                 break;
 99         default:
100                 BUG();
101         }
102 
103         if (lr_desc.state & LR_STATE_PENDING)
104                 lr_val |= ICH_LR_PENDING_BIT;
105         if (lr_desc.state & LR_STATE_ACTIVE)
106                 lr_val |= ICH_LR_ACTIVE_BIT;
107         if (lr_desc.state & LR_EOI_INT)
108                 lr_val |= ICH_LR_EOI;
109         if (lr_desc.state & LR_HW) {
110                 lr_val |= ICH_LR_HW;
111                 lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
112         }
113 
114         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;
115 }
116 
117 static void vgic_v3_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
118                                   struct vgic_lr lr_desc)
119 {
120         if (!(lr_desc.state & LR_STATE_MASK))
121                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
122         else
123                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
124 }
125 
126 static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
127 {
128         return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
129 }
130 
131 static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
132 {
133         return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
134 }
135 
136 static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
137 {
138         vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
139 }
140 
141 static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
142 {
143         u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
144         u32 ret = 0;
145 
146         if (misr & ICH_MISR_EOI)
147                 ret |= INT_STATUS_EOI;
148         if (misr & ICH_MISR_U)
149                 ret |= INT_STATUS_UNDERFLOW;
150 
151         return ret;
152 }
153 
154 static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
155 {
156         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
157 
158         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
159         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
160         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
161         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
162 }
163 
164 static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
165 {
166         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
167 }
168 
169 static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
170 {
171         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
172 }
173 
174 static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
175 {
176         u32 vmcr;
177 
178         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
179         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
180         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
181         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
182 
183         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
184 }
185 
186 static void vgic_v3_enable(struct kvm_vcpu *vcpu)
187 {
188         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
189 
190         /*
191          * By forcing VMCR to zero, the GIC will restore the binary
192          * points to their reset values. Anything else resets to zero
193          * anyway.
194          */
195         vgic_v3->vgic_vmcr = 0;
196 
197         /*
198          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
199          * way, so we force SRE to 1 to demonstrate this to the guest.
200          * This goes with the spec allowing the value to be RAO/WI.
201          */
202         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
203                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
204         else
205                 vgic_v3->vgic_sre = 0;
206 
207         /* Get the show on the road... */
208         vgic_v3->vgic_hcr = ICH_HCR_EN;
209 }
210 
211 static const struct vgic_ops vgic_v3_ops = {
212         .get_lr                 = vgic_v3_get_lr,
213         .set_lr                 = vgic_v3_set_lr,
214         .sync_lr_elrsr          = vgic_v3_sync_lr_elrsr,
215         .get_elrsr              = vgic_v3_get_elrsr,
216         .get_eisr               = vgic_v3_get_eisr,
217         .clear_eisr             = vgic_v3_clear_eisr,
218         .get_interrupt_status   = vgic_v3_get_interrupt_status,
219         .enable_underflow       = vgic_v3_enable_underflow,
220         .disable_underflow      = vgic_v3_disable_underflow,
221         .get_vmcr               = vgic_v3_get_vmcr,
222         .set_vmcr               = vgic_v3_set_vmcr,
223         .enable                 = vgic_v3_enable,
224 };
225 
226 static struct vgic_params vgic_v3_params;
227 
228 /**
229  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
230  * @node:       pointer to the DT node
231  * @ops:        address of a pointer to the GICv3 operations
232  * @params:     address of a pointer to HW-specific parameters
233  *
234  * Returns 0 if a GICv3 has been found, with the low level operations
235  * in *ops and the HW parameters in *params. Returns an error code
236  * otherwise.
237  */
238 int vgic_v3_probe(struct device_node *vgic_node,
239                   const struct vgic_ops **ops,
240                   const struct vgic_params **params)
241 {
242         int ret = 0;
243         u32 gicv_idx;
244         struct resource vcpu_res;
245         struct vgic_params *vgic = &vgic_v3_params;
246 
247         vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
248         if (!vgic->maint_irq) {
249                 kvm_err("error getting vgic maintenance irq from DT\n");
250                 ret = -ENXIO;
251                 goto out;
252         }
253 
254         ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
255 
256         /*
257          * The ListRegs field is 5 bits, but there is a architectural
258          * maximum of 16 list registers. Just ignore bit 4...
259          */
260         vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
261         vgic->can_emulate_gicv2 = false;
262 
263         if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
264                 gicv_idx = 1;
265 
266         gicv_idx += 3; /* Also skip GICD, GICC, GICH */
267         if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
268                 kvm_info("GICv3: no GICV resource entry\n");
269                 vgic->vcpu_base = 0;
270         } else if (!PAGE_ALIGNED(vcpu_res.start)) {
271                 pr_warn("GICV physical address 0x%llx not page aligned\n",
272                         (unsigned long long)vcpu_res.start);
273                 vgic->vcpu_base = 0;
274         } else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
275                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
276                         (unsigned long long)resource_size(&vcpu_res),
277                         PAGE_SIZE);
278                 vgic->vcpu_base = 0;
279         } else {
280                 vgic->vcpu_base = vcpu_res.start;
281                 vgic->can_emulate_gicv2 = true;
282                 kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
283                                         KVM_DEV_TYPE_ARM_VGIC_V2);
284         }
285         if (vgic->vcpu_base == 0)
286                 kvm_info("disabling GICv2 emulation\n");
287         kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
288 
289         vgic->vctrl_base = NULL;
290         vgic->type = VGIC_V3;
291         vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
292 
293         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
294                  vcpu_res.start, vgic->maint_irq);
295 
296         *ops = &vgic_v3_ops;
297         *params = vgic;
298 
299 out:
300         of_node_put(vgic_node);
301         return ret;
302 }
303 

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