~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/virt/kvm/arm/vgic/vgic-v3.c

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This program is free software; you can redistribute it and/or modify
  3  * it under the terms of the GNU General Public License version 2 as
  4  * published by the Free Software Foundation.
  5  *
  6  * This program is distributed in the hope that it will be useful,
  7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  9  * GNU General Public License for more details.
 10  *
 11  * You should have received a copy of the GNU General Public License
 12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
 13  */
 14 
 15 #include <linux/irqchip/arm-gic-v3.h>
 16 #include <linux/kvm.h>
 17 #include <linux/kvm_host.h>
 18 #include <kvm/arm_vgic.h>
 19 #include <asm/kvm_mmu.h>
 20 #include <asm/kvm_asm.h>
 21 
 22 #include "vgic.h"
 23 
 24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
 25 {
 26         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
 27         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 28 
 29         if (cpuif->vgic_misr & ICH_MISR_EOI) {
 30                 unsigned long eisr_bmap = cpuif->vgic_eisr;
 31                 int lr;
 32 
 33                 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
 34                         u32 intid;
 35                         u64 val = cpuif->vgic_lr[lr];
 36 
 37                         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 38                                 intid = val & ICH_LR_VIRTUAL_ID_MASK;
 39                         else
 40                                 intid = val & GICH_LR_VIRTUALID;
 41 
 42                         WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
 43 
 44                         /* Only SPIs require notification */
 45                         if (vgic_valid_spi(vcpu->kvm, intid))
 46                                 kvm_notify_acked_irq(vcpu->kvm, 0,
 47                                                      intid - VGIC_NR_PRIVATE_IRQS);
 48                 }
 49 
 50                 /*
 51                  * In the next iterations of the vcpu loop, if we sync
 52                  * the vgic state after flushing it, but before
 53                  * entering the guest (this happens for pending
 54                  * signals and vmid rollovers), then make sure we
 55                  * don't pick up any old maintenance interrupts here.
 56                  */
 57                 cpuif->vgic_eisr = 0;
 58         }
 59 
 60         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
 61 }
 62 
 63 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
 64 {
 65         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
 66 
 67         cpuif->vgic_hcr |= ICH_HCR_UIE;
 68 }
 69 
 70 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
 71 {
 72         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
 73         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 74         int lr;
 75 
 76         for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
 77                 u64 val = cpuif->vgic_lr[lr];
 78                 u32 intid;
 79                 struct vgic_irq *irq;
 80 
 81                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 82                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
 83                 else
 84                         intid = val & GICH_LR_VIRTUALID;
 85                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
 86                 if (!irq)       /* An LPI could have been unmapped. */
 87                         continue;
 88 
 89                 spin_lock(&irq->irq_lock);
 90 
 91                 /* Always preserve the active bit */
 92                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
 93 
 94                 /* Edge is the only case where we preserve the pending bit */
 95                 if (irq->config == VGIC_CONFIG_EDGE &&
 96                     (val & ICH_LR_PENDING_BIT)) {
 97                         irq->pending = true;
 98 
 99                         if (vgic_irq_is_sgi(intid) &&
100                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
101                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
102 
103                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
104                                 irq->source |= (1 << cpuid);
105                         }
106                 }
107 
108                 /*
109                  * Clear soft pending state when level irqs have been acked.
110                  * Always regenerate the pending state.
111                  */
112                 if (irq->config == VGIC_CONFIG_LEVEL) {
113                         if (!(val & ICH_LR_PENDING_BIT))
114                                 irq->soft_pending = false;
115 
116                         irq->pending = irq->line_level || irq->soft_pending;
117                 }
118 
119                 spin_unlock(&irq->irq_lock);
120                 vgic_put_irq(vcpu->kvm, irq);
121         }
122 }
123 
124 /* Requires the irq to be locked already */
125 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
126 {
127         u32 model = vcpu->kvm->arch.vgic.vgic_model;
128         u64 val = irq->intid;
129 
130         if (irq->pending) {
131                 val |= ICH_LR_PENDING_BIT;
132 
133                 if (irq->config == VGIC_CONFIG_EDGE)
134                         irq->pending = false;
135 
136                 if (vgic_irq_is_sgi(irq->intid) &&
137                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
138                         u32 src = ffs(irq->source);
139 
140                         BUG_ON(!src);
141                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
142                         irq->source &= ~(1 << (src - 1));
143                         if (irq->source)
144                                 irq->pending = true;
145                 }
146         }
147 
148         if (irq->active)
149                 val |= ICH_LR_ACTIVE_BIT;
150 
151         if (irq->hw) {
152                 val |= ICH_LR_HW;
153                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
154         } else {
155                 if (irq->config == VGIC_CONFIG_LEVEL)
156                         val |= ICH_LR_EOI;
157         }
158 
159         /*
160          * We currently only support Group1 interrupts, which is a
161          * known defect. This needs to be addressed at some point.
162          */
163         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
164                 val |= ICH_LR_GROUP;
165 
166         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
167 
168         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
169 }
170 
171 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
172 {
173         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
174 }
175 
176 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
177 {
178         u32 vmcr;
179 
180         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
181         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
182         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
183         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
184 
185         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
186 }
187 
188 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
189 {
190         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
191 
192         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
193         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
194         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
195         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
196 }
197 
198 #define INITIAL_PENDBASER_VALUE                                           \
199         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
200         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
201         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
202 
203 void vgic_v3_enable(struct kvm_vcpu *vcpu)
204 {
205         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
206 
207         /*
208          * By forcing VMCR to zero, the GIC will restore the binary
209          * points to their reset values. Anything else resets to zero
210          * anyway.
211          */
212         vgic_v3->vgic_vmcr = 0;
213         vgic_v3->vgic_elrsr = ~0;
214 
215         /*
216          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
217          * way, so we force SRE to 1 to demonstrate this to the guest.
218          * This goes with the spec allowing the value to be RAO/WI.
219          */
220         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
221                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
222                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
223         } else {
224                 vgic_v3->vgic_sre = 0;
225         }
226 
227         /* Get the show on the road... */
228         vgic_v3->vgic_hcr = ICH_HCR_EN;
229 }
230 
231 /* check for overlapping regions and for regions crossing the end of memory */
232 static bool vgic_v3_check_base(struct kvm *kvm)
233 {
234         struct vgic_dist *d = &kvm->arch.vgic;
235         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
236 
237         redist_size *= atomic_read(&kvm->online_vcpus);
238 
239         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
240                 return false;
241         if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
242                 return false;
243 
244         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
245                 return true;
246         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
247                 return true;
248 
249         return false;
250 }
251 
252 int vgic_v3_map_resources(struct kvm *kvm)
253 {
254         int ret = 0;
255         struct vgic_dist *dist = &kvm->arch.vgic;
256 
257         if (vgic_ready(kvm))
258                 goto out;
259 
260         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
261             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
262                 kvm_err("Need to set vgic distributor addresses first\n");
263                 ret = -ENXIO;
264                 goto out;
265         }
266 
267         if (!vgic_v3_check_base(kvm)) {
268                 kvm_err("VGIC redist and dist frames overlap\n");
269                 ret = -EINVAL;
270                 goto out;
271         }
272 
273         /*
274          * For a VGICv3 we require the userland to explicitly initialize
275          * the VGIC before we need to use it.
276          */
277         if (!vgic_initialized(kvm)) {
278                 ret = -EBUSY;
279                 goto out;
280         }
281 
282         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
283         if (ret) {
284                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
285                 goto out;
286         }
287 
288         ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
289         if (ret) {
290                 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
291                 goto out;
292         }
293 
294         if (vgic_has_its(kvm)) {
295                 ret = vgic_register_its_iodevs(kvm);
296                 if (ret) {
297                         kvm_err("Unable to register VGIC ITS MMIO regions\n");
298                         goto out;
299                 }
300         }
301 
302         dist->ready = true;
303 
304 out:
305         if (ret)
306                 kvm_vgic_destroy(kvm);
307         return ret;
308 }
309 
310 /**
311  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
312  * @node:       pointer to the DT node
313  *
314  * Returns 0 if a GICv3 has been found, returns an error code otherwise
315  */
316 int vgic_v3_probe(const struct gic_kvm_info *info)
317 {
318         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
319         int ret;
320 
321         /*
322          * The ListRegs field is 5 bits, but there is a architectural
323          * maximum of 16 list registers. Just ignore bit 4...
324          */
325         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
326         kvm_vgic_global_state.can_emulate_gicv2 = false;
327 
328         if (!info->vcpu.start) {
329                 kvm_info("GICv3: no GICV resource entry\n");
330                 kvm_vgic_global_state.vcpu_base = 0;
331         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
332                 pr_warn("GICV physical address 0x%llx not page aligned\n",
333                         (unsigned long long)info->vcpu.start);
334                 kvm_vgic_global_state.vcpu_base = 0;
335         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
336                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
337                         (unsigned long long)resource_size(&info->vcpu),
338                         PAGE_SIZE);
339                 kvm_vgic_global_state.vcpu_base = 0;
340         } else {
341                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
342                 kvm_vgic_global_state.can_emulate_gicv2 = true;
343                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
344                 if (ret) {
345                         kvm_err("Cannot register GICv2 KVM device.\n");
346                         return ret;
347                 }
348                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
349         }
350         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
351         if (ret) {
352                 kvm_err("Cannot register GICv3 KVM device.\n");
353                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
354                 return ret;
355         }
356 
357         if (kvm_vgic_global_state.vcpu_base == 0)
358                 kvm_info("disabling GICv2 emulation\n");
359 
360         kvm_vgic_global_state.vctrl_base = NULL;
361         kvm_vgic_global_state.type = VGIC_V3;
362         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
363 
364         return 0;
365 }
366 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp