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TOMOYO Linux Cross Reference
Linux/include/linux/irqchip/arm-gic-v3.h

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Diff markup

Differences between /include/linux/irqchip/arm-gic-v3.h (Version linux-4.0.9) and /include/linux/irqchip/arm-gic-v3.h (Version linux-4.12.14)


  1 /*                                                  1 /*
  2  * Copyright (C) 2013, 2014 ARM Limited, All R      2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
  3  * Author: Marc Zyngier <marc.zyngier@arm.com>      3  * Author: Marc Zyngier <marc.zyngier@arm.com>
  4  *                                                  4  *
  5  *                                                  5  *
  6  * This program is free software; you can redi      6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Publi      7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.       8  * published by the Free Software Foundation.
  9  *                                                  9  *
 10  * This program is distributed in the hope tha     10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the      11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR     12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details     13  * GNU General Public License for more details.
 14  *                                                 14  *
 15  * You should have received a copy of the GNU      15  * You should have received a copy of the GNU General Public License
 16  * along with this program.  If not, see <http     16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 17  */                                                17  */
 18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H               18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
 19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H               19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
 20                                                    20 
 21 #include <asm/sysreg.h>                        << 
 22                                                << 
 23 /*                                                 21 /*
 24  * Distributor registers. We assume we're runn     22  * Distributor registers. We assume we're running non-secure, with ARE
 25  * being set. Secure-only and non-ARE register     23  * being set. Secure-only and non-ARE registers are not described.
 26  */                                                24  */
 27 #define GICD_CTLR                       0x0000     25 #define GICD_CTLR                       0x0000
 28 #define GICD_TYPER                      0x0004     26 #define GICD_TYPER                      0x0004
 29 #define GICD_IIDR                       0x0008     27 #define GICD_IIDR                       0x0008
 30 #define GICD_STATUSR                    0x0010     28 #define GICD_STATUSR                    0x0010
 31 #define GICD_SETSPI_NSR                 0x0040     29 #define GICD_SETSPI_NSR                 0x0040
 32 #define GICD_CLRSPI_NSR                 0x0048     30 #define GICD_CLRSPI_NSR                 0x0048
 33 #define GICD_SETSPI_SR                  0x0050     31 #define GICD_SETSPI_SR                  0x0050
 34 #define GICD_CLRSPI_SR                  0x0058     32 #define GICD_CLRSPI_SR                  0x0058
 35 #define GICD_SEIR                       0x0068     33 #define GICD_SEIR                       0x0068
 36 #define GICD_IGROUPR                    0x0080     34 #define GICD_IGROUPR                    0x0080
 37 #define GICD_ISENABLER                  0x0100     35 #define GICD_ISENABLER                  0x0100
 38 #define GICD_ICENABLER                  0x0180     36 #define GICD_ICENABLER                  0x0180
 39 #define GICD_ISPENDR                    0x0200     37 #define GICD_ISPENDR                    0x0200
 40 #define GICD_ICPENDR                    0x0280     38 #define GICD_ICPENDR                    0x0280
 41 #define GICD_ISACTIVER                  0x0300     39 #define GICD_ISACTIVER                  0x0300
 42 #define GICD_ICACTIVER                  0x0380     40 #define GICD_ICACTIVER                  0x0380
 43 #define GICD_IPRIORITYR                 0x0400     41 #define GICD_IPRIORITYR                 0x0400
 44 #define GICD_ICFGR                      0x0C00     42 #define GICD_ICFGR                      0x0C00
 45 #define GICD_IGRPMODR                   0x0D00     43 #define GICD_IGRPMODR                   0x0D00
 46 #define GICD_NSACR                      0x0E00     44 #define GICD_NSACR                      0x0E00
 47 #define GICD_IROUTER                    0x6000     45 #define GICD_IROUTER                    0x6000
 48 #define GICD_IDREGS                     0xFFD0     46 #define GICD_IDREGS                     0xFFD0
 49 #define GICD_PIDR2                      0xFFE8     47 #define GICD_PIDR2                      0xFFE8
 50                                                    48 
 51 /*                                                 49 /*
 52  * Those registers are actually from GICv2, bu     50  * Those registers are actually from GICv2, but the spec demands that they
 53  * are implemented as RES0 if ARE is 1 (which      51  * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
 54  */                                                52  */
 55 #define GICD_ITARGETSR                  0x0800     53 #define GICD_ITARGETSR                  0x0800
 56 #define GICD_SGIR                       0x0F00     54 #define GICD_SGIR                       0x0F00
 57 #define GICD_CPENDSGIR                  0x0F10     55 #define GICD_CPENDSGIR                  0x0F10
 58 #define GICD_SPENDSGIR                  0x0F20     56 #define GICD_SPENDSGIR                  0x0F20
 59                                                    57 
 60 #define GICD_CTLR_RWP                   (1U <<     58 #define GICD_CTLR_RWP                   (1U << 31)
 61 #define GICD_CTLR_DS                    (1U <<     59 #define GICD_CTLR_DS                    (1U << 6)
 62 #define GICD_CTLR_ARE_NS                (1U <<     60 #define GICD_CTLR_ARE_NS                (1U << 4)
 63 #define GICD_CTLR_ENABLE_G1A            (1U <<     61 #define GICD_CTLR_ENABLE_G1A            (1U << 1)
 64 #define GICD_CTLR_ENABLE_G1             (1U <<     62 #define GICD_CTLR_ENABLE_G1             (1U << 0)
 65                                                    63 
 66 /*                                                 64 /*
 67  * In systems with a single security state (wh     65  * In systems with a single security state (what we emulate in KVM)
 68  * the meaning of the interrupt group enable b     66  * the meaning of the interrupt group enable bits is slightly different
 69  */                                                67  */
 70 #define GICD_CTLR_ENABLE_SS_G1          (1U <<     68 #define GICD_CTLR_ENABLE_SS_G1          (1U << 1)
 71 #define GICD_CTLR_ENABLE_SS_G0          (1U <<     69 #define GICD_CTLR_ENABLE_SS_G0          (1U << 0)
 72                                                    70 
 73 #define GICD_TYPER_LPIS                 (1U <<     71 #define GICD_TYPER_LPIS                 (1U << 17)
 74 #define GICD_TYPER_MBIS                 (1U <<     72 #define GICD_TYPER_MBIS                 (1U << 16)
 75                                                    73 
 76 #define GICD_TYPER_ID_BITS(typer)       ((((ty     74 #define GICD_TYPER_ID_BITS(typer)       ((((typer) >> 19) & 0x1f) + 1)
 77 #define GICD_TYPER_IRQS(typer)          ((((ty     75 #define GICD_TYPER_IRQS(typer)          ((((typer) & 0x1f) + 1) * 32)
 78 #define GICD_TYPER_LPIS                 (1U << << 
 79                                                    76 
 80 #define GICD_IROUTER_SPI_MODE_ONE       (0U <<     77 #define GICD_IROUTER_SPI_MODE_ONE       (0U << 31)
 81 #define GICD_IROUTER_SPI_MODE_ANY       (1U <<     78 #define GICD_IROUTER_SPI_MODE_ANY       (1U << 31)
 82                                                    79 
 83 #define GIC_PIDR2_ARCH_MASK             0xf0       80 #define GIC_PIDR2_ARCH_MASK             0xf0
 84 #define GIC_PIDR2_ARCH_GICv3            0x30       81 #define GIC_PIDR2_ARCH_GICv3            0x30
 85 #define GIC_PIDR2_ARCH_GICv4            0x40       82 #define GIC_PIDR2_ARCH_GICv4            0x40
 86                                                    83 
 87 #define GIC_V3_DIST_SIZE                0x1000     84 #define GIC_V3_DIST_SIZE                0x10000
 88                                                    85 
 89 /*                                                 86 /*
 90  * Re-Distributor registers, offsets from RD_b     87  * Re-Distributor registers, offsets from RD_base
 91  */                                                88  */
 92 #define GICR_CTLR                       GICD_C     89 #define GICR_CTLR                       GICD_CTLR
 93 #define GICR_IIDR                       0x0004     90 #define GICR_IIDR                       0x0004
 94 #define GICR_TYPER                      0x0008     91 #define GICR_TYPER                      0x0008
 95 #define GICR_STATUSR                    GICD_S     92 #define GICR_STATUSR                    GICD_STATUSR
 96 #define GICR_WAKER                      0x0014     93 #define GICR_WAKER                      0x0014
 97 #define GICR_SETLPIR                    0x0040     94 #define GICR_SETLPIR                    0x0040
 98 #define GICR_CLRLPIR                    0x0048     95 #define GICR_CLRLPIR                    0x0048
 99 #define GICR_SEIR                       GICD_S     96 #define GICR_SEIR                       GICD_SEIR
100 #define GICR_PROPBASER                  0x0070     97 #define GICR_PROPBASER                  0x0070
101 #define GICR_PENDBASER                  0x0078     98 #define GICR_PENDBASER                  0x0078
102 #define GICR_INVLPIR                    0x00A0     99 #define GICR_INVLPIR                    0x00A0
103 #define GICR_INVALLR                    0x00B0    100 #define GICR_INVALLR                    0x00B0
104 #define GICR_SYNCR                      0x00C0    101 #define GICR_SYNCR                      0x00C0
105 #define GICR_MOVLPIR                    0x0100    102 #define GICR_MOVLPIR                    0x0100
106 #define GICR_MOVALLR                    0x0110    103 #define GICR_MOVALLR                    0x0110
107 #define GICR_IDREGS                     GICD_I    104 #define GICR_IDREGS                     GICD_IDREGS
108 #define GICR_PIDR2                      GICD_P    105 #define GICR_PIDR2                      GICD_PIDR2
109                                                   106 
110 #define GICR_CTLR_ENABLE_LPIS           (1UL <    107 #define GICR_CTLR_ENABLE_LPIS           (1UL << 0)
111                                                   108 
112 #define GICR_TYPER_CPU_NUMBER(r)        (((r)     109 #define GICR_TYPER_CPU_NUMBER(r)        (((r) >> 8) & 0xffff)
113                                                   110 
114 #define GICR_WAKER_ProcessorSleep       (1U <<    111 #define GICR_WAKER_ProcessorSleep       (1U << 1)
115 #define GICR_WAKER_ChildrenAsleep       (1U <<    112 #define GICR_WAKER_ChildrenAsleep       (1U << 2)
116                                                   113 
117 #define GICR_PROPBASER_NonShareable     (0U << !! 114 #define GIC_BASER_CACHE_nCnB            0ULL
118 #define GICR_PROPBASER_InnerShareable   (1U << !! 115 #define GIC_BASER_CACHE_SameAsInner     0ULL
119 #define GICR_PROPBASER_OuterShareable   (2U << !! 116 #define GIC_BASER_CACHE_nC              1ULL
120 #define GICR_PROPBASER_SHAREABILITY_MASK (3UL  !! 117 #define GIC_BASER_CACHE_RaWt            2ULL
121 #define GICR_PROPBASER_nCnB             (0U << !! 118 #define GIC_BASER_CACHE_RaWb            3ULL
122 #define GICR_PROPBASER_nC               (1U << !! 119 #define GIC_BASER_CACHE_WaWt            4ULL
123 #define GICR_PROPBASER_RaWt             (2U << !! 120 #define GIC_BASER_CACHE_WaWb            5ULL
124 #define GICR_PROPBASER_RaWb             (3U << !! 121 #define GIC_BASER_CACHE_RaWaWt          6ULL
125 #define GICR_PROPBASER_WaWt             (4U << !! 122 #define GIC_BASER_CACHE_RaWaWb          7ULL
126 #define GICR_PROPBASER_WaWb             (5U << !! 123 #define GIC_BASER_CACHE_MASK            7ULL
127 #define GICR_PROPBASER_RaWaWt           (6U << !! 124 #define GIC_BASER_NonShareable          0ULL
128 #define GICR_PROPBASER_RaWaWb           (7U << !! 125 #define GIC_BASER_InnerShareable        1ULL
129 #define GICR_PROPBASER_CACHEABILITY_MASK (7U < !! 126 #define GIC_BASER_OuterShareable        2ULL
130 #define GICR_PROPBASER_IDBITS_MASK      (0x1f) !! 127 #define GIC_BASER_SHAREABILITY_MASK     3ULL
131                                                !! 128 
132 #define GICR_PENDBASER_NonShareable     (0U << !! 129 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type)                  \
133 #define GICR_PENDBASER_InnerShareable   (1U << !! 130         (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
134 #define GICR_PENDBASER_OuterShareable   (2U << !! 131 
135 #define GICR_PENDBASER_SHAREABILITY_MASK (3UL  !! 132 #define GIC_BASER_SHAREABILITY(reg, type)                               \
136 #define GICR_PENDBASER_nCnB             (0U << !! 133         (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
137 #define GICR_PENDBASER_nC               (1U << !! 134 
138 #define GICR_PENDBASER_RaWt             (2U << !! 135 /* encode a size field of width @w containing @n - 1 units */
139 #define GICR_PENDBASER_RaWb             (3U << !! 136 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
140 #define GICR_PENDBASER_WaWt             (4U << !! 137 
141 #define GICR_PENDBASER_WaWb             (5U << !! 138 #define GICR_PROPBASER_SHAREABILITY_SHIFT               (10)
142 #define GICR_PENDBASER_RaWaWt           (6U << !! 139 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT         (7)
143 #define GICR_PENDBASER_RaWaWb           (7U << !! 140 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT         (56)
144 #define GICR_PENDBASER_CACHEABILITY_MASK (7U < !! 141 #define GICR_PROPBASER_SHAREABILITY_MASK                                \
                                                   >> 142         GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
                                                   >> 143 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK                          \
                                                   >> 144         GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
                                                   >> 145 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK                          \
                                                   >> 146         GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
                                                   >> 147 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
                                                   >> 148 
                                                   >> 149 #define GICR_PROPBASER_InnerShareable                                   \
                                                   >> 150         GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
                                                   >> 151 
                                                   >> 152 #define GICR_PROPBASER_nCnB     GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
                                                   >> 153 #define GICR_PROPBASER_nC       GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
                                                   >> 154 #define GICR_PROPBASER_RaWt     GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
                                                   >> 155 #define GICR_PROPBASER_RaWb     GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
                                                   >> 156 #define GICR_PROPBASER_WaWt     GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
                                                   >> 157 #define GICR_PROPBASER_WaWb     GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
                                                   >> 158 #define GICR_PROPBASER_RaWaWt   GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
                                                   >> 159 #define GICR_PROPBASER_RaWaWb   GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
                                                   >> 160 
                                                   >> 161 #define GICR_PROPBASER_IDBITS_MASK                      (0x1f)
                                                   >> 162 #define GICR_PROPBASER_ADDRESS(x)       ((x) & GENMASK_ULL(51, 12))
                                                   >> 163 #define GICR_PENDBASER_ADDRESS(x)       ((x) & GENMASK_ULL(51, 16))
                                                   >> 164 
                                                   >> 165 #define GICR_PENDBASER_SHAREABILITY_SHIFT               (10)
                                                   >> 166 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT         (7)
                                                   >> 167 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT         (56)
                                                   >> 168 #define GICR_PENDBASER_SHAREABILITY_MASK                                \
                                                   >> 169         GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
                                                   >> 170 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK                          \
                                                   >> 171         GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
                                                   >> 172 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK                          \
                                                   >> 173         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
                                                   >> 174 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
                                                   >> 175 
                                                   >> 176 #define GICR_PENDBASER_InnerShareable                                   \
                                                   >> 177         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
                                                   >> 178 
                                                   >> 179 #define GICR_PENDBASER_nCnB     GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
                                                   >> 180 #define GICR_PENDBASER_nC       GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
                                                   >> 181 #define GICR_PENDBASER_RaWt     GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
                                                   >> 182 #define GICR_PENDBASER_RaWb     GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
                                                   >> 183 #define GICR_PENDBASER_WaWt     GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
                                                   >> 184 #define GICR_PENDBASER_WaWb     GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
                                                   >> 185 #define GICR_PENDBASER_RaWaWt   GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
                                                   >> 186 #define GICR_PENDBASER_RaWaWb   GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
                                                   >> 187 
                                                   >> 188 #define GICR_PENDBASER_PTZ                              BIT_ULL(62)
145                                                   189 
146 /*                                                190 /*
147  * Re-Distributor registers, offsets from SGI_    191  * Re-Distributor registers, offsets from SGI_base
148  */                                               192  */
149 #define GICR_IGROUPR0                   GICD_I    193 #define GICR_IGROUPR0                   GICD_IGROUPR
150 #define GICR_ISENABLER0                 GICD_I    194 #define GICR_ISENABLER0                 GICD_ISENABLER
151 #define GICR_ICENABLER0                 GICD_I    195 #define GICR_ICENABLER0                 GICD_ICENABLER
152 #define GICR_ISPENDR0                   GICD_I    196 #define GICR_ISPENDR0                   GICD_ISPENDR
153 #define GICR_ICPENDR0                   GICD_I    197 #define GICR_ICPENDR0                   GICD_ICPENDR
154 #define GICR_ISACTIVER0                 GICD_I    198 #define GICR_ISACTIVER0                 GICD_ISACTIVER
155 #define GICR_ICACTIVER0                 GICD_I    199 #define GICR_ICACTIVER0                 GICD_ICACTIVER
156 #define GICR_IPRIORITYR0                GICD_I    200 #define GICR_IPRIORITYR0                GICD_IPRIORITYR
157 #define GICR_ICFGR0                     GICD_I    201 #define GICR_ICFGR0                     GICD_ICFGR
158 #define GICR_IGRPMODR0                  GICD_I    202 #define GICR_IGRPMODR0                  GICD_IGRPMODR
159 #define GICR_NSACR                      GICD_N    203 #define GICR_NSACR                      GICD_NSACR
160                                                   204 
161 #define GICR_TYPER_PLPIS                (1U <<    205 #define GICR_TYPER_PLPIS                (1U << 0)
162 #define GICR_TYPER_VLPIS                (1U <<    206 #define GICR_TYPER_VLPIS                (1U << 1)
163 #define GICR_TYPER_LAST                 (1U <<    207 #define GICR_TYPER_LAST                 (1U << 4)
164                                                   208 
165 #define GIC_V3_REDIST_SIZE              0x2000    209 #define GIC_V3_REDIST_SIZE              0x20000
166                                                   210 
167 #define LPI_PROP_GROUP1                 (1 <<     211 #define LPI_PROP_GROUP1                 (1 << 1)
168 #define LPI_PROP_ENABLED                (1 <<     212 #define LPI_PROP_ENABLED                (1 << 0)
169                                                   213 
170 /*                                                214 /*
171  * ITS registers, offsets from ITS_base           215  * ITS registers, offsets from ITS_base
172  */                                               216  */
173 #define GITS_CTLR                       0x0000    217 #define GITS_CTLR                       0x0000
174 #define GITS_IIDR                       0x0004    218 #define GITS_IIDR                       0x0004
175 #define GITS_TYPER                      0x0008    219 #define GITS_TYPER                      0x0008
176 #define GITS_CBASER                     0x0080    220 #define GITS_CBASER                     0x0080
177 #define GITS_CWRITER                    0x0088    221 #define GITS_CWRITER                    0x0088
178 #define GITS_CREADR                     0x0090    222 #define GITS_CREADR                     0x0090
179 #define GITS_BASER                      0x0100    223 #define GITS_BASER                      0x0100
                                                   >> 224 #define GITS_IDREGS_BASE                0xffd0
                                                   >> 225 #define GITS_PIDR0                      0xffe0
                                                   >> 226 #define GITS_PIDR1                      0xffe4
180 #define GITS_PIDR2                      GICR_P    227 #define GITS_PIDR2                      GICR_PIDR2
                                                   >> 228 #define GITS_PIDR4                      0xffd0
                                                   >> 229 #define GITS_CIDR0                      0xfff0
                                                   >> 230 #define GITS_CIDR1                      0xfff4
                                                   >> 231 #define GITS_CIDR2                      0xfff8
                                                   >> 232 #define GITS_CIDR3                      0xfffc
181                                                   233 
182 #define GITS_TRANSLATER                 0x1004    234 #define GITS_TRANSLATER                 0x10040
183                                                   235 
184 #define GITS_CTLR_ENABLE                (1U <<    236 #define GITS_CTLR_ENABLE                (1U << 0)
185 #define GITS_CTLR_QUIESCENT             (1U <<    237 #define GITS_CTLR_QUIESCENT             (1U << 31)
186                                                   238 
                                                   >> 239 #define GITS_TYPER_PLPIS                (1UL << 0)
                                                   >> 240 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
                                                   >> 241 #define GITS_TYPER_IDBITS_SHIFT         8
187 #define GITS_TYPER_DEVBITS_SHIFT        13        242 #define GITS_TYPER_DEVBITS_SHIFT        13
188 #define GITS_TYPER_DEVBITS(r)           ((((r)    243 #define GITS_TYPER_DEVBITS(r)           ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
189 #define GITS_TYPER_PTA                  (1UL <    244 #define GITS_TYPER_PTA                  (1UL << 19)
                                                   >> 245 #define GITS_TYPER_HWCOLLCNT_SHIFT      24
190                                                   246 
191 #define GITS_CBASER_VALID               (1UL < !! 247 #define GITS_IIDR_REV_SHIFT             12
192 #define GITS_CBASER_nCnB                (0UL < !! 248 #define GITS_IIDR_REV_MASK              (0xf << GITS_IIDR_REV_SHIFT)
193 #define GITS_CBASER_nC                  (1UL < !! 249 #define GITS_IIDR_REV(r)                (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
194 #define GITS_CBASER_RaWt                (2UL < !! 250 #define GITS_IIDR_PRODUCTID_SHIFT       24
195 #define GITS_CBASER_RaWb                (3UL < !! 251 
196 #define GITS_CBASER_WaWt                (4UL < !! 252 #define GITS_CBASER_VALID                       (1ULL << 63)
197 #define GITS_CBASER_WaWb                (5UL < !! 253 #define GITS_CBASER_SHAREABILITY_SHIFT          (10)
198 #define GITS_CBASER_RaWaWt              (6UL < !! 254 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT    (59)
199 #define GITS_CBASER_RaWaWb              (7UL < !! 255 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT    (53)
200 #define GITS_CBASER_CACHEABILITY_MASK   (7UL < !! 256 #define GITS_CBASER_SHAREABILITY_MASK                                   \
201 #define GITS_CBASER_NonShareable        (0UL < !! 257         GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
202 #define GITS_CBASER_InnerShareable      (1UL < !! 258 #define GITS_CBASER_INNER_CACHEABILITY_MASK                             \
203 #define GITS_CBASER_OuterShareable      (2UL < !! 259         GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
204 #define GITS_CBASER_SHAREABILITY_MASK   (3UL < !! 260 #define GITS_CBASER_OUTER_CACHEABILITY_MASK                             \
                                                   >> 261         GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
                                                   >> 262 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
                                                   >> 263 
                                                   >> 264 #define GITS_CBASER_InnerShareable                                      \
                                                   >> 265         GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
                                                   >> 266 
                                                   >> 267 #define GITS_CBASER_nCnB        GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
                                                   >> 268 #define GITS_CBASER_nC          GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
                                                   >> 269 #define GITS_CBASER_RaWt        GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
                                                   >> 270 #define GITS_CBASER_RaWb        GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
                                                   >> 271 #define GITS_CBASER_WaWt        GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
                                                   >> 272 #define GITS_CBASER_WaWb        GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
                                                   >> 273 #define GITS_CBASER_RaWaWt      GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
                                                   >> 274 #define GITS_CBASER_RaWaWb      GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
205                                                   275 
206 #define GITS_BASER_NR_REGS              8         276 #define GITS_BASER_NR_REGS              8
207                                                   277 
208 #define GITS_BASER_VALID                (1UL < !! 278 #define GITS_BASER_VALID                        (1ULL << 63)
209 #define GITS_BASER_nCnB                 (0UL < !! 279 #define GITS_BASER_INDIRECT                     (1ULL << 62)
210 #define GITS_BASER_nC                   (1UL < !! 280 
211 #define GITS_BASER_RaWt                 (2UL < !! 281 #define GITS_BASER_INNER_CACHEABILITY_SHIFT     (59)
212 #define GITS_BASER_RaWb                 (3UL < !! 282 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT     (53)
213 #define GITS_BASER_WaWt                 (4UL < !! 283 #define GITS_BASER_INNER_CACHEABILITY_MASK                              \
214 #define GITS_BASER_WaWb                 (5UL < !! 284         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
215 #define GITS_BASER_RaWaWt               (6UL < !! 285 #define GITS_BASER_CACHEABILITY_MASK            GITS_BASER_INNER_CACHEABILITY_MASK
216 #define GITS_BASER_RaWaWb               (7UL < !! 286 #define GITS_BASER_OUTER_CACHEABILITY_MASK                              \
217 #define GITS_BASER_CACHEABILITY_MASK    (7UL < !! 287         GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
218 #define GITS_BASER_TYPE_SHIFT           (56)   !! 288 #define GITS_BASER_SHAREABILITY_MASK                                    \
                                                   >> 289         GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
                                                   >> 290 
                                                   >> 291 #define GITS_BASER_nCnB         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
                                                   >> 292 #define GITS_BASER_nC           GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
                                                   >> 293 #define GITS_BASER_RaWt         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
                                                   >> 294 #define GITS_BASER_RaWb         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
                                                   >> 295 #define GITS_BASER_WaWt         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
                                                   >> 296 #define GITS_BASER_WaWb         GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
                                                   >> 297 #define GITS_BASER_RaWaWt       GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
                                                   >> 298 #define GITS_BASER_RaWaWb       GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
                                                   >> 299 
                                                   >> 300 #define GITS_BASER_TYPE_SHIFT                   (56)
219 #define GITS_BASER_TYPE(r)              (((r)     301 #define GITS_BASER_TYPE(r)              (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
220 #define GITS_BASER_ENTRY_SIZE_SHIFT     (48)   !! 302 #define GITS_BASER_ENTRY_SIZE_SHIFT             (48)
221 #define GITS_BASER_ENTRY_SIZE(r)        ((((r) !! 303 #define GITS_BASER_ENTRY_SIZE(r)        ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
222 #define GITS_BASER_NonShareable         (0UL < !! 304 #define GITS_BASER_ENTRY_SIZE_MASK      GENMASK_ULL(52, 48)
223 #define GITS_BASER_InnerShareable       (1UL < << 
224 #define GITS_BASER_OuterShareable       (2UL < << 
225 #define GITS_BASER_SHAREABILITY_SHIFT   (10)      305 #define GITS_BASER_SHAREABILITY_SHIFT   (10)
226 #define GITS_BASER_SHAREABILITY_MASK    (3UL < !! 306 #define GITS_BASER_InnerShareable                                       \
                                                   >> 307         GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
227 #define GITS_BASER_PAGE_SIZE_SHIFT      (8)       308 #define GITS_BASER_PAGE_SIZE_SHIFT      (8)
228 #define GITS_BASER_PAGE_SIZE_4K         (0UL < !! 309 #define GITS_BASER_PAGE_SIZE_4K         (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
229 #define GITS_BASER_PAGE_SIZE_16K        (1UL < !! 310 #define GITS_BASER_PAGE_SIZE_16K        (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
230 #define GITS_BASER_PAGE_SIZE_64K        (2UL < !! 311 #define GITS_BASER_PAGE_SIZE_64K        (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
231 #define GITS_BASER_PAGE_SIZE_MASK       (3UL < !! 312 #define GITS_BASER_PAGE_SIZE_MASK       (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
                                                   >> 313 #define GITS_BASER_PAGES_MAX            256
                                                   >> 314 #define GITS_BASER_PAGES_SHIFT          (0)
                                                   >> 315 #define GITS_BASER_NR_PAGES(r)          (((r) & 0xff) + 1)
232                                                   316 
233 #define GITS_BASER_TYPE_NONE            0         317 #define GITS_BASER_TYPE_NONE            0
234 #define GITS_BASER_TYPE_DEVICE          1         318 #define GITS_BASER_TYPE_DEVICE          1
235 #define GITS_BASER_TYPE_VCPU            2         319 #define GITS_BASER_TYPE_VCPU            2
236 #define GITS_BASER_TYPE_CPU             3      !! 320 #define GITS_BASER_TYPE_RESERVED3       3
237 #define GITS_BASER_TYPE_COLLECTION      4         321 #define GITS_BASER_TYPE_COLLECTION      4
238 #define GITS_BASER_TYPE_RESERVED5       5         322 #define GITS_BASER_TYPE_RESERVED5       5
239 #define GITS_BASER_TYPE_RESERVED6       6         323 #define GITS_BASER_TYPE_RESERVED6       6
240 #define GITS_BASER_TYPE_RESERVED7       7         324 #define GITS_BASER_TYPE_RESERVED7       7
241                                                   325 
                                                   >> 326 #define GITS_LVL1_ENTRY_SIZE           (8UL)
                                                   >> 327 
242 /*                                                328 /*
243  * ITS commands                                   329  * ITS commands
244  */                                               330  */
245 #define GITS_CMD_MAPD                   0x08      331 #define GITS_CMD_MAPD                   0x08
246 #define GITS_CMD_MAPC                   0x09      332 #define GITS_CMD_MAPC                   0x09
247 #define GITS_CMD_MAPVI                  0x0a   !! 333 #define GITS_CMD_MAPTI                  0x0a
                                                   >> 334 #define GITS_CMD_MAPI                   0x0b
248 #define GITS_CMD_MOVI                   0x01      335 #define GITS_CMD_MOVI                   0x01
249 #define GITS_CMD_DISCARD                0x0f      336 #define GITS_CMD_DISCARD                0x0f
250 #define GITS_CMD_INV                    0x0c      337 #define GITS_CMD_INV                    0x0c
251 #define GITS_CMD_MOVALL                 0x0e      338 #define GITS_CMD_MOVALL                 0x0e
252 #define GITS_CMD_INVALL                 0x0d      339 #define GITS_CMD_INVALL                 0x0d
253 #define GITS_CMD_INT                    0x03      340 #define GITS_CMD_INT                    0x03
254 #define GITS_CMD_CLEAR                  0x04      341 #define GITS_CMD_CLEAR                  0x04
255 #define GITS_CMD_SYNC                   0x05      342 #define GITS_CMD_SYNC                   0x05
256                                                   343 
257 /*                                                344 /*
                                                   >> 345  * ITS error numbers
                                                   >> 346  */
                                                   >> 347 #define E_ITS_MOVI_UNMAPPED_INTERRUPT           0x010107
                                                   >> 348 #define E_ITS_MOVI_UNMAPPED_COLLECTION          0x010109
                                                   >> 349 #define E_ITS_INT_UNMAPPED_INTERRUPT            0x010307
                                                   >> 350 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT          0x010507
                                                   >> 351 #define E_ITS_MAPD_DEVICE_OOR                   0x010801
                                                   >> 352 #define E_ITS_MAPD_ITTSIZE_OOR                  0x010802
                                                   >> 353 #define E_ITS_MAPC_PROCNUM_OOR                  0x010902
                                                   >> 354 #define E_ITS_MAPC_COLLECTION_OOR               0x010903
                                                   >> 355 #define E_ITS_MAPTI_UNMAPPED_DEVICE             0x010a04
                                                   >> 356 #define E_ITS_MAPTI_ID_OOR                      0x010a05
                                                   >> 357 #define E_ITS_MAPTI_PHYSICALID_OOR              0x010a06
                                                   >> 358 #define E_ITS_INV_UNMAPPED_INTERRUPT            0x010c07
                                                   >> 359 #define E_ITS_INVALL_UNMAPPED_COLLECTION        0x010d09
                                                   >> 360 #define E_ITS_MOVALL_PROCNUM_OOR                0x010e01
                                                   >> 361 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT        0x010f07
                                                   >> 362 
                                                   >> 363 /*
258  * CPU interface registers                        364  * CPU interface registers
259  */                                               365  */
260 #define ICC_CTLR_EL1_EOImode_drop_dir   (0U << !! 366 #define ICC_CTLR_EL1_EOImode_SHIFT      (1)
261 #define ICC_CTLR_EL1_EOImode_drop       (1U << !! 367 #define ICC_CTLR_EL1_EOImode_drop_dir   (0U << ICC_CTLR_EL1_EOImode_SHIFT)
                                                   >> 368 #define ICC_CTLR_EL1_EOImode_drop       (1U << ICC_CTLR_EL1_EOImode_SHIFT)
                                                   >> 369 #define ICC_CTLR_EL1_EOImode_MASK       (1 << ICC_CTLR_EL1_EOImode_SHIFT)
                                                   >> 370 #define ICC_CTLR_EL1_CBPR_SHIFT         0
                                                   >> 371 #define ICC_CTLR_EL1_CBPR_MASK          (1 << ICC_CTLR_EL1_CBPR_SHIFT)
                                                   >> 372 #define ICC_CTLR_EL1_PRI_BITS_SHIFT     8
                                                   >> 373 #define ICC_CTLR_EL1_PRI_BITS_MASK      (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
                                                   >> 374 #define ICC_CTLR_EL1_ID_BITS_SHIFT      11
                                                   >> 375 #define ICC_CTLR_EL1_ID_BITS_MASK       (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
                                                   >> 376 #define ICC_CTLR_EL1_SEIS_SHIFT         14
                                                   >> 377 #define ICC_CTLR_EL1_SEIS_MASK          (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
                                                   >> 378 #define ICC_CTLR_EL1_A3V_SHIFT          15
                                                   >> 379 #define ICC_CTLR_EL1_A3V_MASK           (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
                                                   >> 380 #define ICC_PMR_EL1_SHIFT               0
                                                   >> 381 #define ICC_PMR_EL1_MASK                (0xff << ICC_PMR_EL1_SHIFT)
                                                   >> 382 #define ICC_BPR0_EL1_SHIFT              0
                                                   >> 383 #define ICC_BPR0_EL1_MASK               (0x7 << ICC_BPR0_EL1_SHIFT)
                                                   >> 384 #define ICC_BPR1_EL1_SHIFT              0
                                                   >> 385 #define ICC_BPR1_EL1_MASK               (0x7 << ICC_BPR1_EL1_SHIFT)
                                                   >> 386 #define ICC_IGRPEN0_EL1_SHIFT           0
                                                   >> 387 #define ICC_IGRPEN0_EL1_MASK            (1 << ICC_IGRPEN0_EL1_SHIFT)
                                                   >> 388 #define ICC_IGRPEN1_EL1_SHIFT           0
                                                   >> 389 #define ICC_IGRPEN1_EL1_MASK            (1 << ICC_IGRPEN1_EL1_SHIFT)
                                                   >> 390 #define ICC_SRE_EL1_DIB                 (1U << 2)
                                                   >> 391 #define ICC_SRE_EL1_DFB                 (1U << 1)
262 #define ICC_SRE_EL1_SRE                 (1U <<    392 #define ICC_SRE_EL1_SRE                 (1U << 0)
263                                                   393 
264 /*                                                394 /*
265  * Hypervisor interface registers (SRE only)      395  * Hypervisor interface registers (SRE only)
266  */                                               396  */
267 #define ICH_LR_VIRTUAL_ID_MASK          ((1UL  !! 397 #define ICH_LR_VIRTUAL_ID_MASK          ((1ULL << 32) - 1)
268                                                   398 
269 #define ICH_LR_EOI                      (1UL < !! 399 #define ICH_LR_EOI                      (1ULL << 41)
270 #define ICH_LR_GROUP                    (1UL < !! 400 #define ICH_LR_GROUP                    (1ULL << 60)
271 #define ICH_LR_STATE                    (3UL < !! 401 #define ICH_LR_HW                       (1ULL << 61)
272 #define ICH_LR_PENDING_BIT              (1UL < !! 402 #define ICH_LR_STATE                    (3ULL << 62)
273 #define ICH_LR_ACTIVE_BIT               (1UL < !! 403 #define ICH_LR_PENDING_BIT              (1ULL << 62)
                                                   >> 404 #define ICH_LR_ACTIVE_BIT               (1ULL << 63)
                                                   >> 405 #define ICH_LR_PHYS_ID_SHIFT            32
                                                   >> 406 #define ICH_LR_PHYS_ID_MASK             (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
                                                   >> 407 #define ICH_LR_PRIORITY_SHIFT           48
                                                   >> 408 
                                                   >> 409 /* These are for GICv2 emulation only */
                                                   >> 410 #define GICH_LR_VIRTUALID               (0x3ffUL << 0)
                                                   >> 411 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
                                                   >> 412 #define GICH_LR_PHYSID_CPUID            (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
274                                                   413 
275 #define ICH_MISR_EOI                    (1 <<     414 #define ICH_MISR_EOI                    (1 << 0)
276 #define ICH_MISR_U                      (1 <<     415 #define ICH_MISR_U                      (1 << 1)
277                                                   416 
278 #define ICH_HCR_EN                      (1 <<     417 #define ICH_HCR_EN                      (1 << 0)
279 #define ICH_HCR_UIE                     (1 <<     418 #define ICH_HCR_UIE                     (1 << 1)
280                                                   419 
281 #define ICH_VMCR_CTLR_SHIFT             0      !! 420 #define ICH_VMCR_ACK_CTL_SHIFT          2
282 #define ICH_VMCR_CTLR_MASK              (0x21f !! 421 #define ICH_VMCR_ACK_CTL_MASK           (1 << ICH_VMCR_ACK_CTL_SHIFT)
                                                   >> 422 #define ICH_VMCR_FIQ_EN_SHIFT           3
                                                   >> 423 #define ICH_VMCR_FIQ_EN_MASK            (1 << ICH_VMCR_FIQ_EN_SHIFT)
                                                   >> 424 #define ICH_VMCR_CBPR_SHIFT             4
                                                   >> 425 #define ICH_VMCR_CBPR_MASK              (1 << ICH_VMCR_CBPR_SHIFT)
                                                   >> 426 #define ICH_VMCR_EOIM_SHIFT             9
                                                   >> 427 #define ICH_VMCR_EOIM_MASK              (1 << ICH_VMCR_EOIM_SHIFT)
283 #define ICH_VMCR_BPR1_SHIFT             18        428 #define ICH_VMCR_BPR1_SHIFT             18
284 #define ICH_VMCR_BPR1_MASK              (7 <<     429 #define ICH_VMCR_BPR1_MASK              (7 << ICH_VMCR_BPR1_SHIFT)
285 #define ICH_VMCR_BPR0_SHIFT             21        430 #define ICH_VMCR_BPR0_SHIFT             21
286 #define ICH_VMCR_BPR0_MASK              (7 <<     431 #define ICH_VMCR_BPR0_MASK              (7 << ICH_VMCR_BPR0_SHIFT)
287 #define ICH_VMCR_PMR_SHIFT              24        432 #define ICH_VMCR_PMR_SHIFT              24
288 #define ICH_VMCR_PMR_MASK               (0xffU    433 #define ICH_VMCR_PMR_MASK               (0xffUL << ICH_VMCR_PMR_SHIFT)
289                                                !! 434 #define ICH_VMCR_ENG0_SHIFT             0
290 #define ICC_EOIR1_EL1                   sys_re !! 435 #define ICH_VMCR_ENG0_MASK              (1 << ICH_VMCR_ENG0_SHIFT)
291 #define ICC_IAR1_EL1                    sys_re !! 436 #define ICH_VMCR_ENG1_SHIFT             1
292 #define ICC_SGI1R_EL1                   sys_re !! 437 #define ICH_VMCR_ENG1_MASK              (1 << ICH_VMCR_ENG1_SHIFT)
293 #define ICC_PMR_EL1                     sys_re !! 438 
294 #define ICC_CTLR_EL1                    sys_re !! 439 #define ICH_VTR_PRI_BITS_SHIFT          29
295 #define ICC_SRE_EL1                     sys_re !! 440 #define ICH_VTR_PRI_BITS_MASK           (7 << ICH_VTR_PRI_BITS_SHIFT)
296 #define ICC_GRPEN1_EL1                  sys_re !! 441 #define ICH_VTR_ID_BITS_SHIFT           23
                                                   >> 442 #define ICH_VTR_ID_BITS_MASK            (7 << ICH_VTR_ID_BITS_SHIFT)
                                                   >> 443 #define ICH_VTR_SEIS_SHIFT              22
                                                   >> 444 #define ICH_VTR_SEIS_MASK               (1 << ICH_VTR_SEIS_SHIFT)
                                                   >> 445 #define ICH_VTR_A3V_SHIFT               21
                                                   >> 446 #define ICH_VTR_A3V_MASK                (1 << ICH_VTR_A3V_SHIFT)
297                                                   447 
298 #define ICC_IAR1_EL1_SPURIOUS           0x3ff     448 #define ICC_IAR1_EL1_SPURIOUS           0x3ff
299                                                   449 
300 #define ICC_SRE_EL2                     sys_re << 
301                                                << 
302 #define ICC_SRE_EL2_SRE                 (1 <<     450 #define ICC_SRE_EL2_SRE                 (1 << 0)
303 #define ICC_SRE_EL2_ENABLE              (1 <<     451 #define ICC_SRE_EL2_ENABLE              (1 << 3)
304                                                   452 
305 #define ICC_SGI1R_TARGET_LIST_SHIFT     0         453 #define ICC_SGI1R_TARGET_LIST_SHIFT     0
306 #define ICC_SGI1R_TARGET_LIST_MASK      (0xfff    454 #define ICC_SGI1R_TARGET_LIST_MASK      (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
307 #define ICC_SGI1R_AFFINITY_1_SHIFT      16        455 #define ICC_SGI1R_AFFINITY_1_SHIFT      16
308 #define ICC_SGI1R_AFFINITY_1_MASK       (0xff     456 #define ICC_SGI1R_AFFINITY_1_MASK       (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
309 #define ICC_SGI1R_SGI_ID_SHIFT          24        457 #define ICC_SGI1R_SGI_ID_SHIFT          24
310 #define ICC_SGI1R_SGI_ID_MASK           (0xff  !! 458 #define ICC_SGI1R_SGI_ID_MASK           (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
311 #define ICC_SGI1R_AFFINITY_2_SHIFT      32        459 #define ICC_SGI1R_AFFINITY_2_SHIFT      32
312 #define ICC_SGI1R_AFFINITY_2_MASK       (0xffU !! 460 #define ICC_SGI1R_AFFINITY_2_MASK       (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
313 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT  40        461 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT  40
314 #define ICC_SGI1R_AFFINITY_3_SHIFT      48        462 #define ICC_SGI1R_AFFINITY_3_SHIFT      48
315 #define ICC_SGI1R_AFFINITY_3_MASK       (0xffU !! 463 #define ICC_SGI1R_AFFINITY_3_MASK       (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
316                                                   464 
317 /*                                             !! 465 #include <asm/arch_gicv3.h>
318  * System register definitions                 << 
319  */                                            << 
320 #define ICH_VSEIR_EL2                   sys_re << 
321 #define ICH_HCR_EL2                     sys_re << 
322 #define ICH_VTR_EL2                     sys_re << 
323 #define ICH_MISR_EL2                    sys_re << 
324 #define ICH_EISR_EL2                    sys_re << 
325 #define ICH_ELSR_EL2                    sys_re << 
326 #define ICH_VMCR_EL2                    sys_re << 
327                                                << 
328 #define __LR0_EL2(x)                    sys_re << 
329 #define __LR8_EL2(x)                    sys_re << 
330                                                << 
331 #define ICH_LR0_EL2                     __LR0_ << 
332 #define ICH_LR1_EL2                     __LR0_ << 
333 #define ICH_LR2_EL2                     __LR0_ << 
334 #define ICH_LR3_EL2                     __LR0_ << 
335 #define ICH_LR4_EL2                     __LR0_ << 
336 #define ICH_LR5_EL2                     __LR0_ << 
337 #define ICH_LR6_EL2                     __LR0_ << 
338 #define ICH_LR7_EL2                     __LR0_ << 
339 #define ICH_LR8_EL2                     __LR8_ << 
340 #define ICH_LR9_EL2                     __LR8_ << 
341 #define ICH_LR10_EL2                    __LR8_ << 
342 #define ICH_LR11_EL2                    __LR8_ << 
343 #define ICH_LR12_EL2                    __LR8_ << 
344 #define ICH_LR13_EL2                    __LR8_ << 
345 #define ICH_LR14_EL2                    __LR8_ << 
346 #define ICH_LR15_EL2                    __LR8_ << 
347                                                << 
348 #define __AP0Rx_EL2(x)                  sys_re << 
349 #define ICH_AP0R0_EL2                   __AP0R << 
350 #define ICH_AP0R1_EL2                   __AP0R << 
351 #define ICH_AP0R2_EL2                   __AP0R << 
352 #define ICH_AP0R3_EL2                   __AP0R << 
353                                                << 
354 #define __AP1Rx_EL2(x)                  sys_re << 
355 #define ICH_AP1R0_EL2                   __AP1R << 
356 #define ICH_AP1R1_EL2                   __AP1R << 
357 #define ICH_AP1R2_EL2                   __AP1R << 
358 #define ICH_AP1R3_EL2                   __AP1R << 
359                                                   466 
360 #ifndef __ASSEMBLY__                              467 #ifndef __ASSEMBLY__
361                                                   468 
362 #include <linux/stringify.h>                   << 
363                                                << 
364 /*                                                469 /*
365  * We need a value to serve as a irq-type for     470  * We need a value to serve as a irq-type for LPIs. Choose one that will
366  * hopefully pique the interest of the reviewe    471  * hopefully pique the interest of the reviewer.
367  */                                               472  */
368 #define GIC_IRQ_TYPE_LPI                0xa110    473 #define GIC_IRQ_TYPE_LPI                0xa110c8ed
369                                                   474 
370 struct rdists {                                   475 struct rdists {
371         struct {                                  476         struct {
372                 void __iomem    *rd_base;         477                 void __iomem    *rd_base;
373                 struct page     *pend_page;       478                 struct page     *pend_page;
374                 phys_addr_t     phys_base;        479                 phys_addr_t     phys_base;
375         } __percpu              *rdist;           480         } __percpu              *rdist;
376         struct page             *prop_page;       481         struct page             *prop_page;
377         int                     id_bits;          482         int                     id_bits;
378         u64                     flags;            483         u64                     flags;
379 };                                                484 };
380                                                   485 
381 static inline void gic_write_eoir(u64 irq)     << 
382 {                                              << 
383         asm volatile("msr_s " __stringify(ICC_ << 
384         isb();                                 << 
385 }                                              << 
386                                                << 
387 struct irq_domain;                                486 struct irq_domain;
                                                   >> 487 struct fwnode_handle;
388 int its_cpu_init(void);                           488 int its_cpu_init(void);
389 int its_init(struct device_node *node, struct  !! 489 int its_init(struct fwnode_handle *handle, struct rdists *rdists,
390              struct irq_domain *domain);          490              struct irq_domain *domain);
                                                   >> 491 
                                                   >> 492 static inline bool gic_enable_sre(void)
                                                   >> 493 {
                                                   >> 494         u32 val;
                                                   >> 495 
                                                   >> 496         val = gic_read_sre();
                                                   >> 497         if (val & ICC_SRE_EL1_SRE)
                                                   >> 498                 return true;
                                                   >> 499 
                                                   >> 500         val |= ICC_SRE_EL1_SRE;
                                                   >> 501         gic_write_sre(val);
                                                   >> 502         val = gic_read_sre();
                                                   >> 503 
                                                   >> 504         return !!(val & ICC_SRE_EL1_SRE);
                                                   >> 505 }
391                                                   506 
392 #endif                                            507 #endif
393                                                   508 
394 #endif                                            509 #endif
395                                                   510 

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