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Linux/arch/arm/common/edma.c

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  1 /*
  2  * EDMA3 support for DaVinci
  3  *
  4  * Copyright (C) 2006-2009 Texas Instruments.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * You should have received a copy of the GNU General Public License
 17  * along with this program; if not, write to the Free Software
 18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 19  */
 20 #include <linux/err.h>
 21 #include <linux/kernel.h>
 22 #include <linux/init.h>
 23 #include <linux/module.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/io.h>
 27 #include <linux/slab.h>
 28 #include <linux/edma.h>
 29 #include <linux/of_address.h>
 30 #include <linux/of_device.h>
 31 #include <linux/of_dma.h>
 32 #include <linux/of_irq.h>
 33 #include <linux/pm_runtime.h>
 34 
 35 #include <linux/platform_data/edma.h>
 36 
 37 /* Offsets matching "struct edmacc_param" */
 38 #define PARM_OPT                0x00
 39 #define PARM_SRC                0x04
 40 #define PARM_A_B_CNT            0x08
 41 #define PARM_DST                0x0c
 42 #define PARM_SRC_DST_BIDX       0x10
 43 #define PARM_LINK_BCNTRLD       0x14
 44 #define PARM_SRC_DST_CIDX       0x18
 45 #define PARM_CCNT               0x1c
 46 
 47 #define PARM_SIZE               0x20
 48 
 49 /* Offsets for EDMA CC global channel registers and their shadows */
 50 #define SH_ER           0x00    /* 64 bits */
 51 #define SH_ECR          0x08    /* 64 bits */
 52 #define SH_ESR          0x10    /* 64 bits */
 53 #define SH_CER          0x18    /* 64 bits */
 54 #define SH_EER          0x20    /* 64 bits */
 55 #define SH_EECR         0x28    /* 64 bits */
 56 #define SH_EESR         0x30    /* 64 bits */
 57 #define SH_SER          0x38    /* 64 bits */
 58 #define SH_SECR         0x40    /* 64 bits */
 59 #define SH_IER          0x50    /* 64 bits */
 60 #define SH_IECR         0x58    /* 64 bits */
 61 #define SH_IESR         0x60    /* 64 bits */
 62 #define SH_IPR          0x68    /* 64 bits */
 63 #define SH_ICR          0x70    /* 64 bits */
 64 #define SH_IEVAL        0x78
 65 #define SH_QER          0x80
 66 #define SH_QEER         0x84
 67 #define SH_QEECR        0x88
 68 #define SH_QEESR        0x8c
 69 #define SH_QSER         0x90
 70 #define SH_QSECR        0x94
 71 #define SH_SIZE         0x200
 72 
 73 /* Offsets for EDMA CC global registers */
 74 #define EDMA_REV        0x0000
 75 #define EDMA_CCCFG      0x0004
 76 #define EDMA_QCHMAP     0x0200  /* 8 registers */
 77 #define EDMA_DMAQNUM    0x0240  /* 8 registers (4 on OMAP-L1xx) */
 78 #define EDMA_QDMAQNUM   0x0260
 79 #define EDMA_QUETCMAP   0x0280
 80 #define EDMA_QUEPRI     0x0284
 81 #define EDMA_EMR        0x0300  /* 64 bits */
 82 #define EDMA_EMCR       0x0308  /* 64 bits */
 83 #define EDMA_QEMR       0x0310
 84 #define EDMA_QEMCR      0x0314
 85 #define EDMA_CCERR      0x0318
 86 #define EDMA_CCERRCLR   0x031c
 87 #define EDMA_EEVAL      0x0320
 88 #define EDMA_DRAE       0x0340  /* 4 x 64 bits*/
 89 #define EDMA_QRAE       0x0380  /* 4 registers */
 90 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
 91 #define EDMA_QSTAT      0x0600  /* 2 registers */
 92 #define EDMA_QWMTHRA    0x0620
 93 #define EDMA_QWMTHRB    0x0624
 94 #define EDMA_CCSTAT     0x0640
 95 
 96 #define EDMA_M          0x1000  /* global channel registers */
 97 #define EDMA_ECR        0x1008
 98 #define EDMA_ECRH       0x100C
 99 #define EDMA_SHADOW0    0x2000  /* 4 regions shadowing global channels */
100 #define EDMA_PARM       0x4000  /* 128 param entries */
101 
102 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
103 
104 #define EDMA_DCHMAP     0x0100  /* 64 registers */
105 
106 /* CCCFG register */
107 #define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
108 #define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
109 #define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
110 #define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
111 #define CHMAP_EXIST             BIT(24)
112 
113 #define EDMA_MAX_DMACH           64
114 #define EDMA_MAX_PARAMENTRY     512
115 
116 /*****************************************************************************/
117 
118 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
119 
120 static inline unsigned int edma_read(unsigned ctlr, int offset)
121 {
122         return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
123 }
124 
125 static inline void edma_write(unsigned ctlr, int offset, int val)
126 {
127         __raw_writel(val, edmacc_regs_base[ctlr] + offset);
128 }
129 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
130                 unsigned or)
131 {
132         unsigned val = edma_read(ctlr, offset);
133         val &= and;
134         val |= or;
135         edma_write(ctlr, offset, val);
136 }
137 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
138 {
139         unsigned val = edma_read(ctlr, offset);
140         val &= and;
141         edma_write(ctlr, offset, val);
142 }
143 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
144 {
145         unsigned val = edma_read(ctlr, offset);
146         val |= or;
147         edma_write(ctlr, offset, val);
148 }
149 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
150 {
151         return edma_read(ctlr, offset + (i << 2));
152 }
153 static inline void edma_write_array(unsigned ctlr, int offset, int i,
154                 unsigned val)
155 {
156         edma_write(ctlr, offset + (i << 2), val);
157 }
158 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
159                 unsigned and, unsigned or)
160 {
161         edma_modify(ctlr, offset + (i << 2), and, or);
162 }
163 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
164 {
165         edma_or(ctlr, offset + (i << 2), or);
166 }
167 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
168                 unsigned or)
169 {
170         edma_or(ctlr, offset + ((i*2 + j) << 2), or);
171 }
172 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
173                 unsigned val)
174 {
175         edma_write(ctlr, offset + ((i*2 + j) << 2), val);
176 }
177 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
178 {
179         return edma_read(ctlr, EDMA_SHADOW0 + offset);
180 }
181 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
182                 int i)
183 {
184         return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
185 }
186 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
187 {
188         edma_write(ctlr, EDMA_SHADOW0 + offset, val);
189 }
190 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
191                 unsigned val)
192 {
193         edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
194 }
195 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
196                 int param_no)
197 {
198         return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
199 }
200 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
201                 unsigned val)
202 {
203         edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
204 }
205 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
206                 unsigned and, unsigned or)
207 {
208         edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
209 }
210 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
211                 unsigned and)
212 {
213         edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
214 }
215 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
216                 unsigned or)
217 {
218         edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
219 }
220 
221 static inline void set_bits(int offset, int len, unsigned long *p)
222 {
223         for (; len > 0; len--)
224                 set_bit(offset + (len - 1), p);
225 }
226 
227 static inline void clear_bits(int offset, int len, unsigned long *p)
228 {
229         for (; len > 0; len--)
230                 clear_bit(offset + (len - 1), p);
231 }
232 
233 /*****************************************************************************/
234 
235 /* actual number of DMA channels and slots on this silicon */
236 struct edma {
237         /* how many dma resources of each type */
238         unsigned        num_channels;
239         unsigned        num_region;
240         unsigned        num_slots;
241         unsigned        num_tc;
242         enum dma_event_q        default_queue;
243 
244         /* list of channels with no even trigger; terminated by "-1" */
245         const s8        *noevent;
246 
247         /* The edma_inuse bit for each PaRAM slot is clear unless the
248          * channel is in use ... by ARM or DSP, for QDMA, or whatever.
249          */
250         DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
251 
252         /* The edma_unused bit for each channel is clear unless
253          * it is not being used on this platform. It uses a bit
254          * of SOC-specific initialization code.
255          */
256         DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
257 
258         unsigned        irq_res_start;
259         unsigned        irq_res_end;
260 
261         struct dma_interrupt_data {
262                 void (*callback)(unsigned channel, unsigned short ch_status,
263                                 void *data);
264                 void *data;
265         } intr_data[EDMA_MAX_DMACH];
266 };
267 
268 static struct edma *edma_cc[EDMA_MAX_CC];
269 static int arch_num_cc;
270 
271 /* dummy param set used to (re)initialize parameter RAM slots */
272 static const struct edmacc_param dummy_paramset = {
273         .link_bcntrld = 0xffff,
274         .ccnt = 1,
275 };
276 
277 static const struct of_device_id edma_of_ids[] = {
278         { .compatible = "ti,edma3", },
279         {}
280 };
281 
282 /*****************************************************************************/
283 
284 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
285                 enum dma_event_q queue_no)
286 {
287         int bit = (ch_no & 0x7) * 4;
288 
289         /* default to low priority queue */
290         if (queue_no == EVENTQ_DEFAULT)
291                 queue_no = edma_cc[ctlr]->default_queue;
292 
293         queue_no &= 7;
294         edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
295                         ~(0x7 << bit), queue_no << bit);
296 }
297 
298 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
299                 int priority)
300 {
301         int bit = queue_no * 4;
302         edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
303                         ((priority & 0x7) << bit));
304 }
305 
306 /**
307  * map_dmach_param - Maps channel number to param entry number
308  *
309  * This maps the dma channel number to param entry numberter. In
310  * other words using the DMA channel mapping registers a param entry
311  * can be mapped to any channel
312  *
313  * Callers are responsible for ensuring the channel mapping logic is
314  * included in that particular EDMA variant (Eg : dm646x)
315  *
316  */
317 static void __init map_dmach_param(unsigned ctlr)
318 {
319         int i;
320         for (i = 0; i < EDMA_MAX_DMACH; i++)
321                 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
322 }
323 
324 static inline void
325 setup_dma_interrupt(unsigned lch,
326         void (*callback)(unsigned channel, u16 ch_status, void *data),
327         void *data)
328 {
329         unsigned ctlr;
330 
331         ctlr = EDMA_CTLR(lch);
332         lch = EDMA_CHAN_SLOT(lch);
333 
334         if (!callback)
335                 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
336                                 BIT(lch & 0x1f));
337 
338         edma_cc[ctlr]->intr_data[lch].callback = callback;
339         edma_cc[ctlr]->intr_data[lch].data = data;
340 
341         if (callback) {
342                 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
343                                 BIT(lch & 0x1f));
344                 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
345                                 BIT(lch & 0x1f));
346         }
347 }
348 
349 static int irq2ctlr(int irq)
350 {
351         if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
352                 return 0;
353         else if (irq >= edma_cc[1]->irq_res_start &&
354                 irq <= edma_cc[1]->irq_res_end)
355                 return 1;
356 
357         return -1;
358 }
359 
360 /******************************************************************************
361  *
362  * DMA interrupt handler
363  *
364  *****************************************************************************/
365 static irqreturn_t dma_irq_handler(int irq, void *data)
366 {
367         int ctlr;
368         u32 sh_ier;
369         u32 sh_ipr;
370         u32 bank;
371 
372         ctlr = irq2ctlr(irq);
373         if (ctlr < 0)
374                 return IRQ_NONE;
375 
376         dev_dbg(data, "dma_irq_handler\n");
377 
378         sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
379         if (!sh_ipr) {
380                 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
381                 if (!sh_ipr)
382                         return IRQ_NONE;
383                 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
384                 bank = 1;
385         } else {
386                 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
387                 bank = 0;
388         }
389 
390         do {
391                 u32 slot;
392                 u32 channel;
393 
394                 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
395 
396                 slot = __ffs(sh_ipr);
397                 sh_ipr &= ~(BIT(slot));
398 
399                 if (sh_ier & BIT(slot)) {
400                         channel = (bank << 5) | slot;
401                         /* Clear the corresponding IPR bits */
402                         edma_shadow0_write_array(ctlr, SH_ICR, bank,
403                                         BIT(slot));
404                         if (edma_cc[ctlr]->intr_data[channel].callback)
405                                 edma_cc[ctlr]->intr_data[channel].callback(
406                                         EDMA_CTLR_CHAN(ctlr, channel),
407                                         EDMA_DMA_COMPLETE,
408                                         edma_cc[ctlr]->intr_data[channel].data);
409                 }
410         } while (sh_ipr);
411 
412         edma_shadow0_write(ctlr, SH_IEVAL, 1);
413         return IRQ_HANDLED;
414 }
415 
416 /******************************************************************************
417  *
418  * DMA error interrupt handler
419  *
420  *****************************************************************************/
421 static irqreturn_t dma_ccerr_handler(int irq, void *data)
422 {
423         int i;
424         int ctlr;
425         unsigned int cnt = 0;
426 
427         ctlr = irq2ctlr(irq);
428         if (ctlr < 0)
429                 return IRQ_NONE;
430 
431         dev_dbg(data, "dma_ccerr_handler\n");
432 
433         if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
434             (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
435             (edma_read(ctlr, EDMA_QEMR) == 0) &&
436             (edma_read(ctlr, EDMA_CCERR) == 0))
437                 return IRQ_NONE;
438 
439         while (1) {
440                 int j = -1;
441                 if (edma_read_array(ctlr, EDMA_EMR, 0))
442                         j = 0;
443                 else if (edma_read_array(ctlr, EDMA_EMR, 1))
444                         j = 1;
445                 if (j >= 0) {
446                         dev_dbg(data, "EMR%d %08x\n", j,
447                                         edma_read_array(ctlr, EDMA_EMR, j));
448                         for (i = 0; i < 32; i++) {
449                                 int k = (j << 5) + i;
450                                 if (edma_read_array(ctlr, EDMA_EMR, j) &
451                                                         BIT(i)) {
452                                         /* Clear the corresponding EMR bits */
453                                         edma_write_array(ctlr, EDMA_EMCR, j,
454                                                         BIT(i));
455                                         /* Clear any SER */
456                                         edma_shadow0_write_array(ctlr, SH_SECR,
457                                                                 j, BIT(i));
458                                         if (edma_cc[ctlr]->intr_data[k].
459                                                                 callback) {
460                                                 edma_cc[ctlr]->intr_data[k].
461                                                 callback(
462                                                 EDMA_CTLR_CHAN(ctlr, k),
463                                                 EDMA_DMA_CC_ERROR,
464                                                 edma_cc[ctlr]->intr_data
465                                                 [k].data);
466                                         }
467                                 }
468                         }
469                 } else if (edma_read(ctlr, EDMA_QEMR)) {
470                         dev_dbg(data, "QEMR %02x\n",
471                                 edma_read(ctlr, EDMA_QEMR));
472                         for (i = 0; i < 8; i++) {
473                                 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
474                                         /* Clear the corresponding IPR bits */
475                                         edma_write(ctlr, EDMA_QEMCR, BIT(i));
476                                         edma_shadow0_write(ctlr, SH_QSECR,
477                                                                 BIT(i));
478 
479                                         /* NOTE:  not reported!! */
480                                 }
481                         }
482                 } else if (edma_read(ctlr, EDMA_CCERR)) {
483                         dev_dbg(data, "CCERR %08x\n",
484                                 edma_read(ctlr, EDMA_CCERR));
485                         /* FIXME:  CCERR.BIT(16) ignored!  much better
486                          * to just write CCERRCLR with CCERR value...
487                          */
488                         for (i = 0; i < 8; i++) {
489                                 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
490                                         /* Clear the corresponding IPR bits */
491                                         edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
492 
493                                         /* NOTE:  not reported!! */
494                                 }
495                         }
496                 }
497                 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
498                     (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
499                     (edma_read(ctlr, EDMA_QEMR) == 0) &&
500                     (edma_read(ctlr, EDMA_CCERR) == 0))
501                         break;
502                 cnt++;
503                 if (cnt > 10)
504                         break;
505         }
506         edma_write(ctlr, EDMA_EEVAL, 1);
507         return IRQ_HANDLED;
508 }
509 
510 static int reserve_contiguous_slots(int ctlr, unsigned int id,
511                                      unsigned int num_slots,
512                                      unsigned int start_slot)
513 {
514         int i, j;
515         unsigned int count = num_slots;
516         int stop_slot = start_slot;
517         DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
518 
519         for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
520                 j = EDMA_CHAN_SLOT(i);
521                 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
522                         /* Record our current beginning slot */
523                         if (count == num_slots)
524                                 stop_slot = i;
525 
526                         count--;
527                         set_bit(j, tmp_inuse);
528 
529                         if (count == 0)
530                                 break;
531                 } else {
532                         clear_bit(j, tmp_inuse);
533 
534                         if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
535                                 stop_slot = i;
536                                 break;
537                         } else {
538                                 count = num_slots;
539                         }
540                 }
541         }
542 
543         /*
544          * We have to clear any bits that we set
545          * if we run out parameter RAM slots, i.e we do find a set
546          * of contiguous parameter RAM slots but do not find the exact number
547          * requested as we may reach the total number of parameter RAM slots
548          */
549         if (i == edma_cc[ctlr]->num_slots)
550                 stop_slot = i;
551 
552         j = start_slot;
553         for_each_set_bit_from(j, tmp_inuse, stop_slot)
554                 clear_bit(j, edma_cc[ctlr]->edma_inuse);
555 
556         if (count)
557                 return -EBUSY;
558 
559         for (j = i - num_slots + 1; j <= i; ++j)
560                 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
561                         &dummy_paramset, PARM_SIZE);
562 
563         return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
564 }
565 
566 static int prepare_unused_channel_list(struct device *dev, void *data)
567 {
568         struct platform_device *pdev = to_platform_device(dev);
569         int i, count, ctlr;
570         struct of_phandle_args  dma_spec;
571 
572         if (dev->of_node) {
573                 count = of_property_count_strings(dev->of_node, "dma-names");
574                 if (count < 0)
575                         return 0;
576                 for (i = 0; i < count; i++) {
577                         if (of_parse_phandle_with_args(dev->of_node, "dmas",
578                                                        "#dma-cells", i,
579                                                        &dma_spec))
580                                 continue;
581 
582                         if (!of_match_node(edma_of_ids, dma_spec.np)) {
583                                 of_node_put(dma_spec.np);
584                                 continue;
585                         }
586 
587                         clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
588                                   edma_cc[0]->edma_unused);
589                         of_node_put(dma_spec.np);
590                 }
591                 return 0;
592         }
593 
594         /* For non-OF case */
595         for (i = 0; i < pdev->num_resources; i++) {
596                 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
597                                 (int)pdev->resource[i].start >= 0) {
598                         ctlr = EDMA_CTLR(pdev->resource[i].start);
599                         clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
600                                   edma_cc[ctlr]->edma_unused);
601                 }
602         }
603 
604         return 0;
605 }
606 
607 /*-----------------------------------------------------------------------*/
608 
609 static bool unused_chan_list_done;
610 
611 /* Resource alloc/free:  dma channels, parameter RAM slots */
612 
613 /**
614  * edma_alloc_channel - allocate DMA channel and paired parameter RAM
615  * @channel: specific channel to allocate; negative for "any unmapped channel"
616  * @callback: optional; to be issued on DMA completion or errors
617  * @data: passed to callback
618  * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
619  *      Controller (TC) executes requests using this channel.  Use
620  *      EVENTQ_DEFAULT unless you really need a high priority queue.
621  *
622  * This allocates a DMA channel and its associated parameter RAM slot.
623  * The parameter RAM is initialized to hold a dummy transfer.
624  *
625  * Normal use is to pass a specific channel number as @channel, to make
626  * use of hardware events mapped to that channel.  When the channel will
627  * be used only for software triggering or event chaining, channels not
628  * mapped to hardware events (or mapped to unused events) are preferable.
629  *
630  * DMA transfers start from a channel using edma_start(), or by
631  * chaining.  When the transfer described in that channel's parameter RAM
632  * slot completes, that slot's data may be reloaded through a link.
633  *
634  * DMA errors are only reported to the @callback associated with the
635  * channel driving that transfer, but transfer completion callbacks can
636  * be sent to another channel under control of the TCC field in
637  * the option word of the transfer's parameter RAM set.  Drivers must not
638  * use DMA transfer completion callbacks for channels they did not allocate.
639  * (The same applies to TCC codes used in transfer chaining.)
640  *
641  * Returns the number of the channel, else negative errno.
642  */
643 int edma_alloc_channel(int channel,
644                 void (*callback)(unsigned channel, u16 ch_status, void *data),
645                 void *data,
646                 enum dma_event_q eventq_no)
647 {
648         unsigned i, done = 0, ctlr = 0;
649         int ret = 0;
650 
651         if (!unused_chan_list_done) {
652                 /*
653                  * Scan all the platform devices to find out the EDMA channels
654                  * used and clear them in the unused list, making the rest
655                  * available for ARM usage.
656                  */
657                 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
658                                 prepare_unused_channel_list);
659                 if (ret < 0)
660                         return ret;
661 
662                 unused_chan_list_done = true;
663         }
664 
665         if (channel >= 0) {
666                 ctlr = EDMA_CTLR(channel);
667                 channel = EDMA_CHAN_SLOT(channel);
668         }
669 
670         if (channel < 0) {
671                 for (i = 0; i < arch_num_cc; i++) {
672                         channel = 0;
673                         for (;;) {
674                                 channel = find_next_bit(edma_cc[i]->edma_unused,
675                                                 edma_cc[i]->num_channels,
676                                                 channel);
677                                 if (channel == edma_cc[i]->num_channels)
678                                         break;
679                                 if (!test_and_set_bit(channel,
680                                                 edma_cc[i]->edma_inuse)) {
681                                         done = 1;
682                                         ctlr = i;
683                                         break;
684                                 }
685                                 channel++;
686                         }
687                         if (done)
688                                 break;
689                 }
690                 if (!done)
691                         return -ENOMEM;
692         } else if (channel >= edma_cc[ctlr]->num_channels) {
693                 return -EINVAL;
694         } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
695                 return -EBUSY;
696         }
697 
698         /* ensure access through shadow region 0 */
699         edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
700 
701         /* ensure no events are pending */
702         edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
703         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
704                         &dummy_paramset, PARM_SIZE);
705 
706         if (callback)
707                 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
708                                         callback, data);
709 
710         map_dmach_queue(ctlr, channel, eventq_no);
711 
712         return EDMA_CTLR_CHAN(ctlr, channel);
713 }
714 EXPORT_SYMBOL(edma_alloc_channel);
715 
716 
717 /**
718  * edma_free_channel - deallocate DMA channel
719  * @channel: dma channel returned from edma_alloc_channel()
720  *
721  * This deallocates the DMA channel and associated parameter RAM slot
722  * allocated by edma_alloc_channel().
723  *
724  * Callers are responsible for ensuring the channel is inactive, and
725  * will not be reactivated by linking, chaining, or software calls to
726  * edma_start().
727  */
728 void edma_free_channel(unsigned channel)
729 {
730         unsigned ctlr;
731 
732         ctlr = EDMA_CTLR(channel);
733         channel = EDMA_CHAN_SLOT(channel);
734 
735         if (channel >= edma_cc[ctlr]->num_channels)
736                 return;
737 
738         setup_dma_interrupt(channel, NULL, NULL);
739         /* REVISIT should probably take out of shadow region 0 */
740 
741         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
742                         &dummy_paramset, PARM_SIZE);
743         clear_bit(channel, edma_cc[ctlr]->edma_inuse);
744 }
745 EXPORT_SYMBOL(edma_free_channel);
746 
747 /**
748  * edma_alloc_slot - allocate DMA parameter RAM
749  * @slot: specific slot to allocate; negative for "any unused slot"
750  *
751  * This allocates a parameter RAM slot, initializing it to hold a
752  * dummy transfer.  Slots allocated using this routine have not been
753  * mapped to a hardware DMA channel, and will normally be used by
754  * linking to them from a slot associated with a DMA channel.
755  *
756  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
757  * slots may be allocated on behalf of DSP firmware.
758  *
759  * Returns the number of the slot, else negative errno.
760  */
761 int edma_alloc_slot(unsigned ctlr, int slot)
762 {
763         if (!edma_cc[ctlr])
764                 return -EINVAL;
765 
766         if (slot >= 0)
767                 slot = EDMA_CHAN_SLOT(slot);
768 
769         if (slot < 0) {
770                 slot = edma_cc[ctlr]->num_channels;
771                 for (;;) {
772                         slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
773                                         edma_cc[ctlr]->num_slots, slot);
774                         if (slot == edma_cc[ctlr]->num_slots)
775                                 return -ENOMEM;
776                         if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
777                                 break;
778                 }
779         } else if (slot < edma_cc[ctlr]->num_channels ||
780                         slot >= edma_cc[ctlr]->num_slots) {
781                 return -EINVAL;
782         } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
783                 return -EBUSY;
784         }
785 
786         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
787                         &dummy_paramset, PARM_SIZE);
788 
789         return EDMA_CTLR_CHAN(ctlr, slot);
790 }
791 EXPORT_SYMBOL(edma_alloc_slot);
792 
793 /**
794  * edma_free_slot - deallocate DMA parameter RAM
795  * @slot: parameter RAM slot returned from edma_alloc_slot()
796  *
797  * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
798  * Callers are responsible for ensuring the slot is inactive, and will
799  * not be activated.
800  */
801 void edma_free_slot(unsigned slot)
802 {
803         unsigned ctlr;
804 
805         ctlr = EDMA_CTLR(slot);
806         slot = EDMA_CHAN_SLOT(slot);
807 
808         if (slot < edma_cc[ctlr]->num_channels ||
809                 slot >= edma_cc[ctlr]->num_slots)
810                 return;
811 
812         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
813                         &dummy_paramset, PARM_SIZE);
814         clear_bit(slot, edma_cc[ctlr]->edma_inuse);
815 }
816 EXPORT_SYMBOL(edma_free_slot);
817 
818 
819 /**
820  * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
821  * The API will return the starting point of a set of
822  * contiguous parameter RAM slots that have been requested
823  *
824  * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
825  * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
826  * @count: number of contiguous Paramter RAM slots
827  * @slot  - the start value of Parameter RAM slot that should be passed if id
828  * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
829  *
830  * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
831  * contiguous Parameter RAM slots from parameter RAM 64 in the case of
832  * DaVinci SOCs and 32 in the case of DA8xx SOCs.
833  *
834  * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
835  * set of contiguous parameter RAM slots from the "slot" that is passed as an
836  * argument to the API.
837  *
838  * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
839  * starts looking for a set of contiguous parameter RAMs from the "slot"
840  * that is passed as an argument to the API. On failure the API will try to
841  * find a set of contiguous Parameter RAM slots from the remaining Parameter
842  * RAM slots
843  */
844 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
845 {
846         /*
847          * The start slot requested should be greater than
848          * the number of channels and lesser than the total number
849          * of slots
850          */
851         if ((id != EDMA_CONT_PARAMS_ANY) &&
852                 (slot < edma_cc[ctlr]->num_channels ||
853                 slot >= edma_cc[ctlr]->num_slots))
854                 return -EINVAL;
855 
856         /*
857          * The number of parameter RAM slots requested cannot be less than 1
858          * and cannot be more than the number of slots minus the number of
859          * channels
860          */
861         if (count < 1 || count >
862                 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
863                 return -EINVAL;
864 
865         switch (id) {
866         case EDMA_CONT_PARAMS_ANY:
867                 return reserve_contiguous_slots(ctlr, id, count,
868                                                  edma_cc[ctlr]->num_channels);
869         case EDMA_CONT_PARAMS_FIXED_EXACT:
870         case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
871                 return reserve_contiguous_slots(ctlr, id, count, slot);
872         default:
873                 return -EINVAL;
874         }
875 
876 }
877 EXPORT_SYMBOL(edma_alloc_cont_slots);
878 
879 /**
880  * edma_free_cont_slots - deallocate DMA parameter RAM slots
881  * @slot: first parameter RAM of a set of parameter RAM slots to be freed
882  * @count: the number of contiguous parameter RAM slots to be freed
883  *
884  * This deallocates the parameter RAM slots allocated by
885  * edma_alloc_cont_slots.
886  * Callers/applications need to keep track of sets of contiguous
887  * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
888  * API.
889  * Callers are responsible for ensuring the slots are inactive, and will
890  * not be activated.
891  */
892 int edma_free_cont_slots(unsigned slot, int count)
893 {
894         unsigned ctlr, slot_to_free;
895         int i;
896 
897         ctlr = EDMA_CTLR(slot);
898         slot = EDMA_CHAN_SLOT(slot);
899 
900         if (slot < edma_cc[ctlr]->num_channels ||
901                 slot >= edma_cc[ctlr]->num_slots ||
902                 count < 1)
903                 return -EINVAL;
904 
905         for (i = slot; i < slot + count; ++i) {
906                 ctlr = EDMA_CTLR(i);
907                 slot_to_free = EDMA_CHAN_SLOT(i);
908 
909                 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
910                         &dummy_paramset, PARM_SIZE);
911                 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
912         }
913 
914         return 0;
915 }
916 EXPORT_SYMBOL(edma_free_cont_slots);
917 
918 /*-----------------------------------------------------------------------*/
919 
920 /* Parameter RAM operations (i) -- read/write partial slots */
921 
922 /**
923  * edma_set_src - set initial DMA source address in parameter RAM slot
924  * @slot: parameter RAM slot being configured
925  * @src_port: physical address of source (memory, controller FIFO, etc)
926  * @addressMode: INCR, except in very rare cases
927  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
928  *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
929  *
930  * Note that the source address is modified during the DMA transfer
931  * according to edma_set_src_index().
932  */
933 void edma_set_src(unsigned slot, dma_addr_t src_port,
934                                 enum address_mode mode, enum fifo_width width)
935 {
936         unsigned ctlr;
937 
938         ctlr = EDMA_CTLR(slot);
939         slot = EDMA_CHAN_SLOT(slot);
940 
941         if (slot < edma_cc[ctlr]->num_slots) {
942                 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
943 
944                 if (mode) {
945                         /* set SAM and program FWID */
946                         i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
947                 } else {
948                         /* clear SAM */
949                         i &= ~SAM;
950                 }
951                 edma_parm_write(ctlr, PARM_OPT, slot, i);
952 
953                 /* set the source port address
954                    in source register of param structure */
955                 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
956         }
957 }
958 EXPORT_SYMBOL(edma_set_src);
959 
960 /**
961  * edma_set_dest - set initial DMA destination address in parameter RAM slot
962  * @slot: parameter RAM slot being configured
963  * @dest_port: physical address of destination (memory, controller FIFO, etc)
964  * @addressMode: INCR, except in very rare cases
965  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
966  *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
967  *
968  * Note that the destination address is modified during the DMA transfer
969  * according to edma_set_dest_index().
970  */
971 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
972                                  enum address_mode mode, enum fifo_width width)
973 {
974         unsigned ctlr;
975 
976         ctlr = EDMA_CTLR(slot);
977         slot = EDMA_CHAN_SLOT(slot);
978 
979         if (slot < edma_cc[ctlr]->num_slots) {
980                 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
981 
982                 if (mode) {
983                         /* set DAM and program FWID */
984                         i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
985                 } else {
986                         /* clear DAM */
987                         i &= ~DAM;
988                 }
989                 edma_parm_write(ctlr, PARM_OPT, slot, i);
990                 /* set the destination port address
991                    in dest register of param structure */
992                 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
993         }
994 }
995 EXPORT_SYMBOL(edma_set_dest);
996 
997 /**
998  * edma_get_position - returns the current transfer point
999  * @slot: parameter RAM slot being examined
1000  * @dst:  true selects the dest position, false the source
1001  *
1002  * Returns the position of the current active slot
1003  */
1004 dma_addr_t edma_get_position(unsigned slot, bool dst)
1005 {
1006         u32 offs, ctlr = EDMA_CTLR(slot);
1007 
1008         slot = EDMA_CHAN_SLOT(slot);
1009 
1010         offs = PARM_OFFSET(slot);
1011         offs += dst ? PARM_DST : PARM_SRC;
1012 
1013         return edma_read(ctlr, offs);
1014 }
1015 
1016 /**
1017  * edma_set_src_index - configure DMA source address indexing
1018  * @slot: parameter RAM slot being configured
1019  * @src_bidx: byte offset between source arrays in a frame
1020  * @src_cidx: byte offset between source frames in a block
1021  *
1022  * Offsets are specified to support either contiguous or discontiguous
1023  * memory transfers, or repeated access to a hardware register, as needed.
1024  * When accessing hardware registers, both offsets are normally zero.
1025  */
1026 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1027 {
1028         unsigned ctlr;
1029 
1030         ctlr = EDMA_CTLR(slot);
1031         slot = EDMA_CHAN_SLOT(slot);
1032 
1033         if (slot < edma_cc[ctlr]->num_slots) {
1034                 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1035                                 0xffff0000, src_bidx);
1036                 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1037                                 0xffff0000, src_cidx);
1038         }
1039 }
1040 EXPORT_SYMBOL(edma_set_src_index);
1041 
1042 /**
1043  * edma_set_dest_index - configure DMA destination address indexing
1044  * @slot: parameter RAM slot being configured
1045  * @dest_bidx: byte offset between destination arrays in a frame
1046  * @dest_cidx: byte offset between destination frames in a block
1047  *
1048  * Offsets are specified to support either contiguous or discontiguous
1049  * memory transfers, or repeated access to a hardware register, as needed.
1050  * When accessing hardware registers, both offsets are normally zero.
1051  */
1052 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1053 {
1054         unsigned ctlr;
1055 
1056         ctlr = EDMA_CTLR(slot);
1057         slot = EDMA_CHAN_SLOT(slot);
1058 
1059         if (slot < edma_cc[ctlr]->num_slots) {
1060                 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1061                                 0x0000ffff, dest_bidx << 16);
1062                 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1063                                 0x0000ffff, dest_cidx << 16);
1064         }
1065 }
1066 EXPORT_SYMBOL(edma_set_dest_index);
1067 
1068 /**
1069  * edma_set_transfer_params - configure DMA transfer parameters
1070  * @slot: parameter RAM slot being configured
1071  * @acnt: how many bytes per array (at least one)
1072  * @bcnt: how many arrays per frame (at least one)
1073  * @ccnt: how many frames per block (at least one)
1074  * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1075  *      the value to reload into bcnt when it decrements to zero
1076  * @sync_mode: ASYNC or ABSYNC
1077  *
1078  * See the EDMA3 documentation to understand how to configure and link
1079  * transfers using the fields in PaRAM slots.  If you are not doing it
1080  * all at once with edma_write_slot(), you will use this routine
1081  * plus two calls each for source and destination, setting the initial
1082  * address and saying how to index that address.
1083  *
1084  * An example of an A-Synchronized transfer is a serial link using a
1085  * single word shift register.  In that case, @acnt would be equal to
1086  * that word size; the serial controller issues a DMA synchronization
1087  * event to transfer each word, and memory access by the DMA transfer
1088  * controller will be word-at-a-time.
1089  *
1090  * An example of an AB-Synchronized transfer is a device using a FIFO.
1091  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1092  * The controller with the FIFO issues DMA synchronization events when
1093  * the FIFO threshold is reached, and the DMA transfer controller will
1094  * transfer one frame to (or from) the FIFO.  It will probably use
1095  * efficient burst modes to access memory.
1096  */
1097 void edma_set_transfer_params(unsigned slot,
1098                 u16 acnt, u16 bcnt, u16 ccnt,
1099                 u16 bcnt_rld, enum sync_dimension sync_mode)
1100 {
1101         unsigned ctlr;
1102 
1103         ctlr = EDMA_CTLR(slot);
1104         slot = EDMA_CHAN_SLOT(slot);
1105 
1106         if (slot < edma_cc[ctlr]->num_slots) {
1107                 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1108                                 0x0000ffff, bcnt_rld << 16);
1109                 if (sync_mode == ASYNC)
1110                         edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1111                 else
1112                         edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1113                 /* Set the acount, bcount, ccount registers */
1114                 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1115                 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1116         }
1117 }
1118 EXPORT_SYMBOL(edma_set_transfer_params);
1119 
1120 /**
1121  * edma_link - link one parameter RAM slot to another
1122  * @from: parameter RAM slot originating the link
1123  * @to: parameter RAM slot which is the link target
1124  *
1125  * The originating slot should not be part of any active DMA transfer.
1126  */
1127 void edma_link(unsigned from, unsigned to)
1128 {
1129         unsigned ctlr_from, ctlr_to;
1130 
1131         ctlr_from = EDMA_CTLR(from);
1132         from = EDMA_CHAN_SLOT(from);
1133         ctlr_to = EDMA_CTLR(to);
1134         to = EDMA_CHAN_SLOT(to);
1135 
1136         if (from >= edma_cc[ctlr_from]->num_slots)
1137                 return;
1138         if (to >= edma_cc[ctlr_to]->num_slots)
1139                 return;
1140         edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1141                                 PARM_OFFSET(to));
1142 }
1143 EXPORT_SYMBOL(edma_link);
1144 
1145 /**
1146  * edma_unlink - cut link from one parameter RAM slot
1147  * @from: parameter RAM slot originating the link
1148  *
1149  * The originating slot should not be part of any active DMA transfer.
1150  * Its link is set to 0xffff.
1151  */
1152 void edma_unlink(unsigned from)
1153 {
1154         unsigned ctlr;
1155 
1156         ctlr = EDMA_CTLR(from);
1157         from = EDMA_CHAN_SLOT(from);
1158 
1159         if (from >= edma_cc[ctlr]->num_slots)
1160                 return;
1161         edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1162 }
1163 EXPORT_SYMBOL(edma_unlink);
1164 
1165 /*-----------------------------------------------------------------------*/
1166 
1167 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1168 
1169 /**
1170  * edma_write_slot - write parameter RAM data for slot
1171  * @slot: number of parameter RAM slot being modified
1172  * @param: data to be written into parameter RAM slot
1173  *
1174  * Use this to assign all parameters of a transfer at once.  This
1175  * allows more efficient setup of transfers than issuing multiple
1176  * calls to set up those parameters in small pieces, and provides
1177  * complete control over all transfer options.
1178  */
1179 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1180 {
1181         unsigned ctlr;
1182 
1183         ctlr = EDMA_CTLR(slot);
1184         slot = EDMA_CHAN_SLOT(slot);
1185 
1186         if (slot >= edma_cc[ctlr]->num_slots)
1187                 return;
1188         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1189                         PARM_SIZE);
1190 }
1191 EXPORT_SYMBOL(edma_write_slot);
1192 
1193 /**
1194  * edma_read_slot - read parameter RAM data from slot
1195  * @slot: number of parameter RAM slot being copied
1196  * @param: where to store copy of parameter RAM data
1197  *
1198  * Use this to read data from a parameter RAM slot, perhaps to
1199  * save them as a template for later reuse.
1200  */
1201 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1202 {
1203         unsigned ctlr;
1204 
1205         ctlr = EDMA_CTLR(slot);
1206         slot = EDMA_CHAN_SLOT(slot);
1207 
1208         if (slot >= edma_cc[ctlr]->num_slots)
1209                 return;
1210         memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1211                         PARM_SIZE);
1212 }
1213 EXPORT_SYMBOL(edma_read_slot);
1214 
1215 /*-----------------------------------------------------------------------*/
1216 
1217 /* Various EDMA channel control operations */
1218 
1219 /**
1220  * edma_pause - pause dma on a channel
1221  * @channel: on which edma_start() has been called
1222  *
1223  * This temporarily disables EDMA hardware events on the specified channel,
1224  * preventing them from triggering new transfers on its behalf
1225  */
1226 void edma_pause(unsigned channel)
1227 {
1228         unsigned ctlr;
1229 
1230         ctlr = EDMA_CTLR(channel);
1231         channel = EDMA_CHAN_SLOT(channel);
1232 
1233         if (channel < edma_cc[ctlr]->num_channels) {
1234                 unsigned int mask = BIT(channel & 0x1f);
1235 
1236                 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1237         }
1238 }
1239 EXPORT_SYMBOL(edma_pause);
1240 
1241 /**
1242  * edma_resume - resumes dma on a paused channel
1243  * @channel: on which edma_pause() has been called
1244  *
1245  * This re-enables EDMA hardware events on the specified channel.
1246  */
1247 void edma_resume(unsigned channel)
1248 {
1249         unsigned ctlr;
1250 
1251         ctlr = EDMA_CTLR(channel);
1252         channel = EDMA_CHAN_SLOT(channel);
1253 
1254         if (channel < edma_cc[ctlr]->num_channels) {
1255                 unsigned int mask = BIT(channel & 0x1f);
1256 
1257                 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1258         }
1259 }
1260 EXPORT_SYMBOL(edma_resume);
1261 
1262 int edma_trigger_channel(unsigned channel)
1263 {
1264         unsigned ctlr;
1265         unsigned int mask;
1266 
1267         ctlr = EDMA_CTLR(channel);
1268         channel = EDMA_CHAN_SLOT(channel);
1269         mask = BIT(channel & 0x1f);
1270 
1271         edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1272 
1273         pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1274                  edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1275         return 0;
1276 }
1277 EXPORT_SYMBOL(edma_trigger_channel);
1278 
1279 /**
1280  * edma_start - start dma on a channel
1281  * @channel: channel being activated
1282  *
1283  * Channels with event associations will be triggered by their hardware
1284  * events, and channels without such associations will be triggered by
1285  * software.  (At this writing there is no interface for using software
1286  * triggers except with channels that don't support hardware triggers.)
1287  *
1288  * Returns zero on success, else negative errno.
1289  */
1290 int edma_start(unsigned channel)
1291 {
1292         unsigned ctlr;
1293 
1294         ctlr = EDMA_CTLR(channel);
1295         channel = EDMA_CHAN_SLOT(channel);
1296 
1297         if (channel < edma_cc[ctlr]->num_channels) {
1298                 int j = channel >> 5;
1299                 unsigned int mask = BIT(channel & 0x1f);
1300 
1301                 /* EDMA channels without event association */
1302                 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1303                         pr_debug("EDMA: ESR%d %08x\n", j,
1304                                 edma_shadow0_read_array(ctlr, SH_ESR, j));
1305                         edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1306                         return 0;
1307                 }
1308 
1309                 /* EDMA channel with event association */
1310                 pr_debug("EDMA: ER%d %08x\n", j,
1311                         edma_shadow0_read_array(ctlr, SH_ER, j));
1312                 /* Clear any pending event or error */
1313                 edma_write_array(ctlr, EDMA_ECR, j, mask);
1314                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1315                 /* Clear any SER */
1316                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1317                 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1318                 pr_debug("EDMA: EER%d %08x\n", j,
1319                         edma_shadow0_read_array(ctlr, SH_EER, j));
1320                 return 0;
1321         }
1322 
1323         return -EINVAL;
1324 }
1325 EXPORT_SYMBOL(edma_start);
1326 
1327 /**
1328  * edma_stop - stops dma on the channel passed
1329  * @channel: channel being deactivated
1330  *
1331  * When @lch is a channel, any active transfer is paused and
1332  * all pending hardware events are cleared.  The current transfer
1333  * may not be resumed, and the channel's Parameter RAM should be
1334  * reinitialized before being reused.
1335  */
1336 void edma_stop(unsigned channel)
1337 {
1338         unsigned ctlr;
1339 
1340         ctlr = EDMA_CTLR(channel);
1341         channel = EDMA_CHAN_SLOT(channel);
1342 
1343         if (channel < edma_cc[ctlr]->num_channels) {
1344                 int j = channel >> 5;
1345                 unsigned int mask = BIT(channel & 0x1f);
1346 
1347                 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1348                 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1349                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1350                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1351 
1352                 pr_debug("EDMA: EER%d %08x\n", j,
1353                                 edma_shadow0_read_array(ctlr, SH_EER, j));
1354 
1355                 /* REVISIT:  consider guarding against inappropriate event
1356                  * chaining by overwriting with dummy_paramset.
1357                  */
1358         }
1359 }
1360 EXPORT_SYMBOL(edma_stop);
1361 
1362 /******************************************************************************
1363  *
1364  * It cleans ParamEntry qand bring back EDMA to initial state if media has
1365  * been removed before EDMA has finished.It is usedful for removable media.
1366  * Arguments:
1367  *      ch_no     - channel no
1368  *
1369  * Return: zero on success, or corresponding error no on failure
1370  *
1371  * FIXME this should not be needed ... edma_stop() should suffice.
1372  *
1373  *****************************************************************************/
1374 
1375 void edma_clean_channel(unsigned channel)
1376 {
1377         unsigned ctlr;
1378 
1379         ctlr = EDMA_CTLR(channel);
1380         channel = EDMA_CHAN_SLOT(channel);
1381 
1382         if (channel < edma_cc[ctlr]->num_channels) {
1383                 int j = (channel >> 5);
1384                 unsigned int mask = BIT(channel & 0x1f);
1385 
1386                 pr_debug("EDMA: EMR%d %08x\n", j,
1387                                 edma_read_array(ctlr, EDMA_EMR, j));
1388                 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1389                 /* Clear the corresponding EMR bits */
1390                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1391                 /* Clear any SER */
1392                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1393                 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1394         }
1395 }
1396 EXPORT_SYMBOL(edma_clean_channel);
1397 
1398 /*
1399  * edma_clear_event - clear an outstanding event on the DMA channel
1400  * Arguments:
1401  *      channel - channel number
1402  */
1403 void edma_clear_event(unsigned channel)
1404 {
1405         unsigned ctlr;
1406 
1407         ctlr = EDMA_CTLR(channel);
1408         channel = EDMA_CHAN_SLOT(channel);
1409 
1410         if (channel >= edma_cc[ctlr]->num_channels)
1411                 return;
1412         if (channel < 32)
1413                 edma_write(ctlr, EDMA_ECR, BIT(channel));
1414         else
1415                 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1416 }
1417 EXPORT_SYMBOL(edma_clear_event);
1418 
1419 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1420                               struct edma *edma_cc, int cc_id)
1421 {
1422         int i;
1423         u32 value, cccfg;
1424         s8 (*queue_priority_map)[2];
1425 
1426         /* Decode the eDMA3 configuration from CCCFG register */
1427         cccfg = edma_read(cc_id, EDMA_CCCFG);
1428 
1429         value = GET_NUM_REGN(cccfg);
1430         edma_cc->num_region = BIT(value);
1431 
1432         value = GET_NUM_DMACH(cccfg);
1433         edma_cc->num_channels = BIT(value + 1);
1434 
1435         value = GET_NUM_PAENTRY(cccfg);
1436         edma_cc->num_slots = BIT(value + 4);
1437 
1438         value = GET_NUM_EVQUE(cccfg);
1439         edma_cc->num_tc = value + 1;
1440 
1441         dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
1442                 cccfg);
1443         dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1444         dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1445         dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
1446         dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
1447 
1448         /* Nothing need to be done if queue priority is provided */
1449         if (pdata->queue_priority_mapping)
1450                 return 0;
1451 
1452         /*
1453          * Configure TC/queue priority as follows:
1454          * Q0 - priority 0
1455          * Q1 - priority 1
1456          * Q2 - priority 2
1457          * ...
1458          * The meaning of priority numbers: 0 highest priority, 7 lowest
1459          * priority. So Q0 is the highest priority queue and the last queue has
1460          * the lowest priority.
1461          */
1462         queue_priority_map = devm_kzalloc(dev,
1463                                           (edma_cc->num_tc + 1) * sizeof(s8),
1464                                           GFP_KERNEL);
1465         if (!queue_priority_map)
1466                 return -ENOMEM;
1467 
1468         for (i = 0; i < edma_cc->num_tc; i++) {
1469                 queue_priority_map[i][0] = i;
1470                 queue_priority_map[i][1] = i;
1471         }
1472         queue_priority_map[i][0] = -1;
1473         queue_priority_map[i][1] = -1;
1474 
1475         pdata->queue_priority_mapping = queue_priority_map;
1476         pdata->default_queue = 0;
1477 
1478         return 0;
1479 }
1480 
1481 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1482 
1483 static int edma_xbar_event_map(struct device *dev, struct device_node *node,
1484                                struct edma_soc_info *pdata, size_t sz)
1485 {
1486         const char pname[] = "ti,edma-xbar-event-map";
1487         struct resource res;
1488         void __iomem *xbar;
1489         s16 (*xbar_chans)[2];
1490         size_t nelm = sz / sizeof(s16);
1491         u32 shift, offset, mux;
1492         int ret, i;
1493 
1494         xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
1495         if (!xbar_chans)
1496                 return -ENOMEM;
1497 
1498         ret = of_address_to_resource(node, 1, &res);
1499         if (ret)
1500                 return -ENOMEM;
1501 
1502         xbar = devm_ioremap(dev, res.start, resource_size(&res));
1503         if (!xbar)
1504                 return -ENOMEM;
1505 
1506         ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
1507         if (ret)
1508                 return -EIO;
1509 
1510         /* Invalidate last entry for the other user of this mess */
1511         nelm >>= 1;
1512         xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
1513 
1514         for (i = 0; i < nelm; i++) {
1515                 shift = (xbar_chans[i][1] & 0x03) << 3;
1516                 offset = xbar_chans[i][1] & 0xfffffffc;
1517                 mux = readl(xbar + offset);
1518                 mux &= ~(0xff << shift);
1519                 mux |= xbar_chans[i][0] << shift;
1520                 writel(mux, (xbar + offset));
1521         }
1522 
1523         pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1524         return 0;
1525 }
1526 
1527 static int edma_of_parse_dt(struct device *dev,
1528                             struct device_node *node,
1529                             struct edma_soc_info *pdata)
1530 {
1531         int ret = 0;
1532         struct property *prop;
1533         size_t sz;
1534         struct edma_rsv_info *rsv_info;
1535 
1536         rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1537         if (!rsv_info)
1538                 return -ENOMEM;
1539         pdata->rsv = rsv_info;
1540 
1541         prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1542         if (prop)
1543                 ret = edma_xbar_event_map(dev, node, pdata, sz);
1544 
1545         return ret;
1546 }
1547 
1548 static struct of_dma_filter_info edma_filter_info = {
1549         .filter_fn = edma_filter_fn,
1550 };
1551 
1552 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1553                                                       struct device_node *node)
1554 {
1555         struct edma_soc_info *info;
1556         int ret;
1557 
1558         info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1559         if (!info)
1560                 return ERR_PTR(-ENOMEM);
1561 
1562         ret = edma_of_parse_dt(dev, node, info);
1563         if (ret)
1564                 return ERR_PTR(ret);
1565 
1566         dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1567         dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
1568         of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1569                                    &edma_filter_info);
1570 
1571         return info;
1572 }
1573 #else
1574 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1575                                                       struct device_node *node)
1576 {
1577         return ERR_PTR(-ENOSYS);
1578 }
1579 #endif
1580 
1581 static int edma_probe(struct platform_device *pdev)
1582 {
1583         struct edma_soc_info    **info = pdev->dev.platform_data;
1584         struct edma_soc_info    *ninfo[EDMA_MAX_CC] = {NULL};
1585         s8              (*queue_priority_mapping)[2];
1586         int                     i, j, off, ln, found = 0;
1587         int                     status = -1;
1588         const s16               (*rsv_chans)[2];
1589         const s16               (*rsv_slots)[2];
1590         const s16               (*xbar_chans)[2];
1591         int                     irq[EDMA_MAX_CC] = {0, 0};
1592         int                     err_irq[EDMA_MAX_CC] = {0, 0};
1593         struct resource         *r[EDMA_MAX_CC] = {NULL};
1594         struct resource         res[EDMA_MAX_CC];
1595         char                    res_name[10];
1596         struct device_node      *node = pdev->dev.of_node;
1597         struct device           *dev = &pdev->dev;
1598         int                     ret;
1599 
1600         if (node) {
1601                 /* Check if this is a second instance registered */
1602                 if (arch_num_cc) {
1603                         dev_err(dev, "only one EDMA instance is supported via DT\n");
1604                         return -ENODEV;
1605                 }
1606 
1607                 ninfo[0] = edma_setup_info_from_dt(dev, node);
1608                 if (IS_ERR(ninfo[0])) {
1609                         dev_err(dev, "failed to get DT data\n");
1610                         return PTR_ERR(ninfo[0]);
1611                 }
1612 
1613                 info = ninfo;
1614         }
1615 
1616         if (!info)
1617                 return -ENODEV;
1618 
1619         pm_runtime_enable(dev);
1620         ret = pm_runtime_get_sync(dev);
1621         if (ret < 0) {
1622                 dev_err(dev, "pm_runtime_get_sync() failed\n");
1623                 return ret;
1624         }
1625 
1626         for (j = 0; j < EDMA_MAX_CC; j++) {
1627                 if (!info[j]) {
1628                         if (!found)
1629                                 return -ENODEV;
1630                         break;
1631                 }
1632                 if (node) {
1633                         ret = of_address_to_resource(node, j, &res[j]);
1634                         if (!ret)
1635                                 r[j] = &res[j];
1636                 } else {
1637                         sprintf(res_name, "edma_cc%d", j);
1638                         r[j] = platform_get_resource_byname(pdev,
1639                                                 IORESOURCE_MEM,
1640                                                 res_name);
1641                 }
1642                 if (!r[j]) {
1643                         if (found)
1644                                 break;
1645                         else
1646                                 return -ENODEV;
1647                 } else {
1648                         found = 1;
1649                 }
1650 
1651                 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1652                 if (IS_ERR(edmacc_regs_base[j]))
1653                         return PTR_ERR(edmacc_regs_base[j]);
1654 
1655                 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1656                                           GFP_KERNEL);
1657                 if (!edma_cc[j])
1658                         return -ENOMEM;
1659 
1660                 /* Get eDMA3 configuration from IP */
1661                 ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
1662                 if (ret)
1663                         return ret;
1664 
1665                 edma_cc[j]->default_queue = info[j]->default_queue;
1666 
1667                 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1668                         edmacc_regs_base[j]);
1669 
1670                 for (i = 0; i < edma_cc[j]->num_slots; i++)
1671                         memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1672                                         &dummy_paramset, PARM_SIZE);
1673 
1674                 /* Mark all channels as unused */
1675                 memset(edma_cc[j]->edma_unused, 0xff,
1676                         sizeof(edma_cc[j]->edma_unused));
1677 
1678                 if (info[j]->rsv) {
1679 
1680                         /* Clear the reserved channels in unused list */
1681                         rsv_chans = info[j]->rsv->rsv_chans;
1682                         if (rsv_chans) {
1683                                 for (i = 0; rsv_chans[i][0] != -1; i++) {
1684                                         off = rsv_chans[i][0];
1685                                         ln = rsv_chans[i][1];
1686                                         clear_bits(off, ln,
1687                                                   edma_cc[j]->edma_unused);
1688                                 }
1689                         }
1690 
1691                         /* Set the reserved slots in inuse list */
1692                         rsv_slots = info[j]->rsv->rsv_slots;
1693                         if (rsv_slots) {
1694                                 for (i = 0; rsv_slots[i][0] != -1; i++) {
1695                                         off = rsv_slots[i][0];
1696                                         ln = rsv_slots[i][1];
1697                                         set_bits(off, ln,
1698                                                 edma_cc[j]->edma_inuse);
1699                                 }
1700                         }
1701                 }
1702 
1703                 /* Clear the xbar mapped channels in unused list */
1704                 xbar_chans = info[j]->xbar_chans;
1705                 if (xbar_chans) {
1706                         for (i = 0; xbar_chans[i][1] != -1; i++) {
1707                                 off = xbar_chans[i][1];
1708                                 clear_bits(off, 1,
1709                                            edma_cc[j]->edma_unused);
1710                         }
1711                 }
1712 
1713                 if (node) {
1714                         irq[j] = irq_of_parse_and_map(node, 0);
1715                         err_irq[j] = irq_of_parse_and_map(node, 2);
1716                 } else {
1717                         char irq_name[10];
1718 
1719                         sprintf(irq_name, "edma%d", j);
1720                         irq[j] = platform_get_irq_byname(pdev, irq_name);
1721 
1722                         sprintf(irq_name, "edma%d_err", j);
1723                         err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1724                 }
1725                 edma_cc[j]->irq_res_start = irq[j];
1726                 edma_cc[j]->irq_res_end = err_irq[j];
1727 
1728                 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1729                                           "edma", dev);
1730                 if (status < 0) {
1731                         dev_dbg(&pdev->dev,
1732                                 "devm_request_irq %d failed --> %d\n",
1733                                 irq[j], status);
1734                         return status;
1735                 }
1736 
1737                 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1738                                           "edma_error", dev);
1739                 if (status < 0) {
1740                         dev_dbg(&pdev->dev,
1741                                 "devm_request_irq %d failed --> %d\n",
1742                                 err_irq[j], status);
1743                         return status;
1744                 }
1745 
1746                 for (i = 0; i < edma_cc[j]->num_channels; i++)
1747                         map_dmach_queue(j, i, info[j]->default_queue);
1748 
1749                 queue_priority_mapping = info[j]->queue_priority_mapping;
1750 
1751                 /* Event queue priority mapping */
1752                 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1753                         assign_priority_to_queue(j,
1754                                                 queue_priority_mapping[i][0],
1755                                                 queue_priority_mapping[i][1]);
1756 
1757                 /* Map the channel to param entry if channel mapping logic
1758                  * exist
1759                  */
1760                 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1761                         map_dmach_param(j);
1762 
1763                 for (i = 0; i < edma_cc[j]->num_region; i++) {
1764                         edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1765                         edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1766                         edma_write_array(j, EDMA_QRAE, i, 0x0);
1767                 }
1768                 arch_num_cc++;
1769         }
1770 
1771         return 0;
1772 }
1773 
1774 static struct platform_driver edma_driver = {
1775         .driver = {
1776                 .name   = "edma",
1777                 .of_match_table = edma_of_ids,
1778         },
1779         .probe = edma_probe,
1780 };
1781 
1782 static int __init edma_init(void)
1783 {
1784         return platform_driver_probe(&edma_driver, edma_probe);
1785 }
1786 arch_initcall(edma_init);
1787 
1788 

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