1 /*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18
19 #include <linux/spi/spi.h>
20
21 #include <asm/mach/map.h>
22
23 #include <mach/dm355.h>
24 #include <mach/clock.h>
25 #include <mach/cputype.h>
26 #include <mach/edma.h>
27 #include <mach/psc.h>
28 #include <mach/mux.h>
29 #include <mach/irqs.h>
30 #include <mach/time.h>
31 #include <mach/serial.h>
32 #include <mach/common.h>
33 #include <mach/asp.h>
34
35 #include "clock.h"
36 #include "mux.h"
37
38 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
39
40 /*
41 * Device specific clocks
42 */
43 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
44
45 static struct pll_data pll1_data = {
46 .num = 1,
47 .phys_base = DAVINCI_PLL1_BASE,
48 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
49 };
50
51 static struct pll_data pll2_data = {
52 .num = 2,
53 .phys_base = DAVINCI_PLL2_BASE,
54 .flags = PLL_HAS_PREDIV,
55 };
56
57 static struct clk ref_clk = {
58 .name = "ref_clk",
59 /* FIXME -- crystal rate is board-specific */
60 .rate = DM355_REF_FREQ,
61 };
62
63 static struct clk pll1_clk = {
64 .name = "pll1",
65 .parent = &ref_clk,
66 .flags = CLK_PLL,
67 .pll_data = &pll1_data,
68 };
69
70 static struct clk pll1_aux_clk = {
71 .name = "pll1_aux_clk",
72 .parent = &pll1_clk,
73 .flags = CLK_PLL | PRE_PLL,
74 };
75
76 static struct clk pll1_sysclk1 = {
77 .name = "pll1_sysclk1",
78 .parent = &pll1_clk,
79 .flags = CLK_PLL,
80 .div_reg = PLLDIV1,
81 };
82
83 static struct clk pll1_sysclk2 = {
84 .name = "pll1_sysclk2",
85 .parent = &pll1_clk,
86 .flags = CLK_PLL,
87 .div_reg = PLLDIV2,
88 };
89
90 static struct clk pll1_sysclk3 = {
91 .name = "pll1_sysclk3",
92 .parent = &pll1_clk,
93 .flags = CLK_PLL,
94 .div_reg = PLLDIV3,
95 };
96
97 static struct clk pll1_sysclk4 = {
98 .name = "pll1_sysclk4",
99 .parent = &pll1_clk,
100 .flags = CLK_PLL,
101 .div_reg = PLLDIV4,
102 };
103
104 static struct clk pll1_sysclkbp = {
105 .name = "pll1_sysclkbp",
106 .parent = &pll1_clk,
107 .flags = CLK_PLL | PRE_PLL,
108 .div_reg = BPDIV
109 };
110
111 static struct clk vpss_dac_clk = {
112 .name = "vpss_dac",
113 .parent = &pll1_sysclk3,
114 .lpsc = DM355_LPSC_VPSS_DAC,
115 };
116
117 static struct clk vpss_master_clk = {
118 .name = "vpss_master",
119 .parent = &pll1_sysclk4,
120 .lpsc = DAVINCI_LPSC_VPSSMSTR,
121 .flags = CLK_PSC,
122 };
123
124 static struct clk vpss_slave_clk = {
125 .name = "vpss_slave",
126 .parent = &pll1_sysclk4,
127 .lpsc = DAVINCI_LPSC_VPSSSLV,
128 };
129
130
131 static struct clk clkout1_clk = {
132 .name = "clkout1",
133 .parent = &pll1_aux_clk,
134 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135 };
136
137 static struct clk clkout2_clk = {
138 .name = "clkout2",
139 .parent = &pll1_sysclkbp,
140 };
141
142 static struct clk pll2_clk = {
143 .name = "pll2",
144 .parent = &ref_clk,
145 .flags = CLK_PLL,
146 .pll_data = &pll2_data,
147 };
148
149 static struct clk pll2_sysclk1 = {
150 .name = "pll2_sysclk1",
151 .parent = &pll2_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV1,
154 };
155
156 static struct clk pll2_sysclkbp = {
157 .name = "pll2_sysclkbp",
158 .parent = &pll2_clk,
159 .flags = CLK_PLL | PRE_PLL,
160 .div_reg = BPDIV
161 };
162
163 static struct clk clkout3_clk = {
164 .name = "clkout3",
165 .parent = &pll2_sysclkbp,
166 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167 };
168
169 static struct clk arm_clk = {
170 .name = "arm_clk",
171 .parent = &pll1_sysclk1,
172 .lpsc = DAVINCI_LPSC_ARM,
173 .flags = ALWAYS_ENABLED,
174 };
175
176 /*
177 * NOT LISTED below, and not touched by Linux
178 * - in SyncReset state by default
179 * .lpsc = DAVINCI_LPSC_TPCC,
180 * .lpsc = DAVINCI_LPSC_TPTC0,
181 * .lpsc = DAVINCI_LPSC_TPTC1,
182 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183 * .lpsc = DAVINCI_LPSC_MEMSTICK,
184 * - in Enabled state by default
185 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
192 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
193 */
194
195 static struct clk mjcp_clk = {
196 .name = "mjcp",
197 .parent = &pll1_sysclk1,
198 .lpsc = DAVINCI_LPSC_IMCOP,
199 };
200
201 static struct clk uart0_clk = {
202 .name = "uart0",
203 .parent = &pll1_aux_clk,
204 .lpsc = DAVINCI_LPSC_UART0,
205 };
206
207 static struct clk uart1_clk = {
208 .name = "uart1",
209 .parent = &pll1_aux_clk,
210 .lpsc = DAVINCI_LPSC_UART1,
211 };
212
213 static struct clk uart2_clk = {
214 .name = "uart2",
215 .parent = &pll1_sysclk2,
216 .lpsc = DAVINCI_LPSC_UART2,
217 };
218
219 static struct clk i2c_clk = {
220 .name = "i2c",
221 .parent = &pll1_aux_clk,
222 .lpsc = DAVINCI_LPSC_I2C,
223 };
224
225 static struct clk asp0_clk = {
226 .name = "asp0",
227 .parent = &pll1_sysclk2,
228 .lpsc = DAVINCI_LPSC_McBSP,
229 };
230
231 static struct clk asp1_clk = {
232 .name = "asp1",
233 .parent = &pll1_sysclk2,
234 .lpsc = DM355_LPSC_McBSP1,
235 };
236
237 static struct clk mmcsd0_clk = {
238 .name = "mmcsd0",
239 .parent = &pll1_sysclk2,
240 .lpsc = DAVINCI_LPSC_MMC_SD,
241 };
242
243 static struct clk mmcsd1_clk = {
244 .name = "mmcsd1",
245 .parent = &pll1_sysclk2,
246 .lpsc = DM355_LPSC_MMC_SD1,
247 };
248
249 static struct clk spi0_clk = {
250 .name = "spi0",
251 .parent = &pll1_sysclk2,
252 .lpsc = DAVINCI_LPSC_SPI,
253 };
254
255 static struct clk spi1_clk = {
256 .name = "spi1",
257 .parent = &pll1_sysclk2,
258 .lpsc = DM355_LPSC_SPI1,
259 };
260
261 static struct clk spi2_clk = {
262 .name = "spi2",
263 .parent = &pll1_sysclk2,
264 .lpsc = DM355_LPSC_SPI2,
265 };
266
267 static struct clk gpio_clk = {
268 .name = "gpio",
269 .parent = &pll1_sysclk2,
270 .lpsc = DAVINCI_LPSC_GPIO,
271 };
272
273 static struct clk aemif_clk = {
274 .name = "aemif",
275 .parent = &pll1_sysclk2,
276 .lpsc = DAVINCI_LPSC_AEMIF,
277 };
278
279 static struct clk pwm0_clk = {
280 .name = "pwm0",
281 .parent = &pll1_aux_clk,
282 .lpsc = DAVINCI_LPSC_PWM0,
283 };
284
285 static struct clk pwm1_clk = {
286 .name = "pwm1",
287 .parent = &pll1_aux_clk,
288 .lpsc = DAVINCI_LPSC_PWM1,
289 };
290
291 static struct clk pwm2_clk = {
292 .name = "pwm2",
293 .parent = &pll1_aux_clk,
294 .lpsc = DAVINCI_LPSC_PWM2,
295 };
296
297 static struct clk pwm3_clk = {
298 .name = "pwm3",
299 .parent = &pll1_aux_clk,
300 .lpsc = DM355_LPSC_PWM3,
301 };
302
303 static struct clk timer0_clk = {
304 .name = "timer0",
305 .parent = &pll1_aux_clk,
306 .lpsc = DAVINCI_LPSC_TIMER0,
307 };
308
309 static struct clk timer1_clk = {
310 .name = "timer1",
311 .parent = &pll1_aux_clk,
312 .lpsc = DAVINCI_LPSC_TIMER1,
313 };
314
315 static struct clk timer2_clk = {
316 .name = "timer2",
317 .parent = &pll1_aux_clk,
318 .lpsc = DAVINCI_LPSC_TIMER2,
319 .usecount = 1, /* REVISIT: why cant' this be disabled? */
320 };
321
322 static struct clk timer3_clk = {
323 .name = "timer3",
324 .parent = &pll1_aux_clk,
325 .lpsc = DM355_LPSC_TIMER3,
326 };
327
328 static struct clk rto_clk = {
329 .name = "rto",
330 .parent = &pll1_aux_clk,
331 .lpsc = DM355_LPSC_RTO,
332 };
333
334 static struct clk usb_clk = {
335 .name = "usb",
336 .parent = &pll1_sysclk2,
337 .lpsc = DAVINCI_LPSC_USB,
338 };
339
340 static struct davinci_clk dm355_clks[] = {
341 CLK(NULL, "ref", &ref_clk),
342 CLK(NULL, "pll1", &pll1_clk),
343 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
344 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
345 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
346 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
347 CLK(NULL, "pll1_aux", &pll1_aux_clk),
348 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
349 CLK(NULL, "vpss_dac", &vpss_dac_clk),
350 CLK(NULL, "vpss_master", &vpss_master_clk),
351 CLK(NULL, "vpss_slave", &vpss_slave_clk),
352 CLK(NULL, "clkout1", &clkout1_clk),
353 CLK(NULL, "clkout2", &clkout2_clk),
354 CLK(NULL, "pll2", &pll2_clk),
355 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
356 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
357 CLK(NULL, "clkout3", &clkout3_clk),
358 CLK(NULL, "arm", &arm_clk),
359 CLK(NULL, "mjcp", &mjcp_clk),
360 CLK(NULL, "uart0", &uart0_clk),
361 CLK(NULL, "uart1", &uart1_clk),
362 CLK(NULL, "uart2", &uart2_clk),
363 CLK("i2c_davinci.1", NULL, &i2c_clk),
364 CLK("davinci-asp.0", NULL, &asp0_clk),
365 CLK("davinci-asp.1", NULL, &asp1_clk),
366 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
367 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
368 CLK(NULL, "spi0", &spi0_clk),
369 CLK(NULL, "spi1", &spi1_clk),
370 CLK(NULL, "spi2", &spi2_clk),
371 CLK(NULL, "gpio", &gpio_clk),
372 CLK(NULL, "aemif", &aemif_clk),
373 CLK(NULL, "pwm0", &pwm0_clk),
374 CLK(NULL, "pwm1", &pwm1_clk),
375 CLK(NULL, "pwm2", &pwm2_clk),
376 CLK(NULL, "pwm3", &pwm3_clk),
377 CLK(NULL, "timer0", &timer0_clk),
378 CLK(NULL, "timer1", &timer1_clk),
379 CLK("watchdog", NULL, &timer2_clk),
380 CLK(NULL, "timer3", &timer3_clk),
381 CLK(NULL, "rto", &rto_clk),
382 CLK(NULL, "usb", &usb_clk),
383 CLK(NULL, NULL, NULL),
384 };
385
386 /*----------------------------------------------------------------------*/
387
388 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
389
390 static struct resource dm355_spi0_resources[] = {
391 {
392 .start = 0x01c66000,
393 .end = 0x01c667ff,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = IRQ_DM355_SPINT0_1,
398 .flags = IORESOURCE_IRQ,
399 },
400 /* Not yet used, so not included:
401 * IORESOURCE_IRQ:
402 * - IRQ_DM355_SPINT0_0
403 * IORESOURCE_DMA:
404 * - DAVINCI_DMA_SPI_SPIX
405 * - DAVINCI_DMA_SPI_SPIR
406 */
407 };
408
409 static struct platform_device dm355_spi0_device = {
410 .name = "spi_davinci",
411 .id = 0,
412 .dev = {
413 .dma_mask = &dm355_spi0_dma_mask,
414 .coherent_dma_mask = DMA_BIT_MASK(32),
415 },
416 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
417 .resource = dm355_spi0_resources,
418 };
419
420 void __init dm355_init_spi0(unsigned chipselect_mask,
421 struct spi_board_info *info, unsigned len)
422 {
423 /* for now, assume we need MISO */
424 davinci_cfg_reg(DM355_SPI0_SDI);
425
426 /* not all slaves will be wired up */
427 if (chipselect_mask & BIT(0))
428 davinci_cfg_reg(DM355_SPI0_SDENA0);
429 if (chipselect_mask & BIT(1))
430 davinci_cfg_reg(DM355_SPI0_SDENA1);
431
432 spi_register_board_info(info, len);
433
434 platform_device_register(&dm355_spi0_device);
435 }
436
437 /*----------------------------------------------------------------------*/
438
439 #define PINMUX0 0x00
440 #define PINMUX1 0x04
441 #define PINMUX2 0x08
442 #define PINMUX3 0x0c
443 #define PINMUX4 0x10
444 #define INTMUX 0x18
445 #define EVTMUX 0x1c
446
447 /*
448 * Device specific mux setup
449 *
450 * soc description mux mode mode mux dbg
451 * reg offset mask mode
452 */
453 static const struct mux_config dm355_pins[] = {
454 #ifdef CONFIG_DAVINCI_MUX
455 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
456
457 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
458 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
459 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
460 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
461 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
462 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
463
464 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
465 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
466
467 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
468 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
469 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
470 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
471 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
472 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
473
474 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
475 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
476 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
477
478 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
479 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
480 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
481
482 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
483 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
484 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
485
486 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
487 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
488 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
489 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
490 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
491
492 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
493 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
494 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
495 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
496 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
497 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
498 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
499 #endif
500 };
501
502 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
503 [IRQ_DM355_CCDC_VDINT0] = 2,
504 [IRQ_DM355_CCDC_VDINT1] = 6,
505 [IRQ_DM355_CCDC_VDINT2] = 6,
506 [IRQ_DM355_IPIPE_HST] = 6,
507 [IRQ_DM355_H3AINT] = 6,
508 [IRQ_DM355_IPIPE_SDR] = 6,
509 [IRQ_DM355_IPIPEIFINT] = 6,
510 [IRQ_DM355_OSDINT] = 7,
511 [IRQ_DM355_VENCINT] = 6,
512 [IRQ_ASQINT] = 6,
513 [IRQ_IMXINT] = 6,
514 [IRQ_USBINT] = 4,
515 [IRQ_DM355_RTOINT] = 4,
516 [IRQ_DM355_UARTINT2] = 7,
517 [IRQ_DM355_TINT6] = 7,
518 [IRQ_CCINT0] = 5, /* dma */
519 [IRQ_CCERRINT] = 5, /* dma */
520 [IRQ_TCERRINT0] = 5, /* dma */
521 [IRQ_TCERRINT] = 5, /* dma */
522 [IRQ_DM355_SPINT2_1] = 7,
523 [IRQ_DM355_TINT7] = 4,
524 [IRQ_DM355_SDIOINT0] = 7,
525 [IRQ_MBXINT] = 7,
526 [IRQ_MBRINT] = 7,
527 [IRQ_MMCINT] = 7,
528 [IRQ_DM355_MMCINT1] = 7,
529 [IRQ_DM355_PWMINT3] = 7,
530 [IRQ_DDRINT] = 7,
531 [IRQ_AEMIFINT] = 7,
532 [IRQ_DM355_SDIOINT1] = 4,
533 [IRQ_TINT0_TINT12] = 2, /* clockevent */
534 [IRQ_TINT0_TINT34] = 2, /* clocksource */
535 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
536 [IRQ_TINT1_TINT34] = 7, /* system tick */
537 [IRQ_PWMINT0] = 7,
538 [IRQ_PWMINT1] = 7,
539 [IRQ_PWMINT2] = 7,
540 [IRQ_I2C] = 3,
541 [IRQ_UARTINT0] = 3,
542 [IRQ_UARTINT1] = 3,
543 [IRQ_DM355_SPINT0_0] = 3,
544 [IRQ_DM355_SPINT0_1] = 3,
545 [IRQ_DM355_GPIO0] = 3,
546 [IRQ_DM355_GPIO1] = 7,
547 [IRQ_DM355_GPIO2] = 4,
548 [IRQ_DM355_GPIO3] = 4,
549 [IRQ_DM355_GPIO4] = 7,
550 [IRQ_DM355_GPIO5] = 7,
551 [IRQ_DM355_GPIO6] = 7,
552 [IRQ_DM355_GPIO7] = 7,
553 [IRQ_DM355_GPIO8] = 7,
554 [IRQ_DM355_GPIO9] = 7,
555 [IRQ_DM355_GPIOBNK0] = 7,
556 [IRQ_DM355_GPIOBNK1] = 7,
557 [IRQ_DM355_GPIOBNK2] = 7,
558 [IRQ_DM355_GPIOBNK3] = 7,
559 [IRQ_DM355_GPIOBNK4] = 7,
560 [IRQ_DM355_GPIOBNK5] = 7,
561 [IRQ_DM355_GPIOBNK6] = 7,
562 [IRQ_COMMTX] = 7,
563 [IRQ_COMMRX] = 7,
564 [IRQ_EMUINT] = 7,
565 };
566
567 /*----------------------------------------------------------------------*/
568
569 static const s8 dma_chan_dm355_no_event[] = {
570 12, 13, 24, 56, 57,
571 58, 59, 60, 61, 62,
572 63,
573 -1
574 };
575
576 static const s8
577 queue_tc_mapping[][2] = {
578 /* {event queue no, TC no} */
579 {0, 0},
580 {1, 1},
581 {-1, -1},
582 };
583
584 static const s8
585 queue_priority_mapping[][2] = {
586 /* {event queue no, Priority} */
587 {0, 3},
588 {1, 7},
589 {-1, -1},
590 };
591
592 static struct edma_soc_info dm355_edma_info[] = {
593 {
594 .n_channel = 64,
595 .n_region = 4,
596 .n_slot = 128,
597 .n_tc = 2,
598 .n_cc = 1,
599 .noevent = dma_chan_dm355_no_event,
600 .queue_tc_mapping = queue_tc_mapping,
601 .queue_priority_mapping = queue_priority_mapping,
602 },
603 };
604
605 static struct resource edma_resources[] = {
606 {
607 .name = "edma_cc0",
608 .start = 0x01c00000,
609 .end = 0x01c00000 + SZ_64K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 {
613 .name = "edma_tc0",
614 .start = 0x01c10000,
615 .end = 0x01c10000 + SZ_1K - 1,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .name = "edma_tc1",
620 .start = 0x01c10400,
621 .end = 0x01c10400 + SZ_1K - 1,
622 .flags = IORESOURCE_MEM,
623 },
624 {
625 .name = "edma0",
626 .start = IRQ_CCINT0,
627 .flags = IORESOURCE_IRQ,
628 },
629 {
630 .name = "edma0_err",
631 .start = IRQ_CCERRINT,
632 .flags = IORESOURCE_IRQ,
633 },
634 /* not using (or muxing) TC*_ERR */
635 };
636
637 static struct platform_device dm355_edma_device = {
638 .name = "edma",
639 .id = 0,
640 .dev.platform_data = dm355_edma_info,
641 .num_resources = ARRAY_SIZE(edma_resources),
642 .resource = edma_resources,
643 };
644
645 static struct resource dm355_asp1_resources[] = {
646 {
647 .start = DAVINCI_ASP1_BASE,
648 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .start = DAVINCI_DMA_ASP1_TX,
653 .end = DAVINCI_DMA_ASP1_TX,
654 .flags = IORESOURCE_DMA,
655 },
656 {
657 .start = DAVINCI_DMA_ASP1_RX,
658 .end = DAVINCI_DMA_ASP1_RX,
659 .flags = IORESOURCE_DMA,
660 },
661 };
662
663 static struct platform_device dm355_asp1_device = {
664 .name = "davinci-asp",
665 .id = 1,
666 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
667 .resource = dm355_asp1_resources,
668 };
669
670 static struct resource dm355_vpss_resources[] = {
671 {
672 /* VPSS BL Base address */
673 .name = "vpss",
674 .start = 0x01c70800,
675 .end = 0x01c70800 + 0xff,
676 .flags = IORESOURCE_MEM,
677 },
678 {
679 /* VPSS CLK Base address */
680 .name = "vpss",
681 .start = 0x01c70000,
682 .end = 0x01c70000 + 0xf,
683 .flags = IORESOURCE_MEM,
684 },
685 };
686
687 static struct platform_device dm355_vpss_device = {
688 .name = "vpss",
689 .id = -1,
690 .dev.platform_data = "dm355_vpss",
691 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
692 .resource = dm355_vpss_resources,
693 };
694
695 static struct resource vpfe_resources[] = {
696 {
697 .start = IRQ_VDINT0,
698 .end = IRQ_VDINT0,
699 .flags = IORESOURCE_IRQ,
700 },
701 {
702 .start = IRQ_VDINT1,
703 .end = IRQ_VDINT1,
704 .flags = IORESOURCE_IRQ,
705 },
706 /* CCDC Base address */
707 {
708 .flags = IORESOURCE_MEM,
709 .start = 0x01c70600,
710 .end = 0x01c70600 + 0x1ff,
711 },
712 };
713
714 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
715 static struct platform_device vpfe_capture_dev = {
716 .name = CAPTURE_DRV_NAME,
717 .id = -1,
718 .num_resources = ARRAY_SIZE(vpfe_resources),
719 .resource = vpfe_resources,
720 .dev = {
721 .dma_mask = &vpfe_capture_dma_mask,
722 .coherent_dma_mask = DMA_BIT_MASK(32),
723 },
724 };
725
726 void dm355_set_vpfe_config(struct vpfe_config *cfg)
727 {
728 vpfe_capture_dev.dev.platform_data = cfg;
729 }
730
731 /*----------------------------------------------------------------------*/
732
733 static struct map_desc dm355_io_desc[] = {
734 {
735 .virtual = IO_VIRT,
736 .pfn = __phys_to_pfn(IO_PHYS),
737 .length = IO_SIZE,
738 .type = MT_DEVICE
739 },
740 {
741 .virtual = SRAM_VIRT,
742 .pfn = __phys_to_pfn(0x00010000),
743 .length = SZ_32K,
744 /* MT_MEMORY_NONCACHED requires supersection alignment */
745 .type = MT_DEVICE,
746 },
747 };
748
749 /* Contents of JTAG ID register used to identify exact cpu type */
750 static struct davinci_id dm355_ids[] = {
751 {
752 .variant = 0x0,
753 .part_no = 0xb73b,
754 .manufacturer = 0x00f,
755 .cpu_id = DAVINCI_CPU_ID_DM355,
756 .name = "dm355",
757 },
758 };
759
760 static void __iomem *dm355_psc_bases[] = {
761 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
762 };
763
764 /*
765 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
766 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
767 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
768 * T1_TOP: Timer 1, top : <unused>
769 */
770 struct davinci_timer_info dm355_timer_info = {
771 .timers = davinci_timer_instance,
772 .clockevent_id = T0_BOT,
773 .clocksource_id = T0_TOP,
774 };
775
776 static struct plat_serial8250_port dm355_serial_platform_data[] = {
777 {
778 .mapbase = DAVINCI_UART0_BASE,
779 .irq = IRQ_UARTINT0,
780 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
781 UPF_IOREMAP,
782 .iotype = UPIO_MEM,
783 .regshift = 2,
784 },
785 {
786 .mapbase = DAVINCI_UART1_BASE,
787 .irq = IRQ_UARTINT1,
788 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
789 UPF_IOREMAP,
790 .iotype = UPIO_MEM,
791 .regshift = 2,
792 },
793 {
794 .mapbase = DM355_UART2_BASE,
795 .irq = IRQ_DM355_UARTINT2,
796 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
797 UPF_IOREMAP,
798 .iotype = UPIO_MEM,
799 .regshift = 2,
800 },
801 {
802 .flags = 0
803 },
804 };
805
806 static struct platform_device dm355_serial_device = {
807 .name = "serial8250",
808 .id = PLAT8250_DEV_PLATFORM,
809 .dev = {
810 .platform_data = dm355_serial_platform_data,
811 },
812 };
813
814 static struct davinci_soc_info davinci_soc_info_dm355 = {
815 .io_desc = dm355_io_desc,
816 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
817 .jtag_id_base = IO_ADDRESS(0x01c40028),
818 .ids = dm355_ids,
819 .ids_num = ARRAY_SIZE(dm355_ids),
820 .cpu_clks = dm355_clks,
821 .psc_bases = dm355_psc_bases,
822 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
823 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
824 .pinmux_pins = dm355_pins,
825 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
826 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
827 .intc_type = DAVINCI_INTC_TYPE_AINTC,
828 .intc_irq_prios = dm355_default_priorities,
829 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
830 .timer_info = &dm355_timer_info,
831 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
832 .gpio_num = 104,
833 .gpio_irq = IRQ_DM355_GPIOBNK0,
834 .serial_dev = &dm355_serial_device,
835 .sram_dma = 0x00010000,
836 .sram_len = SZ_32K,
837 };
838
839 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
840 {
841 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
842 if (evt_enable & ASP1_TX_EVT_EN)
843 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
844
845 if (evt_enable & ASP1_RX_EVT_EN)
846 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
847
848 dm355_asp1_device.dev.platform_data = pdata;
849 platform_device_register(&dm355_asp1_device);
850 }
851
852 void __init dm355_init(void)
853 {
854 davinci_common_init(&davinci_soc_info_dm355);
855 }
856
857 static int __init dm355_init_devices(void)
858 {
859 if (!cpu_is_davinci_dm355())
860 return 0;
861
862 davinci_cfg_reg(DM355_INT_EDMA_CC);
863 platform_device_register(&dm355_edma_device);
864 platform_device_register(&dm355_vpss_device);
865 /*
866 * setup Mux configuration for vpfe input and register
867 * vpfe capture platform device
868 */
869 davinci_cfg_reg(DM355_VIN_PCLK);
870 davinci_cfg_reg(DM355_VIN_CAM_WEN);
871 davinci_cfg_reg(DM355_VIN_CAM_VD);
872 davinci_cfg_reg(DM355_VIN_CAM_HD);
873 davinci_cfg_reg(DM355_VIN_YIN_EN);
874 davinci_cfg_reg(DM355_VIN_CINL_EN);
875 davinci_cfg_reg(DM355_VIN_CINH_EN);
876 platform_device_register(&vpfe_capture_dev);
877
878 return 0;
879 }
880 postcore_initcall(dm355_init_devices);
881
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.