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Linux/arch/arm/mm/mmu.c

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  1 /*
  2  *  linux/arch/arm/mm/mmu.c
  3  *
  4  *  Copyright (C) 1995-2005 Russell King
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 #include <linux/module.h>
 11 #include <linux/kernel.h>
 12 #include <linux/errno.h>
 13 #include <linux/init.h>
 14 #include <linux/mman.h>
 15 #include <linux/nodemask.h>
 16 #include <linux/memblock.h>
 17 #include <linux/fs.h>
 18 #include <linux/vmalloc.h>
 19 #include <linux/sizes.h>
 20 
 21 #include <asm/cp15.h>
 22 #include <asm/cputype.h>
 23 #include <asm/sections.h>
 24 #include <asm/cachetype.h>
 25 #include <asm/sections.h>
 26 #include <asm/setup.h>
 27 #include <asm/smp_plat.h>
 28 #include <asm/tlb.h>
 29 #include <asm/highmem.h>
 30 #include <asm/system_info.h>
 31 #include <asm/traps.h>
 32 #include <asm/procinfo.h>
 33 #include <asm/memory.h>
 34 
 35 #include <asm/mach/arch.h>
 36 #include <asm/mach/map.h>
 37 #include <asm/mach/pci.h>
 38 
 39 #include "mm.h"
 40 #include "tcm.h"
 41 
 42 /*
 43  * empty_zero_page is a special page that is used for
 44  * zero-initialized data and COW.
 45  */
 46 struct page *empty_zero_page;
 47 EXPORT_SYMBOL(empty_zero_page);
 48 
 49 /*
 50  * The pmd table for the upper-most set of pages.
 51  */
 52 pmd_t *top_pmd;
 53 
 54 #define CPOLICY_UNCACHED        0
 55 #define CPOLICY_BUFFERED        1
 56 #define CPOLICY_WRITETHROUGH    2
 57 #define CPOLICY_WRITEBACK       3
 58 #define CPOLICY_WRITEALLOC      4
 59 
 60 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
 61 static unsigned int ecc_mask __initdata = 0;
 62 pgprot_t pgprot_user;
 63 pgprot_t pgprot_kernel;
 64 pgprot_t pgprot_hyp_device;
 65 pgprot_t pgprot_s2;
 66 pgprot_t pgprot_s2_device;
 67 
 68 EXPORT_SYMBOL(pgprot_user);
 69 EXPORT_SYMBOL(pgprot_kernel);
 70 
 71 struct cachepolicy {
 72         const char      policy[16];
 73         unsigned int    cr_mask;
 74         pmdval_t        pmd;
 75         pteval_t        pte;
 76         pteval_t        pte_s2;
 77 };
 78 
 79 #ifdef CONFIG_ARM_LPAE
 80 #define s2_policy(policy)       policy
 81 #else
 82 #define s2_policy(policy)       0
 83 #endif
 84 
 85 static struct cachepolicy cache_policies[] __initdata = {
 86         {
 87                 .policy         = "uncached",
 88                 .cr_mask        = CR_W|CR_C,
 89                 .pmd            = PMD_SECT_UNCACHED,
 90                 .pte            = L_PTE_MT_UNCACHED,
 91                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
 92         }, {
 93                 .policy         = "buffered",
 94                 .cr_mask        = CR_C,
 95                 .pmd            = PMD_SECT_BUFFERED,
 96                 .pte            = L_PTE_MT_BUFFERABLE,
 97                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
 98         }, {
 99                 .policy         = "writethrough",
100                 .cr_mask        = 0,
101                 .pmd            = PMD_SECT_WT,
102                 .pte            = L_PTE_MT_WRITETHROUGH,
103                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
104         }, {
105                 .policy         = "writeback",
106                 .cr_mask        = 0,
107                 .pmd            = PMD_SECT_WB,
108                 .pte            = L_PTE_MT_WRITEBACK,
109                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
110         }, {
111                 .policy         = "writealloc",
112                 .cr_mask        = 0,
113                 .pmd            = PMD_SECT_WBWA,
114                 .pte            = L_PTE_MT_WRITEALLOC,
115                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
116         }
117 };
118 
119 #ifdef CONFIG_CPU_CP15
120 /*
121  * These are useful for identifying cache coherency
122  * problems by allowing the cache or the cache and
123  * writebuffer to be turned off.  (Note: the write
124  * buffer should not be on and the cache off).
125  */
126 static int __init early_cachepolicy(char *p)
127 {
128         int i;
129 
130         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
131                 int len = strlen(cache_policies[i].policy);
132 
133                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
134                         cachepolicy = i;
135                         cr_alignment &= ~cache_policies[i].cr_mask;
136                         cr_no_alignment &= ~cache_policies[i].cr_mask;
137                         break;
138                 }
139         }
140         if (i == ARRAY_SIZE(cache_policies))
141                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
142         /*
143          * This restriction is partly to do with the way we boot; it is
144          * unpredictable to have memory mapped using two different sets of
145          * memory attributes (shared, type, and cache attribs).  We can not
146          * change these attributes once the initial assembly has setup the
147          * page tables.
148          */
149         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
150                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
151                 cachepolicy = CPOLICY_WRITEBACK;
152         }
153         flush_cache_all();
154         set_cr(cr_alignment);
155         return 0;
156 }
157 early_param("cachepolicy", early_cachepolicy);
158 
159 static int __init early_nocache(char *__unused)
160 {
161         char *p = "buffered";
162         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
163         early_cachepolicy(p);
164         return 0;
165 }
166 early_param("nocache", early_nocache);
167 
168 static int __init early_nowrite(char *__unused)
169 {
170         char *p = "uncached";
171         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
172         early_cachepolicy(p);
173         return 0;
174 }
175 early_param("nowb", early_nowrite);
176 
177 #ifndef CONFIG_ARM_LPAE
178 static int __init early_ecc(char *p)
179 {
180         if (memcmp(p, "on", 2) == 0)
181                 ecc_mask = PMD_PROTECTION;
182         else if (memcmp(p, "off", 3) == 0)
183                 ecc_mask = 0;
184         return 0;
185 }
186 early_param("ecc", early_ecc);
187 #endif
188 
189 static int __init noalign_setup(char *__unused)
190 {
191         cr_alignment &= ~CR_A;
192         cr_no_alignment &= ~CR_A;
193         set_cr(cr_alignment);
194         return 1;
195 }
196 __setup("noalign", noalign_setup);
197 
198 #ifndef CONFIG_SMP
199 void adjust_cr(unsigned long mask, unsigned long set)
200 {
201         unsigned long flags;
202 
203         mask &= ~CR_A;
204 
205         set &= mask;
206 
207         local_irq_save(flags);
208 
209         cr_no_alignment = (cr_no_alignment & ~mask) | set;
210         cr_alignment = (cr_alignment & ~mask) | set;
211 
212         set_cr((get_cr() & ~mask) | set);
213 
214         local_irq_restore(flags);
215 }
216 #endif
217 
218 #else /* ifdef CONFIG_CPU_CP15 */
219 
220 static int __init early_cachepolicy(char *p)
221 {
222         pr_warning("cachepolicy kernel parameter not supported without cp15\n");
223 }
224 early_param("cachepolicy", early_cachepolicy);
225 
226 static int __init noalign_setup(char *__unused)
227 {
228         pr_warning("noalign kernel parameter not supported without cp15\n");
229 }
230 __setup("noalign", noalign_setup);
231 
232 #endif /* ifdef CONFIG_CPU_CP15 / else */
233 
234 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
235 #define PROT_PTE_S2_DEVICE      PROT_PTE_DEVICE
236 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
237 
238 static struct mem_type mem_types[] = {
239         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
240                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
241                                   L_PTE_SHARED,
242                 .prot_pte_s2    = s2_policy(PROT_PTE_S2_DEVICE) |
243                                   s2_policy(L_PTE_S2_MT_DEV_SHARED) |
244                                   L_PTE_SHARED,
245                 .prot_l1        = PMD_TYPE_TABLE,
246                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
247                 .domain         = DOMAIN_IO,
248         },
249         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
250                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
251                 .prot_l1        = PMD_TYPE_TABLE,
252                 .prot_sect      = PROT_SECT_DEVICE,
253                 .domain         = DOMAIN_IO,
254         },
255         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
256                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
257                 .prot_l1        = PMD_TYPE_TABLE,
258                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
259                 .domain         = DOMAIN_IO,
260         },
261         [MT_DEVICE_WC] = {      /* ioremap_wc */
262                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
263                 .prot_l1        = PMD_TYPE_TABLE,
264                 .prot_sect      = PROT_SECT_DEVICE,
265                 .domain         = DOMAIN_IO,
266         },
267         [MT_UNCACHED] = {
268                 .prot_pte       = PROT_PTE_DEVICE,
269                 .prot_l1        = PMD_TYPE_TABLE,
270                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
271                 .domain         = DOMAIN_IO,
272         },
273         [MT_CACHECLEAN] = {
274                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
275                 .domain    = DOMAIN_KERNEL,
276         },
277 #ifndef CONFIG_ARM_LPAE
278         [MT_MINICLEAN] = {
279                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
280                 .domain    = DOMAIN_KERNEL,
281         },
282 #endif
283         [MT_LOW_VECTORS] = {
284                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
285                                 L_PTE_RDONLY,
286                 .prot_l1   = PMD_TYPE_TABLE,
287                 .domain    = DOMAIN_USER,
288         },
289         [MT_HIGH_VECTORS] = {
290                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
291                                 L_PTE_USER | L_PTE_RDONLY,
292                 .prot_l1   = PMD_TYPE_TABLE,
293                 .domain    = DOMAIN_USER,
294         },
295         [MT_MEMORY_RWX] = {
296                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
297                 .prot_l1   = PMD_TYPE_TABLE,
298                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
299                 .domain    = DOMAIN_KERNEL,
300         },
301         [MT_MEMORY_RW] = {
302                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303                              L_PTE_XN,
304                 .prot_l1   = PMD_TYPE_TABLE,
305                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306                 .domain    = DOMAIN_KERNEL,
307         },
308         [MT_ROM] = {
309                 .prot_sect = PMD_TYPE_SECT,
310                 .domain    = DOMAIN_KERNEL,
311         },
312         [MT_MEMORY_RWX_NONCACHED] = {
313                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
314                                 L_PTE_MT_BUFFERABLE,
315                 .prot_l1   = PMD_TYPE_TABLE,
316                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
317                 .domain    = DOMAIN_KERNEL,
318         },
319         [MT_MEMORY_RW_DTCM] = {
320                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321                                 L_PTE_XN,
322                 .prot_l1   = PMD_TYPE_TABLE,
323                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
324                 .domain    = DOMAIN_KERNEL,
325         },
326         [MT_MEMORY_RWX_ITCM] = {
327                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
328                 .prot_l1   = PMD_TYPE_TABLE,
329                 .domain    = DOMAIN_KERNEL,
330         },
331         [MT_MEMORY_RW_SO] = {
332                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
333                                 L_PTE_MT_UNCACHED | L_PTE_XN,
334                 .prot_l1   = PMD_TYPE_TABLE,
335                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
336                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
337                 .domain    = DOMAIN_KERNEL,
338         },
339         [MT_MEMORY_DMA_READY] = {
340                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341                                 L_PTE_XN,
342                 .prot_l1   = PMD_TYPE_TABLE,
343                 .domain    = DOMAIN_KERNEL,
344         },
345 };
346 
347 const struct mem_type *get_mem_type(unsigned int type)
348 {
349         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
350 }
351 EXPORT_SYMBOL(get_mem_type);
352 
353 #define PTE_SET_FN(_name, pteop) \
354 static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
355                         void *data) \
356 { \
357         pte_t pte = pteop(*ptep); \
358 \
359         set_pte_ext(ptep, pte, 0); \
360         return 0; \
361 } \
362 
363 #define SET_MEMORY_FN(_name, callback) \
364 int set_memory_##_name(unsigned long addr, int numpages) \
365 { \
366         unsigned long start = addr; \
367         unsigned long size = PAGE_SIZE*numpages; \
368         unsigned end = start + size; \
369 \
370         if (start < MODULES_VADDR || start >= MODULES_END) \
371                 return -EINVAL;\
372 \
373         if (end < MODULES_VADDR || end >= MODULES_END) \
374                 return -EINVAL; \
375 \
376         apply_to_page_range(&init_mm, start, size, callback, NULL); \
377         flush_tlb_kernel_range(start, end); \
378         return 0;\
379 }
380 
381 PTE_SET_FN(ro, pte_wrprotect)
382 PTE_SET_FN(rw, pte_mkwrite)
383 PTE_SET_FN(x, pte_mkexec)
384 PTE_SET_FN(nx, pte_mknexec)
385 
386 SET_MEMORY_FN(ro, pte_set_ro)
387 SET_MEMORY_FN(rw, pte_set_rw)
388 SET_MEMORY_FN(x, pte_set_x)
389 SET_MEMORY_FN(nx, pte_set_nx)
390 
391 /*
392  * Adjust the PMD section entries according to the CPU in use.
393  */
394 static void __init build_mem_type_table(void)
395 {
396         struct cachepolicy *cp;
397         unsigned int cr = get_cr();
398         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
399         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
400         int cpu_arch = cpu_architecture();
401         int i;
402 
403         if (cpu_arch < CPU_ARCH_ARMv6) {
404 #if defined(CONFIG_CPU_DCACHE_DISABLE)
405                 if (cachepolicy > CPOLICY_BUFFERED)
406                         cachepolicy = CPOLICY_BUFFERED;
407 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
408                 if (cachepolicy > CPOLICY_WRITETHROUGH)
409                         cachepolicy = CPOLICY_WRITETHROUGH;
410 #endif
411         }
412         if (cpu_arch < CPU_ARCH_ARMv5) {
413                 if (cachepolicy >= CPOLICY_WRITEALLOC)
414                         cachepolicy = CPOLICY_WRITEBACK;
415                 ecc_mask = 0;
416         }
417         if (is_smp())
418                 cachepolicy = CPOLICY_WRITEALLOC;
419 
420         /*
421          * Strip out features not present on earlier architectures.
422          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
423          * without extended page tables don't have the 'Shared' bit.
424          */
425         if (cpu_arch < CPU_ARCH_ARMv5)
426                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
427                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
428         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
429                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
430                         mem_types[i].prot_sect &= ~PMD_SECT_S;
431 
432         /*
433          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
434          * "update-able on write" bit on ARM610).  However, Xscale and
435          * Xscale3 require this bit to be cleared.
436          */
437         if (cpu_is_xscale() || cpu_is_xsc3()) {
438                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
439                         mem_types[i].prot_sect &= ~PMD_BIT4;
440                         mem_types[i].prot_l1 &= ~PMD_BIT4;
441                 }
442         } else if (cpu_arch < CPU_ARCH_ARMv6) {
443                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
444                         if (mem_types[i].prot_l1)
445                                 mem_types[i].prot_l1 |= PMD_BIT4;
446                         if (mem_types[i].prot_sect)
447                                 mem_types[i].prot_sect |= PMD_BIT4;
448                 }
449         }
450 
451         /*
452          * Mark the device areas according to the CPU/architecture.
453          */
454         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
455                 if (!cpu_is_xsc3()) {
456                         /*
457                          * Mark device regions on ARMv6+ as execute-never
458                          * to prevent speculative instruction fetches.
459                          */
460                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
461                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
462                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
463                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
464 
465                         /* Also setup NX memory mapping */
466                         mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
467                 }
468                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
469                         /*
470                          * For ARMv7 with TEX remapping,
471                          * - shared device is SXCB=1100
472                          * - nonshared device is SXCB=0100
473                          * - write combine device mem is SXCB=0001
474                          * (Uncached Normal memory)
475                          */
476                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
477                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
478                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
479                 } else if (cpu_is_xsc3()) {
480                         /*
481                          * For Xscale3,
482                          * - shared device is TEXCB=00101
483                          * - nonshared device is TEXCB=01000
484                          * - write combine device mem is TEXCB=00100
485                          * (Inner/Outer Uncacheable in xsc3 parlance)
486                          */
487                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
488                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
489                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
490                 } else {
491                         /*
492                          * For ARMv6 and ARMv7 without TEX remapping,
493                          * - shared device is TEXCB=00001
494                          * - nonshared device is TEXCB=01000
495                          * - write combine device mem is TEXCB=00100
496                          * (Uncached Normal in ARMv6 parlance).
497                          */
498                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
499                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
500                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
501                 }
502         } else {
503                 /*
504                  * On others, write combining is "Uncached/Buffered"
505                  */
506                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
507         }
508 
509         /*
510          * Now deal with the memory-type mappings
511          */
512         cp = &cache_policies[cachepolicy];
513         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
514         s2_pgprot = cp->pte_s2;
515         hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
516         s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
517 
518         /*
519          * We don't use domains on ARMv6 (since this causes problems with
520          * v6/v7 kernels), so we must use a separate memory type for user
521          * r/o, kernel r/w to map the vectors page.
522          */
523 #ifndef CONFIG_ARM_LPAE
524         if (cpu_arch == CPU_ARCH_ARMv6)
525                 vecs_pgprot |= L_PTE_MT_VECTORS;
526 #endif
527 
528         /*
529          * ARMv6 and above have extended page tables.
530          */
531         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
532 #ifndef CONFIG_ARM_LPAE
533                 /*
534                  * Mark cache clean areas and XIP ROM read only
535                  * from SVC mode and no access from userspace.
536                  */
537                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
538                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
539                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
540 #endif
541 
542                 if (is_smp()) {
543                         /*
544                          * Mark memory with the "shared" attribute
545                          * for SMP systems
546                          */
547                         user_pgprot |= L_PTE_SHARED;
548                         kern_pgprot |= L_PTE_SHARED;
549                         vecs_pgprot |= L_PTE_SHARED;
550                         s2_pgprot |= L_PTE_SHARED;
551                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
552                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
553                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
554                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
555                         mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
556                         mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
557                         mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
558                         mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
559                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
560                         mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
561                         mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
562                 }
563         }
564 
565         /*
566          * Non-cacheable Normal - intended for memory areas that must
567          * not cause dirty cache line writebacks when used
568          */
569         if (cpu_arch >= CPU_ARCH_ARMv6) {
570                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
571                         /* Non-cacheable Normal is XCB = 001 */
572                         mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
573                                 PMD_SECT_BUFFERED;
574                 } else {
575                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
576                         mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
577                                 PMD_SECT_TEX(1);
578                 }
579         } else {
580                 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
581         }
582 
583 #ifdef CONFIG_ARM_LPAE
584         /*
585          * Do not generate access flag faults for the kernel mappings.
586          */
587         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
588                 mem_types[i].prot_pte |= PTE_EXT_AF;
589                 if (mem_types[i].prot_sect)
590                         mem_types[i].prot_sect |= PMD_SECT_AF;
591         }
592         kern_pgprot |= PTE_EXT_AF;
593         vecs_pgprot |= PTE_EXT_AF;
594 #endif
595 
596         for (i = 0; i < 16; i++) {
597                 pteval_t v = pgprot_val(protection_map[i]);
598                 protection_map[i] = __pgprot(v | user_pgprot);
599         }
600 
601         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
602         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
603 
604         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
605         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
606                                  L_PTE_DIRTY | kern_pgprot);
607         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
608         pgprot_s2_device  = __pgprot(s2_device_pgprot);
609         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
610 
611         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
612         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
613         mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
614         mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
615         mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
616         mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
617         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
618         mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
619         mem_types[MT_ROM].prot_sect |= cp->pmd;
620 
621         switch (cp->pmd) {
622         case PMD_SECT_WT:
623                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
624                 break;
625         case PMD_SECT_WB:
626         case PMD_SECT_WBWA:
627                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
628                 break;
629         }
630         pr_info("Memory policy: %sData cache %s\n",
631                 ecc_mask ? "ECC enabled, " : "", cp->policy);
632 
633         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
634                 struct mem_type *t = &mem_types[i];
635                 if (t->prot_l1)
636                         t->prot_l1 |= PMD_DOMAIN(t->domain);
637                 if (t->prot_sect)
638                         t->prot_sect |= PMD_DOMAIN(t->domain);
639         }
640 }
641 
642 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
643 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
644                               unsigned long size, pgprot_t vma_prot)
645 {
646         if (!pfn_valid(pfn))
647                 return pgprot_noncached(vma_prot);
648         else if (file->f_flags & O_SYNC)
649                 return pgprot_writecombine(vma_prot);
650         return vma_prot;
651 }
652 EXPORT_SYMBOL(phys_mem_access_prot);
653 #endif
654 
655 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
656 
657 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
658 {
659         void *ptr = __va(memblock_alloc(sz, align));
660         memset(ptr, 0, sz);
661         return ptr;
662 }
663 
664 static void __init *early_alloc(unsigned long sz)
665 {
666         return early_alloc_aligned(sz, sz);
667 }
668 
669 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
670 {
671         if (pmd_none(*pmd)) {
672                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
673                 __pmd_populate(pmd, __pa(pte), prot);
674         }
675         BUG_ON(pmd_bad(*pmd));
676         return pte_offset_kernel(pmd, addr);
677 }
678 
679 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
680                                   unsigned long end, unsigned long pfn,
681                                   const struct mem_type *type)
682 {
683         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
684         do {
685                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
686                 pfn++;
687         } while (pte++, addr += PAGE_SIZE, addr != end);
688 }
689 
690 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
691                         unsigned long end, phys_addr_t phys,
692                         const struct mem_type *type)
693 {
694         pmd_t *p = pmd;
695 
696 #ifndef CONFIG_ARM_LPAE
697         /*
698          * In classic MMU format, puds and pmds are folded in to
699          * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
700          * group of L1 entries making up one logical pointer to
701          * an L2 table (2MB), where as PMDs refer to the individual
702          * L1 entries (1MB). Hence increment to get the correct
703          * offset for odd 1MB sections.
704          * (See arch/arm/include/asm/pgtable-2level.h)
705          */
706         if (addr & SECTION_SIZE)
707                 pmd++;
708 #endif
709         do {
710                 *pmd = __pmd(phys | type->prot_sect);
711                 phys += SECTION_SIZE;
712         } while (pmd++, addr += SECTION_SIZE, addr != end);
713 
714         flush_pmd_entry(p);
715 }
716 
717 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
718                                       unsigned long end, phys_addr_t phys,
719                                       const struct mem_type *type)
720 {
721         pmd_t *pmd = pmd_offset(pud, addr);
722         unsigned long next;
723 
724         do {
725                 /*
726                  * With LPAE, we must loop over to map
727                  * all the pmds for the given range.
728                  */
729                 next = pmd_addr_end(addr, end);
730 
731                 /*
732                  * Try a section mapping - addr, next and phys must all be
733                  * aligned to a section boundary.
734                  */
735                 if (type->prot_sect &&
736                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
737                         __map_init_section(pmd, addr, next, phys, type);
738                 } else {
739                         alloc_init_pte(pmd, addr, next,
740                                                 __phys_to_pfn(phys), type);
741                 }
742 
743                 phys += next - addr;
744 
745         } while (pmd++, addr = next, addr != end);
746 }
747 
748 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
749                                   unsigned long end, phys_addr_t phys,
750                                   const struct mem_type *type)
751 {
752         pud_t *pud = pud_offset(pgd, addr);
753         unsigned long next;
754 
755         do {
756                 next = pud_addr_end(addr, end);
757                 alloc_init_pmd(pud, addr, next, phys, type);
758                 phys += next - addr;
759         } while (pud++, addr = next, addr != end);
760 }
761 
762 #ifndef CONFIG_ARM_LPAE
763 static void __init create_36bit_mapping(struct map_desc *md,
764                                         const struct mem_type *type)
765 {
766         unsigned long addr, length, end;
767         phys_addr_t phys;
768         pgd_t *pgd;
769 
770         addr = md->virtual;
771         phys = __pfn_to_phys(md->pfn);
772         length = PAGE_ALIGN(md->length);
773 
774         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
775                 printk(KERN_ERR "MM: CPU does not support supersection "
776                        "mapping for 0x%08llx at 0x%08lx\n",
777                        (long long)__pfn_to_phys((u64)md->pfn), addr);
778                 return;
779         }
780 
781         /* N.B. ARMv6 supersections are only defined to work with domain 0.
782          *      Since domain assignments can in fact be arbitrary, the
783          *      'domain == 0' check below is required to insure that ARMv6
784          *      supersections are only allocated for domain 0 regardless
785          *      of the actual domain assignments in use.
786          */
787         if (type->domain) {
788                 printk(KERN_ERR "MM: invalid domain in supersection "
789                        "mapping for 0x%08llx at 0x%08lx\n",
790                        (long long)__pfn_to_phys((u64)md->pfn), addr);
791                 return;
792         }
793 
794         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
795                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
796                        " at 0x%08lx invalid alignment\n",
797                        (long long)__pfn_to_phys((u64)md->pfn), addr);
798                 return;
799         }
800 
801         /*
802          * Shift bits [35:32] of address into bits [23:20] of PMD
803          * (See ARMv6 spec).
804          */
805         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
806 
807         pgd = pgd_offset_k(addr);
808         end = addr + length;
809         do {
810                 pud_t *pud = pud_offset(pgd, addr);
811                 pmd_t *pmd = pmd_offset(pud, addr);
812                 int i;
813 
814                 for (i = 0; i < 16; i++)
815                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
816 
817                 addr += SUPERSECTION_SIZE;
818                 phys += SUPERSECTION_SIZE;
819                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
820         } while (addr != end);
821 }
822 #endif  /* !CONFIG_ARM_LPAE */
823 
824 /*
825  * Create the page directory entries and any necessary
826  * page tables for the mapping specified by `md'.  We
827  * are able to cope here with varying sizes and address
828  * offsets, and we take full advantage of sections and
829  * supersections.
830  */
831 static void __init create_mapping(struct map_desc *md)
832 {
833         unsigned long addr, length, end;
834         phys_addr_t phys;
835         const struct mem_type *type;
836         pgd_t *pgd;
837 
838         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
839                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
840                        " at 0x%08lx in user region\n",
841                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
842                 return;
843         }
844 
845         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
846             md->virtual >= PAGE_OFFSET &&
847             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
848                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
849                        " at 0x%08lx out of vmalloc space\n",
850                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
851         }
852 
853         type = &mem_types[md->type];
854 
855 #ifndef CONFIG_ARM_LPAE
856         /*
857          * Catch 36-bit addresses
858          */
859         if (md->pfn >= 0x100000) {
860                 create_36bit_mapping(md, type);
861                 return;
862         }
863 #endif
864 
865         addr = md->virtual & PAGE_MASK;
866         phys = __pfn_to_phys(md->pfn);
867         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
868 
869         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
870                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
871                        "be mapped using pages, ignoring.\n",
872                        (long long)__pfn_to_phys(md->pfn), addr);
873                 return;
874         }
875 
876         pgd = pgd_offset_k(addr);
877         end = addr + length;
878         do {
879                 unsigned long next = pgd_addr_end(addr, end);
880 
881                 alloc_init_pud(pgd, addr, next, phys, type);
882 
883                 phys += next - addr;
884                 addr = next;
885         } while (pgd++, addr != end);
886 }
887 
888 /*
889  * Create the architecture specific mappings
890  */
891 void __init iotable_init(struct map_desc *io_desc, int nr)
892 {
893         struct map_desc *md;
894         struct vm_struct *vm;
895         struct static_vm *svm;
896 
897         if (!nr)
898                 return;
899 
900         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
901 
902         for (md = io_desc; nr; md++, nr--) {
903                 create_mapping(md);
904 
905                 vm = &svm->vm;
906                 vm->addr = (void *)(md->virtual & PAGE_MASK);
907                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
908                 vm->phys_addr = __pfn_to_phys(md->pfn);
909                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
910                 vm->flags |= VM_ARM_MTYPE(md->type);
911                 vm->caller = iotable_init;
912                 add_static_vm_early(svm++);
913         }
914 }
915 
916 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
917                                   void *caller)
918 {
919         struct vm_struct *vm;
920         struct static_vm *svm;
921 
922         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
923 
924         vm = &svm->vm;
925         vm->addr = (void *)addr;
926         vm->size = size;
927         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
928         vm->caller = caller;
929         add_static_vm_early(svm);
930 }
931 
932 #ifndef CONFIG_ARM_LPAE
933 
934 /*
935  * The Linux PMD is made of two consecutive section entries covering 2MB
936  * (see definition in include/asm/pgtable-2level.h).  However a call to
937  * create_mapping() may optimize static mappings by using individual
938  * 1MB section mappings.  This leaves the actual PMD potentially half
939  * initialized if the top or bottom section entry isn't used, leaving it
940  * open to problems if a subsequent ioremap() or vmalloc() tries to use
941  * the virtual space left free by that unused section entry.
942  *
943  * Let's avoid the issue by inserting dummy vm entries covering the unused
944  * PMD halves once the static mappings are in place.
945  */
946 
947 static void __init pmd_empty_section_gap(unsigned long addr)
948 {
949         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
950 }
951 
952 static void __init fill_pmd_gaps(void)
953 {
954         struct static_vm *svm;
955         struct vm_struct *vm;
956         unsigned long addr, next = 0;
957         pmd_t *pmd;
958 
959         list_for_each_entry(svm, &static_vmlist, list) {
960                 vm = &svm->vm;
961                 addr = (unsigned long)vm->addr;
962                 if (addr < next)
963                         continue;
964 
965                 /*
966                  * Check if this vm starts on an odd section boundary.
967                  * If so and the first section entry for this PMD is free
968                  * then we block the corresponding virtual address.
969                  */
970                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
971                         pmd = pmd_off_k(addr);
972                         if (pmd_none(*pmd))
973                                 pmd_empty_section_gap(addr & PMD_MASK);
974                 }
975 
976                 /*
977                  * Then check if this vm ends on an odd section boundary.
978                  * If so and the second section entry for this PMD is empty
979                  * then we block the corresponding virtual address.
980                  */
981                 addr += vm->size;
982                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
983                         pmd = pmd_off_k(addr) + 1;
984                         if (pmd_none(*pmd))
985                                 pmd_empty_section_gap(addr);
986                 }
987 
988                 /* no need to look at any vm entry until we hit the next PMD */
989                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
990         }
991 }
992 
993 #else
994 #define fill_pmd_gaps() do { } while (0)
995 #endif
996 
997 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
998 static void __init pci_reserve_io(void)
999 {
1000         struct static_vm *svm;
1001 
1002         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1003         if (svm)
1004                 return;
1005 
1006         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1007 }
1008 #else
1009 #define pci_reserve_io() do { } while (0)
1010 #endif
1011 
1012 #ifdef CONFIG_DEBUG_LL
1013 void __init debug_ll_io_init(void)
1014 {
1015         struct map_desc map;
1016 
1017         debug_ll_addr(&map.pfn, &map.virtual);
1018         if (!map.pfn || !map.virtual)
1019                 return;
1020         map.pfn = __phys_to_pfn(map.pfn);
1021         map.virtual &= PAGE_MASK;
1022         map.length = PAGE_SIZE;
1023         map.type = MT_DEVICE;
1024         iotable_init(&map, 1);
1025 }
1026 #endif
1027 
1028 static void * __initdata vmalloc_min =
1029         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1030 
1031 /*
1032  * vmalloc=size forces the vmalloc area to be exactly 'size'
1033  * bytes. This can be used to increase (or decrease) the vmalloc
1034  * area - the default is 240m.
1035  */
1036 static int __init early_vmalloc(char *arg)
1037 {
1038         unsigned long vmalloc_reserve = memparse(arg, NULL);
1039 
1040         if (vmalloc_reserve < SZ_16M) {
1041                 vmalloc_reserve = SZ_16M;
1042                 printk(KERN_WARNING
1043                         "vmalloc area too small, limiting to %luMB\n",
1044                         vmalloc_reserve >> 20);
1045         }
1046 
1047         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1048                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1049                 printk(KERN_WARNING
1050                         "vmalloc area is too big, limiting to %luMB\n",
1051                         vmalloc_reserve >> 20);
1052         }
1053 
1054         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1055         return 0;
1056 }
1057 early_param("vmalloc", early_vmalloc);
1058 
1059 phys_addr_t arm_lowmem_limit __initdata = 0;
1060 
1061 void __init sanity_check_meminfo(void)
1062 {
1063         phys_addr_t memblock_limit = 0;
1064         int i, j, highmem = 0;
1065         phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1066 
1067         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1068                 struct membank *bank = &meminfo.bank[j];
1069                 phys_addr_t size_limit;
1070 
1071                 *bank = meminfo.bank[i];
1072                 size_limit = bank->size;
1073 
1074                 if (bank->start >= vmalloc_limit)
1075                         highmem = 1;
1076                 else
1077                         size_limit = vmalloc_limit - bank->start;
1078 
1079                 bank->highmem = highmem;
1080 
1081 #ifdef CONFIG_HIGHMEM
1082                 /*
1083                  * Split those memory banks which are partially overlapping
1084                  * the vmalloc area greatly simplifying things later.
1085                  */
1086                 if (!highmem && bank->size > size_limit) {
1087                         if (meminfo.nr_banks >= NR_BANKS) {
1088                                 printk(KERN_CRIT "NR_BANKS too low, "
1089                                                  "ignoring high memory\n");
1090                         } else {
1091                                 memmove(bank + 1, bank,
1092                                         (meminfo.nr_banks - i) * sizeof(*bank));
1093                                 meminfo.nr_banks++;
1094                                 i++;
1095                                 bank[1].size -= size_limit;
1096                                 bank[1].start = vmalloc_limit;
1097                                 bank[1].highmem = highmem = 1;
1098                                 j++;
1099                         }
1100                         bank->size = size_limit;
1101                 }
1102 #else
1103                 /*
1104                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1105                  */
1106                 if (highmem) {
1107                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1108                                "(!CONFIG_HIGHMEM).\n",
1109                                (unsigned long long)bank->start,
1110                                (unsigned long long)bank->start + bank->size - 1);
1111                         continue;
1112                 }
1113 
1114                 /*
1115                  * Check whether this memory bank would partially overlap
1116                  * the vmalloc area.
1117                  */
1118                 if (bank->size > size_limit) {
1119                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1120                                "to -%.8llx (vmalloc region overlap).\n",
1121                                (unsigned long long)bank->start,
1122                                (unsigned long long)bank->start + bank->size - 1,
1123                                (unsigned long long)bank->start + size_limit - 1);
1124                         bank->size = size_limit;
1125                 }
1126 #endif
1127                 if (!bank->highmem) {
1128                         phys_addr_t bank_end = bank->start + bank->size;
1129 
1130                         if (bank_end > arm_lowmem_limit)
1131                                 arm_lowmem_limit = bank_end;
1132 
1133                         /*
1134                          * Find the first non-section-aligned page, and point
1135                          * memblock_limit at it. This relies on rounding the
1136                          * limit down to be section-aligned, which happens at
1137                          * the end of this function.
1138                          *
1139                          * With this algorithm, the start or end of almost any
1140                          * bank can be non-section-aligned. The only exception
1141                          * is that the start of the bank 0 must be section-
1142                          * aligned, since otherwise memory would need to be
1143                          * allocated when mapping the start of bank 0, which
1144                          * occurs before any free memory is mapped.
1145                          */
1146                         if (!memblock_limit) {
1147                                 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1148                                         memblock_limit = bank->start;
1149                                 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1150                                         memblock_limit = bank_end;
1151                         }
1152                 }
1153                 j++;
1154         }
1155 #ifdef CONFIG_HIGHMEM
1156         if (highmem) {
1157                 const char *reason = NULL;
1158 
1159                 if (cache_is_vipt_aliasing()) {
1160                         /*
1161                          * Interactions between kmap and other mappings
1162                          * make highmem support with aliasing VIPT caches
1163                          * rather difficult.
1164                          */
1165                         reason = "with VIPT aliasing cache";
1166                 }
1167                 if (reason) {
1168                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1169                                 reason);
1170                         while (j > 0 && meminfo.bank[j - 1].highmem)
1171                                 j--;
1172                 }
1173         }
1174 #endif
1175         meminfo.nr_banks = j;
1176         high_memory = __va(arm_lowmem_limit - 1) + 1;
1177 
1178         /*
1179          * Round the memblock limit down to a section size.  This
1180          * helps to ensure that we will allocate memory from the
1181          * last full section, which should be mapped.
1182          */
1183         if (memblock_limit)
1184                 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1185         if (!memblock_limit)
1186                 memblock_limit = arm_lowmem_limit;
1187 
1188         memblock_set_current_limit(memblock_limit);
1189 }
1190 
1191 static inline void prepare_page_table(void)
1192 {
1193         unsigned long addr;
1194         phys_addr_t end;
1195 
1196         /*
1197          * Clear out all the mappings below the kernel image.
1198          */
1199         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1200                 pmd_clear(pmd_off_k(addr));
1201 
1202 #ifdef CONFIG_XIP_KERNEL
1203         /* The XIP kernel is mapped in the module area -- skip over it */
1204         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1205 #endif
1206         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1207                 pmd_clear(pmd_off_k(addr));
1208 
1209         /*
1210          * Find the end of the first block of lowmem.
1211          */
1212         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1213         if (end >= arm_lowmem_limit)
1214                 end = arm_lowmem_limit;
1215 
1216         /*
1217          * Clear out all the kernel space mappings, except for the first
1218          * memory bank, up to the vmalloc region.
1219          */
1220         for (addr = __phys_to_virt(end);
1221              addr < VMALLOC_START; addr += PMD_SIZE)
1222                 pmd_clear(pmd_off_k(addr));
1223 }
1224 
1225 #ifdef CONFIG_ARM_LPAE
1226 /* the first page is reserved for pgd */
1227 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1228                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1229 #else
1230 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1231 #endif
1232 
1233 /*
1234  * Reserve the special regions of memory
1235  */
1236 void __init arm_mm_memblock_reserve(void)
1237 {
1238         /*
1239          * Reserve the page tables.  These are already in use,
1240          * and can only be in node 0.
1241          */
1242         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1243 
1244 #ifdef CONFIG_SA1111
1245         /*
1246          * Because of the SA1111 DMA bug, we want to preserve our
1247          * precious DMA-able memory...
1248          */
1249         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1250 #endif
1251 }
1252 
1253 /*
1254  * Set up the device mappings.  Since we clear out the page tables for all
1255  * mappings above VMALLOC_START, we will remove any debug device mappings.
1256  * This means you have to be careful how you debug this function, or any
1257  * called function.  This means you can't use any function or debugging
1258  * method which may touch any device, otherwise the kernel _will_ crash.
1259  */
1260 static void __init devicemaps_init(const struct machine_desc *mdesc)
1261 {
1262         struct map_desc map;
1263         unsigned long addr;
1264         void *vectors;
1265 
1266         /*
1267          * Allocate the vector page early.
1268          */
1269         vectors = early_alloc(PAGE_SIZE * 2);
1270 
1271         early_trap_init(vectors);
1272 
1273         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1274                 pmd_clear(pmd_off_k(addr));
1275 
1276         /*
1277          * Map the kernel if it is XIP.
1278          * It is always first in the modulearea.
1279          */
1280 #ifdef CONFIG_XIP_KERNEL
1281         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1282         map.virtual = MODULES_VADDR;
1283         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1284         map.type = MT_ROM;
1285         create_mapping(&map);
1286 #endif
1287 
1288         /*
1289          * Map the cache flushing regions.
1290          */
1291 #ifdef FLUSH_BASE
1292         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1293         map.virtual = FLUSH_BASE;
1294         map.length = SZ_1M;
1295         map.type = MT_CACHECLEAN;
1296         create_mapping(&map);
1297 #endif
1298 #ifdef FLUSH_BASE_MINICACHE
1299         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1300         map.virtual = FLUSH_BASE_MINICACHE;
1301         map.length = SZ_1M;
1302         map.type = MT_MINICLEAN;
1303         create_mapping(&map);
1304 #endif
1305 
1306         /*
1307          * Create a mapping for the machine vectors at the high-vectors
1308          * location (0xffff0000).  If we aren't using high-vectors, also
1309          * create a mapping at the low-vectors virtual address.
1310          */
1311         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1312         map.virtual = 0xffff0000;
1313         map.length = PAGE_SIZE;
1314 #ifdef CONFIG_KUSER_HELPERS
1315         map.type = MT_HIGH_VECTORS;
1316 #else
1317         map.type = MT_LOW_VECTORS;
1318 #endif
1319         create_mapping(&map);
1320 
1321         if (!vectors_high()) {
1322                 map.virtual = 0;
1323                 map.length = PAGE_SIZE * 2;
1324                 map.type = MT_LOW_VECTORS;
1325                 create_mapping(&map);
1326         }
1327 
1328         /* Now create a kernel read-only mapping */
1329         map.pfn += 1;
1330         map.virtual = 0xffff0000 + PAGE_SIZE;
1331         map.length = PAGE_SIZE;
1332         map.type = MT_LOW_VECTORS;
1333         create_mapping(&map);
1334 
1335         /*
1336          * Ask the machine support to map in the statically mapped devices.
1337          */
1338         if (mdesc->map_io)
1339                 mdesc->map_io();
1340         else
1341                 debug_ll_io_init();
1342         fill_pmd_gaps();
1343 
1344         /* Reserve fixed i/o space in VMALLOC region */
1345         pci_reserve_io();
1346 
1347         /*
1348          * Finally flush the caches and tlb to ensure that we're in a
1349          * consistent state wrt the writebuffer.  This also ensures that
1350          * any write-allocated cache lines in the vector page are written
1351          * back.  After this point, we can start to touch devices again.
1352          */
1353         local_flush_tlb_all();
1354         flush_cache_all();
1355 }
1356 
1357 static void __init kmap_init(void)
1358 {
1359 #ifdef CONFIG_HIGHMEM
1360         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1361                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1362 #endif
1363 }
1364 
1365 static void __init map_lowmem(void)
1366 {
1367         struct memblock_region *reg;
1368         unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1369         unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1370 
1371         /* Map all the lowmem memory banks. */
1372         for_each_memblock(memory, reg) {
1373                 phys_addr_t start = reg->base;
1374                 phys_addr_t end = start + reg->size;
1375                 struct map_desc map;
1376 
1377                 if (end > arm_lowmem_limit)
1378                         end = arm_lowmem_limit;
1379                 if (start >= end)
1380                         break;
1381 
1382                 if (end < kernel_x_start || start >= kernel_x_end) {
1383                         map.pfn = __phys_to_pfn(start);
1384                         map.virtual = __phys_to_virt(start);
1385                         map.length = end - start;
1386                         map.type = MT_MEMORY_RWX;
1387 
1388                         create_mapping(&map);
1389                 } else {
1390                         /* This better cover the entire kernel */
1391                         if (start < kernel_x_start) {
1392                                 map.pfn = __phys_to_pfn(start);
1393                                 map.virtual = __phys_to_virt(start);
1394                                 map.length = kernel_x_start - start;
1395                                 map.type = MT_MEMORY_RW;
1396 
1397                                 create_mapping(&map);
1398                         }
1399 
1400                         map.pfn = __phys_to_pfn(kernel_x_start);
1401                         map.virtual = __phys_to_virt(kernel_x_start);
1402                         map.length = kernel_x_end - kernel_x_start;
1403                         map.type = MT_MEMORY_RWX;
1404 
1405                         create_mapping(&map);
1406 
1407                         if (kernel_x_end < end) {
1408                                 map.pfn = __phys_to_pfn(kernel_x_end);
1409                                 map.virtual = __phys_to_virt(kernel_x_end);
1410                                 map.length = end - kernel_x_end;
1411                                 map.type = MT_MEMORY_RW;
1412 
1413                                 create_mapping(&map);
1414                         }
1415                 }
1416         }
1417 }
1418 
1419 #ifdef CONFIG_ARM_LPAE
1420 /*
1421  * early_paging_init() recreates boot time page table setup, allowing machines
1422  * to switch over to a high (>4G) address space on LPAE systems
1423  */
1424 void __init early_paging_init(const struct machine_desc *mdesc,
1425                               struct proc_info_list *procinfo)
1426 {
1427         pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1428         unsigned long map_start, map_end;
1429         pgd_t *pgd0, *pgdk;
1430         pud_t *pud0, *pudk, *pud_start;
1431         pmd_t *pmd0, *pmdk;
1432         phys_addr_t phys;
1433         int i;
1434 
1435         if (!(mdesc->init_meminfo))
1436                 return;
1437 
1438         /* remap kernel code and data */
1439         map_start = init_mm.start_code & PMD_MASK;
1440         map_end   = ALIGN(init_mm.brk, PMD_SIZE);
1441 
1442         /* get a handle on things... */
1443         pgd0 = pgd_offset_k(0);
1444         pud_start = pud0 = pud_offset(pgd0, 0);
1445         pmd0 = pmd_offset(pud0, 0);
1446 
1447         pgdk = pgd_offset_k(map_start);
1448         pudk = pud_offset(pgdk, map_start);
1449         pmdk = pmd_offset(pudk, map_start);
1450 
1451         mdesc->init_meminfo();
1452 
1453         /* Run the patch stub to update the constants */
1454         fixup_pv_table(&__pv_table_begin,
1455                 (&__pv_table_end - &__pv_table_begin) << 2);
1456 
1457         /*
1458          * Cache cleaning operations for self-modifying code
1459          * We should clean the entries by MVA but running a
1460          * for loop over every pv_table entry pointer would
1461          * just complicate the code.
1462          */
1463         flush_cache_louis();
1464         dsb();
1465         isb();
1466 
1467         /* remap level 1 table */
1468         for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1469                 set_pud(pud0,
1470                         __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1471                 pmd0 += PTRS_PER_PMD;
1472         }
1473 
1474         /* remap pmds for kernel mapping */
1475         phys = __pa(map_start);
1476         do {
1477                 *pmdk++ = __pmd(phys | pmdprot);
1478                 phys += PMD_SIZE;
1479         } while (phys < map_end);
1480 
1481         flush_cache_all();
1482         cpu_switch_mm(pgd0, &init_mm);
1483         cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1484         local_flush_bp_all();
1485         local_flush_tlb_all();
1486 }
1487 
1488 #else
1489 
1490 void __init early_paging_init(const struct machine_desc *mdesc,
1491                               struct proc_info_list *procinfo)
1492 {
1493         if (mdesc->init_meminfo)
1494                 mdesc->init_meminfo();
1495 }
1496 
1497 #endif
1498 
1499 /*
1500  * paging_init() sets up the page tables, initialises the zone memory
1501  * maps, and sets up the zero page, bad page and bad page tables.
1502  */
1503 void __init paging_init(const struct machine_desc *mdesc)
1504 {
1505         void *zero_page;
1506 
1507         build_mem_type_table();
1508         prepare_page_table();
1509         map_lowmem();
1510         dma_contiguous_remap();
1511         devicemaps_init(mdesc);
1512         kmap_init();
1513         tcm_init();
1514 
1515         top_pmd = pmd_off_k(0xffff0000);
1516 
1517         /* allocate the zero page. */
1518         zero_page = early_alloc(PAGE_SIZE);
1519 
1520         bootmem_init();
1521 
1522         empty_zero_page = virt_to_page(zero_page);
1523         __flush_dcache_page(NULL, empty_zero_page);
1524 }
1525 

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