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Linux/arch/arm64/include/asm/kvm_host.h

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  1 /*
  2  * Copyright (C) 2012,2013 - ARM Ltd
  3  * Author: Marc Zyngier <marc.zyngier@arm.com>
  4  *
  5  * Derived from arch/arm/include/asm/kvm_host.h:
  6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  7  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #ifndef __ARM64_KVM_HOST_H__
 23 #define __ARM64_KVM_HOST_H__
 24 
 25 #include <linux/types.h>
 26 #include <linux/kvm_types.h>
 27 #include <asm/cpufeature.h>
 28 #include <asm/daifflags.h>
 29 #include <asm/fpsimd.h>
 30 #include <asm/kvm.h>
 31 #include <asm/kvm_asm.h>
 32 #include <asm/kvm_mmio.h>
 33 
 34 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
 35 
 36 #define KVM_USER_MEM_SLOTS 512
 37 #define KVM_HALT_POLL_NS_DEFAULT 500000
 38 
 39 #include <kvm/arm_vgic.h>
 40 #include <kvm/arm_arch_timer.h>
 41 #include <kvm/arm_pmu.h>
 42 
 43 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
 44 
 45 #define KVM_VCPU_MAX_FEATURES 4
 46 
 47 #define KVM_REQ_SLEEP \
 48         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 49 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
 50 
 51 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 52 
 53 int __attribute_const__ kvm_target_cpu(void);
 54 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 55 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
 56 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
 57 
 58 struct kvm_arch {
 59         /* The VMID generation used for the virt. memory system */
 60         u64    vmid_gen;
 61         u32    vmid;
 62 
 63         /* 1-level 2nd stage table and lock */
 64         spinlock_t pgd_lock;
 65         pgd_t *pgd;
 66 
 67         /* VTTBR value associated with above pgd and vmid */
 68         u64    vttbr;
 69 
 70         /* The last vcpu id that ran on each physical CPU */
 71         int __percpu *last_vcpu_ran;
 72 
 73         /* The maximum number of vCPUs depends on the used GIC model */
 74         int max_vcpus;
 75 
 76         /* Interrupt controller */
 77         struct vgic_dist        vgic;
 78 
 79         /* Mandated version of PSCI */
 80         u32 psci_version;
 81 };
 82 
 83 #define KVM_NR_MEM_OBJS     40
 84 
 85 /*
 86  * We don't want allocation failures within the mmu code, so we preallocate
 87  * enough memory for a single page fault in a cache.
 88  */
 89 struct kvm_mmu_memory_cache {
 90         int nobjs;
 91         void *objects[KVM_NR_MEM_OBJS];
 92 };
 93 
 94 struct kvm_vcpu_fault_info {
 95         u32 esr_el2;            /* Hyp Syndrom Register */
 96         u64 far_el2;            /* Hyp Fault Address Register */
 97         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
 98         u64 disr_el1;           /* Deferred [SError] Status Register */
 99 };
100 
101 /*
102  * 0 is reserved as an invalid value.
103  * Order should be kept in sync with the save/restore code.
104  */
105 enum vcpu_sysreg {
106         __INVALID_SYSREG__,
107         MPIDR_EL1,      /* MultiProcessor Affinity Register */
108         CSSELR_EL1,     /* Cache Size Selection Register */
109         SCTLR_EL1,      /* System Control Register */
110         ACTLR_EL1,      /* Auxiliary Control Register */
111         CPACR_EL1,      /* Coprocessor Access Control */
112         TTBR0_EL1,      /* Translation Table Base Register 0 */
113         TTBR1_EL1,      /* Translation Table Base Register 1 */
114         TCR_EL1,        /* Translation Control Register */
115         ESR_EL1,        /* Exception Syndrome Register */
116         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
117         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
118         FAR_EL1,        /* Fault Address Register */
119         MAIR_EL1,       /* Memory Attribute Indirection Register */
120         VBAR_EL1,       /* Vector Base Address Register */
121         CONTEXTIDR_EL1, /* Context ID Register */
122         TPIDR_EL0,      /* Thread ID, User R/W */
123         TPIDRRO_EL0,    /* Thread ID, User R/O */
124         TPIDR_EL1,      /* Thread ID, Privileged */
125         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
126         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
127         PAR_EL1,        /* Physical Address Register */
128         MDSCR_EL1,      /* Monitor Debug System Control Register */
129         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
130         DISR_EL1,       /* Deferred Interrupt Status Register */
131 
132         /* Performance Monitors Registers */
133         PMCR_EL0,       /* Control Register */
134         PMSELR_EL0,     /* Event Counter Selection Register */
135         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
136         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
137         PMCCNTR_EL0,    /* Cycle Counter Register */
138         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
139         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
140         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
141         PMCNTENSET_EL0, /* Count Enable Set Register */
142         PMINTENSET_EL1, /* Interrupt Enable Set Register */
143         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
144         PMSWINC_EL0,    /* Software Increment Register */
145         PMUSERENR_EL0,  /* User Enable Register */
146 
147         /* 32bit specific registers. Keep them at the end of the range */
148         DACR32_EL2,     /* Domain Access Control Register */
149         IFSR32_EL2,     /* Instruction Fault Status Register */
150         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
151         DBGVCR32_EL2,   /* Debug Vector Catch Register */
152 
153         NR_SYS_REGS     /* Nothing after this line! */
154 };
155 
156 /* 32bit mapping */
157 #define c0_MPIDR        (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
158 #define c0_CSSELR       (CSSELR_EL1 * 2)/* Cache Size Selection Register */
159 #define c1_SCTLR        (SCTLR_EL1 * 2) /* System Control Register */
160 #define c1_ACTLR        (ACTLR_EL1 * 2) /* Auxiliary Control Register */
161 #define c1_CPACR        (CPACR_EL1 * 2) /* Coprocessor Access Control */
162 #define c2_TTBR0        (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
163 #define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
164 #define c2_TTBR1        (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
165 #define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
166 #define c2_TTBCR        (TCR_EL1 * 2)   /* Translation Table Base Control R. */
167 #define c3_DACR         (DACR32_EL2 * 2)/* Domain Access Control Register */
168 #define c5_DFSR         (ESR_EL1 * 2)   /* Data Fault Status Register */
169 #define c5_IFSR         (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
170 #define c5_ADFSR        (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
171 #define c5_AIFSR        (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
172 #define c6_DFAR         (FAR_EL1 * 2)   /* Data Fault Address Register */
173 #define c6_IFAR         (c6_DFAR + 1)   /* Instruction Fault Address Register */
174 #define c7_PAR          (PAR_EL1 * 2)   /* Physical Address Register */
175 #define c7_PAR_high     (c7_PAR + 1)    /* PAR top 32 bits */
176 #define c10_PRRR        (MAIR_EL1 * 2)  /* Primary Region Remap Register */
177 #define c10_NMRR        (c10_PRRR + 1)  /* Normal Memory Remap Register */
178 #define c12_VBAR        (VBAR_EL1 * 2)  /* Vector Base Address Register */
179 #define c13_CID         (CONTEXTIDR_EL1 * 2)    /* Context ID Register */
180 #define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
181 #define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
182 #define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
183 #define c10_AMAIR0      (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
184 #define c10_AMAIR1      (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
185 #define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
186 
187 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
188 #define cp14_DBGBCR0    (DBGBCR0_EL1 * 2)
189 #define cp14_DBGBVR0    (DBGBVR0_EL1 * 2)
190 #define cp14_DBGBXVR0   (cp14_DBGBVR0 + 1)
191 #define cp14_DBGWCR0    (DBGWCR0_EL1 * 2)
192 #define cp14_DBGWVR0    (DBGWVR0_EL1 * 2)
193 #define cp14_DBGDCCINT  (MDCCINT_EL1 * 2)
194 
195 #define NR_COPRO_REGS   (NR_SYS_REGS * 2)
196 
197 struct kvm_cpu_context {
198         struct kvm_regs gp_regs;
199         union {
200                 u64 sys_regs[NR_SYS_REGS];
201                 u32 copro[NR_COPRO_REGS];
202         };
203 
204         struct kvm_vcpu *__hyp_running_vcpu;
205 };
206 
207 typedef struct kvm_cpu_context kvm_cpu_context_t;
208 
209 struct kvm_vcpu_arch {
210         struct kvm_cpu_context ctxt;
211 
212         /* HYP configuration */
213         u64 hcr_el2;
214         u32 mdcr_el2;
215 
216         /* Exception Information */
217         struct kvm_vcpu_fault_info fault;
218 
219         /* Guest debug state */
220         u64 debug_flags;
221 
222         /*
223          * We maintain more than a single set of debug registers to support
224          * debugging the guest from the host and to maintain separate host and
225          * guest state during world switches. vcpu_debug_state are the debug
226          * registers of the vcpu as the guest sees them.  host_debug_state are
227          * the host registers which are saved and restored during
228          * world switches. external_debug_state contains the debug
229          * values we want to debug the guest. This is set via the
230          * KVM_SET_GUEST_DEBUG ioctl.
231          *
232          * debug_ptr points to the set of debug registers that should be loaded
233          * onto the hardware when running the guest.
234          */
235         struct kvm_guest_debug_arch *debug_ptr;
236         struct kvm_guest_debug_arch vcpu_debug_state;
237         struct kvm_guest_debug_arch external_debug_state;
238 
239         /* Pointer to host CPU context */
240         kvm_cpu_context_t *host_cpu_context;
241         struct {
242                 /* {Break,watch}point registers */
243                 struct kvm_guest_debug_arch regs;
244                 /* Statistical profiling extension */
245                 u64 pmscr_el1;
246         } host_debug_state;
247 
248         /* VGIC state */
249         struct vgic_cpu vgic_cpu;
250         struct arch_timer_cpu timer_cpu;
251         struct kvm_pmu pmu;
252 
253         /*
254          * Anything that is not used directly from assembly code goes
255          * here.
256          */
257 
258         /*
259          * Guest registers we preserve during guest debugging.
260          *
261          * These shadow registers are updated by the kvm_handle_sys_reg
262          * trap handler if the guest accesses or updates them while we
263          * are using guest debug.
264          */
265         struct {
266                 u32     mdscr_el1;
267         } guest_debug_preserved;
268 
269         /* vcpu power-off state */
270         bool power_off;
271 
272         /* Don't run the guest (internal implementation need) */
273         bool pause;
274 
275         /* IO related fields */
276         struct kvm_decode mmio_decode;
277 
278         /* Interrupt related fields */
279         u64 irq_lines;          /* IRQ and FIQ levels */
280 
281         /* Cache some mmu pages needed inside spinlock regions */
282         struct kvm_mmu_memory_cache mmu_page_cache;
283 
284         /* Target CPU and feature flags */
285         int target;
286         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
287 
288         /* Detect first run of a vcpu */
289         bool has_run_once;
290 
291         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
292         u64 vsesr_el2;
293 };
294 
295 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.gp_regs)
296 #define vcpu_sys_reg(v,r)       ((v)->arch.ctxt.sys_regs[(r)])
297 /*
298  * CP14 and CP15 live in the same array, as they are backed by the
299  * same system registers.
300  */
301 #define vcpu_cp14(v,r)          ((v)->arch.ctxt.copro[(r)])
302 #define vcpu_cp15(v,r)          ((v)->arch.ctxt.copro[(r)])
303 
304 #ifdef CONFIG_CPU_BIG_ENDIAN
305 #define vcpu_cp15_64_high(v,r)  vcpu_cp15((v),(r))
306 #define vcpu_cp15_64_low(v,r)   vcpu_cp15((v),(r) + 1)
307 #else
308 #define vcpu_cp15_64_high(v,r)  vcpu_cp15((v),(r) + 1)
309 #define vcpu_cp15_64_low(v,r)   vcpu_cp15((v),(r))
310 #endif
311 
312 struct kvm_vm_stat {
313         ulong remote_tlb_flush;
314 };
315 
316 struct kvm_vcpu_stat {
317         u64 halt_successful_poll;
318         u64 halt_attempted_poll;
319         u64 halt_poll_invalid;
320         u64 halt_wakeup;
321         u64 hvc_exit_stat;
322         u64 wfe_exit_stat;
323         u64 wfi_exit_stat;
324         u64 mmio_exit_user;
325         u64 mmio_exit_kernel;
326         u64 exits;
327 };
328 
329 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
330 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
331 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
332 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
333 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
334 
335 #define KVM_ARCH_WANT_MMU_NOTIFIER
336 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
337 int kvm_unmap_hva_range(struct kvm *kvm,
338                         unsigned long start, unsigned long end);
339 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
340 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
341 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
342 
343 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
344 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
345 void kvm_arm_halt_guest(struct kvm *kvm);
346 void kvm_arm_resume_guest(struct kvm *kvm);
347 
348 u64 __kvm_call_hyp(void *hypfn, ...);
349 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
350 
351 void force_vm_exit(const cpumask_t *mask);
352 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
353 
354 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
355                 int exception_index);
356 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
357                        int exception_index);
358 
359 int kvm_perf_init(void);
360 int kvm_perf_teardown(void);
361 
362 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
363 
364 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
365                                        unsigned long hyp_stack_ptr,
366                                        unsigned long vector_ptr)
367 {
368         /*
369          * Call initialization code, and switch to the full blown HYP code.
370          * If the cpucaps haven't been finalized yet, something has gone very
371          * wrong, and hyp will crash and burn when it uses any
372          * cpus_have_const_cap() wrapper.
373          */
374         BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
375         __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
376 }
377 
378 static inline void kvm_arch_hardware_unsetup(void) {}
379 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
380 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
381 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
382 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
383 
384 void kvm_arm_init_debug(void);
385 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
386 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
387 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
388 bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
389 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
390                                struct kvm_device_attr *attr);
391 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
392                                struct kvm_device_attr *attr);
393 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
394                                struct kvm_device_attr *attr);
395 
396 static inline void __cpu_init_stage2(void)
397 {
398         u32 parange = kvm_call_hyp(__init_stage2_translation);
399 
400         WARN_ONCE(parange < 40,
401                   "PARange is %d bits, unsupported configuration!", parange);
402 }
403 
404 /*
405  * All host FP/SIMD state is restored on guest exit, so nothing needs
406  * doing here except in the SVE case:
407 */
408 static inline void kvm_fpsimd_flush_cpu_state(void)
409 {
410         if (system_supports_sve())
411                 sve_flush_cpu_state();
412 }
413 
414 static inline void kvm_arm_vhe_guest_enter(void)
415 {
416         local_daif_mask();
417 }
418 
419 static inline void kvm_arm_vhe_guest_exit(void)
420 {
421         local_daif_restore(DAIF_PROCCTX_NOIRQ);
422 }
423 
424 static inline bool kvm_arm_harden_branch_predictor(void)
425 {
426         return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
427 }
428 
429 #endif /* __ARM64_KVM_HOST_H__ */
430 

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