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TOMOYO Linux Cross Reference
Linux/arch/arm64/kvm/sys_regs.c

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  1 /*
  2  * Copyright (C) 2012,2013 - ARM Ltd
  3  * Author: Marc Zyngier <marc.zyngier@arm.com>
  4  *
  5  * Derived from arch/arm/kvm/coproc.c:
  6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
  8  *          Christoffer Dall <c.dall@virtualopensystems.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License, version 2, as
 12  * published by the Free Software Foundation.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 21  */
 22 
 23 #include <linux/bsearch.h>
 24 #include <linux/kvm_host.h>
 25 #include <linux/mm.h>
 26 #include <linux/uaccess.h>
 27 
 28 #include <asm/cacheflush.h>
 29 #include <asm/cputype.h>
 30 #include <asm/debug-monitors.h>
 31 #include <asm/esr.h>
 32 #include <asm/kvm_arm.h>
 33 #include <asm/kvm_asm.h>
 34 #include <asm/kvm_coproc.h>
 35 #include <asm/kvm_emulate.h>
 36 #include <asm/kvm_host.h>
 37 #include <asm/kvm_mmu.h>
 38 #include <asm/perf_event.h>
 39 
 40 #include <trace/events/kvm.h>
 41 
 42 #include "sys_regs.h"
 43 
 44 #include "trace.h"
 45 
 46 /*
 47  * All of this file is extremly similar to the ARM coproc.c, but the
 48  * types are different. My gut feeling is that it should be pretty
 49  * easy to merge, but that would be an ABI breakage -- again. VFP
 50  * would also need to be abstracted.
 51  *
 52  * For AArch32, we only take care of what is being trapped. Anything
 53  * that has to do with init and userspace access has to go via the
 54  * 64bit interface.
 55  */
 56 
 57 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
 58 static u32 cache_levels;
 59 
 60 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
 61 #define CSSELR_MAX 12
 62 
 63 /* Which cache CCSIDR represents depends on CSSELR value. */
 64 static u32 get_ccsidr(u32 csselr)
 65 {
 66         u32 ccsidr;
 67 
 68         /* Make sure noone else changes CSSELR during this! */
 69         local_irq_disable();
 70         /* Put value into CSSELR */
 71         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
 72         isb();
 73         /* Read result out of CCSIDR */
 74         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
 75         local_irq_enable();
 76 
 77         return ccsidr;
 78 }
 79 
 80 /*
 81  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
 82  */
 83 static bool access_dcsw(struct kvm_vcpu *vcpu,
 84                         struct sys_reg_params *p,
 85                         const struct sys_reg_desc *r)
 86 {
 87         if (!p->is_write)
 88                 return read_from_write_only(vcpu, p);
 89 
 90         kvm_set_way_flush(vcpu);
 91         return true;
 92 }
 93 
 94 /*
 95  * Generic accessor for VM registers. Only called as long as HCR_TVM
 96  * is set. If the guest enables the MMU, we stop trapping the VM
 97  * sys_regs and leave it in complete control of the caches.
 98  */
 99 static bool access_vm_reg(struct kvm_vcpu *vcpu,
100                           struct sys_reg_params *p,
101                           const struct sys_reg_desc *r)
102 {
103         bool was_enabled = vcpu_has_cache_enabled(vcpu);
104 
105         BUG_ON(!p->is_write);
106 
107         if (!p->is_aarch32) {
108                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
109         } else {
110                 if (!p->is_32bit)
111                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
112                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
113         }
114 
115         kvm_toggle_cache(vcpu, was_enabled);
116         return true;
117 }
118 
119 /*
120  * Trap handler for the GICv3 SGI generation system register.
121  * Forward the request to the VGIC emulation.
122  * The cp15_64 code makes sure this automatically works
123  * for both AArch64 and AArch32 accesses.
124  */
125 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
126                            struct sys_reg_params *p,
127                            const struct sys_reg_desc *r)
128 {
129         if (!p->is_write)
130                 return read_from_write_only(vcpu, p);
131 
132         vgic_v3_dispatch_sgi(vcpu, p->regval);
133 
134         return true;
135 }
136 
137 static bool access_gic_sre(struct kvm_vcpu *vcpu,
138                            struct sys_reg_params *p,
139                            const struct sys_reg_desc *r)
140 {
141         if (p->is_write)
142                 return ignore_write(vcpu, p);
143 
144         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
145         return true;
146 }
147 
148 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
149                         struct sys_reg_params *p,
150                         const struct sys_reg_desc *r)
151 {
152         if (p->is_write)
153                 return ignore_write(vcpu, p);
154         else
155                 return read_zero(vcpu, p);
156 }
157 
158 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
159                            struct sys_reg_params *p,
160                            const struct sys_reg_desc *r)
161 {
162         if (p->is_write) {
163                 return ignore_write(vcpu, p);
164         } else {
165                 p->regval = (1 << 3);
166                 return true;
167         }
168 }
169 
170 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
171                                    struct sys_reg_params *p,
172                                    const struct sys_reg_desc *r)
173 {
174         if (p->is_write) {
175                 return ignore_write(vcpu, p);
176         } else {
177                 u32 val;
178                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
179                 p->regval = val;
180                 return true;
181         }
182 }
183 
184 /*
185  * We want to avoid world-switching all the DBG registers all the
186  * time:
187  * 
188  * - If we've touched any debug register, it is likely that we're
189  *   going to touch more of them. It then makes sense to disable the
190  *   traps and start doing the save/restore dance
191  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
192  *   then mandatory to save/restore the registers, as the guest
193  *   depends on them.
194  * 
195  * For this, we use a DIRTY bit, indicating the guest has modified the
196  * debug registers, used as follow:
197  *
198  * On guest entry:
199  * - If the dirty bit is set (because we're coming back from trapping),
200  *   disable the traps, save host registers, restore guest registers.
201  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
202  *   set the dirty bit, disable the traps, save host registers,
203  *   restore guest registers.
204  * - Otherwise, enable the traps
205  *
206  * On guest exit:
207  * - If the dirty bit is set, save guest registers, restore host
208  *   registers and clear the dirty bit. This ensure that the host can
209  *   now use the debug registers.
210  */
211 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
212                             struct sys_reg_params *p,
213                             const struct sys_reg_desc *r)
214 {
215         if (p->is_write) {
216                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
217                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
218         } else {
219                 p->regval = vcpu_sys_reg(vcpu, r->reg);
220         }
221 
222         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
223 
224         return true;
225 }
226 
227 /*
228  * reg_to_dbg/dbg_to_reg
229  *
230  * A 32 bit write to a debug register leave top bits alone
231  * A 32 bit read from a debug register only returns the bottom bits
232  *
233  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
234  * hyp.S code switches between host and guest values in future.
235  */
236 static void reg_to_dbg(struct kvm_vcpu *vcpu,
237                        struct sys_reg_params *p,
238                        u64 *dbg_reg)
239 {
240         u64 val = p->regval;
241 
242         if (p->is_32bit) {
243                 val &= 0xffffffffUL;
244                 val |= ((*dbg_reg >> 32) << 32);
245         }
246 
247         *dbg_reg = val;
248         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
249 }
250 
251 static void dbg_to_reg(struct kvm_vcpu *vcpu,
252                        struct sys_reg_params *p,
253                        u64 *dbg_reg)
254 {
255         p->regval = *dbg_reg;
256         if (p->is_32bit)
257                 p->regval &= 0xffffffffUL;
258 }
259 
260 static bool trap_bvr(struct kvm_vcpu *vcpu,
261                      struct sys_reg_params *p,
262                      const struct sys_reg_desc *rd)
263 {
264         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
265 
266         if (p->is_write)
267                 reg_to_dbg(vcpu, p, dbg_reg);
268         else
269                 dbg_to_reg(vcpu, p, dbg_reg);
270 
271         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
272 
273         return true;
274 }
275 
276 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
277                 const struct kvm_one_reg *reg, void __user *uaddr)
278 {
279         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
280 
281         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
282                 return -EFAULT;
283         return 0;
284 }
285 
286 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
287         const struct kvm_one_reg *reg, void __user *uaddr)
288 {
289         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
290 
291         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
292                 return -EFAULT;
293         return 0;
294 }
295 
296 static void reset_bvr(struct kvm_vcpu *vcpu,
297                       const struct sys_reg_desc *rd)
298 {
299         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
300 }
301 
302 static bool trap_bcr(struct kvm_vcpu *vcpu,
303                      struct sys_reg_params *p,
304                      const struct sys_reg_desc *rd)
305 {
306         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
307 
308         if (p->is_write)
309                 reg_to_dbg(vcpu, p, dbg_reg);
310         else
311                 dbg_to_reg(vcpu, p, dbg_reg);
312 
313         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
314 
315         return true;
316 }
317 
318 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
319                 const struct kvm_one_reg *reg, void __user *uaddr)
320 {
321         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
322 
323         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
324                 return -EFAULT;
325 
326         return 0;
327 }
328 
329 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
330         const struct kvm_one_reg *reg, void __user *uaddr)
331 {
332         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
333 
334         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
335                 return -EFAULT;
336         return 0;
337 }
338 
339 static void reset_bcr(struct kvm_vcpu *vcpu,
340                       const struct sys_reg_desc *rd)
341 {
342         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
343 }
344 
345 static bool trap_wvr(struct kvm_vcpu *vcpu,
346                      struct sys_reg_params *p,
347                      const struct sys_reg_desc *rd)
348 {
349         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
350 
351         if (p->is_write)
352                 reg_to_dbg(vcpu, p, dbg_reg);
353         else
354                 dbg_to_reg(vcpu, p, dbg_reg);
355 
356         trace_trap_reg(__func__, rd->reg, p->is_write,
357                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
358 
359         return true;
360 }
361 
362 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
363                 const struct kvm_one_reg *reg, void __user *uaddr)
364 {
365         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
366 
367         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
368                 return -EFAULT;
369         return 0;
370 }
371 
372 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
373         const struct kvm_one_reg *reg, void __user *uaddr)
374 {
375         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
376 
377         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
378                 return -EFAULT;
379         return 0;
380 }
381 
382 static void reset_wvr(struct kvm_vcpu *vcpu,
383                       const struct sys_reg_desc *rd)
384 {
385         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
386 }
387 
388 static bool trap_wcr(struct kvm_vcpu *vcpu,
389                      struct sys_reg_params *p,
390                      const struct sys_reg_desc *rd)
391 {
392         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
393 
394         if (p->is_write)
395                 reg_to_dbg(vcpu, p, dbg_reg);
396         else
397                 dbg_to_reg(vcpu, p, dbg_reg);
398 
399         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
400 
401         return true;
402 }
403 
404 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
405                 const struct kvm_one_reg *reg, void __user *uaddr)
406 {
407         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
408 
409         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
410                 return -EFAULT;
411         return 0;
412 }
413 
414 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
415         const struct kvm_one_reg *reg, void __user *uaddr)
416 {
417         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
418 
419         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
420                 return -EFAULT;
421         return 0;
422 }
423 
424 static void reset_wcr(struct kvm_vcpu *vcpu,
425                       const struct sys_reg_desc *rd)
426 {
427         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
428 }
429 
430 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
431 {
432         u64 amair;
433 
434         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
435         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
436 }
437 
438 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
439 {
440         u64 mpidr;
441 
442         /*
443          * Map the vcpu_id into the first three affinity level fields of
444          * the MPIDR. We limit the number of VCPUs in level 0 due to a
445          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
446          * of the GICv3 to be able to address each CPU directly when
447          * sending IPIs.
448          */
449         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
450         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
451         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
452         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
453 }
454 
455 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
456 {
457         u64 pmcr, val;
458 
459         asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
460         /* Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) is reset to UNKNOWN
461          * except PMCR.E resetting to zero.
462          */
463         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
464                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
465         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
466 }
467 
468 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
469 {
470         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
471 
472         return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
473 }
474 
475 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
476 {
477         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
478 
479         return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
480                  || vcpu_mode_priv(vcpu));
481 }
482 
483 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
484 {
485         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
486 
487         return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
488                  || vcpu_mode_priv(vcpu));
489 }
490 
491 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
492 {
493         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
494 
495         return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
496                  || vcpu_mode_priv(vcpu));
497 }
498 
499 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
500                         const struct sys_reg_desc *r)
501 {
502         u64 val;
503 
504         if (!kvm_arm_pmu_v3_ready(vcpu))
505                 return trap_raz_wi(vcpu, p, r);
506 
507         if (pmu_access_el0_disabled(vcpu))
508                 return false;
509 
510         if (p->is_write) {
511                 /* Only update writeable bits of PMCR */
512                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
513                 val &= ~ARMV8_PMU_PMCR_MASK;
514                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
515                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
516                 kvm_pmu_handle_pmcr(vcpu, val);
517         } else {
518                 /* PMCR.P & PMCR.C are RAZ */
519                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
520                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
521                 p->regval = val;
522         }
523 
524         return true;
525 }
526 
527 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
528                           const struct sys_reg_desc *r)
529 {
530         if (!kvm_arm_pmu_v3_ready(vcpu))
531                 return trap_raz_wi(vcpu, p, r);
532 
533         if (pmu_access_event_counter_el0_disabled(vcpu))
534                 return false;
535 
536         if (p->is_write)
537                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
538         else
539                 /* return PMSELR.SEL field */
540                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
541                             & ARMV8_PMU_COUNTER_MASK;
542 
543         return true;
544 }
545 
546 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
547                           const struct sys_reg_desc *r)
548 {
549         u64 pmceid;
550 
551         if (!kvm_arm_pmu_v3_ready(vcpu))
552                 return trap_raz_wi(vcpu, p, r);
553 
554         BUG_ON(p->is_write);
555 
556         if (pmu_access_el0_disabled(vcpu))
557                 return false;
558 
559         if (!(p->Op2 & 1))
560                 asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
561         else
562                 asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
563 
564         p->regval = pmceid;
565 
566         return true;
567 }
568 
569 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
570 {
571         u64 pmcr, val;
572 
573         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
574         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
575         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
576                 return false;
577 
578         return true;
579 }
580 
581 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
582                               struct sys_reg_params *p,
583                               const struct sys_reg_desc *r)
584 {
585         u64 idx;
586 
587         if (!kvm_arm_pmu_v3_ready(vcpu))
588                 return trap_raz_wi(vcpu, p, r);
589 
590         if (r->CRn == 9 && r->CRm == 13) {
591                 if (r->Op2 == 2) {
592                         /* PMXEVCNTR_EL0 */
593                         if (pmu_access_event_counter_el0_disabled(vcpu))
594                                 return false;
595 
596                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
597                               & ARMV8_PMU_COUNTER_MASK;
598                 } else if (r->Op2 == 0) {
599                         /* PMCCNTR_EL0 */
600                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
601                                 return false;
602 
603                         idx = ARMV8_PMU_CYCLE_IDX;
604                 } else {
605                         return false;
606                 }
607         } else if (r->CRn == 0 && r->CRm == 9) {
608                 /* PMCCNTR */
609                 if (pmu_access_event_counter_el0_disabled(vcpu))
610                         return false;
611 
612                 idx = ARMV8_PMU_CYCLE_IDX;
613         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
614                 /* PMEVCNTRn_EL0 */
615                 if (pmu_access_event_counter_el0_disabled(vcpu))
616                         return false;
617 
618                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
619         } else {
620                 return false;
621         }
622 
623         if (!pmu_counter_idx_valid(vcpu, idx))
624                 return false;
625 
626         if (p->is_write) {
627                 if (pmu_access_el0_disabled(vcpu))
628                         return false;
629 
630                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
631         } else {
632                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
633         }
634 
635         return true;
636 }
637 
638 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
639                                const struct sys_reg_desc *r)
640 {
641         u64 idx, reg;
642 
643         if (!kvm_arm_pmu_v3_ready(vcpu))
644                 return trap_raz_wi(vcpu, p, r);
645 
646         if (pmu_access_el0_disabled(vcpu))
647                 return false;
648 
649         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
650                 /* PMXEVTYPER_EL0 */
651                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
652                 reg = PMEVTYPER0_EL0 + idx;
653         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
654                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
655                 if (idx == ARMV8_PMU_CYCLE_IDX)
656                         reg = PMCCFILTR_EL0;
657                 else
658                         /* PMEVTYPERn_EL0 */
659                         reg = PMEVTYPER0_EL0 + idx;
660         } else {
661                 BUG();
662         }
663 
664         if (!pmu_counter_idx_valid(vcpu, idx))
665                 return false;
666 
667         if (p->is_write) {
668                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
669                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
670         } else {
671                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
672         }
673 
674         return true;
675 }
676 
677 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
678                            const struct sys_reg_desc *r)
679 {
680         u64 val, mask;
681 
682         if (!kvm_arm_pmu_v3_ready(vcpu))
683                 return trap_raz_wi(vcpu, p, r);
684 
685         if (pmu_access_el0_disabled(vcpu))
686                 return false;
687 
688         mask = kvm_pmu_valid_counter_mask(vcpu);
689         if (p->is_write) {
690                 val = p->regval & mask;
691                 if (r->Op2 & 0x1) {
692                         /* accessing PMCNTENSET_EL0 */
693                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
694                         kvm_pmu_enable_counter(vcpu, val);
695                 } else {
696                         /* accessing PMCNTENCLR_EL0 */
697                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
698                         kvm_pmu_disable_counter(vcpu, val);
699                 }
700         } else {
701                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
702         }
703 
704         return true;
705 }
706 
707 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
708                            const struct sys_reg_desc *r)
709 {
710         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
711 
712         if (!kvm_arm_pmu_v3_ready(vcpu))
713                 return trap_raz_wi(vcpu, p, r);
714 
715         if (!vcpu_mode_priv(vcpu))
716                 return false;
717 
718         if (p->is_write) {
719                 u64 val = p->regval & mask;
720 
721                 if (r->Op2 & 0x1)
722                         /* accessing PMINTENSET_EL1 */
723                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
724                 else
725                         /* accessing PMINTENCLR_EL1 */
726                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
727         } else {
728                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
729         }
730 
731         return true;
732 }
733 
734 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
735                          const struct sys_reg_desc *r)
736 {
737         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
738 
739         if (!kvm_arm_pmu_v3_ready(vcpu))
740                 return trap_raz_wi(vcpu, p, r);
741 
742         if (pmu_access_el0_disabled(vcpu))
743                 return false;
744 
745         if (p->is_write) {
746                 if (r->CRm & 0x2)
747                         /* accessing PMOVSSET_EL0 */
748                         kvm_pmu_overflow_set(vcpu, p->regval & mask);
749                 else
750                         /* accessing PMOVSCLR_EL0 */
751                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
752         } else {
753                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
754         }
755 
756         return true;
757 }
758 
759 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
760                            const struct sys_reg_desc *r)
761 {
762         u64 mask;
763 
764         if (!kvm_arm_pmu_v3_ready(vcpu))
765                 return trap_raz_wi(vcpu, p, r);
766 
767         if (pmu_write_swinc_el0_disabled(vcpu))
768                 return false;
769 
770         if (p->is_write) {
771                 mask = kvm_pmu_valid_counter_mask(vcpu);
772                 kvm_pmu_software_increment(vcpu, p->regval & mask);
773                 return true;
774         }
775 
776         return false;
777 }
778 
779 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
780                              const struct sys_reg_desc *r)
781 {
782         if (!kvm_arm_pmu_v3_ready(vcpu))
783                 return trap_raz_wi(vcpu, p, r);
784 
785         if (p->is_write) {
786                 if (!vcpu_mode_priv(vcpu))
787                         return false;
788 
789                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
790                                                     & ARMV8_PMU_USERENR_MASK;
791         } else {
792                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
793                             & ARMV8_PMU_USERENR_MASK;
794         }
795 
796         return true;
797 }
798 
799 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
800 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
801         /* DBGBVRn_EL1 */                                               \
802         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
803           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
804         /* DBGBCRn_EL1 */                                               \
805         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
806           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
807         /* DBGWVRn_EL1 */                                               \
808         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
809           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
810         /* DBGWCRn_EL1 */                                               \
811         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
812           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
813 
814 /* Macro to expand the PMEVCNTRn_EL0 register */
815 #define PMU_PMEVCNTR_EL0(n)                                             \
816         /* PMEVCNTRn_EL0 */                                             \
817         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
818           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
819           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
820 
821 /* Macro to expand the PMEVTYPERn_EL0 register */
822 #define PMU_PMEVTYPER_EL0(n)                                            \
823         /* PMEVTYPERn_EL0 */                                            \
824         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
825           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
826           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
827 
828 /*
829  * Architected system registers.
830  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
831  *
832  * Debug handling: We do trap most, if not all debug related system
833  * registers. The implementation is good enough to ensure that a guest
834  * can use these with minimal performance degradation. The drawback is
835  * that we don't implement any of the external debug, none of the
836  * OSlock protocol. This should be revisited if we ever encounter a
837  * more demanding guest...
838  */
839 static const struct sys_reg_desc sys_reg_descs[] = {
840         /* DC ISW */
841         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
842           access_dcsw },
843         /* DC CSW */
844         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
845           access_dcsw },
846         /* DC CISW */
847         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
848           access_dcsw },
849 
850         DBG_BCR_BVR_WCR_WVR_EL1(0),
851         DBG_BCR_BVR_WCR_WVR_EL1(1),
852         /* MDCCINT_EL1 */
853         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
854           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
855         /* MDSCR_EL1 */
856         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
857           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
858         DBG_BCR_BVR_WCR_WVR_EL1(2),
859         DBG_BCR_BVR_WCR_WVR_EL1(3),
860         DBG_BCR_BVR_WCR_WVR_EL1(4),
861         DBG_BCR_BVR_WCR_WVR_EL1(5),
862         DBG_BCR_BVR_WCR_WVR_EL1(6),
863         DBG_BCR_BVR_WCR_WVR_EL1(7),
864         DBG_BCR_BVR_WCR_WVR_EL1(8),
865         DBG_BCR_BVR_WCR_WVR_EL1(9),
866         DBG_BCR_BVR_WCR_WVR_EL1(10),
867         DBG_BCR_BVR_WCR_WVR_EL1(11),
868         DBG_BCR_BVR_WCR_WVR_EL1(12),
869         DBG_BCR_BVR_WCR_WVR_EL1(13),
870         DBG_BCR_BVR_WCR_WVR_EL1(14),
871         DBG_BCR_BVR_WCR_WVR_EL1(15),
872 
873         /* MDRAR_EL1 */
874         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
875           trap_raz_wi },
876         /* OSLAR_EL1 */
877         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
878           trap_raz_wi },
879         /* OSLSR_EL1 */
880         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
881           trap_oslsr_el1 },
882         /* OSDLR_EL1 */
883         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
884           trap_raz_wi },
885         /* DBGPRCR_EL1 */
886         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
887           trap_raz_wi },
888         /* DBGCLAIMSET_EL1 */
889         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
890           trap_raz_wi },
891         /* DBGCLAIMCLR_EL1 */
892         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
893           trap_raz_wi },
894         /* DBGAUTHSTATUS_EL1 */
895         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
896           trap_dbgauthstatus_el1 },
897 
898         /* MDCCSR_EL1 */
899         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
900           trap_raz_wi },
901         /* DBGDTR_EL0 */
902         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
903           trap_raz_wi },
904         /* DBGDTR[TR]X_EL0 */
905         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
906           trap_raz_wi },
907 
908         /* DBGVCR32_EL2 */
909         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
910           NULL, reset_val, DBGVCR32_EL2, 0 },
911 
912         /* MPIDR_EL1 */
913         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
914           NULL, reset_mpidr, MPIDR_EL1 },
915         /* SCTLR_EL1 */
916         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
917           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
918         /* CPACR_EL1 */
919         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
920           NULL, reset_val, CPACR_EL1, 0 },
921         /* TTBR0_EL1 */
922         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
923           access_vm_reg, reset_unknown, TTBR0_EL1 },
924         /* TTBR1_EL1 */
925         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
926           access_vm_reg, reset_unknown, TTBR1_EL1 },
927         /* TCR_EL1 */
928         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
929           access_vm_reg, reset_val, TCR_EL1, 0 },
930 
931         /* AFSR0_EL1 */
932         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
933           access_vm_reg, reset_unknown, AFSR0_EL1 },
934         /* AFSR1_EL1 */
935         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
936           access_vm_reg, reset_unknown, AFSR1_EL1 },
937         /* ESR_EL1 */
938         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
939           access_vm_reg, reset_unknown, ESR_EL1 },
940         /* FAR_EL1 */
941         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
942           access_vm_reg, reset_unknown, FAR_EL1 },
943         /* PAR_EL1 */
944         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
945           NULL, reset_unknown, PAR_EL1 },
946 
947         /* PMINTENSET_EL1 */
948         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
949           access_pminten, reset_unknown, PMINTENSET_EL1 },
950         /* PMINTENCLR_EL1 */
951         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
952           access_pminten, NULL, PMINTENSET_EL1 },
953 
954         /* MAIR_EL1 */
955         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
956           access_vm_reg, reset_unknown, MAIR_EL1 },
957         /* AMAIR_EL1 */
958         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
959           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
960 
961         /* VBAR_EL1 */
962         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
963           NULL, reset_val, VBAR_EL1, 0 },
964 
965         /* ICC_SGI1R_EL1 */
966         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
967           access_gic_sgi },
968         /* ICC_SRE_EL1 */
969         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
970           access_gic_sre },
971 
972         /* CONTEXTIDR_EL1 */
973         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
974           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
975         /* TPIDR_EL1 */
976         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
977           NULL, reset_unknown, TPIDR_EL1 },
978 
979         /* CNTKCTL_EL1 */
980         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
981           NULL, reset_val, CNTKCTL_EL1, 0},
982 
983         /* CSSELR_EL1 */
984         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
985           NULL, reset_unknown, CSSELR_EL1 },
986 
987         /* PMCR_EL0 */
988         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
989           access_pmcr, reset_pmcr, },
990         /* PMCNTENSET_EL0 */
991         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
992           access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
993         /* PMCNTENCLR_EL0 */
994         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
995           access_pmcnten, NULL, PMCNTENSET_EL0 },
996         /* PMOVSCLR_EL0 */
997         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
998           access_pmovs, NULL, PMOVSSET_EL0 },
999         /* PMSWINC_EL0 */
1000         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
1001           access_pmswinc, reset_unknown, PMSWINC_EL0 },
1002         /* PMSELR_EL0 */
1003         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
1004           access_pmselr, reset_unknown, PMSELR_EL0 },
1005         /* PMCEID0_EL0 */
1006         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
1007           access_pmceid },
1008         /* PMCEID1_EL0 */
1009         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
1010           access_pmceid },
1011         /* PMCCNTR_EL0 */
1012         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
1013           access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1014         /* PMXEVTYPER_EL0 */
1015         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
1016           access_pmu_evtyper },
1017         /* PMXEVCNTR_EL0 */
1018         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
1019           access_pmu_evcntr },
1020         /* PMUSERENR_EL0
1021          * This register resets as unknown in 64bit mode while it resets as zero
1022          * in 32bit mode. Here we choose to reset it as zero for consistency.
1023          */
1024         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
1025           access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1026         /* PMOVSSET_EL0 */
1027         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
1028           access_pmovs, reset_unknown, PMOVSSET_EL0 },
1029 
1030         /* TPIDR_EL0 */
1031         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1032           NULL, reset_unknown, TPIDR_EL0 },
1033         /* TPIDRRO_EL0 */
1034         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1035           NULL, reset_unknown, TPIDRRO_EL0 },
1036 
1037         /* PMEVCNTRn_EL0 */
1038         PMU_PMEVCNTR_EL0(0),
1039         PMU_PMEVCNTR_EL0(1),
1040         PMU_PMEVCNTR_EL0(2),
1041         PMU_PMEVCNTR_EL0(3),
1042         PMU_PMEVCNTR_EL0(4),
1043         PMU_PMEVCNTR_EL0(5),
1044         PMU_PMEVCNTR_EL0(6),
1045         PMU_PMEVCNTR_EL0(7),
1046         PMU_PMEVCNTR_EL0(8),
1047         PMU_PMEVCNTR_EL0(9),
1048         PMU_PMEVCNTR_EL0(10),
1049         PMU_PMEVCNTR_EL0(11),
1050         PMU_PMEVCNTR_EL0(12),
1051         PMU_PMEVCNTR_EL0(13),
1052         PMU_PMEVCNTR_EL0(14),
1053         PMU_PMEVCNTR_EL0(15),
1054         PMU_PMEVCNTR_EL0(16),
1055         PMU_PMEVCNTR_EL0(17),
1056         PMU_PMEVCNTR_EL0(18),
1057         PMU_PMEVCNTR_EL0(19),
1058         PMU_PMEVCNTR_EL0(20),
1059         PMU_PMEVCNTR_EL0(21),
1060         PMU_PMEVCNTR_EL0(22),
1061         PMU_PMEVCNTR_EL0(23),
1062         PMU_PMEVCNTR_EL0(24),
1063         PMU_PMEVCNTR_EL0(25),
1064         PMU_PMEVCNTR_EL0(26),
1065         PMU_PMEVCNTR_EL0(27),
1066         PMU_PMEVCNTR_EL0(28),
1067         PMU_PMEVCNTR_EL0(29),
1068         PMU_PMEVCNTR_EL0(30),
1069         /* PMEVTYPERn_EL0 */
1070         PMU_PMEVTYPER_EL0(0),
1071         PMU_PMEVTYPER_EL0(1),
1072         PMU_PMEVTYPER_EL0(2),
1073         PMU_PMEVTYPER_EL0(3),
1074         PMU_PMEVTYPER_EL0(4),
1075         PMU_PMEVTYPER_EL0(5),
1076         PMU_PMEVTYPER_EL0(6),
1077         PMU_PMEVTYPER_EL0(7),
1078         PMU_PMEVTYPER_EL0(8),
1079         PMU_PMEVTYPER_EL0(9),
1080         PMU_PMEVTYPER_EL0(10),
1081         PMU_PMEVTYPER_EL0(11),
1082         PMU_PMEVTYPER_EL0(12),
1083         PMU_PMEVTYPER_EL0(13),
1084         PMU_PMEVTYPER_EL0(14),
1085         PMU_PMEVTYPER_EL0(15),
1086         PMU_PMEVTYPER_EL0(16),
1087         PMU_PMEVTYPER_EL0(17),
1088         PMU_PMEVTYPER_EL0(18),
1089         PMU_PMEVTYPER_EL0(19),
1090         PMU_PMEVTYPER_EL0(20),
1091         PMU_PMEVTYPER_EL0(21),
1092         PMU_PMEVTYPER_EL0(22),
1093         PMU_PMEVTYPER_EL0(23),
1094         PMU_PMEVTYPER_EL0(24),
1095         PMU_PMEVTYPER_EL0(25),
1096         PMU_PMEVTYPER_EL0(26),
1097         PMU_PMEVTYPER_EL0(27),
1098         PMU_PMEVTYPER_EL0(28),
1099         PMU_PMEVTYPER_EL0(29),
1100         PMU_PMEVTYPER_EL0(30),
1101         /* PMCCFILTR_EL0
1102          * This register resets as unknown in 64bit mode while it resets as zero
1103          * in 32bit mode. Here we choose to reset it as zero for consistency.
1104          */
1105         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1106           access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1107 
1108         /* DACR32_EL2 */
1109         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1110           NULL, reset_unknown, DACR32_EL2 },
1111         /* IFSR32_EL2 */
1112         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1113           NULL, reset_unknown, IFSR32_EL2 },
1114         /* FPEXC32_EL2 */
1115         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1116           NULL, reset_val, FPEXC32_EL2, 0x70 },
1117 };
1118 
1119 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1120                         struct sys_reg_params *p,
1121                         const struct sys_reg_desc *r)
1122 {
1123         if (p->is_write) {
1124                 return ignore_write(vcpu, p);
1125         } else {
1126                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1127                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1128                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1129 
1130                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1131                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1132                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1133                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1134                 return true;
1135         }
1136 }
1137 
1138 static bool trap_debug32(struct kvm_vcpu *vcpu,
1139                          struct sys_reg_params *p,
1140                          const struct sys_reg_desc *r)
1141 {
1142         if (p->is_write) {
1143                 vcpu_cp14(vcpu, r->reg) = p->regval;
1144                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1145         } else {
1146                 p->regval = vcpu_cp14(vcpu, r->reg);
1147         }
1148 
1149         return true;
1150 }
1151 
1152 /* AArch32 debug register mappings
1153  *
1154  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1155  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1156  *
1157  * All control registers and watchpoint value registers are mapped to
1158  * the lower 32 bits of their AArch64 equivalents. We share the trap
1159  * handlers with the above AArch64 code which checks what mode the
1160  * system is in.
1161  */
1162 
1163 static bool trap_xvr(struct kvm_vcpu *vcpu,
1164                      struct sys_reg_params *p,
1165                      const struct sys_reg_desc *rd)
1166 {
1167         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1168 
1169         if (p->is_write) {
1170                 u64 val = *dbg_reg;
1171 
1172                 val &= 0xffffffffUL;
1173                 val |= p->regval << 32;
1174                 *dbg_reg = val;
1175 
1176                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1177         } else {
1178                 p->regval = *dbg_reg >> 32;
1179         }
1180 
1181         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1182 
1183         return true;
1184 }
1185 
1186 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1187         /* DBGBVRn */                                                   \
1188         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1189         /* DBGBCRn */                                                   \
1190         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1191         /* DBGWVRn */                                                   \
1192         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1193         /* DBGWCRn */                                                   \
1194         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1195 
1196 #define DBGBXVR(n)                                                      \
1197         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1198 
1199 /*
1200  * Trapped cp14 registers. We generally ignore most of the external
1201  * debug, on the principle that they don't really make sense to a
1202  * guest. Revisit this one day, would this principle change.
1203  */
1204 static const struct sys_reg_desc cp14_regs[] = {
1205         /* DBGIDR */
1206         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1207         /* DBGDTRRXext */
1208         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1209 
1210         DBG_BCR_BVR_WCR_WVR(0),
1211         /* DBGDSCRint */
1212         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1213         DBG_BCR_BVR_WCR_WVR(1),
1214         /* DBGDCCINT */
1215         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1216         /* DBGDSCRext */
1217         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1218         DBG_BCR_BVR_WCR_WVR(2),
1219         /* DBGDTR[RT]Xint */
1220         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1221         /* DBGDTR[RT]Xext */
1222         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1223         DBG_BCR_BVR_WCR_WVR(3),
1224         DBG_BCR_BVR_WCR_WVR(4),
1225         DBG_BCR_BVR_WCR_WVR(5),
1226         /* DBGWFAR */
1227         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1228         /* DBGOSECCR */
1229         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1230         DBG_BCR_BVR_WCR_WVR(6),
1231         /* DBGVCR */
1232         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1233         DBG_BCR_BVR_WCR_WVR(7),
1234         DBG_BCR_BVR_WCR_WVR(8),
1235         DBG_BCR_BVR_WCR_WVR(9),
1236         DBG_BCR_BVR_WCR_WVR(10),
1237         DBG_BCR_BVR_WCR_WVR(11),
1238         DBG_BCR_BVR_WCR_WVR(12),
1239         DBG_BCR_BVR_WCR_WVR(13),
1240         DBG_BCR_BVR_WCR_WVR(14),
1241         DBG_BCR_BVR_WCR_WVR(15),
1242 
1243         /* DBGDRAR (32bit) */
1244         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1245 
1246         DBGBXVR(0),
1247         /* DBGOSLAR */
1248         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1249         DBGBXVR(1),
1250         /* DBGOSLSR */
1251         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1252         DBGBXVR(2),
1253         DBGBXVR(3),
1254         /* DBGOSDLR */
1255         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1256         DBGBXVR(4),
1257         /* DBGPRCR */
1258         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1259         DBGBXVR(5),
1260         DBGBXVR(6),
1261         DBGBXVR(7),
1262         DBGBXVR(8),
1263         DBGBXVR(9),
1264         DBGBXVR(10),
1265         DBGBXVR(11),
1266         DBGBXVR(12),
1267         DBGBXVR(13),
1268         DBGBXVR(14),
1269         DBGBXVR(15),
1270 
1271         /* DBGDSAR (32bit) */
1272         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1273 
1274         /* DBGDEVID2 */
1275         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1276         /* DBGDEVID1 */
1277         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1278         /* DBGDEVID */
1279         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1280         /* DBGCLAIMSET */
1281         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1282         /* DBGCLAIMCLR */
1283         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1284         /* DBGAUTHSTATUS */
1285         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1286 };
1287 
1288 /* Trapped cp14 64bit registers */
1289 static const struct sys_reg_desc cp14_64_regs[] = {
1290         /* DBGDRAR (64bit) */
1291         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1292 
1293         /* DBGDSAR (64bit) */
1294         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1295 };
1296 
1297 /* Macro to expand the PMEVCNTRn register */
1298 #define PMU_PMEVCNTR(n)                                                 \
1299         /* PMEVCNTRn */                                                 \
1300         { Op1(0), CRn(0b1110),                                          \
1301           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1302           access_pmu_evcntr }
1303 
1304 /* Macro to expand the PMEVTYPERn register */
1305 #define PMU_PMEVTYPER(n)                                                \
1306         /* PMEVTYPERn */                                                \
1307         { Op1(0), CRn(0b1110),                                          \
1308           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1309           access_pmu_evtyper }
1310 
1311 /*
1312  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1313  * depending on the way they are accessed (as a 32bit or a 64bit
1314  * register).
1315  */
1316 static const struct sys_reg_desc cp15_regs[] = {
1317         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1318 
1319         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1320         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1321         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1322         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1323         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1324         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1325         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1326         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1327         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1328         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1329         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1330 
1331         /*
1332          * DC{C,I,CI}SW operations:
1333          */
1334         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1335         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1336         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1337 
1338         /* PMU */
1339         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1340         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1341         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1342         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1343         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1344         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1345         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1346         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1347         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1348         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1349         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1350         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1351         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1352         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1353         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1354 
1355         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1356         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1357         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1358         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1359 
1360         /* ICC_SRE */
1361         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1362 
1363         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1364 
1365         /* PMEVCNTRn */
1366         PMU_PMEVCNTR(0),
1367         PMU_PMEVCNTR(1),
1368         PMU_PMEVCNTR(2),
1369         PMU_PMEVCNTR(3),
1370         PMU_PMEVCNTR(4),
1371         PMU_PMEVCNTR(5),
1372         PMU_PMEVCNTR(6),
1373         PMU_PMEVCNTR(7),
1374         PMU_PMEVCNTR(8),
1375         PMU_PMEVCNTR(9),
1376         PMU_PMEVCNTR(10),
1377         PMU_PMEVCNTR(11),
1378         PMU_PMEVCNTR(12),
1379         PMU_PMEVCNTR(13),
1380         PMU_PMEVCNTR(14),
1381         PMU_PMEVCNTR(15),
1382         PMU_PMEVCNTR(16),
1383         PMU_PMEVCNTR(17),
1384         PMU_PMEVCNTR(18),
1385         PMU_PMEVCNTR(19),
1386         PMU_PMEVCNTR(20),
1387         PMU_PMEVCNTR(21),
1388         PMU_PMEVCNTR(22),
1389         PMU_PMEVCNTR(23),
1390         PMU_PMEVCNTR(24),
1391         PMU_PMEVCNTR(25),
1392         PMU_PMEVCNTR(26),
1393         PMU_PMEVCNTR(27),
1394         PMU_PMEVCNTR(28),
1395         PMU_PMEVCNTR(29),
1396         PMU_PMEVCNTR(30),
1397         /* PMEVTYPERn */
1398         PMU_PMEVTYPER(0),
1399         PMU_PMEVTYPER(1),
1400         PMU_PMEVTYPER(2),
1401         PMU_PMEVTYPER(3),
1402         PMU_PMEVTYPER(4),
1403         PMU_PMEVTYPER(5),
1404         PMU_PMEVTYPER(6),
1405         PMU_PMEVTYPER(7),
1406         PMU_PMEVTYPER(8),
1407         PMU_PMEVTYPER(9),
1408         PMU_PMEVTYPER(10),
1409         PMU_PMEVTYPER(11),
1410         PMU_PMEVTYPER(12),
1411         PMU_PMEVTYPER(13),
1412         PMU_PMEVTYPER(14),
1413         PMU_PMEVTYPER(15),
1414         PMU_PMEVTYPER(16),
1415         PMU_PMEVTYPER(17),
1416         PMU_PMEVTYPER(18),
1417         PMU_PMEVTYPER(19),
1418         PMU_PMEVTYPER(20),
1419         PMU_PMEVTYPER(21),
1420         PMU_PMEVTYPER(22),
1421         PMU_PMEVTYPER(23),
1422         PMU_PMEVTYPER(24),
1423         PMU_PMEVTYPER(25),
1424         PMU_PMEVTYPER(26),
1425         PMU_PMEVTYPER(27),
1426         PMU_PMEVTYPER(28),
1427         PMU_PMEVTYPER(29),
1428         PMU_PMEVTYPER(30),
1429         /* PMCCFILTR */
1430         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1431 };
1432 
1433 static const struct sys_reg_desc cp15_64_regs[] = {
1434         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1435         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1436         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1437         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1438 };
1439 
1440 /* Target specific emulation tables */
1441 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1442 
1443 void kvm_register_target_sys_reg_table(unsigned int target,
1444                                        struct kvm_sys_reg_target_table *table)
1445 {
1446         target_tables[target] = table;
1447 }
1448 
1449 /* Get specific register table for this target. */
1450 static const struct sys_reg_desc *get_target_table(unsigned target,
1451                                                    bool mode_is_64,
1452                                                    size_t *num)
1453 {
1454         struct kvm_sys_reg_target_table *table;
1455 
1456         table = target_tables[target];
1457         if (mode_is_64) {
1458                 *num = table->table64.num;
1459                 return table->table64.table;
1460         } else {
1461                 *num = table->table32.num;
1462                 return table->table32.table;
1463         }
1464 }
1465 
1466 #define reg_to_match_value(x)                                           \
1467         ({                                                              \
1468                 unsigned long val;                                      \
1469                 val  = (x)->Op0 << 14;                                  \
1470                 val |= (x)->Op1 << 11;                                  \
1471                 val |= (x)->CRn << 7;                                   \
1472                 val |= (x)->CRm << 3;                                   \
1473                 val |= (x)->Op2;                                        \
1474                 val;                                                    \
1475          })
1476 
1477 static int match_sys_reg(const void *key, const void *elt)
1478 {
1479         const unsigned long pval = (unsigned long)key;
1480         const struct sys_reg_desc *r = elt;
1481 
1482         return pval - reg_to_match_value(r);
1483 }
1484 
1485 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1486                                          const struct sys_reg_desc table[],
1487                                          unsigned int num)
1488 {
1489         unsigned long pval = reg_to_match_value(params);
1490 
1491         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1492 }
1493 
1494 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1495 {
1496         kvm_inject_undefined(vcpu);
1497         return 1;
1498 }
1499 
1500 /*
1501  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1502  *                call the corresponding trap handler.
1503  *
1504  * @params: pointer to the descriptor of the access
1505  * @table: array of trap descriptors
1506  * @num: size of the trap descriptor array
1507  *
1508  * Return 0 if the access has been handled, and -1 if not.
1509  */
1510 static int emulate_cp(struct kvm_vcpu *vcpu,
1511                       struct sys_reg_params *params,
1512                       const struct sys_reg_desc *table,
1513                       size_t num)
1514 {
1515         const struct sys_reg_desc *r;
1516 
1517         if (!table)
1518                 return -1;      /* Not handled */
1519 
1520         r = find_reg(params, table, num);
1521 
1522         if (r) {
1523                 /*
1524                  * Not having an accessor means that we have
1525                  * configured a trap that we don't know how to
1526                  * handle. This certainly qualifies as a gross bug
1527                  * that should be fixed right away.
1528                  */
1529                 BUG_ON(!r->access);
1530 
1531                 if (likely(r->access(vcpu, params, r))) {
1532                         /* Skip instruction, since it was emulated */
1533                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1534                         /* Handled */
1535                         return 0;
1536                 }
1537         }
1538 
1539         /* Not handled */
1540         return -1;
1541 }
1542 
1543 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1544                                 struct sys_reg_params *params)
1545 {
1546         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1547         int cp = -1;
1548 
1549         switch(hsr_ec) {
1550         case ESR_ELx_EC_CP15_32:
1551         case ESR_ELx_EC_CP15_64:
1552                 cp = 15;
1553                 break;
1554         case ESR_ELx_EC_CP14_MR:
1555         case ESR_ELx_EC_CP14_64:
1556                 cp = 14;
1557                 break;
1558         default:
1559                 WARN_ON(1);
1560         }
1561 
1562         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1563                 cp, *vcpu_pc(vcpu));
1564         print_sys_reg_instr(params);
1565         kvm_inject_undefined(vcpu);
1566 }
1567 
1568 /**
1569  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1570  * @vcpu: The VCPU pointer
1571  * @run:  The kvm_run struct
1572  */
1573 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1574                             const struct sys_reg_desc *global,
1575                             size_t nr_global,
1576                             const struct sys_reg_desc *target_specific,
1577                             size_t nr_specific)
1578 {
1579         struct sys_reg_params params;
1580         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1581         int Rt = (hsr >> 5) & 0xf;
1582         int Rt2 = (hsr >> 10) & 0xf;
1583 
1584         params.is_aarch32 = true;
1585         params.is_32bit = false;
1586         params.CRm = (hsr >> 1) & 0xf;
1587         params.is_write = ((hsr & 1) == 0);
1588 
1589         params.Op0 = 0;
1590         params.Op1 = (hsr >> 16) & 0xf;
1591         params.Op2 = 0;
1592         params.CRn = 0;
1593 
1594         /*
1595          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1596          * backends between AArch32 and AArch64, we get away with it.
1597          */
1598         if (params.is_write) {
1599                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1600                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1601         }
1602 
1603         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1604                 goto out;
1605         if (!emulate_cp(vcpu, &params, global, nr_global))
1606                 goto out;
1607 
1608         unhandled_cp_access(vcpu, &params);
1609 
1610 out:
1611         /* Split up the value between registers for the read side */
1612         if (!params.is_write) {
1613                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1614                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1615         }
1616 
1617         return 1;
1618 }
1619 
1620 /**
1621  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1622  * @vcpu: The VCPU pointer
1623  * @run:  The kvm_run struct
1624  */
1625 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1626                             const struct sys_reg_desc *global,
1627                             size_t nr_global,
1628                             const struct sys_reg_desc *target_specific,
1629                             size_t nr_specific)
1630 {
1631         struct sys_reg_params params;
1632         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1633         int Rt  = (hsr >> 5) & 0xf;
1634 
1635         params.is_aarch32 = true;
1636         params.is_32bit = true;
1637         params.CRm = (hsr >> 1) & 0xf;
1638         params.regval = vcpu_get_reg(vcpu, Rt);
1639         params.is_write = ((hsr & 1) == 0);
1640         params.CRn = (hsr >> 10) & 0xf;
1641         params.Op0 = 0;
1642         params.Op1 = (hsr >> 14) & 0x7;
1643         params.Op2 = (hsr >> 17) & 0x7;
1644 
1645         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1646             !emulate_cp(vcpu, &params, global, nr_global)) {
1647                 if (!params.is_write)
1648                         vcpu_set_reg(vcpu, Rt, params.regval);
1649                 return 1;
1650         }
1651 
1652         unhandled_cp_access(vcpu, &params);
1653         return 1;
1654 }
1655 
1656 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1657 {
1658         const struct sys_reg_desc *target_specific;
1659         size_t num;
1660 
1661         target_specific = get_target_table(vcpu->arch.target, false, &num);
1662         return kvm_handle_cp_64(vcpu,
1663                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1664                                 target_specific, num);
1665 }
1666 
1667 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1668 {
1669         const struct sys_reg_desc *target_specific;
1670         size_t num;
1671 
1672         target_specific = get_target_table(vcpu->arch.target, false, &num);
1673         return kvm_handle_cp_32(vcpu,
1674                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1675                                 target_specific, num);
1676 }
1677 
1678 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1679 {
1680         return kvm_handle_cp_64(vcpu,
1681                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1682                                 NULL, 0);
1683 }
1684 
1685 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1686 {
1687         return kvm_handle_cp_32(vcpu,
1688                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1689                                 NULL, 0);
1690 }
1691 
1692 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1693                            struct sys_reg_params *params)
1694 {
1695         size_t num;
1696         const struct sys_reg_desc *table, *r;
1697 
1698         table = get_target_table(vcpu->arch.target, true, &num);
1699 
1700         /* Search target-specific then generic table. */
1701         r = find_reg(params, table, num);
1702         if (!r)
1703                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1704 
1705         if (likely(r)) {
1706                 /*
1707                  * Not having an accessor means that we have
1708                  * configured a trap that we don't know how to
1709                  * handle. This certainly qualifies as a gross bug
1710                  * that should be fixed right away.
1711                  */
1712                 BUG_ON(!r->access);
1713 
1714                 if (likely(r->access(vcpu, params, r))) {
1715                         /* Skip instruction, since it was emulated */
1716                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1717                         return 1;
1718                 }
1719                 /* If access function fails, it should complain. */
1720         } else {
1721                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1722                         *vcpu_pc(vcpu));
1723                 print_sys_reg_instr(params);
1724         }
1725         kvm_inject_undefined(vcpu);
1726         return 1;
1727 }
1728 
1729 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1730                               const struct sys_reg_desc *table, size_t num)
1731 {
1732         unsigned long i;
1733 
1734         for (i = 0; i < num; i++)
1735                 if (table[i].reset)
1736                         table[i].reset(vcpu, &table[i]);
1737 }
1738 
1739 /**
1740  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1741  * @vcpu: The VCPU pointer
1742  * @run:  The kvm_run struct
1743  */
1744 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1745 {
1746         struct sys_reg_params params;
1747         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1748         int Rt = (esr >> 5) & 0x1f;
1749         int ret;
1750 
1751         trace_kvm_handle_sys_reg(esr);
1752 
1753         params.is_aarch32 = false;
1754         params.is_32bit = false;
1755         params.Op0 = (esr >> 20) & 3;
1756         params.Op1 = (esr >> 14) & 0x7;
1757         params.CRn = (esr >> 10) & 0xf;
1758         params.CRm = (esr >> 1) & 0xf;
1759         params.Op2 = (esr >> 17) & 0x7;
1760         params.regval = vcpu_get_reg(vcpu, Rt);
1761         params.is_write = !(esr & 1);
1762 
1763         ret = emulate_sys_reg(vcpu, &params);
1764 
1765         if (!params.is_write)
1766                 vcpu_set_reg(vcpu, Rt, params.regval);
1767         return ret;
1768 }
1769 
1770 /******************************************************************************
1771  * Userspace API
1772  *****************************************************************************/
1773 
1774 static bool index_to_params(u64 id, struct sys_reg_params *params)
1775 {
1776         switch (id & KVM_REG_SIZE_MASK) {
1777         case KVM_REG_SIZE_U64:
1778                 /* Any unused index bits means it's not valid. */
1779                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1780                               | KVM_REG_ARM_COPROC_MASK
1781                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1782                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1783                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1784                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1785                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1786                         return false;
1787                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1788                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1789                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1790                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1791                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1792                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1793                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1794                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1795                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1796                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1797                 return true;
1798         default:
1799                 return false;
1800         }
1801 }
1802 
1803 /* Decode an index value, and find the sys_reg_desc entry. */
1804 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1805                                                     u64 id)
1806 {
1807         size_t num;
1808         const struct sys_reg_desc *table, *r;
1809         struct sys_reg_params params;
1810 
1811         /* We only do sys_reg for now. */
1812         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1813                 return NULL;
1814 
1815         if (!index_to_params(id, &params))
1816                 return NULL;
1817 
1818         table = get_target_table(vcpu->arch.target, true, &num);
1819         r = find_reg(&params, table, num);
1820         if (!r)
1821                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1822 
1823         /* Not saved in the sys_reg array? */
1824         if (r && !r->reg)
1825                 r = NULL;
1826 
1827         return r;
1828 }
1829 
1830 /*
1831  * These are the invariant sys_reg registers: we let the guest see the
1832  * host versions of these, so they're part of the guest state.
1833  *
1834  * A future CPU may provide a mechanism to present different values to
1835  * the guest, or a future kvm may trap them.
1836  */
1837 
1838 #define FUNCTION_INVARIANT(reg)                                         \
1839         static void get_##reg(struct kvm_vcpu *v,                       \
1840                               const struct sys_reg_desc *r)             \
1841         {                                                               \
1842                 u64 val;                                                \
1843                                                                         \
1844                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
1845                              : "=r" (val));                             \
1846                 ((struct sys_reg_desc *)r)->val = val;                  \
1847         }
1848 
1849 FUNCTION_INVARIANT(midr_el1)
1850 FUNCTION_INVARIANT(ctr_el0)
1851 FUNCTION_INVARIANT(revidr_el1)
1852 FUNCTION_INVARIANT(id_pfr0_el1)
1853 FUNCTION_INVARIANT(id_pfr1_el1)
1854 FUNCTION_INVARIANT(id_dfr0_el1)
1855 FUNCTION_INVARIANT(id_afr0_el1)
1856 FUNCTION_INVARIANT(id_mmfr0_el1)
1857 FUNCTION_INVARIANT(id_mmfr1_el1)
1858 FUNCTION_INVARIANT(id_mmfr2_el1)
1859 FUNCTION_INVARIANT(id_mmfr3_el1)
1860 FUNCTION_INVARIANT(id_isar0_el1)
1861 FUNCTION_INVARIANT(id_isar1_el1)
1862 FUNCTION_INVARIANT(id_isar2_el1)
1863 FUNCTION_INVARIANT(id_isar3_el1)
1864 FUNCTION_INVARIANT(id_isar4_el1)
1865 FUNCTION_INVARIANT(id_isar5_el1)
1866 FUNCTION_INVARIANT(clidr_el1)
1867 FUNCTION_INVARIANT(aidr_el1)
1868 
1869 /* ->val is filled in by kvm_sys_reg_table_init() */
1870 static struct sys_reg_desc invariant_sys_regs[] = {
1871         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1872           NULL, get_midr_el1 },
1873         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1874           NULL, get_revidr_el1 },
1875         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1876           NULL, get_id_pfr0_el1 },
1877         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1878           NULL, get_id_pfr1_el1 },
1879         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1880           NULL, get_id_dfr0_el1 },
1881         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1882           NULL, get_id_afr0_el1 },
1883         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1884           NULL, get_id_mmfr0_el1 },
1885         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1886           NULL, get_id_mmfr1_el1 },
1887         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1888           NULL, get_id_mmfr2_el1 },
1889         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1890           NULL, get_id_mmfr3_el1 },
1891         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1892           NULL, get_id_isar0_el1 },
1893         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1894           NULL, get_id_isar1_el1 },
1895         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1896           NULL, get_id_isar2_el1 },
1897         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1898           NULL, get_id_isar3_el1 },
1899         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1900           NULL, get_id_isar4_el1 },
1901         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1902           NULL, get_id_isar5_el1 },
1903         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1904           NULL, get_clidr_el1 },
1905         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1906           NULL, get_aidr_el1 },
1907         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1908           NULL, get_ctr_el0 },
1909 };
1910 
1911 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1912 {
1913         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1914                 return -EFAULT;
1915         return 0;
1916 }
1917 
1918 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1919 {
1920         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1921                 return -EFAULT;
1922         return 0;
1923 }
1924 
1925 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1926 {
1927         struct sys_reg_params params;
1928         const struct sys_reg_desc *r;
1929 
1930         if (!index_to_params(id, &params))
1931                 return -ENOENT;
1932 
1933         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1934         if (!r)
1935                 return -ENOENT;
1936 
1937         return reg_to_user(uaddr, &r->val, id);
1938 }
1939 
1940 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1941 {
1942         struct sys_reg_params params;
1943         const struct sys_reg_desc *r;
1944         int err;
1945         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1946 
1947         if (!index_to_params(id, &params))
1948                 return -ENOENT;
1949         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1950         if (!r)
1951                 return -ENOENT;
1952 
1953         err = reg_from_user(&val, uaddr, id);
1954         if (err)
1955                 return err;
1956 
1957         /* This is what we mean by invariant: you can't change it. */
1958         if (r->val != val)
1959                 return -EINVAL;
1960 
1961         return 0;
1962 }
1963 
1964 static bool is_valid_cache(u32 val)
1965 {
1966         u32 level, ctype;
1967 
1968         if (val >= CSSELR_MAX)
1969                 return false;
1970 
1971         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1972         level = (val >> 1);
1973         ctype = (cache_levels >> (level * 3)) & 7;
1974 
1975         switch (ctype) {
1976         case 0: /* No cache */
1977                 return false;
1978         case 1: /* Instruction cache only */
1979                 return (val & 1);
1980         case 2: /* Data cache only */
1981         case 4: /* Unified cache */
1982                 return !(val & 1);
1983         case 3: /* Separate instruction and data caches */
1984                 return true;
1985         default: /* Reserved: we can't know instruction or data. */
1986                 return false;
1987         }
1988 }
1989 
1990 static int demux_c15_get(u64 id, void __user *uaddr)
1991 {
1992         u32 val;
1993         u32 __user *uval = uaddr;
1994 
1995         /* Fail if we have unknown bits set. */
1996         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1997                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1998                 return -ENOENT;
1999 
2000         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2001         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2002                 if (KVM_REG_SIZE(id) != 4)
2003                         return -ENOENT;
2004                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2005                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2006                 if (!is_valid_cache(val))
2007                         return -ENOENT;
2008 
2009                 return put_user(get_ccsidr(val), uval);
2010         default:
2011                 return -ENOENT;
2012         }
2013 }
2014 
2015 static int demux_c15_set(u64 id, void __user *uaddr)
2016 {
2017         u32 val, newval;
2018         u32 __user *uval = uaddr;
2019 
2020         /* Fail if we have unknown bits set. */
2021         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2022                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2023                 return -ENOENT;
2024 
2025         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2026         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2027                 if (KVM_REG_SIZE(id) != 4)
2028                         return -ENOENT;
2029                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2030                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2031                 if (!is_valid_cache(val))
2032                         return -ENOENT;
2033 
2034                 if (get_user(newval, uval))
2035                         return -EFAULT;
2036 
2037                 /* This is also invariant: you can't change it. */
2038                 if (newval != get_ccsidr(val))
2039                         return -EINVAL;
2040                 return 0;
2041         default:
2042                 return -ENOENT;
2043         }
2044 }
2045 
2046 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2047 {
2048         const struct sys_reg_desc *r;
2049         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2050 
2051         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2052                 return demux_c15_get(reg->id, uaddr);
2053 
2054         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2055                 return -ENOENT;
2056 
2057         r = index_to_sys_reg_desc(vcpu, reg->id);
2058         if (!r)
2059                 return get_invariant_sys_reg(reg->id, uaddr);
2060 
2061         if (r->get_user)
2062                 return (r->get_user)(vcpu, r, reg, uaddr);
2063 
2064         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2065 }
2066 
2067 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2068 {
2069         const struct sys_reg_desc *r;
2070         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2071 
2072         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2073                 return demux_c15_set(reg->id, uaddr);
2074 
2075         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2076                 return -ENOENT;
2077 
2078         r = index_to_sys_reg_desc(vcpu, reg->id);
2079         if (!r)
2080                 return set_invariant_sys_reg(reg->id, uaddr);
2081 
2082         if (r->set_user)
2083                 return (r->set_user)(vcpu, r, reg, uaddr);
2084 
2085         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2086 }
2087 
2088 static unsigned int num_demux_regs(void)
2089 {
2090         unsigned int i, count = 0;
2091 
2092         for (i = 0; i < CSSELR_MAX; i++)
2093                 if (is_valid_cache(i))
2094                         count++;
2095 
2096         return count;
2097 }
2098 
2099 static int write_demux_regids(u64 __user *uindices)
2100 {
2101         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2102         unsigned int i;
2103 
2104         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2105         for (i = 0; i < CSSELR_MAX; i++) {
2106                 if (!is_valid_cache(i))
2107                         continue;
2108                 if (put_user(val | i, uindices))
2109                         return -EFAULT;
2110                 uindices++;
2111         }
2112         return 0;
2113 }
2114 
2115 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2116 {
2117         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2118                 KVM_REG_ARM64_SYSREG |
2119                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2120                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2121                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2122                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2123                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2124 }
2125 
2126 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2127 {
2128         if (!*uind)
2129                 return true;
2130 
2131         if (put_user(sys_reg_to_index(reg), *uind))
2132                 return false;
2133 
2134         (*uind)++;
2135         return true;
2136 }
2137 
2138 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2139 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2140 {
2141         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2142         unsigned int total = 0;
2143         size_t num;
2144 
2145         /* We check for duplicates here, to allow arch-specific overrides. */
2146         i1 = get_target_table(vcpu->arch.target, true, &num);
2147         end1 = i1 + num;
2148         i2 = sys_reg_descs;
2149         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2150 
2151         BUG_ON(i1 == end1 || i2 == end2);
2152 
2153         /* Walk carefully, as both tables may refer to the same register. */
2154         while (i1 || i2) {
2155                 int cmp = cmp_sys_reg(i1, i2);
2156                 /* target-specific overrides generic entry. */
2157                 if (cmp <= 0) {
2158                         /* Ignore registers we trap but don't save. */
2159                         if (i1->reg) {
2160                                 if (!copy_reg_to_user(i1, &uind))
2161                                         return -EFAULT;
2162                                 total++;
2163                         }
2164                 } else {
2165                         /* Ignore registers we trap but don't save. */
2166                         if (i2->reg) {
2167                                 if (!copy_reg_to_user(i2, &uind))
2168                                         return -EFAULT;
2169                                 total++;
2170                         }
2171                 }
2172 
2173                 if (cmp <= 0 && ++i1 == end1)
2174                         i1 = NULL;
2175                 if (cmp >= 0 && ++i2 == end2)
2176                         i2 = NULL;
2177         }
2178         return total;
2179 }
2180 
2181 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2182 {
2183         return ARRAY_SIZE(invariant_sys_regs)
2184                 + num_demux_regs()
2185                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2186 }
2187 
2188 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2189 {
2190         unsigned int i;
2191         int err;
2192 
2193         /* Then give them all the invariant registers' indices. */
2194         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2195                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2196                         return -EFAULT;
2197                 uindices++;
2198         }
2199 
2200         err = walk_sys_regs(vcpu, uindices);
2201         if (err < 0)
2202                 return err;
2203         uindices += err;
2204 
2205         return write_demux_regids(uindices);
2206 }
2207 
2208 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2209 {
2210         unsigned int i;
2211 
2212         for (i = 1; i < n; i++) {
2213                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2214                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2215                         return 1;
2216                 }
2217         }
2218 
2219         return 0;
2220 }
2221 
2222 void kvm_sys_reg_table_init(void)
2223 {
2224         unsigned int i;
2225         struct sys_reg_desc clidr;
2226 
2227         /* Make sure tables are unique and in order. */
2228         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2229         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2230         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2231         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2232         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2233         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2234 
2235         /* We abuse the reset function to overwrite the table itself. */
2236         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2237                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2238 
2239         /*
2240          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2241          *
2242          *   If software reads the Cache Type fields from Ctype1
2243          *   upwards, once it has seen a value of 0b000, no caches
2244          *   exist at further-out levels of the hierarchy. So, for
2245          *   example, if Ctype3 is the first Cache Type field with a
2246          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2247          *   ignored.
2248          */
2249         get_clidr_el1(NULL, &clidr); /* Ugly... */
2250         cache_levels = clidr.val;
2251         for (i = 0; i < 7; i++)
2252                 if (((cache_levels >> (i*3)) & 7) == 0)
2253                         break;
2254         /* Clear all higher bits. */
2255         cache_levels &= (1 << (i*3))-1;
2256 }
2257 
2258 /**
2259  * kvm_reset_sys_regs - sets system registers to reset value
2260  * @vcpu: The VCPU pointer
2261  *
2262  * This function finds the right table above and sets the registers on the
2263  * virtual CPU struct to their architecturally defined reset values.
2264  */
2265 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2266 {
2267         size_t num;
2268         const struct sys_reg_desc *table;
2269 
2270         /* Catch someone adding a register without putting in reset entry. */
2271         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2272 
2273         /* Generic chip reset first (so target could override). */
2274         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2275 
2276         table = get_target_table(vcpu->arch.target, true, &num);
2277         reset_sys_reg_descs(vcpu, table, num);
2278 
2279         for (num = 1; num < NR_SYS_REGS; num++)
2280                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2281                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2282 }
2283 

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