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Linux/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h

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  1 #ifndef __bif_core_defs_h
  2 #define __bif_core_defs_h
  3 
  4 /*
  5  * This file is autogenerated from
  6  *   file:           ../../inst/bif/rtl/bif_core_regs.r
  7  *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
  8  *     last modfied: Mon Apr 11 16:06:33 2005
  9  *
 10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
 11  *      id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
 12  * Any changes here will be lost.
 13  *
 14  * -*- buffer-read-only: t -*-
 15  */
 16 /* Main access macros */
 17 #ifndef REG_RD
 18 #define REG_RD( scope, inst, reg ) \
 19   REG_READ( reg_##scope##_##reg, \
 20             (inst) + REG_RD_ADDR_##scope##_##reg )
 21 #endif
 22 
 23 #ifndef REG_WR
 24 #define REG_WR( scope, inst, reg, val ) \
 25   REG_WRITE( reg_##scope##_##reg, \
 26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 27 #endif
 28 
 29 #ifndef REG_RD_VECT
 30 #define REG_RD_VECT( scope, inst, reg, index ) \
 31   REG_READ( reg_##scope##_##reg, \
 32             (inst) + REG_RD_ADDR_##scope##_##reg + \
 33             (index) * STRIDE_##scope##_##reg )
 34 #endif
 35 
 36 #ifndef REG_WR_VECT
 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
 38   REG_WRITE( reg_##scope##_##reg, \
 39              (inst) + REG_WR_ADDR_##scope##_##reg + \
 40              (index) * STRIDE_##scope##_##reg, (val) )
 41 #endif
 42 
 43 #ifndef REG_RD_INT
 44 #define REG_RD_INT( scope, inst, reg ) \
 45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
 46 #endif
 47 
 48 #ifndef REG_WR_INT
 49 #define REG_WR_INT( scope, inst, reg, val ) \
 50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 51 #endif
 52 
 53 #ifndef REG_RD_INT_VECT
 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
 55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
 56             (index) * STRIDE_##scope##_##reg )
 57 #endif
 58 
 59 #ifndef REG_WR_INT_VECT
 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
 61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
 62              (index) * STRIDE_##scope##_##reg, (val) )
 63 #endif
 64 
 65 #ifndef REG_TYPE_CONV
 66 #define REG_TYPE_CONV( type, orgtype, val ) \
 67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
 68 #endif
 69 
 70 #ifndef reg_page_size
 71 #define reg_page_size 8192
 72 #endif
 73 
 74 #ifndef REG_ADDR
 75 #define REG_ADDR( scope, inst, reg ) \
 76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
 77 #endif
 78 
 79 #ifndef REG_ADDR_VECT
 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
 81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
 82     (index) * STRIDE_##scope##_##reg )
 83 #endif
 84 
 85 /* C-code for register scope bif_core */
 86 
 87 /* Register rw_grp1_cfg, scope bif_core, type rw */
 88 typedef struct {
 89   unsigned int lw        : 6;
 90   unsigned int ew        : 3;
 91   unsigned int zw        : 3;
 92   unsigned int aw        : 2;
 93   unsigned int dw        : 2;
 94   unsigned int ewb       : 2;
 95   unsigned int bw        : 1;
 96   unsigned int wr_extend : 1;
 97   unsigned int erc_en    : 1;
 98   unsigned int mode      : 1;
 99   unsigned int dummy1    : 10;
100 } reg_bif_core_rw_grp1_cfg;
101 #define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
102 #define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
103 
104 /* Register rw_grp2_cfg, scope bif_core, type rw */
105 typedef struct {
106   unsigned int lw        : 6;
107   unsigned int ew        : 3;
108   unsigned int zw        : 3;
109   unsigned int aw        : 2;
110   unsigned int dw        : 2;
111   unsigned int ewb       : 2;
112   unsigned int bw        : 1;
113   unsigned int wr_extend : 1;
114   unsigned int erc_en    : 1;
115   unsigned int mode      : 1;
116   unsigned int dummy1    : 10;
117 } reg_bif_core_rw_grp2_cfg;
118 #define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
119 #define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
120 
121 /* Register rw_grp3_cfg, scope bif_core, type rw */
122 typedef struct {
123   unsigned int lw         : 6;
124   unsigned int ew         : 3;
125   unsigned int zw         : 3;
126   unsigned int aw         : 2;
127   unsigned int dw         : 2;
128   unsigned int ewb        : 2;
129   unsigned int bw         : 1;
130   unsigned int wr_extend  : 1;
131   unsigned int erc_en     : 1;
132   unsigned int mode       : 1;
133   unsigned int dummy1     : 2;
134   unsigned int gated_csp0 : 2;
135   unsigned int gated_csp1 : 2;
136   unsigned int gated_csp2 : 2;
137   unsigned int gated_csp3 : 2;
138 } reg_bif_core_rw_grp3_cfg;
139 #define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
140 #define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
141 
142 /* Register rw_grp4_cfg, scope bif_core, type rw */
143 typedef struct {
144   unsigned int lw         : 6;
145   unsigned int ew         : 3;
146   unsigned int zw         : 3;
147   unsigned int aw         : 2;
148   unsigned int dw         : 2;
149   unsigned int ewb        : 2;
150   unsigned int bw         : 1;
151   unsigned int wr_extend  : 1;
152   unsigned int erc_en     : 1;
153   unsigned int mode       : 1;
154   unsigned int dummy1     : 4;
155   unsigned int gated_csp4 : 2;
156   unsigned int gated_csp5 : 2;
157   unsigned int gated_csp6 : 2;
158 } reg_bif_core_rw_grp4_cfg;
159 #define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
160 #define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
161 
162 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
163 typedef struct {
164   unsigned int bank_sel : 5;
165   unsigned int ca       : 3;
166   unsigned int type     : 1;
167   unsigned int bw       : 1;
168   unsigned int sh       : 3;
169   unsigned int wmm      : 1;
170   unsigned int sh16     : 1;
171   unsigned int grp_sel  : 5;
172   unsigned int dummy1   : 12;
173 } reg_bif_core_rw_sdram_cfg_grp0;
174 #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
175 #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
176 
177 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
178 typedef struct {
179   unsigned int bank_sel : 5;
180   unsigned int ca       : 3;
181   unsigned int type     : 1;
182   unsigned int bw       : 1;
183   unsigned int sh       : 3;
184   unsigned int wmm      : 1;
185   unsigned int sh16     : 1;
186   unsigned int dummy1   : 17;
187 } reg_bif_core_rw_sdram_cfg_grp1;
188 #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
189 #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
190 
191 /* Register rw_sdram_timing, scope bif_core, type rw */
192 typedef struct {
193   unsigned int cl    : 3;
194   unsigned int rcd   : 3;
195   unsigned int rp    : 3;
196   unsigned int rc    : 2;
197   unsigned int dpl   : 2;
198   unsigned int pde   : 1;
199   unsigned int ref   : 2;
200   unsigned int cpd   : 1;
201   unsigned int sdcke : 1;
202   unsigned int sdclk : 1;
203   unsigned int dummy1 : 13;
204 } reg_bif_core_rw_sdram_timing;
205 #define REG_RD_ADDR_bif_core_rw_sdram_timing 24
206 #define REG_WR_ADDR_bif_core_rw_sdram_timing 24
207 
208 /* Register rw_sdram_cmd, scope bif_core, type rw */
209 typedef struct {
210   unsigned int cmd      : 3;
211   unsigned int mrs_data : 15;
212   unsigned int dummy1   : 14;
213 } reg_bif_core_rw_sdram_cmd;
214 #define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
215 #define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
216 
217 /* Register rs_sdram_ref_stat, scope bif_core, type rs */
218 typedef struct {
219   unsigned int ok : 1;
220   unsigned int dummy1 : 31;
221 } reg_bif_core_rs_sdram_ref_stat;
222 #define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
223 
224 /* Register r_sdram_ref_stat, scope bif_core, type r */
225 typedef struct {
226   unsigned int ok : 1;
227   unsigned int dummy1 : 31;
228 } reg_bif_core_r_sdram_ref_stat;
229 #define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
230 
231 
232 /* Constants */
233 enum {
234   regk_bif_core_bank2                      = 0x00000000,
235   regk_bif_core_bank4                      = 0x00000001,
236   regk_bif_core_bit10                      = 0x0000000a,
237   regk_bif_core_bit11                      = 0x0000000b,
238   regk_bif_core_bit12                      = 0x0000000c,
239   regk_bif_core_bit13                      = 0x0000000d,
240   regk_bif_core_bit14                      = 0x0000000e,
241   regk_bif_core_bit15                      = 0x0000000f,
242   regk_bif_core_bit16                      = 0x00000010,
243   regk_bif_core_bit17                      = 0x00000011,
244   regk_bif_core_bit18                      = 0x00000012,
245   regk_bif_core_bit19                      = 0x00000013,
246   regk_bif_core_bit20                      = 0x00000014,
247   regk_bif_core_bit21                      = 0x00000015,
248   regk_bif_core_bit22                      = 0x00000016,
249   regk_bif_core_bit23                      = 0x00000017,
250   regk_bif_core_bit24                      = 0x00000018,
251   regk_bif_core_bit25                      = 0x00000019,
252   regk_bif_core_bit26                      = 0x0000001a,
253   regk_bif_core_bit27                      = 0x0000001b,
254   regk_bif_core_bit28                      = 0x0000001c,
255   regk_bif_core_bit29                      = 0x0000001d,
256   regk_bif_core_bit9                       = 0x00000009,
257   regk_bif_core_bw16                       = 0x00000001,
258   regk_bif_core_bw32                       = 0x00000000,
259   regk_bif_core_bwe                        = 0x00000000,
260   regk_bif_core_cwe                        = 0x00000001,
261   regk_bif_core_e15us                      = 0x00000001,
262   regk_bif_core_e7800ns                    = 0x00000002,
263   regk_bif_core_grp0                       = 0x00000000,
264   regk_bif_core_grp1                       = 0x00000001,
265   regk_bif_core_mrs                        = 0x00000003,
266   regk_bif_core_no                         = 0x00000000,
267   regk_bif_core_none                       = 0x00000000,
268   regk_bif_core_nop                        = 0x00000000,
269   regk_bif_core_off                        = 0x00000000,
270   regk_bif_core_pre                        = 0x00000002,
271   regk_bif_core_r_sdram_ref_stat_default   = 0x00000001,
272   regk_bif_core_rd                         = 0x00000002,
273   regk_bif_core_ref                        = 0x00000001,
274   regk_bif_core_rs_sdram_ref_stat_default  = 0x00000001,
275   regk_bif_core_rw_grp1_cfg_default        = 0x000006cf,
276   regk_bif_core_rw_grp2_cfg_default        = 0x000006cf,
277   regk_bif_core_rw_grp3_cfg_default        = 0x000006cf,
278   regk_bif_core_rw_grp4_cfg_default        = 0x000006cf,
279   regk_bif_core_rw_sdram_cfg_grp1_default  = 0x00000000,
280   regk_bif_core_slf                        = 0x00000004,
281   regk_bif_core_wr                         = 0x00000001,
282   regk_bif_core_yes                        = 0x00000001
283 };
284 #endif /* __bif_core_defs_h */
285 

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