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Linux/arch/i386/kernel/smp.c

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  1 /*
  2  *      Intel SMP support routines.
  3  *
  4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  5  *      (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
  6  *
  7  *      This code is released under the GNU General Public License version 2 or
  8  *      later.
  9  */
 10 
 11 #include <linux/init.h>
 12 
 13 #include <linux/mm.h>
 14 #include <linux/irq.h>
 15 #include <linux/delay.h>
 16 #include <linux/spinlock.h>
 17 #include <linux/smp_lock.h>
 18 #include <linux/kernel_stat.h>
 19 #include <linux/mc146818rtc.h>
 20 #include <linux/cache.h>
 21 #include <linux/interrupt.h>
 22 
 23 #include <asm/mtrr.h>
 24 #include <asm/pgalloc.h>
 25 #include <asm/tlbflush.h>
 26 #include <mach_ipi.h>
 27 #include <mach_apic.h>
 28 
 29 /*
 30  *      Some notes on x86 processor bugs affecting SMP operation:
 31  *
 32  *      Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
 33  *      The Linux implications for SMP are handled as follows:
 34  *
 35  *      Pentium III / [Xeon]
 36  *              None of the E1AP-E3AP errata are visible to the user.
 37  *
 38  *      E1AP.   see PII A1AP
 39  *      E2AP.   see PII A2AP
 40  *      E3AP.   see PII A3AP
 41  *
 42  *      Pentium II / [Xeon]
 43  *              None of the A1AP-A3AP errata are visible to the user.
 44  *
 45  *      A1AP.   see PPro 1AP
 46  *      A2AP.   see PPro 2AP
 47  *      A3AP.   see PPro 7AP
 48  *
 49  *      Pentium Pro
 50  *              None of 1AP-9AP errata are visible to the normal user,
 51  *      except occasional delivery of 'spurious interrupt' as trap #15.
 52  *      This is very rare and a non-problem.
 53  *
 54  *      1AP.    Linux maps APIC as non-cacheable
 55  *      2AP.    worked around in hardware
 56  *      3AP.    fixed in C0 and above steppings microcode update.
 57  *              Linux does not use excessive STARTUP_IPIs.
 58  *      4AP.    worked around in hardware
 59  *      5AP.    symmetric IO mode (normal Linux operation) not affected.
 60  *              'noapic' mode has vector 0xf filled out properly.
 61  *      6AP.    'noapic' mode might be affected - fixed in later steppings
 62  *      7AP.    We do not assume writes to the LVT deassering IRQs
 63  *      8AP.    We do not enable low power mode (deep sleep) during MP bootup
 64  *      9AP.    We do not use mixed mode
 65  *
 66  *      Pentium
 67  *              There is a marginal case where REP MOVS on 100MHz SMP
 68  *      machines with B stepping processors can fail. XXX should provide
 69  *      an L1cache=Writethrough or L1cache=off option.
 70  *
 71  *              B stepping CPUs may hang. There are hardware work arounds
 72  *      for this. We warn about it in case your board doesn't have the work
 73  *      arounds. Basically thats so I can tell anyone with a B stepping
 74  *      CPU and SMP problems "tough".
 75  *
 76  *      Specific items [From Pentium Processor Specification Update]
 77  *
 78  *      1AP.    Linux doesn't use remote read
 79  *      2AP.    Linux doesn't trust APIC errors
 80  *      3AP.    We work around this
 81  *      4AP.    Linux never generated 3 interrupts of the same priority
 82  *              to cause a lost local interrupt.
 83  *      5AP.    Remote read is never used
 84  *      6AP.    not affected - worked around in hardware
 85  *      7AP.    not affected - worked around in hardware
 86  *      8AP.    worked around in hardware - we get explicit CS errors if not
 87  *      9AP.    only 'noapic' mode affected. Might generate spurious
 88  *              interrupts, we log only the first one and count the
 89  *              rest silently.
 90  *      10AP.   not affected - worked around in hardware
 91  *      11AP.   Linux reads the APIC between writes to avoid this, as per
 92  *              the documentation. Make sure you preserve this as it affects
 93  *              the C stepping chips too.
 94  *      12AP.   not affected - worked around in hardware
 95  *      13AP.   not affected - worked around in hardware
 96  *      14AP.   we always deassert INIT during bootup
 97  *      15AP.   not affected - worked around in hardware
 98  *      16AP.   not affected - worked around in hardware
 99  *      17AP.   not affected - worked around in hardware
100  *      18AP.   not affected - worked around in hardware
101  *      19AP.   not affected - worked around in BIOS
102  *
103  *      If this sounds worrying believe me these bugs are either ___RARE___,
104  *      or are signal timing bugs worked around in hardware and there's
105  *      about nothing of note with C stepping upwards.
106  */
107 
108 struct tlb_state cpu_tlbstate[NR_CPUS] __cacheline_aligned = {[0 ... NR_CPUS-1] = { &init_mm, 0, }};
109 
110 /*
111  * the following functions deal with sending IPIs between CPUs.
112  *
113  * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
114  */
115 
116 static inline int __prepare_ICR (unsigned int shortcut, int vector)
117 {
118         return APIC_DM_FIXED | shortcut | vector | APIC_DEST_LOGICAL;
119 }
120 
121 static inline int __prepare_ICR2 (unsigned int mask)
122 {
123         return SET_APIC_DEST_FIELD(mask);
124 }
125 
126 inline void __send_IPI_shortcut(unsigned int shortcut, int vector)
127 {
128         /*
129          * Subtle. In the case of the 'never do double writes' workaround
130          * we have to lock out interrupts to be safe.  As we don't care
131          * of the value read we use an atomic rmw access to avoid costly
132          * cli/sti.  Otherwise we use an even cheaper single atomic write
133          * to the APIC.
134          */
135         unsigned int cfg;
136 
137         /*
138          * Wait for idle.
139          */
140         apic_wait_icr_idle();
141 
142         /*
143          * No need to touch the target chip field
144          */
145         cfg = __prepare_ICR(shortcut, vector);
146 
147         /*
148          * Send the IPI. The write to APIC_ICR fires this off.
149          */
150         apic_write_around(APIC_ICR, cfg);
151 }
152 
153 void send_IPI_self(int vector)
154 {
155         __send_IPI_shortcut(APIC_DEST_SELF, vector);
156 }
157 
158 /*
159  * This is only used on smaller machines.
160  */
161 inline void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
162 {
163         unsigned long mask = cpus_coerce(cpumask);
164         unsigned long cfg;
165         unsigned long flags;
166 
167         local_irq_save(flags);
168                 
169         /*
170          * Wait for idle.
171          */
172         apic_wait_icr_idle();
173                 
174         /*
175          * prepare target chip field
176          */
177         cfg = __prepare_ICR2(mask);
178         apic_write_around(APIC_ICR2, cfg);
179                 
180         /*
181          * program the ICR 
182          */
183         cfg = __prepare_ICR(0, vector);
184                         
185         /*
186          * Send the IPI. The write to APIC_ICR fires this off.
187          */
188         apic_write_around(APIC_ICR, cfg);
189 
190         local_irq_restore(flags);
191 }
192 
193 inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
194 {
195         unsigned long cfg, flags;
196         unsigned int query_cpu;
197 
198         /*
199          * Hack. The clustered APIC addressing mode doesn't allow us to send 
200          * to an arbitrary mask, so I do a unicasts to each CPU instead. This 
201          * should be modified to do 1 message per cluster ID - mbligh
202          */ 
203 
204         local_irq_save(flags);
205 
206         for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
207                 if (cpu_isset(query_cpu, mask)) {
208                 
209                         /*
210                          * Wait for idle.
211                          */
212                         apic_wait_icr_idle();
213                 
214                         /*
215                          * prepare target chip field
216                          */
217                         cfg = __prepare_ICR2(cpu_to_logical_apicid(query_cpu));
218                         apic_write_around(APIC_ICR2, cfg);
219                 
220                         /*
221                          * program the ICR 
222                          */
223                         cfg = __prepare_ICR(0, vector);
224                         
225                         /*
226                          * Send the IPI. The write to APIC_ICR fires this off.
227                          */
228                         apic_write_around(APIC_ICR, cfg);
229                 }
230         }
231         local_irq_restore(flags);
232 }
233 
234 /*
235  *      Smarter SMP flushing macros. 
236  *              c/o Linus Torvalds.
237  *
238  *      These mean you can really definitely utterly forget about
239  *      writing to user space from interrupts. (Its not allowed anyway).
240  *
241  *      Optimizations Manfred Spraul <manfred@colorfullife.com>
242  */
243 
244 static cpumask_t flush_cpumask;
245 static struct mm_struct * flush_mm;
246 static unsigned long flush_va;
247 static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
248 #define FLUSH_ALL       0xffffffff
249 
250 /*
251  * We cannot call mmdrop() because we are in interrupt context, 
252  * instead update mm->cpu_vm_mask.
253  *
254  * We need to reload %cr3 since the page tables may be going
255  * away from under us..
256  */
257 static inline void leave_mm (unsigned long cpu)
258 {
259         if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
260                 BUG();
261         cpu_clear(cpu, cpu_tlbstate[cpu].active_mm->cpu_vm_mask);
262         load_cr3(swapper_pg_dir);
263 }
264 
265 /*
266  *
267  * The flush IPI assumes that a thread switch happens in this order:
268  * [cpu0: the cpu that switches]
269  * 1) switch_mm() either 1a) or 1b)
270  * 1a) thread switch to a different mm
271  * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
272  *      Stop ipi delivery for the old mm. This is not synchronized with
273  *      the other cpus, but smp_invalidate_interrupt ignore flush ipis
274  *      for the wrong mm, and in the worst case we perform a superflous
275  *      tlb flush.
276  * 1a2) set cpu_tlbstate to TLBSTATE_OK
277  *      Now the smp_invalidate_interrupt won't call leave_mm if cpu0
278  *      was in lazy tlb mode.
279  * 1a3) update cpu_tlbstate[].active_mm
280  *      Now cpu0 accepts tlb flushes for the new mm.
281  * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
282  *      Now the other cpus will send tlb flush ipis.
283  * 1a4) change cr3.
284  * 1b) thread switch without mm change
285  *      cpu_tlbstate[].active_mm is correct, cpu0 already handles
286  *      flush ipis.
287  * 1b1) set cpu_tlbstate to TLBSTATE_OK
288  * 1b2) test_and_set the cpu bit in cpu_vm_mask.
289  *      Atomically set the bit [other cpus will start sending flush ipis],
290  *      and test the bit.
291  * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
292  * 2) switch %%esp, ie current
293  *
294  * The interrupt must handle 2 special cases:
295  * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
296  * - the cpu performs speculative tlb reads, i.e. even if the cpu only
297  *   runs in kernel space, the cpu could load tlb entries for user space
298  *   pages.
299  *
300  * The good news is that cpu_tlbstate is local to each cpu, no
301  * write/read ordering problems.
302  */
303 
304 /*
305  * TLB flush IPI:
306  *
307  * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
308  * 2) Leave the mm if we are in the lazy tlb mode.
309  */
310 
311 asmlinkage void smp_invalidate_interrupt (void)
312 {
313         unsigned long cpu;
314 
315         cpu = get_cpu();
316 
317         if (!cpu_isset(cpu, flush_cpumask))
318                 goto out;
319                 /* 
320                  * This was a BUG() but until someone can quote me the
321                  * line from the intel manual that guarantees an IPI to
322                  * multiple CPUs is retried _only_ on the erroring CPUs
323                  * its staying as a return
324                  *
325                  * BUG();
326                  */
327                  
328         if (flush_mm == cpu_tlbstate[cpu].active_mm) {
329                 if (cpu_tlbstate[cpu].state == TLBSTATE_OK) {
330                         if (flush_va == FLUSH_ALL)
331                                 local_flush_tlb();
332                         else
333                                 __flush_tlb_one(flush_va);
334                 } else
335                         leave_mm(cpu);
336         }
337         ack_APIC_irq();
338         smp_mb__before_clear_bit();
339         cpu_clear(cpu, flush_cpumask);
340         smp_mb__after_clear_bit();
341 out:
342         put_cpu_no_resched();
343 }
344 
345 static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
346                                                 unsigned long va)
347 {
348         cpumask_t tmp;
349         /*
350          * A couple of (to be removed) sanity checks:
351          *
352          * - we do not send IPIs to not-yet booted CPUs.
353          * - current CPU must not be in mask
354          * - mask must exist :)
355          */
356         BUG_ON(cpus_empty(cpumask));
357 
358         cpus_and(tmp, cpumask, cpu_online_map);
359         BUG_ON(!cpus_equal(cpumask, tmp));
360         BUG_ON(cpu_isset(smp_processor_id(), cpumask));
361         BUG_ON(!mm);
362 
363         /*
364          * i'm not happy about this global shared spinlock in the
365          * MM hot path, but we'll see how contended it is.
366          * Temporarily this turns IRQs off, so that lockups are
367          * detected by the NMI watchdog.
368          */
369         spin_lock(&tlbstate_lock);
370         
371         flush_mm = mm;
372         flush_va = va;
373 #if NR_CPUS <= BITS_PER_LONG
374         atomic_set_mask(cpumask, &flush_cpumask);
375 #else
376         {
377                 int k;
378                 unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
379                 unsigned long *cpu_mask = (unsigned long *)&cpumask;
380                 for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
381                         atomic_set_mask(cpu_mask[k], &flush_mask[k]);
382         }
383 #endif
384         /*
385          * We have to send the IPI only to
386          * CPUs affected.
387          */
388         send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
389 
390         while (!cpus_empty(flush_cpumask))
391                 /* nothing. lockup detection does not belong here */
392                 mb();
393 
394         flush_mm = NULL;
395         flush_va = 0;
396         spin_unlock(&tlbstate_lock);
397 }
398         
399 void flush_tlb_current_task(void)
400 {
401         struct mm_struct *mm = current->mm;
402         cpumask_t cpu_mask;
403 
404         preempt_disable();
405         cpu_mask = mm->cpu_vm_mask;
406         cpu_clear(smp_processor_id(), cpu_mask);
407 
408         local_flush_tlb();
409         if (!cpus_empty(cpu_mask))
410                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
411         preempt_enable();
412 }
413 
414 void flush_tlb_mm (struct mm_struct * mm)
415 {
416         cpumask_t cpu_mask;
417 
418         preempt_disable();
419         cpu_mask = mm->cpu_vm_mask;
420         cpu_clear(smp_processor_id(), cpu_mask);
421 
422         if (current->active_mm == mm) {
423                 if (current->mm)
424                         local_flush_tlb();
425                 else
426                         leave_mm(smp_processor_id());
427         }
428         if (!cpus_empty(cpu_mask))
429                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
430 
431         preempt_enable();
432 }
433 
434 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
435 {
436         struct mm_struct *mm = vma->vm_mm;
437         cpumask_t cpu_mask;
438 
439         preempt_disable();
440         cpu_mask = mm->cpu_vm_mask;
441         cpu_clear(smp_processor_id(), cpu_mask);
442 
443         if (current->active_mm == mm) {
444                 if(current->mm)
445                         __flush_tlb_one(va);
446                  else
447                         leave_mm(smp_processor_id());
448         }
449 
450         if (!cpus_empty(cpu_mask))
451                 flush_tlb_others(cpu_mask, mm, va);
452 
453         preempt_enable();
454 }
455 
456 static void do_flush_tlb_all(void* info)
457 {
458         unsigned long cpu = smp_processor_id();
459 
460         __flush_tlb_all();
461         if (cpu_tlbstate[cpu].state == TLBSTATE_LAZY)
462                 leave_mm(cpu);
463 }
464 
465 void flush_tlb_all(void)
466 {
467         on_each_cpu(do_flush_tlb_all, 0, 1, 1);
468 }
469 
470 /*
471  * this function sends a 'reschedule' IPI to another CPU.
472  * it goes straight through and wastes no time serializing
473  * anything. Worst case is that we lose a reschedule ...
474  */
475 void smp_send_reschedule(int cpu)
476 {
477         send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
478 }
479 
480 /*
481  * Structure and data for smp_call_function(). This is designed to minimise
482  * static memory requirements. It also looks cleaner.
483  */
484 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
485 
486 struct call_data_struct {
487         void (*func) (void *info);
488         void *info;
489         atomic_t started;
490         atomic_t finished;
491         int wait;
492 };
493 
494 static struct call_data_struct * call_data;
495 
496 /*
497  * this function sends a 'generic call function' IPI to all other CPUs
498  * in the system.
499  */
500 
501 int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
502                         int wait)
503 /*
504  * [SUMMARY] Run a function on all other CPUs.
505  * <func> The function to run. This must be fast and non-blocking.
506  * <info> An arbitrary pointer to pass to the function.
507  * <nonatomic> currently unused.
508  * <wait> If true, wait (atomically) until function has completed on other CPUs.
509  * [RETURNS] 0 on success, else a negative status code. Does not return until
510  * remote CPUs are nearly ready to execute <<func>> or are or have executed.
511  *
512  * You must not call this function with disabled interrupts or from a
513  * hardware interrupt handler or from a bottom half handler.
514  */
515 {
516         struct call_data_struct data;
517         int cpus = num_online_cpus()-1;
518 
519         if (!cpus)
520                 return 0;
521 
522         data.func = func;
523         data.info = info;
524         atomic_set(&data.started, 0);
525         data.wait = wait;
526         if (wait)
527                 atomic_set(&data.finished, 0);
528 
529         spin_lock(&call_lock);
530         call_data = &data;
531         mb();
532         
533         /* Send a message to all other CPUs and wait for them to respond */
534         send_IPI_allbutself(CALL_FUNCTION_VECTOR);
535 
536         /* Wait for response */
537         while (atomic_read(&data.started) != cpus)
538                 barrier();
539 
540         if (wait)
541                 while (atomic_read(&data.finished) != cpus)
542                         barrier();
543         spin_unlock(&call_lock);
544 
545         return 0;
546 }
547 
548 static void stop_this_cpu (void * dummy)
549 {
550         /*
551          * Remove this CPU:
552          */
553         cpu_clear(smp_processor_id(), cpu_online_map);
554         local_irq_disable();
555         disable_local_APIC();
556         if (cpu_data[smp_processor_id()].hlt_works_ok)
557                 for(;;) __asm__("hlt");
558         for (;;);
559 }
560 
561 /*
562  * this function calls the 'stop' function on all other CPUs in the system.
563  */
564 
565 void smp_send_stop(void)
566 {
567         smp_call_function(stop_this_cpu, NULL, 1, 0);
568 
569         local_irq_disable();
570         disable_local_APIC();
571         local_irq_enable();
572 }
573 
574 /*
575  * Reschedule call back. Nothing to do,
576  * all the work is done automatically when
577  * we return from the interrupt.
578  */
579 asmlinkage void smp_reschedule_interrupt(void)
580 {
581         ack_APIC_irq();
582 }
583 
584 asmlinkage void smp_call_function_interrupt(void)
585 {
586         void (*func) (void *info) = call_data->func;
587         void *info = call_data->info;
588         int wait = call_data->wait;
589 
590         ack_APIC_irq();
591         /*
592          * Notify initiating CPU that I've grabbed the data and am
593          * about to execute the function
594          */
595         mb();
596         atomic_inc(&call_data->started);
597         /*
598          * At this point the info structure may be out of scope unless wait==1
599          */
600         irq_enter();
601         (*func)(info);
602         irq_exit();
603 
604         if (wait) {
605                 mb();
606                 atomic_inc(&call_data->finished);
607         }
608 }
609 
610 

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