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TOMOYO Linux Cross Reference
Linux/arch/mips/include/asm/octeon/cvmx-wqe.h

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  1 /***********************license start***************
  2  * Author: Cavium Networks
  3  *
  4  * Contact: support@caviumnetworks.com
  5  * This file is part of the OCTEON SDK
  6  *
  7  * Copyright (c) 2003-2008 Cavium Networks
  8  *
  9  * This file is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License, Version 2, as
 11  * published by the Free Software Foundation.
 12  *
 13  * This file is distributed in the hope that it will be useful, but
 14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16  * NONINFRINGEMENT.  See the GNU General Public License for more
 17  * details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this file; if not, write to the Free Software
 21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22  * or visit http://www.gnu.org/licenses/.
 23  *
 24  * This file may also be available under a different license from Cavium.
 25  * Contact Cavium Networks for more information
 26  ***********************license end**************************************/
 27 
 28 /**
 29  *
 30  * This header file defines the work queue entry (wqe) data structure.
 31  * Since this is a commonly used structure that depends on structures
 32  * from several hardware blocks, those definitions have been placed
 33  * in this file to create a single point of definition of the wqe
 34  * format.
 35  * Data structures are still named according to the block that they
 36  * relate to.
 37  *
 38  */
 39 
 40 #ifndef __CVMX_WQE_H__
 41 #define __CVMX_WQE_H__
 42 
 43 #include <asm/octeon/cvmx-packet.h>
 44 
 45 
 46 #define OCT_TAG_TYPE_STRING(x)                                          \
 47         (((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" :              \
 48                 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" :        \
 49                         (((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" :    \
 50                                 "NULL_NULL")))
 51 
 52 /**
 53  * HW decode / err_code in work queue entry
 54  */
 55 typedef union {
 56         uint64_t u64;
 57 
 58         /* Use this struct if the hardware determines that the packet is IP */
 59         struct {
 60 #ifdef __BIG_ENDIAN_BITFIELD
 61                 /* HW sets this to the number of buffers used by this packet */
 62                 uint64_t bufs:8;
 63                 /* HW sets to the number of L2 bytes prior to the IP */
 64                 uint64_t ip_offset:8;
 65                 /* set to 1 if we found DSA/VLAN in the L2 */
 66                 uint64_t vlan_valid:1;
 67                 /* Set to 1 if the DSA/VLAN tag is stacked */
 68                 uint64_t vlan_stacked:1;
 69                 uint64_t unassigned:1;
 70                 /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
 71                 uint64_t vlan_cfi:1;
 72                 /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
 73                 uint64_t vlan_id:12;
 74                 /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
 75                 uint64_t pr:4;
 76                 uint64_t unassigned2:8;
 77                 /* the packet needs to be decompressed */
 78                 uint64_t dec_ipcomp:1;
 79                 /* the packet is either TCP or UDP */
 80                 uint64_t tcp_or_udp:1;
 81                 /* the packet needs to be decrypted (ESP or AH) */
 82                 uint64_t dec_ipsec:1;
 83                 /* the packet is IPv6 */
 84                 uint64_t is_v6:1;
 85 
 86                 /*
 87                  * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
 88                  * software, etc.).
 89                  */
 90 
 91                 /*
 92                  * reserved for software use, hardware will clear on
 93                  * packet creation.
 94                  */
 95                 uint64_t software:1;
 96                 /* exceptional conditions below */
 97                 /* the receive interface hardware detected an L4 error
 98                  * (only applies if !is_frag) (only applies if
 99                  * !rcv_error && !not_IP && !IP_exc && !is_frag)
100                  * failure indicated in err_code below, decode:
101                  *
102                  * - 1 = Malformed L4
103                  * - 2 = L4 Checksum Error: the L4 checksum value is
104                  * - 3 = UDP Length Error: The UDP length field would
105                  *       make the UDP data longer than what remains in
106                  *       the IP packet (as defined by the IP header
107                  *       length field).
108                  * - 4 = Bad L4 Port: either the source or destination
109                  *       TCP/UDP port is 0.
110                  * - 8 = TCP FIN Only: the packet is TCP and only the
111                  *       FIN flag set.
112                  * - 9 = TCP No Flags: the packet is TCP and no flags
113                  *       are set.
114                  * - 10 = TCP FIN RST: the packet is TCP and both FIN
115                  *        and RST are set.
116                  * - 11 = TCP SYN URG: the packet is TCP and both SYN
117                  *        and URG are set.
118                  * - 12 = TCP SYN RST: the packet is TCP and both SYN
119                  *        and RST are set.
120                  * - 13 = TCP SYN FIN: the packet is TCP and both SYN
121                  *        and FIN are set.
122                  */
123                 uint64_t L4_error:1;
124                 /* set if the packet is a fragment */
125                 uint64_t is_frag:1;
126                 /* the receive interface hardware detected an IP error
127                  * / exception (only applies if !rcv_error && !not_IP)
128                  * failure indicated in err_code below, decode:
129                  *
130                  * - 1 = Not IP: the IP version field is neither 4 nor
131                  *       6.
132                  * - 2 = IPv4 Header Checksum Error: the IPv4 header
133                  *       has a checksum violation.
134                  * - 3 = IP Malformed Header: the packet is not long
135                  *       enough to contain the IP header.
136                  * - 4 = IP Malformed: the packet is not long enough
137                  *       to contain the bytes indicated by the IP
138                  *       header. Pad is allowed.
139                  * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
140                  *       Hop Count field are zero.
141                  * - 6 = IP Options
142                  */
143                 uint64_t IP_exc:1;
144                 /*
145                  * Set if the hardware determined that the packet is a
146                  * broadcast.
147                  */
148                 uint64_t is_bcast:1;
149                 /*
150                  * St if the hardware determined that the packet is a
151                  * multi-cast.
152                  */
153                 uint64_t is_mcast:1;
154                 /*
155                  * Set if the packet may not be IP (must be zero in
156                  * this case).
157                  */
158                 uint64_t not_IP:1;
159                 /*
160                  * The receive interface hardware detected a receive
161                  * error (must be zero in this case).
162                  */
163                 uint64_t rcv_error:1;
164                 /* lower err_code = first-level descriptor of the
165                  * work */
166                 /* zero for packet submitted by hardware that isn't on
167                  * the slow path */
168                 /* type is cvmx_pip_err_t */
169                 uint64_t err_code:8;
170 #else
171                 uint64_t err_code:8;
172                 uint64_t rcv_error:1;
173                 uint64_t not_IP:1;
174                 uint64_t is_mcast:1;
175                 uint64_t is_bcast:1;
176                 uint64_t IP_exc:1;
177                 uint64_t is_frag:1;
178                 uint64_t L4_error:1;
179                 uint64_t software:1;
180                 uint64_t is_v6:1;
181                 uint64_t dec_ipsec:1;
182                 uint64_t tcp_or_udp:1;
183                 uint64_t dec_ipcomp:1;
184                 uint64_t unassigned2:4;
185                 uint64_t unassigned2a:4;
186                 uint64_t pr:4;
187                 uint64_t vlan_id:12;
188                 uint64_t vlan_cfi:1;
189                 uint64_t unassigned:1;
190                 uint64_t vlan_stacked:1;
191                 uint64_t vlan_valid:1;
192                 uint64_t ip_offset:8;
193                 uint64_t bufs:8;
194 #endif
195         } s;
196 
197         /* use this to get at the 16 vlan bits */
198         struct {
199 #ifdef __BIG_ENDIAN_BITFIELD
200                 uint64_t unused1:16;
201                 uint64_t vlan:16;
202                 uint64_t unused2:32;
203 #else
204                 uint64_t unused2:32;
205                 uint64_t vlan:16;
206                 uint64_t unused1:16;
207 
208 #endif
209         } svlan;
210 
211         /*
212          * use this struct if the hardware could not determine that
213          * the packet is ip.
214          */
215         struct {
216 #ifdef __BIG_ENDIAN_BITFIELD
217                 /*
218                  * HW sets this to the number of buffers used by this
219                  * packet.
220                  */
221                 uint64_t bufs:8;
222                 uint64_t unused:8;
223                 /* set to 1 if we found DSA/VLAN in the L2 */
224                 uint64_t vlan_valid:1;
225                 /* Set to 1 if the DSA/VLAN tag is stacked */
226                 uint64_t vlan_stacked:1;
227                 uint64_t unassigned:1;
228                 /*
229                  * HW sets to the DSA/VLAN CFI flag (valid when
230                  * vlan_valid)
231                  */
232                 uint64_t vlan_cfi:1;
233                 /*
234                  * HW sets to the DSA/VLAN_ID field (valid when
235                  * vlan_valid).
236                  */
237                 uint64_t vlan_id:12;
238                 /*
239                  * Ring Identifier (if PCIe). Requires
240                  * PIP_GBL_CTL[RING_EN]=1
241                  */
242                 uint64_t pr:4;
243                 uint64_t unassigned2:12;
244                 /*
245                  * reserved for software use, hardware will clear on
246                  * packet creation.
247                  */
248                 uint64_t software:1;
249                 uint64_t unassigned3:1;
250                 /*
251                  * set if the hardware determined that the packet is
252                  * rarp.
253                  */
254                 uint64_t is_rarp:1;
255                 /*
256                  * set if the hardware determined that the packet is
257                  * arp
258                  */
259                 uint64_t is_arp:1;
260                 /*
261                  * set if the hardware determined that the packet is a
262                  * broadcast.
263                  */
264                 uint64_t is_bcast:1;
265                 /*
266                  * set if the hardware determined that the packet is a
267                  * multi-cast
268                  */
269                 uint64_t is_mcast:1;
270                 /*
271                  * set if the packet may not be IP (must be one in
272                  * this case)
273                  */
274                 uint64_t not_IP:1;
275                 /* The receive interface hardware detected a receive
276                  * error.  Failure indicated in err_code below,
277                  * decode:
278                  *
279                  * - 1 = partial error: a packet was partially
280                  *       received, but internal buffering / bandwidth
281                  *       was not adequate to receive the entire
282                  *       packet.
283                  * - 2 = jabber error: the RGMII packet was too large
284                  *       and is truncated.
285                  * - 3 = overrun error: the RGMII packet is longer
286                  *       than allowed and had an FCS error.
287                  * - 4 = oversize error: the RGMII packet is longer
288                  *       than allowed.
289                  * - 5 = alignment error: the RGMII packet is not an
290                  *       integer number of bytes
291                  *       and had an FCS error (100M and 10M only).
292                  * - 6 = fragment error: the RGMII packet is shorter
293                  *       than allowed and had an FCS error.
294                  * - 7 = GMX FCS error: the RGMII packet had an FCS
295                  *       error.
296                  * - 8 = undersize error: the RGMII packet is shorter
297                  *       than allowed.
298                  * - 9 = extend error: the RGMII packet had an extend
299                  *       error.
300                  * - 10 = length mismatch error: the RGMII packet had
301                  *        a length that did not match the length field
302                  *        in the L2 HDR.
303                  * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
304                  *        packet had one or more data reception errors
305                  *        (RXERR) or the SPI4 packet had one or more
306                  *        DIP4 errors.
307                  * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
308                  *        packet was not large enough to cover the
309                  *        skipped bytes or the SPI4 packet was
310                  *        terminated with an About EOPS.
311                  * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
312                  *        RGMII packet had a studder error (data not
313                  *        repeated - 10/100M only) or the SPI4 packet
314                  *        was sent to an NXA.
315                  * - 16 = FCS error: a SPI4.2 packet had an FCS error.
316                  * - 17 = Skip error: a packet was not large enough to
317                  *        cover the skipped bytes.
318                  * - 18 = L2 header malformed: the packet is not long
319                  *        enough to contain the L2.
320                  */
321 
322                 uint64_t rcv_error:1;
323                 /*
324                  * lower err_code = first-level descriptor of the
325                  * work
326                  */
327                 /*
328                  * zero for packet submitted by hardware that isn't on
329                  * the slow path
330                  */
331                 /* type is cvmx_pip_err_t (union, so can't use directly */
332                 uint64_t err_code:8;
333 #else
334                 uint64_t err_code:8;
335                 uint64_t rcv_error:1;
336                 uint64_t not_IP:1;
337                 uint64_t is_mcast:1;
338                 uint64_t is_bcast:1;
339                 uint64_t is_arp:1;
340                 uint64_t is_rarp:1;
341                 uint64_t unassigned3:1;
342                 uint64_t software:1;
343                 uint64_t unassigned2:4;
344                 uint64_t unassigned2a:8;
345                 uint64_t pr:4;
346                 uint64_t vlan_id:12;
347                 uint64_t vlan_cfi:1;
348                 uint64_t unassigned:1;
349                 uint64_t vlan_stacked:1;
350                 uint64_t vlan_valid:1;
351                 uint64_t unused:8;
352                 uint64_t bufs:8;
353 #endif
354         } snoip;
355 
356 } cvmx_pip_wqe_word2;
357 
358 /**
359  * Work queue entry format
360  *
361  * must be 8-byte aligned
362  */
363 typedef struct {
364 
365     /*****************************************************************
366      * WORD 0
367      *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
368      */
369 
370 #ifdef __BIG_ENDIAN_BITFIELD
371     /**
372      * raw chksum result generated by the HW
373      */
374         uint16_t hw_chksum;
375     /**
376      * Field unused by hardware - available for software
377      */
378         uint8_t unused;
379     /**
380      * Next pointer used by hardware for list maintenance.
381      * May be written/read by HW before the work queue
382      *           entry is scheduled to a PP
383      * (Only 36 bits used in Octeon 1)
384      */
385         uint64_t next_ptr:40;
386 #else
387         uint64_t next_ptr:40;
388         uint8_t unused;
389         uint16_t hw_chksum;
390 #endif
391 
392     /*****************************************************************
393      * WORD 1
394      *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
395      */
396 
397 #ifdef __BIG_ENDIAN_BITFIELD
398     /**
399      * HW sets to the total number of bytes in the packet
400      */
401         uint64_t len:16;
402     /**
403      * HW sets this to input physical port
404      */
405         uint64_t ipprt:6;
406 
407     /**
408      * HW sets this to what it thought the priority of the input packet was
409      */
410         uint64_t qos:3;
411 
412     /**
413      * the group that the work queue entry will be scheduled to
414      */
415         uint64_t grp:4;
416     /**
417      * the type of the tag (ORDERED, ATOMIC, NULL)
418      */
419         uint64_t tag_type:3;
420     /**
421      * the synchronization/ordering tag
422      */
423         uint64_t tag:32;
424 #else
425         uint64_t tag:32;
426         uint64_t tag_type:2;
427         uint64_t zero_2:1;
428         uint64_t grp:4;
429         uint64_t qos:3;
430         uint64_t ipprt:6;
431         uint64_t len:16;
432 #endif
433 
434     /**
435      * WORD 2 HW WRITE: the following 64-bits are filled in by
436      *   hardware when a packet arrives This indicates a variety of
437      *   status and error conditions.
438      */
439         cvmx_pip_wqe_word2 word2;
440 
441     /**
442      * Pointer to the first segment of the packet.
443      */
444         union cvmx_buf_ptr packet_ptr;
445 
446     /**
447      *   HW WRITE: octeon will fill in a programmable amount from the
448      *             packet, up to (at most, but perhaps less) the amount
449      *             needed to fill the work queue entry to 128 bytes
450      *
451      *   If the packet is recognized to be IP, the hardware starts
452      *   (except that the IPv4 header is padded for appropriate
453      *   alignment) writing here where the IP header starts.  If the
454      *   packet is not recognized to be IP, the hardware starts
455      *   writing the beginning of the packet here.
456      */
457         uint8_t packet_data[96];
458 
459     /**
460      * If desired, SW can make the work Q entry any length. For the
461      * purposes of discussion here, Assume 128B always, as this is all that
462      * the hardware deals with.
463      *
464      */
465 
466 } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
467 
468 #endif /* __CVMX_WQE_H__ */
469 

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