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Linux/arch/mips/pci/pci-legacy.c

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  1 /*
  2  * This program is free software; you can redistribute  it and/or modify it
  3  * under  the terms of  the GNU General  Public License as published by the
  4  * Free Software Foundation;  either version 2 of the  License, or (at your
  5  * option) any later version.
  6  *
  7  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
  8  * Copyright (C) 2011 Wind River Systems,
  9  *   written by Ralf Baechle (ralf@linux-mips.org)
 10  */
 11 #include <linux/bug.h>
 12 #include <linux/kernel.h>
 13 #include <linux/mm.h>
 14 #include <linux/bootmem.h>
 15 #include <linux/export.h>
 16 #include <linux/init.h>
 17 #include <linux/types.h>
 18 #include <linux/pci.h>
 19 #include <linux/of_address.h>
 20 
 21 #include <asm/cpu-info.h>
 22 
 23 /*
 24  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 25  * assignments.
 26  */
 27 
 28 /*
 29  * The PCI controller list.
 30  */
 31 static LIST_HEAD(controllers);
 32 
 33 static int pci_initialized;
 34 
 35 /*
 36  * We need to avoid collisions with `mirrored' VGA ports
 37  * and other strange ISA hardware, so we always want the
 38  * addresses to be allocated in the 0x000-0x0ff region
 39  * modulo 0x400.
 40  *
 41  * Why? Because some silly external IO cards only decode
 42  * the low 10 bits of the IO address. The 0x00-0xff region
 43  * is reserved for motherboard devices that decode all 16
 44  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 45  * but we want to try to avoid allocating at 0x2900-0x2bff
 46  * which might have be mirrored at 0x0100-0x03ff..
 47  */
 48 resource_size_t
 49 pcibios_align_resource(void *data, const struct resource *res,
 50                        resource_size_t size, resource_size_t align)
 51 {
 52         struct pci_dev *dev = data;
 53         struct pci_controller *hose = dev->sysdata;
 54         resource_size_t start = res->start;
 55 
 56         if (res->flags & IORESOURCE_IO) {
 57                 /* Make sure we start at our min on all hoses */
 58                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
 59                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
 60 
 61                 /*
 62                  * Put everything into 0x00-0xff region modulo 0x400
 63                  */
 64                 if (start & 0x300)
 65                         start = (start + 0x3ff) & ~0x3ff;
 66         } else if (res->flags & IORESOURCE_MEM) {
 67                 /* Make sure we start at our min on all hoses */
 68                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
 69                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
 70         }
 71 
 72         return start;
 73 }
 74 
 75 static void pcibios_scanbus(struct pci_controller *hose)
 76 {
 77         static int next_busno;
 78         static int need_domain_info;
 79         LIST_HEAD(resources);
 80         struct pci_bus *bus;
 81 
 82         if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
 83                 next_busno = (*hose->get_busno)();
 84 
 85         pci_add_resource_offset(&resources,
 86                                 hose->mem_resource, hose->mem_offset);
 87         pci_add_resource_offset(&resources,
 88                                 hose->io_resource, hose->io_offset);
 89         pci_add_resource(&resources, hose->busn_resource);
 90         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
 91                                 &resources);
 92         hose->bus = bus;
 93 
 94         need_domain_info = need_domain_info || pci_domain_nr(bus);
 95         set_pci_need_domain_info(hose, need_domain_info);
 96 
 97         if (!bus) {
 98                 pci_free_resource_list(&resources);
 99                 return;
100         }
101 
102         next_busno = bus->busn_res.end + 1;
103         /* Don't allow 8-bit bus number overflow inside the hose -
104            reserve some space for bridges. */
105         if (next_busno > 224) {
106                 next_busno = 0;
107                 need_domain_info = 1;
108         }
109 
110         /*
111          * We insert PCI resources into the iomem_resource and
112          * ioport_resource trees in either pci_bus_claim_resources()
113          * or pci_bus_assign_resources().
114          */
115         if (pci_has_flag(PCI_PROBE_ONLY)) {
116                 pci_bus_claim_resources(bus);
117         } else {
118                 pci_bus_size_bridges(bus);
119                 pci_bus_assign_resources(bus);
120         }
121         pci_bus_add_devices(bus);
122 }
123 
124 #ifdef CONFIG_OF
125 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
126 {
127         struct of_pci_range range;
128         struct of_pci_range_parser parser;
129 
130         pr_info("PCI host bridge %s ranges:\n", node->full_name);
131         hose->of_node = node;
132 
133         if (of_pci_range_parser_init(&parser, node))
134                 return;
135 
136         for_each_of_pci_range(&parser, &range) {
137                 struct resource *res = NULL;
138 
139                 switch (range.flags & IORESOURCE_TYPE_BITS) {
140                 case IORESOURCE_IO:
141                         pr_info("  IO 0x%016llx..0x%016llx\n",
142                                 range.cpu_addr,
143                                 range.cpu_addr + range.size - 1);
144                         hose->io_map_base =
145                                 (unsigned long)ioremap(range.cpu_addr,
146                                                        range.size);
147                         res = hose->io_resource;
148                         break;
149                 case IORESOURCE_MEM:
150                         pr_info(" MEM 0x%016llx..0x%016llx\n",
151                                 range.cpu_addr,
152                                 range.cpu_addr + range.size - 1);
153                         res = hose->mem_resource;
154                         break;
155                 }
156                 if (res != NULL)
157                         of_pci_range_to_resource(&range, node, res);
158         }
159 }
160 
161 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
162 {
163         struct pci_controller *hose = bus->sysdata;
164 
165         return of_node_get(hose->of_node);
166 }
167 #endif
168 
169 static DEFINE_MUTEX(pci_scan_mutex);
170 
171 void register_pci_controller(struct pci_controller *hose)
172 {
173         struct resource *parent;
174 
175         parent = hose->mem_resource->parent;
176         if (!parent)
177                 parent = &iomem_resource;
178 
179         if (request_resource(parent, hose->mem_resource) < 0)
180                 goto out;
181 
182         parent = hose->io_resource->parent;
183         if (!parent)
184                 parent = &ioport_resource;
185 
186         if (request_resource(parent, hose->io_resource) < 0) {
187                 release_resource(hose->mem_resource);
188                 goto out;
189         }
190 
191         INIT_LIST_HEAD(&hose->list);
192         list_add_tail(&hose->list, &controllers);
193 
194         /*
195          * Do not panic here but later - this might happen before console init.
196          */
197         if (!hose->io_map_base) {
198                 printk(KERN_WARNING
199                        "registering PCI controller with io_map_base unset\n");
200         }
201 
202         /*
203          * Scan the bus if it is register after the PCI subsystem
204          * initialization.
205          */
206         if (pci_initialized) {
207                 mutex_lock(&pci_scan_mutex);
208                 pcibios_scanbus(hose);
209                 mutex_unlock(&pci_scan_mutex);
210         }
211 
212         return;
213 
214 out:
215         printk(KERN_WARNING
216                "Skipping PCI bus scan due to resource conflict\n");
217 }
218 
219 static int __init pcibios_init(void)
220 {
221         struct pci_controller *hose;
222 
223         /* Scan all of the recorded PCI controllers.  */
224         list_for_each_entry(hose, &controllers, list)
225                 pcibios_scanbus(hose);
226 
227         pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
228 
229         pci_initialized = 1;
230 
231         return 0;
232 }
233 
234 subsys_initcall(pcibios_init);
235 
236 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
237 {
238         u16 cmd, old_cmd;
239         int idx;
240         struct resource *r;
241 
242         pci_read_config_word(dev, PCI_COMMAND, &cmd);
243         old_cmd = cmd;
244         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
245                 /* Only set up the requested stuff */
246                 if (!(mask & (1<<idx)))
247                         continue;
248 
249                 r = &dev->resource[idx];
250                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
251                         continue;
252                 if ((idx == PCI_ROM_RESOURCE) &&
253                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
254                         continue;
255                 if (!r->start && r->end) {
256                         printk(KERN_ERR "PCI: Device %s not available "
257                                "because of resource collisions\n",
258                                pci_name(dev));
259                         return -EINVAL;
260                 }
261                 if (r->flags & IORESOURCE_IO)
262                         cmd |= PCI_COMMAND_IO;
263                 if (r->flags & IORESOURCE_MEM)
264                         cmd |= PCI_COMMAND_MEMORY;
265         }
266         if (cmd != old_cmd) {
267                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
268                        pci_name(dev), old_cmd, cmd);
269                 pci_write_config_word(dev, PCI_COMMAND, cmd);
270         }
271         return 0;
272 }
273 
274 int pcibios_enable_device(struct pci_dev *dev, int mask)
275 {
276         int err;
277 
278         if ((err = pcibios_enable_resources(dev, mask)) < 0)
279                 return err;
280 
281         return pcibios_plat_dev_init(dev);
282 }
283 
284 void pcibios_fixup_bus(struct pci_bus *bus)
285 {
286         struct pci_dev *dev = bus->self;
287 
288         if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
289             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
290                 pci_read_bridge_bases(bus);
291         }
292 }
293 
294 char * (*pcibios_plat_setup)(char *str) __initdata;
295 
296 char *__init pcibios_setup(char *str)
297 {
298         if (pcibios_plat_setup)
299                 return pcibios_plat_setup(str);
300         return str;
301 }
302 

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